Intersil ISL8225MEVAL4Z Isl8225meval4z dual 15a/optional 30a cascadable evaluation board setup procedure Datasheet

Application Note 1793
ISL8225MEVAL4Z Dual 15A/Optional 30A Cascadable
Evaluation Board Setup Procedure
The ISL8225M is a complete, dual step-down switching mode
DC/DC module. The dual outputs can easily be paralleled for
single-output, high-current use. It is easy to apply this
high-power, current-sharing DC/DC power module to
power-hungry datacom, telecom, and FPGA applications. All
that is needed in order to have a complete, dual 15A design
ready for use are the ISL8225M, a few passive components,
and VOUT setting resistors.
Recommended Equipment
The simplicity of the ISL8225M is its off-the-shelf, unassisted
implementation. Patented current sharing in multi-phase
operation greatly reduces ripple currents, BOM costs, and
complexity. The ISL8225M has a thermally enhanced, compact
17mm x17mm x 7.5mm QFN package that operates at full load
and over-temperature without requiring forced-air cooling. Easy
access to all pins, with few external components, reduces PCB
design to a component layer and a simple ground layer.
Quick Start
This ISL8225MEVAL4Z evaluation board is designed for dual
15A output applications. Optionally, this board can easily be
converted for 30A single output use. Multiple
ISL8225MEVAL4Z boards can be cascadable through the
SYNC and CLKOUT pins to operate with phase shifting, for
paralleling or multiple output use. The input voltage of this
board is 4.5V to 20V and the default outputs on this board are
set at 1.2V and 1.5V.
Related Resources
See how-to
video at
intersil.com/
evid03
• 0V to 20V power supply with at least 5A source current
capability
• Electronic load capable of sinking current up to 30A
• Digital multimeters (DMMs)
• 100MHz quad-trace oscilloscope
For dual output operation, the inputs are BA7 (VIN1), BA8
(GND), BA3 (VIN2) and BA4 (GND). The outputs are BA5
(VOUT1), BA6 (GND), BA1 (VOUT2) and BA2 (GND).
For paralleled single output operation, the inputs are BA7
(VIN1) and BA8 (GND). The outputs are BA5 (VOUT1) and BA6
(GND) with BA5 and BA1 shorted.
Dual Output Mode
1. Connect a power supply capable of sourcing at least 5A to
the inputs BA7 (VIN1), BA8 (GND), BA3 (VIN2) and BA4
(GND) of the ISL8225MEVAL4Z evaluation board, with a
voltage between 4.5V to 20V. VIN1 and VIN2 can be
different with R18 and R19 open.
2. Connect an electronic load or the device to be powered to
the outputs BA5 (VOUT1) and BA6 (GND), BA1 (VOUT2) and
BA2 (GND) of the board. All connections, especially the low
voltage, high current VOUT lines, should be able to carry the
desired load current and should be made as short as
possible.
V
VOUT2
+
-
+
LOAD2
(0A~15A)
4.5V TO 20V
LOAD1 +
(0A~15A) V
VIN
VOUT1
-
V
+
FIGURE 1. ISL8225MEVAL4Z BOARD IMAGE
December 6, 2012
AN1793.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright Intersil Americas Inc. 2012. All Rights Reserved.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1793
3. Make sure that the setup is connected correctly. Turn on the
power supply. If the board is working properly, the green LED
will illuminate; if not, the red LED will illuminate (recheck the
wire/jumper connections in this case). Measure the output
voltages, VOUT1, which should be at 1.2V and VOUT2, which
should be at 1.5V
4. If different output voltages are desired, board resistors can be
exchanged to provide the desired VOUT. Please refer to Table 1
for R2/R4 resistor values, which can be used to produce
different output voltages.
For 12V VIN and VOUT more than 1.5V, the switching frequency
will need to be adjusted, as shown in Table 1. The resistor RFSET
can be adjusted for the desired frequency. No frequency
adjustments are necessary for VOUT below 1.5V. For 5V VIN, the
frequency does not need to be adjusted and the module default
frequency can be used at any allowed VOUT. If the output voltage
is set to more than 1.8V, the output current will need to be
derated to allow for safe operation. Please refer to the derating
curves in the ISL8225M datasheet.
TABLE 1. VALUE OF BOTTOM RESISTOR (TOP RESISTOR R1,
R3 = 1kΩ) AND FREQUENCY SELECTION FOR DIFFERENT
OUTPUT VOLTAGES
VOUT
(V)
R2 /R4
(Ω)
FREQUENCY
(kHz)
RFSET (Ω)
(VIN = 12V)
1.0
1500
DEFAULT
OPEN
1.2
1000
DEFAULT
OPEN
1.5
665
DEFAULT
OPEN
2.5
316
650
249k
3.3
221
800
124k
5.0
137
950
82.5k
5.5
121
950
82.5k
Optional Paralleled Single Output Mode
1. To set up the parallel mode, short JP1 (ENC), JP2 (VMON) and
JP3 (COMP) with a jumper. To set up 180° interleaving phase
between 2 channels, short the MODE pin and GND pin of JP6
with a jumper.
2. Remove R9 and R13. Change R14 to 0Ω. Change R18 and
R19 to 0Ω. Short VOUT1 to VOUT2 using short wires or copper
straps. Add C2 for a 470pF capacitor.
3. Connect a power supply capable of sourcing at least 5A to the
inputs BA7 (VIN1), BA8 (GND), BA3 (VIN2) and BA4 (GND) of
the ISL8225MEVAL4Z evaluation board, with a voltage
between 4.5V to 20V. VIN1 and VIN2 need to be shorted
together.
4. Connect an electronic load or the device to be powered to the
outputs BA5 (VOUT1) and BA6 (GND) of the board. All
connections, especially the low voltage, high current VOUT
lines, should be able to carry the desired load current and
should be made as short as possible.
5. Make sure the setup is connected correctly prior to applying any
power to the board. Adjust the power supply to 12V and turn on
the input power supply. If the board is working properly, the green
LED will illuminate; if not, the red LED will illuminate (recheck the
2
wire/jumper connections in this case). Measure the output
voltages, VOUT1, which should be at 1.2V.
6. Apply any load that is less than 30A for normal steady state
operation. Refer to Table 1 to change the output voltage by
changing resistor R2.
TABLE 2. BOARD CONFIGURATION FOR SINGLE OUTPUT 30A
APPLICATION
ENC
VMON
MODE
COMP
R9
R13
R14
Dual
OPEN
OPEN
OPEN
OPEN
0
0
OPEN
Single
ON
ON
ON
ON
OPEN
OPEN
0
Optional Cascadable Mode
Cascadable mode is needed when multiple evaluation boards
are used for paralleling or multiple output use. To demo the
parallel features, it is recommended to use ISL8225MEVAL2Z
6-phase evaluation board for an easy and efficient setup (see
AN1789). Otherwise, follow the steps shown below:
1. In order to generate CLKOUT at a shifted phase clock signal,
the control loop of VOUT2 needs to be disabled by connecting
VSEN2- to VCC.
2. Program MODE and VSEN2+ pin voltages to set the CLKOUT
signal and the shifted degrees between two phases on the
board (refer to Table 3).
3. Use a coaxial cable to connect CLKOUT (J5) to SYNC (J2) of the
next evaluation board, which can be programed for parallel or
dual output use.
4. If the second board is programed for parallel use, the ISHARE
pins of the first and second boards need to be tied together.
Using two twisted wires, short two different jumpers of JP7
(ISHARE/SGND) on two evaluation boards. Add 1nF
capacitors of C14 for different boards to decouple the noise.
5. If the third board is used in cascadable mode, the second
board can only be used in the parallel mode to generate the
CLKOUT signal for the SYNC pin on the third board.
6. Follow the instructions from Steps 1 through 5 for more
cascadable boards.
Evaluation Board Information
The evaluation board size is 114.3mm x 76.2mm. It is a 4-layer
board, containing 2-ounce copper on the top and bottom layers
and 1-ounce copper on all internal layers. The board can be used
as a dual 15A reference design. Refer to “Layout” on page 6. The
board is made of FR4 material and all components, including the
solder attachment, are lead-free.
Thermal Considerations and Current Derating
For high current applications, board layout is very critical in order
to make the module operate safely and deliver maximum
allowable power. To carry large currents, the board layout needs
to be designed carefully to maximize thermal performance. To
achieve this, select enough trace width, copper weight and the
proper connectors.
This evaluation board is designed for running dual 15A at room
temperature without additional cooling systems needed.
AN1793.1
December 6, 2012
Application Note 1793
However, if the output voltage is increased or the board is
operated at elevated temperatures, then the available current is
derated. Refer to the derated current curves in the datasheet to
determine the output current available.
For layout of designs using the ISL8225M, the thermal
performance can be improved by adhering to the following
design tips:
1. Use the top and bottom layers to carry the large current.
VOUT1, VOUT2, Phase 1, Phase 2, PGND, VIN1 and VIN2
should have large, solid planes. Place enough thermal vias to
connect the power planes in different layers under and
around the module.
2. Phase 1 and Phase 2 pads are switching nodes that generate
switching noise. Keep these pads under the module. For
noise-sensitive applications, it is recommended to keep
phase pads only on the top and inner layers of the PCB; do not
place phase pads exposed to the outside on the bottom layer
of the PCB. To improve the thermal performance, the phase
pads can be extended in the inner layer, as shown in Phase 1
and Phase 2 pads on layer 2 (Figure 5) for this dual 15A
evaluation board. Make sure that layer 1 and layer 3 have the
GND layers to cover the extended areas of phase pads at
layer 2 to avoid noise coupling.
3. Place the modules evenly on the board and leave enough
space between modules. If the board space is limited, try to
put the modules with low power loss closely together (i.e. low
VOUT or IOUT) while still separating the module with high power
loss.
4. If the ambient temperature is high or the board space is
limited, airflow is needed to dissipate more heat from the
modules. A heat sink can also be applied to the top side of the
module to further improve the thermal performance (heat
sink recommendation: Aavid Thermalloy, part number
375424B00034G, www.aavid.com).
3
AN1793.1
December 6, 2012
Application Note 1793
TABLE 3. ISL8225M OPERATION MODES
1ST MODULE (I = INPUT; O = OUTPUT; I/O = INPUT AND OUTPUT, BI-DIRECTION)
MODE
EN1/FF1 EN2/FF2
(I)
(I)
VSEN2(I)
1
0
0
-
2A
0
1
Active
2B
1
0
-
3A
1
1
3B
1
3C
MODES OF OPERATION
OPERATION OPERATION
VMON1
MODE
CLKOUT/REFIN
OF 2ND 2ND CHANNEL
MODE
OF 2ND
WRT 1ST
OF 3RD
MODE VSEN2+
VMON2 MODULE WRT 1ST (O)
(I)
(I)
(I OR O)
(Note 2) (Note 2)
(NOTE 1)
MODULE
MODULE
-
OUTPUT
(SEE
DESCRIPTION
FOR DETAILS)
-
-
-
-
-
-
Disabled
-
Active
-
VMON1 =
VMON2 to Keep
PGOOD Valid
-
-
Single Phase
-
-
-
VMON1 =
VMON2 to Keep
PGOOD Valid
-
-
Single Phase
<VCC -0.7V Active Active
29% to 45%
of VCC (I)
Active
-
0°
-
-
Dual Regulator
1
<VCC -0.7V Active Active
45% to 62%
of VCC (I)
Active
-
90°
-
-
Dual Regulator
1
1
<VCC -0.7V Active Active >62% of VCC (I)
Active
-
180°
-
-
Dual Regulator
4
1
1
<VCC -0.7V Active Active <29% of VCC (I)
Active
-
-60°
-
-
DDR Mode
5A
1
1
VCC
GND
-
60°
VMON1
or
Divider
-
180°
-
-
2-Phase
5B
1
1
VCC
GND
-
60°
Divider
Divider
180°
5B
5B
6-Phase
5C
1
1
VCC
GND
-
60°
VMON1
or
Divider
Active
180°
5C
5C
3 Outputs
6
1
1
VCC
VCC
GND
120°
1kΩ
Active
240°
2B
-
3-Phase
7A
1
1
VCC
VCC
VCC
90°
1kΩ
Divider
180°
7A
-
4-Phase
7B
1
1
VCC
VCC
VCC
90°
1kΩ
Active
180°
7B
-
2 Outputs
(1st module in
Mode 7A)
7C
1
1
VCC
VCC
VCC
90°
1kΩ
Active
180°
3, 4
-
3 Outputs
(1st module in
Mode 7A)
-
Active Active
-
-
8
Cascaded Module Operation MODEs 5B+5B+7A+5B+5B+5B/7A, No External Clock Required
12-Phase
9
External Clock or External Logic Circuits Required for Equal Phase Interval
5, 7, 8, 9, 10, 11,
or
(PHASE >12)
NOTE:
1. “2ND CHANNEL WRT 1ST” means “second channel with respect to first;” in other words, Channel 2 lags Channel 1 by the degrees specified in this
column. For example, 90° means Channel 2 lags Channel 1 by 90°; -60° means Channel 2 leads Channel 1 by 60°.
2. “VMON1” means that the pin is tied to the VMON1 pin of the same module.
“Divider” means that there is a resistor divider from VOUT to SGND; refer to Figure 24 in the ISL8225M datasheet.
“1kΩ” means that there is a 1kΩ resistor connecting the pin to SGND; refer to Figure 22 in the ISL8225M datasheet.
4
AN1793.1
December 6, 2012
ISL8225MEVAL4Z Board Schematic
VOUT2
VOUT1
4 J1
GND
R14
0
C04
330UF
OPEN
C03
C02
OPEN
C01
C16
1K
47UF
BA5
1000PF
OPEN
R22
R1
P5
VOUT1
P6
GND
BA6
R21
21
22
23
25
C8
1000PF
E
IN
VCC
DNP
OUT
C1
4
3
VCC
D
6
DNP
4.7UF
VIN2
OUT
SGND
ISL8225MIRZ
VCC
D
D
E
**
8
EN/FF2
EN/FF1
17
OUT
16
IN
15
14
13
IN
OPEN
C14
1
JP7
VMON1
CLKOUT
EN/FF2
EN/FF1
P7
D
VIN1
VIN1
BA7
3
4
VMON1
VCC
0
2
1000PF
C5
1
JP4
2
R6
DNP
IN
D
IN
IN
R19
E
COMP1
DNP
JP3
C2
DNP
DNP
C3
IN
DRAWN BY:
TIM KLEMANN
DATE:
ENGINEER:
DATE:
GROUND AND
GROUND ARE TIED TOGETHER AT PIN 6 OF U1.
UPDATED BY:
DATE:
D
E
STEVEN MCGEE
TITLE:
ISL8225M
EVALUATION BOARD
SCHEMATIC
10/26/2012
TESTER
MASK#
FILENAME:
D
FIGURE 2. ISL8225MEVAL4Z BOARD SCHEMATIC
DATE:
JIAN YIN
08/04/2011
RELEASED BY:
NOTE: **
2
COMP2
COMP
1
IN
Q1
1
2N7002-7-F
VIN1
2
VIN2
D
LED1
SSL_LXA3025IGC
PGOOD
R18
D
EN/FF1
3 4
C4
1000PF
1
JP5
EN2
2
4.12K
R8
DNP
C6
C7
DNP
IN
EN/FF1
ENC
EN/FF2
4.12K
VMON
JP2
1
JP1
OUT
IN
3.32K
OUT
2
VMON2
3.32K
R12
RED
IN
D
3
D
1
E
16.5K
1
R11
R5
12
2
PHASE1
E
GRN
11
10
16.5K
R7
PHASE2
GND
D
E
E
BA8
5J5
P8
R13
DNP
R16
C10
BA4
CLKOUT
1
2
IN
OPEN
330UF
CLKOUT
2
CIN1
CIN2
22UF
PHASE1
N/C
GND
PHASE2
CIN3
9
22UF
PGND
22UF
CIN6
CIN5
22UF
P4
330UF
CIN4
1
BA3
VSEN1-
CLKOUT
OUT
Application Note 1793
7
U1
SYNC
ISHARE
18
2
5
RFSET
OUT
19
ISHARE
SYNC
COMP1
20
VIN1
1
2
J25
ISHARE
VMON1
VMON2
VIN2
D
OUT
DNP
2
R15
JP6
MODE
VMON2
MODE
4
COMP1
PGND
1
3
VOUT1
VSEN1+
MODE
VOUT2
PGOOD
OUT
COMP2
VSEN2-
2
VSEN2+
E
COMP2
VIN2
OPEN
1K
0
DNP
E
1
2
R10
0
IN
1
5
VCC
26
BA2
P3
C21
R9
R2
R4
C15
1000PF
C05
47UF
C06
OPEN
47UF
C07
OPEN
C010
C08
330UF
P2
1K
PGOOD
OUT
R3
24
0
BA1
C18
R20
OPEN
OPEN
E
665
1000PF
VOUT2
C12
C09
C11
3
3
J4 4
P1
47UF
1
2
C9
~/ISL8225M/ISL8225MEVAL4ZD
HRDWR ID
ISL8225MEVAL4Z
SHEET
1
REV.
OF
D
1
AN1793.1
December 6, 2012
Layout
6
FIGURE 4. TOP LAYER COMPONENT SIDE
FIGURE 5. LAYER 2
FIGURE 6. LAYER 3
Application Note 1793
AN1793.1
December 6, 2012
FIGURE 3. TOP SILK SCREEN
Layout
(Continued)
7
FIGURE 8. BOTTOM SILK SCREEN
Application Note 1793
FIGURE 7. BOTTOM LAYER SOLDER SIDE
AN1793.1
December 6, 2012
Bill of Materials
PART NUMBER
REF DES
QTY
VALUE
TOL. VOLTAGE POWER PACKAGE TYPE
10TPB330M
C04, C08
2
330µF
20%
131-4353-00
J1, J4
2
CONN
TEK131-4353-00
2N7002-7-F
Q1
1
SOT23
SOT23
31-5329-52RFX
J2, J5
2
CONN
CON_BNC_31_5329_52RFX
5002
P1-P8
8
THOLE
MTP500X
8
575-4
10V
SMD
JEDEC TYPE
MANUFACTURER
DESCRIPTION
CAP_7343_149
BA1-BA8
8
CONN
CON_BAN_575
CIN1, CIN4
2
330µF
20%
25V
SMD
CAPAE_315X402
GRM21BR71C475KA73L
C1
1
4.7µF
10%
16V
805
CAP_0805
Murata
Ceramic Capacitor
GRM32ER71A476KE15L
C01, C03, C05, C07
4
47µF
10%
10V
1210
CAP_1210
Murata
Ceramic Chip Capacitor
OPEN
5%
EEVHA1E331UP
H1045-OPEN
4
OPEN
603
CAP_0603
Generic
Multilayer Capacitor
C15, C16
2
1000pF 10%
16V
603
CAP_0603
Generic
Multilayer Capacitor
H1045-00102-50V10
C4, C5, C8, C9
4
1000pF 10%
50V
603
CAP_0603
Generic
Multilayer Capacitor
C10, C11, C12, C14
6
OPEN
5%
OPEN
603
CAP_0603
Generic
Multilayer Capacitor
OPEN
Generic
Ceramic Chip Capacitor
Taiyo Yuden
Ceramic Chip Capacitor
H1045-OPEN
H1082-OPEN
C02, C06, C09, C010
4
OPEN
10%
1210
CAP_1210
H2505-DNP-DNP-1
R14-R16, R21, RFSET
5
DNP
1%
DNP
603
RES_0603
H2511-00R00-1/16W1
R9, R10, R13, R17, R20
5
0Ω
1%
1/16W
603
RES_0603
H2511-01001-1/16W1
R1, R2, R3, R6, R8
4
1kΩ
1%
1/16W
603
RES_0603
H2511-03321-1/16W1
R11, R12
2
3.32kΩ
1%
1/16W
603
RES_0603
H2511-16501-1/16W1
R5, R7
2
16.5kΩ
1%
1/16W
603
RES_0603
H2511-04121-1/16W1
R6, R8
2
4.12kΩ
1%
1/16W
603
RES_0603
H2511-06650-1/16W1
R4
1
665Ω
1%
1/16W
603
RES_0603
OPEN
0%
1/10W
H2512-OPEN
R18, R19
2
805
RES_0805
ISL8225MIRZ
U1
1
QFN
QFN26_670X670_ISL8225M
JUMPER2_100
JP1-JP7
7
THOLE
LED1
1
SMD
LED_3X2_5MM
CIN2, CIN3, CIN5, CIN6
4
1210
CAP_1210
SSL-LXA3025IGC
TMK325B7226MM-TR
22µF
20%
25V
JUMPER-1
Application Note 1793
C2, C3, C6, C7
H1045-00102-16V10
AN1793.1
December 6, 2012
Application Note 1793
ISL8225MEVAL4Z Efficiency Curves
100
3.3V
95
100
1.8V
2.5V
95
90
85
1V
80
1.2V
EFFICIENCY (%)
EFFICIENCY (%)
90
1.5V
75
70
65
85
75
55
2
4
6
8
10
LOAD CURRENT (A)
12
14
FIGURE 9. EFFICIENCY vs LOAD CURRENT (5VIN AT 500kHz)
16
1V AT 500kHz
65
60
50
1.8V AT 500kHz
1.2V AT 500kHz
70
55
0
1.5V AT 500kHz
80
60
50
2.5V AT 500kHz
3.3V AT 650kHz
5V AT 850kHz
0
2
4
6
8
10
12
14
16
LOAD CURRENT (A)
FIGURE 10. EFFICIENCY vs LOAD CURRENT (12V IN)
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
AN1793.1
December 6, 2012
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