ISL9212B ® Data Sheet March 21, 2007 FN6399.0 Charging System Safety Circuit Features The ISL9212B is an integrated circuit (IC) optimized to provide a Li-ion battery redundant safety protection from failures of a charging system. The IC monitors the input voltage, the battery voltage, and the charge current. When any of the three parameters exceeds its limit, the IC turns off an internal P-Channel MOSFET to remove the power from the charging system. In addition to the above protected parameters, the IC also monitors its own internal temperature and turns off the P-Channel MOSFET when the die temperature exceeds +140°C. Together with the battery charger IC and the protection module in a battery pack, the charging system using the ISL9212B has triple-level protection and is two-fault tolerant. • Fully Integrated Protection Circuit for Three Protection Variables - User Programmable Overcurrent Protection Threshold - Input Overvoltage Protection in Less Than 1µs - Battery Overvoltage Protection The IC is designed to turn on the internal PFET slowly to avoid inrush current at power-up but will turn off the PFET quickly when input overvoltage is detected in order to remove the power before any damage occurs. The ISL9212B has a logic warning output to indicate the fault and an enable input to allow the system to remove the input power. ISL9212BIRZ* (Note) • Warning Output to Indicate the Occurrence of Faults • Enable Input • Thermal Enhanced DFN Package • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Cell Phones • Digital Still Cameras • PDAs and Smart Phones • Desktop Chargers TEMP. RANGE PART (°C) MARKING 2BZ • High Accuracy Protection Thresholds • Portable Instruments Ordering Information PART NUMBER • High Immunity of False Triggering Under Transients PACKAGE PKG. DWG. # -40 to +85 12 Ld 4x3 TDFN L12.4x3A (Pb-free) ISL9212EVAL1 ISL9212B Evaluation Board Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Technical Brief TB379 “Thermal Characterization of Packaged Semiconductor Devices” *Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • Technical Brief TB389 “PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages” Pinout ISL9212B (12 LD 4x3 TDFN) TOP VIEW Typical Application Circuit INPUT VIN OUT C1 ISL6292 BATTERY CHARGER ISL9212B 1 12 NC VIN 2 11 OUT GND 3 WRN 4 9 ILIM NC 5 8 VB NC 6 7 EN EPAD 10 OUT VB ILIM RVB EN RILIM VIN WRN GND 1 + NOTE: EPAD must be electrically connected to the GND pin. BATTERY PACK CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL9212B Absolute Maximum Ratings (Reference to GND) Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 30V Output and VB Pin (OUT, VB) (Note 1) . . . . . . . . . . . . . . . -0.3 to 7V Other Pins (ILIM, WRN, EN) . . . . . . . . . . . . . . . . . . . . . -0.3 to 5.5V Thermal Resistance (Notes 2, 3) θJA (°C/W) θJC (°C/W) 4x3 TDFN Package . . . . . . . . . . . . . . . 41 3.5 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3V to 6.5V Operating Current Range. . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. +150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150°C junction may trigger the shutdown of the device even before +150°C, since this number is specified as typical. ΝΟΤΕΣ: 1. The maximum voltage rating for the VB pin under continuous operating conditions is 5.5V. All other pins are allowed to operate continuously at the absolute maximum ratings. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 3. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications Typical values are tested at VIN = 5V and +25°C Ambient Temperature, maximum and minimum values are guaranteed over the recommended operating conditions, unless otherwise noted. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 2.40 2.58 2.70 V - 100 - mV When enabled 0.75 0.90 1.10 mA When disabled 30 60 100 μA 6.65 6.80 7.00 V POWER-ON RESET Rising VIN Threshold VPOR POR Hysteresis VIN Bias Current IVIN VIN Bias Current PROTECTIONS Input Overvoltage Protection (OVP) VOVP Input OVP Hysteresis - 60 100 mV Input OVP Falling Threshold 6.55 - - V Input OVP Propagation Delay - - 1 μs 0.93 1.00 1.07 A Overcurrent Protection Blanking Time BTOCP - 170 - μs Battery Overvoltage Protection Threshold VBOVP 4.28 4.34 4.40 V Overcurrent Protection IOCP VVB = 3V, RILIM = 25kΩ Battery OVP Threshold Hysteresis Battery OVP Falling Threshold Battery OVP Blanking Time BTBOVP VVB = 4.34V - 30 - mV 4.25 - - V - 180 - μs - - 20 nA Over-Temperature Protection Rising Threshold - 140 - °C Over-Temperature Protection Falling Threshold - 90 - °C EN Input Logic HIGH 1.5 - - V EN Input Logic LOW - - 0.4 V VB Pin Leakage Current LOGIC EN Internal Pull Down Resistor WRN Output Logic Low Sink 5mA current WRN Output Logic High Leakage Current 100 200 400 kΩ - 0.35 0.80 V - - 1 μA - 170 280 mΩ POWER MOSFET ON-Resistance rDS(ON) 2 4.6V < VIN < 6.5V FN6399.0 March 21, 2007 ISL9212B Pin Descriptions VB (Pin 8) VIN (Pins 1, 2) Battery voltage monitoring input. This pin is connected to the battery pack positive terminal via an isolation resistor. The input power source. The VIN can withstand 30V input. ILIM (Pin 9) GND (Pin 3) System ground reference. Overcurrent protection threshold setting pin. Connect a resistor between this pin and GND to set the OCP threshold. WRN (Pin 4) OUT (Pins 10, 11) WRN is an open-drain logic output that turns LOW when any protection event occurs. Output pin. EPAD NC (Pins 5, 6, 12) The exposed pad at the bottom of the DFN package for enhancing thermal performance. Must be electrically connected to the GND pin. No connection and must be left floating. EN (Pin 7) Enable input. Pull this pin to low or leave it floating to enable the IC and force it to high, which will disable the IC. Typical Applications INPUT VIN OUT C1 ISL6292 BATTERY CHARGER PART ISL9212B RVB 25kΩ RVB 200kΩ to 1MΩ 1µF/16V X5R ceramic capacitor BATTERY PACK WRN GND C1 + EN RILIM RILIM VB ILIM DESCRIPTION Block Diagram INPUT OUT VIN ISL6292 BATTERY CHARGER Q1 Q2 POR PRE-REG REF Q3 ILIM FET DRIVER RILIM CP2 R1 EA 0.8V CP1 CP3 LOGIC VB R VB 1.2V R2 R3 Q4 R4 Q5 WRN GND BUF + R5 EN FIGURE 1. BLOCK DIAGRAM 3 FN6399.0 March 21, 2007 ISL9212B Typical Operating Performance The test conditions for the Typical Operating Performance are: VIN = 5V, TA = +25°C, RILIM = 25.5kΩ, RVB = 200kΩ, Unless Otherwise Noted. VIN (2V/DIV) VIN (2V/div) VIN VIN (1V/div) (1V/DIV) OUT OUT (1V/div) (1V/DIV) OUT (2V/DIV) OUT (2V/div) LOADCurrent CURRENT Load 200mA/DIV (200mA/div) WRN (5V/DIV) WRN (5V/div) TIME: 5ms/DIV Time: 5ms/div FIGURE 2. CAPTURED WAVEFORMS FOR POWER-UP. THE OUTPUT IS LOADED WITH A 10Ω RESISTOR TIME:200ms/div 200ms/DIV Time: TIME: 2μs/div 2µs/DIV Time: FIGURE 3. CAPTURED WAVEFORMS WHEN THE INPUT VOLTAGE STEPS FROM 6.5V TO 10.5V VIN (2V/div) (2V/DIV) VIN VIN (2V/DIV) VIN (2V/div) OUT (2V/div) (2V/DIV) OUT OUT OUT(2V/DIV) (2V/div) WRN (5V/DIV) WRN (5V/div) WRN (5V/DIV) WRN (5V/div) Time: TIME: 5ms/div 5ms/DIV FIGURE 4. CAPTURED WAVEFORMS WHEN THE INPUT GRADUALLY RISES TO THE INPUT OVERVOLTAGE THRESHOLD FIGURE 5. TRANSIENT WHEN THE INPUT VOLTAGE STEPS FROM 7.5V TO 6.5V TIME: 20s/DIV Time: 20s/div VIN (2V/DIV) VIN (2V/div) VIN(1V/div) (1V/DIV) VIN VB (1V/DIV) VB (1V/div) OUT (2V/DIV) OUT (2V/div) IILIM (1V/div) LIM (2V/DIV) OUT (1V/DIV) OUT (1V/div) WRN (5V/DIV) WRN (5V/div) WRN (5V/div) (5V/DIV) Time: WRN TIME: 500μs/div 500µs/DIV FIGURE 6. TRANSIENT WAVEFORMS WHEN INPUT STEPS FROM 0V TO 9V 4 FIGURE 7. BATTERY OVERVOLTAGE PROTECTION. THE IC IS LATCHED OFF AFTER 16 COUNTS OF PROTECTION. VB VOLTAGE VARIES BETWEEN 4.3V TO 4.5V FN6399.0 March 21, 2007 ISL9212B Typical Operating Performance The test conditions for the Typical Operating Performance are: VIN = 5V, TA = +25°C, RILIM = 25.5kΩ, RVB = 200kΩ, Unless Otherwise Noted. (Continued) TIME: 200ms/DIV Time: 200ms/div TIME: 10ms/DIV Time: 10ms/div VIN (1V/DIV) VIN (1V/div) V VIN (1V/div) IN (1V/DIV) OUT (1V/DIV) OUT (1V/div) LoadCURRENT Current LOAD 500mA/DIV (500mA/div) LoadCURRENT Current LOAD 500mA/DIV (500mA/div) OUT (1V/DIV) OUT (1V/div) WRN (5V/DIV) WRN (5V/div) WRN (5V/DIV) WRN (5V/div) FIGURE 8. POWER-UP WAVEFORMS WHEN OUTPUT IS SHORT-CIRCUITED FIGURE 9. ZOOMED-IN VIEW OF FIGURE 8 (BLUE: LOAD CURRENT; PINK: OUT PIN VOLTAGE) 1200 1000 6.5V/ENABLED 1000 800 800 CURRENT (µA) INPUT BIAS CURRENT (µA) 900 ENABLED 600 400 DISABLED 700 600 30V/ENABLED 500 400 300 200 200 4.3V/ENABLED 5V/ENABLED 30V/DISABLED 6.5V/DISABLED 5V/DISABLED 4.3V/DISABLED 100 0 0 5 10 15 20 25 30 0 -50 35 -20 FIGURE 10. INPUT BIAS CURRENT vs INPUT VOLTAGE WHEN ENABLED AND DISABLED 40 70 100 130 FIGURE 11. INPUT BIAS CURRENT AT DIFFERENT INPUT VOLTAGES WHEN ENABLED AND DISABLED 6.95 2.60 2.58 6.90 RISING THRESHOLD RISING THRESHOLD 2.56 6.85 VOVP (V) VPOR (V) 10 TEMPERATURE (°C) INPUT VOLTAGE (V) 2.54 2.52 6.80 6.75 2.50 FALLING THRESHOLD 2.46 -50 FALLING THRESHOLD 6.70 2.48 -20 10 40 70 100 TEMPERATURE (°C) FIGURE 12. VPOR vs TEMPERATURE 5 130 6.65 -50 -20 10 40 70 100 130 TEMPERATURE (°C) FIGURE 13. INPUT OVERVOLTAGE PROTECTION THRESHOLDS vs TEMPERATURE FN6399.0 March 21, 2007 ISL9212B Typical Operating Performance The test conditions for the Typical Operating Performance are: VIN = 5V, TA = +25°C, RILIM = 25.5kΩ, RVB = 200kΩ, Unless Otherwise Noted. (Continued) 1050 1040 200 CURRENT LIMIT = 1A 195 190 1030 185 1010 BTOCP (µs) IOCP (mA) 1020 6.5V 5V 1000 990 175 170 165 980 160 3V 4.3V 970 960 -50 180 -20 155 10 40 70 100 150 -50 130 -20 TEMPERATURE (°C) FIGURE 14. OVERCURRENT PROTECTION THRESHOLDS vs TEMPERATURE AT VARIOUS INPUT VOLTAGES 70 100 130 4.380 4.370 510 RISING MAX 4.3V 4.360 505 6.5V 4.350 500 4.340 495 VB IOCP (mA) 40 FIGURE 15. OVERCURRENT PROTECTION BLANKING TIME vs TEMPERATURE 515 490 4.330 4.320 3V 485 4.310 480 FALLING MIN 4.300 475 4.290 5V 4.280 -60 -40 -20 470 -50 -20 10 40 70 100 130 FIGURE 16. OVERCURRENT PROTECTION THRESHOLDS vs TEMPERATURE AT VARIOUS INPUT VOLTAGES 20 40 60 80 100 120 140 FIGURE 17. BATTERY VOLTAGE OVP THRESHOLDS vs TEMPERATURE AT VARIOUS INPUT VOLTAGES 3.0 200 VB PIN LEAKAGE CURRENT (nA) 195 190 185 180 175 170 165 160 155 150 -50 0 TEMPERATURE (°C) TEMPERATURE (°C) BTBOVP (µs) 10 TEMPERATURE (°C) -20 10 40 70 100 TEMPERATURE (°C) FIGURE 18. BATTERY OVP BLANKING TIME 6 130 TESTED AT 5V 2.5 2.0 1.5 1.0 0.5 0 -50 -20 10 40 70 100 130 TEMPERATURE (°C) FIGURE 19. VB PIN LEAKAGE CURRENT vs TEMPERATURE FN6399.0 March 21, 2007 ISL9212B Typical Operating Performance The test conditions for the Typical Operating Performance are: VIN = 5V, TA = +25°C, RILIM = 25.5kΩ, RVB = 200kΩ, Unless Otherwise Noted. (Continued) 2.0 EN PIN INTERNAL PULL-DOWN (kΩ) 250 1.8 EN THRESHOLD (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -20 10 40 70 100 240 230 220 210 200 190 180 170 160 150 130 -50 -20 TEMPERATURE (°C) 10 40 70 100 130 TEMPERATURE (°C) FIGURE 20. EN INPUT THRESHOLD vs TEMPERATURE FIGURE 21. EN PIN INTERNAL PULL-DOWN RESISTANCE 0.35 0.30 rDS(ON) (Ω) 0.25 0.20 0.15 0.10 0.05 FROM TOP TO BOTTOM VIN AND ILOAD ARE: 3V/1.5A, 3V/0.5A, 4.6V/1.5A, 4.6V/0.5A, 5V/1.5A, 5V/0.5A, 6.5V/1.5A, AND 6.5V/0.5A 0 -50 -20 10 40 70 TEMPERATURE (°C) 100 130 FIGURE 22. ON-RESISTANCE vs TEMPERATURE AT DIFFERENT INPUT VOLTAGES AND LOAD CURRENTS Theory of Operation Power-Up The ISL9212B is an integrated circuit (IC) optimized to provide a redundant safety protection to a Li-ion battery from charging system failures. The IC monitors the input voltage, the battery voltage and the charge current. When any of the above three parameters exceeds its limit, the IC turns off an internal P-Channel MOSFET to remove the power from the charging system. In addition to the above protected parameters, the IC also monitors its own internal temperature and turns off the P-Channel MOSFET when the temperature exceeds +140°C. Together with the battery charger IC and the protection module in a battery pack, the charging system has triple-level protection from overcharging the Li-ion battery and is two-fault tolerant. The ISL9212B protects up to 30V input voltage. The ISL9212B has a power-on reset (POR) threshold of 2.6V with a built-in hysteresis of 100mV. Before the input voltage reaches the POR threshold, the internal power PFET is off. Approximately 10ms after the input voltage exceeds the POR threshold, the IC resets itself and begins the softstart. The 10ms delay allows any transients at the input during a hot insertion of the power supply to settle down before the IC starts to operate. The soft-start slowly turns on the power PFET to reduce the inrush current as well as the input voltage drop during the transition. The power-up behavior is illustrated in Figure 2. 7 Input Overvoltage Protection (OVP) The input voltage is monitored by the comparator CP1 in the Block Diagram (Figure 1). CP1 has an accurate reference of 1.2V from the bandgap reference. The OVP threshold is set by the resistive divider consisting of R1 and R2. The protection threshold is set to 6.8V. When the input voltage FN6399.0 March 21, 2007 ISL9212B exceeds the threshold, the CP1 outputs a logic signal to turn off the power PFET within 1µs (see Figure 3) to prevent the high input voltage from damaging the electronics in the handheld system. The hysteresis for the input OVP threshold is given in “Electrical Specifications” on page 2. When the input overvoltage condition is removed, the ISL9212B re-enables the output by running through the softstart, as shown in Figure 5. Because of the 10ms second delay before the soft-start, the output is never enabled if the input rises above the OVP threshold quickly, as shown in Figure 6. turned off permanently, unless the input power is recycled or the enable pin is toggled. Figure 8 and Figure 9 illustrate the waveforms during the power-up when the output is short-circuited to ground. Internal Over-Temperature Protection The ISL9212B monitors its own internal temperature to prevent thermal failures. When the internal temperature reaches +140°C, the IC turns off the P-Channel power MOSFET. The IC does not resume operation until the internal temperature drops below +90°C. Battery Overvoltage Protection External Enable Control The battery voltage OVP is realized with the VB pin. The comparator CP3, as shown in Figure 1, monitors the VB pin and issues an overvoltage signal when the battery voltage exceeds the 4.34V battery OVP threshold. The threshold has 30mV built-in hysteresis. The comparator CP3 has a built-in 180µs blanking time to prevent any transient voltage from triggering the OVP. If the OVP situation still exists after the blanking time, the power PFET is turned off. The control logic contains a 4-bit binary counter that if the battery overvoltage event occurs 16 times, the power PFET is turned off permanently, as shown in Figure 7. Recycling the input power or toggling the enable (EN) input will reset the counter and restart the ISL9212B. The ISL9212B offers an enable (EN) input. When the EN pin is pulled to logic HIGH, the protection IC is shut down. The internal control circuit as well as the power PFET are turned off. Both 4-bit binary counters for the battery OVP and the OCP are reset to zero when the IC is re-enabled. The EN pin has an internal 200kΩ pull-down resistor. Leaving the EN pin floating or driving it to below 0.4V enables the IC. The resistor between the VB pin and the battery, RVB, (as shown in the “Typical Application Circuit” on page 1) is an important component. This resistor provides a current limit in case the VB pin is shorted to the input voltage under a failure mode. The VB pin leakage current under normal operation is negligible to allow a resistance of 200kΩ to 1MΩ be used. Applications Information Overcurrent Protection (OCP) The current in the power PFET is limited to prevent charging the battery with an excessive current. The current is sensed using the voltage drop across the power FET after the FET is turned on. The reference of the OCP is generated using a sensing FET Q2, as shown in Figure 1. The current in the sensing FET is forced to the value programmed by the ILIM pin. The size of the power FET Q1 is 31,250 times the size of the sensing FET. Therefore, when the current in the power FET is 31,250 times the current in the sensing FET, the drain voltage of the power FET falls below that of the sensing FET. The comparator CP2 then outputs a signal to turn off the power FET. The OCP threshold can be calculated using Equation 1: 0.8V 25000 I LIM = --------------- ⋅ 31250 = ---------------R ILIM R ILIM (EQ. 1) where the 0.8V is the regulated voltage at the ILIM pin. The OCP comparator CP2 has a built-in 170µs delay to prevent false triggering by transient signals. The OCP function also has a 4-bit binary counter that accumulates during an OCP event. When the total count reaches 16, the power PFET is 8 Warning Indication Output The WRN pin is an open-drain output that indicates a LOW signal when any of the three protection events happens. This allows the microprocessor to give an indication to the user to further enhance the safety of the charging system. The ISL9212B is designed to meet the “Lithium-Safe” criteria when operating together with the ISL6292 family Li-ion battery chargers. The “Lithium-Safe” criteria requires the charger output to fall within the green region shown in Figure 23 under normal operating conditions and NOT to fall in the red region when there is a single fault in the charging system. Taking into account the safety circuit in a Li-ion battery pack, the charging system is allowed to have two faults without creating hazardous conditions for the battery cell. The output of any ISL6292 family chargers, such as the ISL6292C, has a typical I-V curve shown with the blue lines under normal operation, which is within the green region. The function of the ISL9212B is to add an redundant protection layer such that, under any single fault condition, the charging system output does not exceed the I-V limits shown with the red lines. As a result, the charging system adopting the ISL9212B and the ISL6292C chip set can easily pass the “Lithium-Safe” criteria test procedures. The ISL9212B is a simple device that requires only three external components, in addition to the ISL6292 charger circuit, to meet the “Lithium-Safe” criteria, as shown in the “Typical Application Circuit” on page 1. The selection of the current limit resistor RILIM is given in “Overcurrent Protection (OCP)” on page 8. FN6399.0 March 21, 2007 ISL9212B RVB Selection The RVB prevents a large current from the VB pin to the battery terminal, in case the ISL9212B fails. The recommended value should be between 200kΩ to 1MΩ. With 200kΩ resistance, the worst case current flowing from the VB pin to the charger output is: ( 30V – 4.2V ) ⁄ ( 200kΩ ) = 130μA The error of the battery OVP threshold is the original accuracy at the VB pin, (given in “Electrical Specifications” on page 2) plus the voltage built across the RVB by the VB pin leakage current. The VB pin leakage current is less than 20nA, as given in “Electrical Specifications” on page 2. With the 200kΩ resistor, the worst-case additional error is 4mV and with a 1MΩ resistor, the worst-case additional error is 20mV. 1000 RPU ISL6292C LIMITS RWRN EN Q5 REN R5 FIGURE 24. DIGITAL SIGNAL INTERFACE BETWEEN ISL9212B AND MCU Capacitor Selection The input capacitor (C1 in the “Typical Application Circuit” on page 1) is for decoupling. Higher value reduces the voltage drop or the over shoot during transients. C1 1 WRN Q4 Two scenarios can cause the input voltage over shoot. The first one is when the AC adapter is inserted live (hot insertion) and the second one is when the current in the power PFET of the ISL9212B has a step-down change. Figure 25 shows an equivalent circuit for the ISL9212B input. The cable between the AC/DC converter output and the handheld system input has a parasitic inductor. The parasitic resistor is the lumped sum of various components, such as the cable, the adapter output capacitor ESR, the connector contact resistance, and so on. ISL9212 LIMITS 0 MCU VIO (EQ. 2) assuming the VB pin voltage is 30V under a failure mode and the battery voltage is 4.2V. Such a small current can be easily absorbed by the bias current of other components in the handheld system. Increasing the RVB value reduces the worst case current, but at the same time increases the error for the 4.4V battery OVP threshold. CHARGE CURRENT (mA) ISL9212 2 3 4 5 L R C2 6 BATTERY VOLTAGE (V) AC/DC ISL9212 FIGURE 23. LITHIUM-SAFE OPERATING REGIONS ADAPTER Interfacing to MCU CABLE HANDHELD SYSTEM FIGURE 25. EQUIVALENT CIRCUIT FOR THE ISL9212B INPUT The ISL9212B has the enable (EN) and the warning (WRN) digital signals that can be interfaced to a microcontroller unit (MCU). Both signals can be left floating if not used. When interfacing to an MCU, it is highly recommended to insert a resistor between the ISL9212B signal pin and the MCU GPIO pin, as shown in Figure 24. The resistor creates an isolation to limit the current, in case a high voltage shows up at the ISL9212B pins under a failure mode. The recommended resistance ranges from 10kΩ to 100kΩ. The selection of the REN is dependent on the IO voltage (VIO) of the MCU. REN should be selected so that the ISL9212B EN pin voltage is above the disable threshold when the GPIO output of the MCU is high. 9 During the load current step-down transient, the energy stored in the parasitic inductor is used to charge the input decoupling capacitor, C2. The ISL9212B is designed to turn off the power PFET slowly during the OCP, the battery OVP event, and when the device is disabled via the EN pin. Because of such design, the input over shoot during those events is not significant. During an input OVP, however, the PFET is turned in less than 1µs and can lead to significant over shoot. Higher capacitance reduces this type of over shoot. The over shoot caused by a hot insertion is not very dependent on the decoupling capacitance value, especially when ceramic type capacitors are used for decoupling. In theory, the over shoot can rise up to twice of the DC output FN6399.0 March 21, 2007 ISL9212B voltage of the AC adapter. The actual peak voltage is dependent on the damping factor that is mainly determined by the parasitic resistance (R in Figure 25). In practice, the input decoupling capacitor is recommended to use a 16V X5R dielectric ceramic capacitor with a value between 0.1µF to 1µF. The output of the ISL9212B and the input of the charging circuit typically share one decoupling capacitor. The selection of that capacitor is mainly determined by the requirement of the charging circuit. When using the ISL6292 family chargers, a 1µF, 6.3V, X5R capacitor is recommended. 10 Layout Recommendation The ISL9212B uses a thermally enhanced DFN package. The exposed pad under the package should be connected to the ground plane electrically as well as thermally. A grid of 1.0mm to 1.2mm pitch thermal vias in two rows and 4 to 5 vias per row is recommended (refer to the ISL9212BEVAL1 evaluation board layout). The vias should be about 0.3mm to 0.33mm in diameter. Use some copper on the component layer if possible to further improve the thermal performance but it is not mandatory. Since the ISL9212B is a protection device, the layout should also pay attention to the spacing between tracks. When the distance between the edges of two tracks is less than 0.76mm, an FMEA (failure mechanism and effect analysis) should be performed to ensure that a short between those two tracks does not lead to the charger output exceeding the “Lithium-Safe” region limits. Intersil will have the FMEA document for the solution using the ISL9212B and the ISL6292C chip set but the layout FMEA should be added as part of the analysis. FN6399.0 March 21, 2007 ISL9212B Thin Dual Flat No-Lead Plastic Package (TDFN) L12.4x3A 2X 12 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-229-WGED-4 ISSUE C) 0.15 C A A D 2X MILLIMETERS 0.15 C B SYMBOL E MIN A 0.70 A1 - A3 6 INDEX AREA b D2 B 0.18 E2 A SIDE VIEW C SEATING PLANE 6 INDEX AREA C 0.08 C A3 7 8 - 0.23 0.30 5,8 3.15 3.30 3.40 7,8 3.00 BSC 1.55 e 1.70 1.80 7,8 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 12 2 Nd 6 3 2. N is the number of terminals. 2 3. Nd refers to the number of terminals on D. NX k 4. All dimensions are in millimeters. Angles are in degrees. E2 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. E2/2 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX L N N-1 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. NX b e 5 (Nd-1)Xe REF. BOTTOM VIEW NX (b) 0.05 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. (DATUM A) 8 - NOTES: D2/2 1 - Rev. 0 1/06 D2 (DATUM B) 0.10 NOTES 0.80 4.00 BSC E // MAX 0.75 0.20 REF D TOP VIEW NOMINAL 0.10 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. M C A B CL (A1) L 5 e SECTION "C-C" TERMINAL TIP FOR EVEN TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6399.0 March 21, 2007