Intersil ISLA118P50IRZ 8-bit, 500msps a/d converter Datasheet

ISLA118P50
Features
The ISLA118P50 is a low-power, high-performance,
500MSPS analog-to-digital converter designed with
Intersil’s proprietary FemtoCharge® technology on a
standard CMOS process. The ISLA118P50 is part of a
pin-compatible portfolio of 8, 10 and 12-bit A/Ds. This
device an upgrade of the KAD551XP-50 product family
and is pin similar.
• 1.15GHz Analog Input Bandwidth
The device utilizes two time-interleaved 250MSPS unit
A/Ds to achieve the ultimate sample rate of 500MSPS. A
single 500MHz conversion clock is presented to the
converter, and all interleave clocking is managed
internally. The proprietary Intersil Interleave Engine
(I2E) performs automatic fine correction of offset, gain,
and sample time skew mismatches between the unit
A/Ds to optimize performance. No external interleaving
algorithm is required.
• Over-Range Indicator
A serial peripheral interface (SPI) port allows for
extensive configurability of the A/D. The SPI also controls
the interleave correction circuitry, allowing the system to
issue continuous calibration commands as well as
configure many dynamic parameters.
Applications
• 90fs Clock Jitter
• Automatic Fine Interleave Correction Calibration
• Multiple Chip Time Alignment Support via the
Synchronous Clock Divider Reset
• Programmable Gain, Offset and Skew control
• Clock Phase Selection
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data
Format
• DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Test Patterns and Internal
Temperature Sensor
• Radar and Electronic/Signal Intelligence
• Broadband Communications
• High-Performance Data Acquisition
Digital output data is presented in selectable LVDS or
CMOS formats. The ISLA118P50 is available in a
72-contact QFN package with an exposed paddle.
Performance is specified over the full industrial
temperature range (-40°C to +85°C).
Block Diagram
CLKOUTP
CLOCK
MANAGEMENT
CLKN
RESOLUTION
SPEED
(MSPS)
ISLA112P50
12
500
ISLA110P50
10
500
ISLA118P50
8
500
MODEL
OVDD
CLKDIVRSTP
AVDD
CLKP
CLKDIVRSTN
Pin-Compatible Family
CLKOUTN
Key Specifications
8 -BIT
250MSPS
ADC
SHA
D[7:0]P
D[7:0]N
VREF
VINP
ORP
DIGITAL
Gain/ Offset/ Skew
Adjustments
VINN
I2E
• SNR = 49.9dBFS for fIN = 190MHz (-1dBFS)
• SFDR = 68dBc for fIN = 190MHz (-1dBFS)
• Total Power Consumption = 428mW
ORN
ERROR
CORRECTION
OUTFMT
OUTMODE
VCM
8 -BIT
250MSPS
ADC
SHA
VREF
June 4, 2010
FN7565.1
1
OGND
CSB
SCLK
SDIO
SDO
RESETN
SPI
CONTROL
AGND
NAPSLP
1.25V +
–
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISLA118P50
8-Bit, 500MSPS A/D Converter
ISLA118P50
Table of Contents
Block Diagram ................................................... 1
Pin-Compatible Family....................................... 1
FS/4 Filter .................................................... 19
Nyquist Zones ............................................... 19
Configurability and Communication .................. 20
Key Specifications ............................................. 1
Clock Divider Synchronous Reset .................... 20
Pin Descriptions ................................................ 4
Serial Peripheral Interface .............................. 22
Absolute Maximum Ratings .............................. 5
SPI Physical Interface ....................................
SPI Configuration ..........................................
Device Information ........................................
Indexed Device Configuration/Control ..............
AC RMS Power Threshold ................................
Address 0x60-0x64: I2E initialization ...............
Device Test...................................................
SPI Memory Map ...........................................
Thermal Information ........................................ 5
Recommended Operating Conditions ................ 5
Digital Specifications ........................................ 8
Timing Diagrams ............................................... 8
Switching Specifications .................................... 9
Typical Performance Curves ............................ 10
Theory of Operation......................................... 14
Functional Description.....................................
Power-On Calibration ......................................
User Initiated Reset........................................
Analog Input .................................................
Clock Input ...................................................
Jitter ............................................................
Voltage Reference ..........................................
Digital Outputs ..............................................
Over Range Indicator......................................
Power Dissipation...........................................
Nap/Sleep .....................................................
Data Format ..................................................
14
14
15
15
16
16
17
17
17
17
17
18
I2E Requirements and Restrictions ................. 19
Overview........................................................ 19
Active Run State ............................................ 19
Power Meter .................................................. 19
2
22
23
23
23
25
26
27
28
Equivalent Circuits .......................................... 30
A/D Evaluation Platform ................................. 32
Layout Considerations..................................... 32
Split Ground and Power Planes ........................
Clock Input Considerations .............................
Exposed Paddle .............................................
Bypass and Filtering.......................................
LVDS Outputs ...............................................
LVCMOS Outputs ...........................................
Unused Inputs ..............................................
32
32
32
32
32
32
32
Definitions....................................................... 32
Revision History.................................................. 34
Products.......................................................... 34
Package Outline Drawing ............................... 35
FN7565.1
June 4, 2010
ISLA118P50
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
ISLA118P50IRZ
SPEED
(MSPS)
TEMP. RANGE
(°C)
500
-40 to +85
ISLA118P50 IRZ
PACKAGE
(Pb-Free)
72 Ld QFN
PKG.
DWG. #
L72.10x10C
NOTE:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA118P50. For more information on MSL please
see techbrief TB363.
Pin Configuration
AVSS
AVDD
OUTFMT
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
D7P
D7N
D6P
D6N
D5P
D5N
OVDD
OVSS
ISLA118P50
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD
1
54 D4P
DNC
2
53 D4N
RES
3
52 D3P
RES
4
51 D3N
DNC
5
50 D2P
AVDD
6
49 D2N
AVSS
7
48 CLKOUTP
AVSS
8
47 CLKOUTN
VINN
9
46 RLVDS
PD
VINP 10
AVSS 11
r
45 OVSS
44 D1P
on
i
t
ma
r
fo
n
I
al
i
t
en
d
i
nf
AVDD 12
DNC 13
DNC 14
VCM 15
DNC 16
DNC 17
43 D1N
42 D0P
41 D0N
40 DNC
39 DNC
38 DNC
CONNECT THERMAL PAD TO AVSS
CLKDIVRSTP
CLKDIVRSTN
31
32
33
34
35
36
OVDD
OVDD
30
DNC
29
DNC
28
DNC
27
DNC
26
DNC
25
37 DNC
DNC
24
OVSS
CLKN
23
RESETN
CLKP
22
AVDD
21
NAPSLP
20
OUTMODE
19
AVDD
DNC 18
FIGURE 1. PIN CONFIGURATION
3
FN7565.1
June 4, 2010
ISLA118P50
Pin Descriptions
PIN NUMBER
LVDS [LVCMOS]
NAME
1, 6, 12, 19, 24, 71
AVDD
2, 5, 13, 14, 16, 17, 18,
30, 31, 32, 33, 34, 35,
37, 38, 39, 40
DNC
Do Not Connect
3, 4
RES
Reserved. (4.7kΩ pull-up to OVDD is required for each of these pins)
7, 8, 11, 72
AVSS
9, 10
VINN, VINP
15
VCM
20, 21
CLKP, CLKN
22
OUTMODE
23
NAPSLP
Tri-Level Power Control (Nap, Sleep modes)
25
RESETN
Power On Reset (Active Low)
26, 45, 55, 65
OVSS
Output Ground
27, 36, 56
OVDD
1.8V Output Supply
28, 29
CLKDIVRSTP,
CLKDIVRSTN
41, 42
D0N, D0P [NC, D0]
LVDS Bit 0 Output Complement, True [NC, LVCMOS Bit 0]
43, 44
D1N, D1P [NC, D1]
LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1]
46
RLVDS
47, 48
CLKOUTN, CLKOUTP
[NC, CLKOUT]
LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT]
49, 50
D2N, D2P [NC, D2]
LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2]
51, 52
D3N, D3P [NC, D3]
LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3]
53, 54
D4N, D4P [NC, D4]
LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4]
57, 58
D5N, D5P [NC, D5]
LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5]
59, 60
D6N, D6P [NC, D6]
LVDS Bit 6 Output Complement, True [NC, LVCMOS Bit 6]
61, 62
D7N, D7P [NC, D7]
LVDS Bit 7 (MSB) Output Complement, True [NC, LVCMOS Bit 7]
63, 64
ORN, ORP [NC, OR]
LVDS Over Range Complement, True [NC, LVCMOS Over Range]
66
SDO
SPI Serial Data Output (4.7kΩ pull-up to OVDD is required)
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
70
OUTFMT
PD
AVSS
LVDS [LVCMOS] FUNCTION
1.8V Analog Supply
Analog Ground
Analog Input Negative, Positive
Common Mode Output
Clock Input True, Complement
Tri-Level Output Mode (LVDS, LVCMOS)
Sample Clock Synchronous Divider Reset Positive, Negative
LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1% resistor)
Tri-Level Output Data Format (Two’s Comp., Gray Code, Offset Binary)
Exposed Paddle - Analog Ground
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection)
4
FN7565.1
June 4, 2010
ISLA118P50
Absolute Maximum Ratings
AVDD to AVSS . . . . . .
OVDD to OVSS. . . . . .
AVSS to OVSS . . . . . .
Analog Inputs to AVSS
Clock Inputs to AVSS .
Logic Input to AVSS . .
Logic Inputs to OVSS .
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Thermal Information
. . . . . . -0.4V to
. . . . . . -0.4V to
. . . . . . -0.3V to
-0.4V to AVDD +
-0.4V to AVDD +
-0.4V to OVDD +
-0.4V to OVDD +
Thermal Resistance (Typical)
2.1V
2.1V
0.3V
0.3V
0.3V
0.3V
0.3V
θJA (°C/W) θJC (°C/W)
72 Ld QFN (Notes 3, 4, 5) . . . . . . .
23
0.75
Storage Temperature . . . . . . . . . . . . . . . . -65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Temperature . . . . . . . . . . . . . . . -40°C to +85°C
NOTES:
3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379 for details.
4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
5. For solder stencil layout and reflow guidelines, please see Tech Brief TB389.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS,
FIN = 105MHz, fSAMPLE = 500MSPS, after completion of I2E calibration.
ISLA118P50
(Note 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.41
1.45
1.52
VP-P
DC SPECIFICATIONS (Note 6)
Analog Input
Full-Scale Analog Input Range
VFS
Differential
Input Resistance
RIN
Differential
500
Ω
Input Capacitance
CIN
Differential
1.9
pF
Full Temp
325
ppm/°C
Full Scale Range Temp. Drift
AVTC
Input Offset Voltage
VOS
Gain Error
-10
EG
Common-Mode Output Voltage
±2.0
10
±2.0
VCM
435
535
mV
%
635
mV
Clock Inputs
Inputs Common Mode Voltage
0.9
V
0.2
1.8
V
AVDD
1.7
1.8
1.8V Digital Supply Voltage
OVDD
1.7
1.8V Analog Supply Current
IAVDD
1.8V Digital Supply Current (Note 7)
IOVDD
CLKP,CLKN Input Swing
Power Requirements
1.8V Analog Supply Voltage
Power Supply Rejection Ratio
PSRR
3mA LVDS, I2E powered down,
FS/4 Filter powered down
1.9
V
1.8
1.9
V
173
186
mA
72
79
mA
3mA LVDS, I2E On, FS/4 Filter On
117
mA
30MHz, 200mVP-P
-36
dB
2mA LVDS, I2E powered down,
Fs/4 Filter powered down
428
mW
3mA LVDS, I2E powered down,
FS/4 Filter powered down
441
3mA LVDS, I2E On, FS/4 Filter
powered down
508
mW
3mA LVDS, I2E On, FS/4 Filter On
522
mW
Total Power Dissipation
Normal Mode
PD
5
477
mW
FN7565.1
June 4, 2010
ISLA118P50
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS,
FIN = 105MHz, fSAMPLE = 500MSPS, after completion of I2E calibration. (Continued)
ISLA118P50
(Note 6)
TYP
MAX
UNITS
Nap Mode
PD
164
179
mW
Sleep Mode
PD
28
34
mW
PARAMETER
SYMBOL
CONDITIONS
MIN
Nap Mode Wakeup Time (Note 8)
Sample Clock Running
2.75
µs
Sleep Mode Wakeup Time (Note 8)
Sample Clock Running
1
ms
AC SPECIFICATIONS (Note 9)
Differential Nonlinearity
DNL
-0.1
±0.02
0.1
LSB
Integral Nonlinearity
INL
-0.15
±0.03
0.15
LSB
Minimum Conversion Rate (Note 10)
fS MIN
Maximum Conversion Rate
fS MAX
Signal-to-Noise Ratio (Notes 11, 12)
SNR
80
500
fIN = 10MHz
fIN = 105MHz
Signal-to-Noise and Distortion
(Notes 11, 12)
Effective Number of Bits (Notes 11, 12)
SINAD
49.9
dBFS
49.9
dBFS
fIN = 364MHz
49.8
dBFS
fIN = 495MHz
49.8
dBFS
fIN = 605MHz
49.8
dBFS
fIN = 995MHz
49.6
dBFS
fIN = 10MHz
49.9
dBFS
49.9
dBFS
fIN = 190MHz
49.9
dBFS
fIN = 364MHz
49.8
dBFS
fIN = 495MHz
49.7
dBFS
fIN = 605MHz
49.5
dBFS
fIN = 995MHz
49.1
dBFS
Intermodulation Distortion
SFDR
7.99
Bits
7.99
Bits
fIN = 190MHz
7.99
Bits
fIN = 364MHz
7.97
Bits
fIN = 495MHz
7.97
Bits
fIN = 605MHz
7.93
Bits
fIN = 995MHz
7.36
Bits
68
dBc
7.90
fIN = 10MHz
fIN = 105MHz
IMD
49.3
fIN = 10MHz
fIN = 105MHz
Spurious-Free Dynamic Range
(Notes 11, 12)
68
dBc
fIN = 190MHz
63.5
68
dBc
fIN = 364MHz
67
dBc
fIN = 495MHz
67
dBc
fIN = 605MHz
63
dBc
fIN = 995MHz
48
dBc
fIN = 70MHz
80
dBc
fIN = 170MHz
80
dBc
Word Error Rate
WER
10-12
Full Power Bandwidth
FPBW
1.15
6
dBFS
fIN = 190MHz
fIN = 105MHz
ENOB
49.9
49.4
MSPS
MSPS
GHz
FN7565.1
June 4, 2010
ISLA118P50
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS,
FIN = 105MHz, fSAMPLE = 500MSPS, after completion of I2E calibration. (Continued)
ISLA118P50
(Note 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I2E Specifications
Offset mismatch-induced spurious
power
I2E Settling Times
Minimum Duration of Valid Analog
Input (Note 13)
Largest Interleave Spur
Total Interleave Spurious Power
Sample Time Mismatch Between Unit
A/Ds
No I2E Calibration performed
-70
Active Run state enabled
-81
dBFS
dBFS
I2Epost_t
Calibration settling time for Active
Run state
1000
ms
tTE
Allow one I2E iteration of Offset,
Gain and Phase correction
500
µs
fIN = 10MHz to 240MHz, Active
Run State enabled, in Track Mode
-94
dBc
fIN = 10MHz to 240MHz, Active
Run State enabled and previously
settled, in Hold Mode
-82
dBc
fIN = 260MHz to 490MHz, Active
Run State enabled, in Track Mode
-89
dBc
fIN = 260MHz to 490MHz, Active
Run State enabled and previously
settled, in Hold Mode
-79
dBc
Active Run State enabled, in Track
Mode, fIN is a broadband signal in
the 1st Nyquist zone
-90
dBc
Active Run State enabled, in Track
Mode, fIN is a broadband signal in
the 2nd Nyquist zone
-85
dBc
Active Run State enabled, in Track
Mode
30
fs
0.01
%
1
mV
Gain Mismatch Between Unit A/Ds
Offset Mismatch Between Unit A/Ds
NOTES:
6. Unless otherwise noted, parameters with Min and/or MAX limits are 100% production tested at their worst case temperature
extreme (+85°C).
7. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load
on each digital output.
8. See “Nap/Sleep” for more detail.
9. AC Specifications apply after internal calibration of the A/D is invoked at the given sample rate and temperature. Refer to
“Power-On Calibration” and “User Initiated Reset” for more detail.
10. The DLL Range setting must be changed for low speed operation.
11. The offset mismatch-induced spur energy, which occurs at fSAMPLE/2, is not included in any specification unless otherwise
noted.
12. This specification only applies when I2E is in Active Run state, and in Track Mode.
13. Limits are specified over the full operating temperature and voltage range and are established by characterization and not
production tested.
7
FN7565.1
June 4, 2010
ISLA118P50
Digital Specifications
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0
1
10
µA
-25
-12
-5
µA
CMOS INPUTS
Input Current High
(SDIO,RESETN,CSB,SCLK)
IIH
VIN = 1.8V
Input Current Low
(SDIO,RESETN,CSB,SCLK)
IIL
VIN = 0V
Input Voltage High
(SDIO, RESETN,CSB,SCLK)
VIH
Input Voltage Low
(SDIO, RESETN,CSB,SCLK)
VIL
Input Current High
(OUTMODE, NAPSLP,
OUTFMT) (Note 14)
IIH
15
Input Current Low
(OUTMODE, NAPSLP,
OUTFMT)
IIL
-40
Input Capacitance
CDI
1.17
V
0.63
V
25
40
µA
25
-15
µA
3
pF
LVDS INPUTS (ClkdivrstP, ClkdivrstN)
Input Common Mode Range
VICM
825
1575
mV
Input Differential Swing
(peak to peak, single ended)
VID
250
450
mV
Input Pull-up and Pull-down
Resistance
RIpu
1
MΩ
620
mVP-P
LVDS OUTPUTS
VT
3mA Mode
VOS_LVDS
3mA Mode
Differential Output Voltage
(Note 15)
Output Offset Voltage
950
965
980
mV
Output Rise Time
tR
625
ps
Output Fall Time
tF
625
ps
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
OVDD - 0.3
OVDD - 0.1
V
0.1
0.3
V
Output Rise Time
tR
2
ns
Output Fall Time
tF
2
ns
Timing Diagrams
SAMPLE N
SAMPLE N
INP
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
tDC
D[7:0]P
D[7:0]N
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tPD
DATA
N-L
DATA
N-L+1
DATA
N-L+2
FIGURE 2. LVDS TIMING DIAGRAM
8
DATA
N
D[7:0]P
D[7:0]N
tPD
DATA
N-L
DATA
N-L+1
DATA
N-L+2
DATA
N
FIGURE 3. CMOS TIMING DIAGRAM
FN7565.1
June 4, 2010
ISLA118P50
Switching Specifications
PARAMETER
CONDITION
SYMBOL
MIN
TYP
MAX
UNITS
A/D OUTPUT
Aperture Delay
tA
RMS Aperture Jitter
375
jA
Input Clock to Output Clock
Propagation Delay
ps
90
fs
AVDD, OVDD = 1.8V, TA = 25°C
tCPD
2.6
2.9
3.3
ns
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
tCPD
2.0
2.6
3.6
ns
dtCPD
-450
450
ps
tPD
1.74
2.6
3.83
ns
tDC
-250
0
250
ps
Synchronous Clock Divider Reset
Setup Time (with respect to the
positive edge of CLKP)
tRSTS
300
75
ps
Synchronous Clock Divider Reset Hold
Time (with respect to the positive
edge of CLKP)
tRSTH
450
150
ps
Relative Input Clock to Output Clock
AVDD, OVDD = 1.7V to 1.9V,
Propagation Delay Matching (Note 16) TA = -40°C to +85°C
Input Clock to Data Propagation
Delay, LVDS Mode
Output Clock to Data Propagation
Delay (Note 13)
Synchronous Clock Divider Reset
Recovery Time
LVDS or CMOS Mode
DLL recovery time after
Synchronous Reset
Latency (Pipeline Delay) (Note 17)
Overvoltage Recovery
tRSTRT
52
µs
L
17
cycles
tOVR
1
cycles
SPI INTERFACE (Notes 18, 19)
SCLK Period
Write Operation
t
CLK
32
Read Operation
cycles
(Note 18)
tCLK
132
cycles
CSB↓ to SCLK↑ Setup Time
Read or Write
tS
2
cycles
CSB↑ after SCLK↑ Hold Time
Read or Write
tH
11
cycles
Data Valid to SCLK↑ Setup Time
Write
tDSW
2
cycles
Data Valid after SCLK↑ Hold Time
Write
tDHW
8
cycles
Data Valid after SCLK↓ Time
Read
tDVR
Data Invalid after SCLK↑ Time
Read
tDHR
6
cycles
Sleep Mode CSB↓ to SCLK↑ Setup
Time (Note 20)
Read or Write in Sleep Mode
tS
150
µs
33
cycles
NOTES:
14. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to
ground or AVDD depending on desired function.
15. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential
swing.
16. The relative propagation delay is the timing of the output clock of any A/D with respect to the nominal timing of any other
A/D, given that all devices are clocked at the same time and are matched in temperature and voltage. It is specified over the
full operating temperature and voltage range, and is established by characterizaton and not production tested.
17. The pipeline latency of this converter is fixed.
18. SPI Interface timing is directly proportional to the A/D sample period (tSAMPLE).
19. The SPI may operate asynchronously with respect to the A/D sample clock.
20. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal
mode CSB setup time (4ns min).
9
FN7565.1
June 4, 2010
ISLA118P50
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V,
TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS.
-40
HARMONIC MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
70
SFDR
65
60
55
50
SNR
45
40
0M
200M
400M
600M
800M
1G
-50
HD3
-60
HD2
-70
-80
-90
-100
0M
200M
80
-30
SFDR (dBFS)
60
SNR AND SFDR
SNR AND SFDR
800M
1G
-20
70
50
SNR (dBFS)
SFDR (dBc)
30
SNR (dBc)
20
10
-40
-35
HD2 (dBc)
-40
HD3 (dBc)
-50
-60
-70
-80
HD2 (dBFS)
-90
-30
-25
-20
-15
-10
INPUT AMPLITUDE (dBFS)
-5
-100
0
HD3 (dBFS)
-40
-35
-30
-25
-20
-15
-10
INPUT AMPLITUDE (dBFS)
-5
0
FIGURE 7. HD2 AND HD3 vs AIN
FIGURE 6. SNR AND SFDR vs AIN
75
100
SFDR
70
HD3
90
65
HD2
80
60
dBc
SNR (dBFS) AND SFDR (dBc)
600M
FIGURE 5. HD2 AND HD3 vs fIN
FIGURE 4. SNR AND SFDR vs fIN
40
400M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
55
70
60
50
SNR
50
45
40
250
300
350
400
450
SAMPLE RATE (MSPS)
FIGURE 8. SNR AND SFDR vs fSAMPLE
10
500
40
250
300
350
400
450
500
SAMPLE RATE (MSPS)
FIGURE 9. HD2 AND HD3 vs fSAMPLE
FN7565.1
June 4, 2010
ISLA118P50
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V,
TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. (Continued)
550
0.10
0.08
TOTAL POWER (mW)
500
0.06
DNL (LSBs)
0.04
450
400
350
0.02
0
-0.02
-0.04
-0.06
-0.08
300
250
300
350
400
450
-0.1
500
0
50
100
SAMPLE RATE (MHz)
FIGURE 10. POWER vs fSAMPLE IN 3mA LVDS MODE
SNRFS (dBFS) AND SFDR (dBc)
-0.02
-0.04
-0.06
-0.08
50
100
150
200
250
CODE
50
SNR
45
40
300 350 400 450 500 550 600 650 700 750 800
VCM (mV)
FIGURE 13. SNR AND SFDR vs VCM
-10
FIGURE 12. INTEGRAL NONLINEARITY
4M
2M
0
0
127
128
CODE
FIGURE 14. NOISE HISTOGRAM
11
129
-30
-50
0
6M
-70
AMPLITUDE (dBFS)
8M
AIN = -1.0dBFS
SNR = 49.88 dBFS
SFDR = 67.36 dBc
SINAD = 49.85 dBFS
-90
10,005,230
10M
-110
12M
FREQUENCY (MHz)
100
0
55
250
0
60
200
0.02
50
INL (LSBs)
0.04
SFDR
65
150
0.06
NUMBER OF HITS
250
70
0.08
0
200
FIGURE 11. DIFFERENTIAL NONLINEARITY
0.10
-0.10
150
CODE
FIGURE 15. SINGLE-TONE SPECTRUM @ 105MHz
FN7565.1
June 4, 2010
ISLA118P50
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V,
TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. (Continued)
AIN = -1.0dBFS
SNR = 49.89 dBFS
SFDR = 68.06 dBc
SINAD = 49.86 dBFS
-30
-50
-70
-90
-110
-30
-50
-70
-90
-110
0
50
100
AIN = -1.0dBFS
SNR = 49.84 dBFS
SFDR = 67.57 dBc
SINAD = 49.77 dBFS
-10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-10
150
200
250
0
50
FREQUENCY (MHz)
FIGURE 16. SINGLE-TONE SPECTRUM @ 190MHz
AMPLITUDE (dBFS)
-30
150
200
250
-50
-70
-90
FIGURE 17. SINGLE-TONE SPECTRUM @ 495MHz
0
IMD = 80dBc
-10
AMPLITUDE (dBFS)
AIN = -1.0dBFS
SNR = 49.63 dBFS
SFDR = 49.24 dBc
SINAD = 46.76 dBFS
-10
100
FREQUENCY (MHz)
-20
-30
-40
-50
-60
-70
-80
-90
-110
0
50
100
150
200
-100
250
0
50
200
250
FIGURE 19. TWO-TONE SPECTRUM @ 70MHz
(1MHz SPACING)
75
0
SNRFS (dBFS) and SFDR (dBc)
IMD = 80dBc
-10
AMPLITUDE (dBFS)
150
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 18. SINGLE-TONE SPECTRUM @ 995MHz
-20
-30
-40
-50
-60
-70
-80
-90
-100
100
0
50
100
150
200
FREQUENCY (MHz)
FIGURE 20. TWO-TONE SPECTRUM @ 170MHz
(1MHz SPACING)
12
250
SFDR
70
65
60
55
50
SNR
45
40
0
50
100
150
200
250
FREQUENCY (MHz)
FIGURE 21. INPUT FREQUENCY SWEEP WITH I2E
FROZEN, I2E PREVIOUSLY CALIBRATED @
105MHz
FN7565.1
June 4, 2010
ISLA118P50
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V,
TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. (Continued)
75
SNRFS (dBFS) AND SFDR (dBc)
SNRFS (dBFS) AND SFDR (dBc)
80
75
SFDR
70
65
60
55
SNR
50
45
40
250
300
350
400
450
500
70
SFDR
65
60
55
SNR
50
45
40
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
FREQUENCY (MHz)
FIGURE 22. INPUT FREQUENCY SWEEP WITH I2E
FROZEN, I2E PREVIOUSLY CALIBRATED @
330MHz
FIGURE 23. TEMPERATURE SWEEP WITH I2E FROZEN,
I2E PREVIOUSLY CALIBRATED
SNRFS (dBFS) AND SFDR (dBc)
75
SFDR
70
65
60
55
50
SNR
45
40
1.65
1.70
1.75
1.80
1.85
1.90
1.95
SUPPLY VOLTAGE (AVDD)
FIGURE 24. ANALOG SUPPLY VOLTAGE SWEEP WITH I2E FROZEN, I2E PREVIOUSLY CALIBRATED
13
FN7565.1
June 4, 2010
ISLA118P50
Theory of Operation
mismatches create spurs at DC and multiples of
fNYQUIST.
Functional Description
The ISLA118P50 is based upon an 8-bit, 250MSPS A/D
converter core that utilizes a pipelined successive
approximation architecture (Figure 25). The input
voltage is captured by a Sample-Hold Amplifier (SHA)
and converted to a unit of charge. Proprietary
charge-domain techniques are used to successively
compare the input to a series of reference charges.
Decisions made during the successive approximation
operations determine the digital code for each input
value. The converter pipeline requires twelve samples to
produce a result. Digital error correction is also applied,
resulting in a total latency of 17 clock cycles. This is
evident to the user as a latency between the start of a
conversion and the data being available on the digital
outputs.
Power-On Calibration
As mentioned previously, the cores perform a
self-calibration at start-up. An internal power-on-reset
(POR) circuit detects the supply voltage ramps and
initiates the calibration when the analog and digital
supply voltages are above a threshold. The following
conditions must be adhered to for the power-on
calibration to execute successfully:
• A frequency-stable conversion clock must be applied
to the CLKP/CLKN pins
• DNC pins must not be connected
• SDO (pin 66) must be high
• RESETN (pin 25) must begin low
The device contains two core A/D converters with
carefully matched transfer characteristics. The cores are
clocked on alternate clock edges, resulting in a doubling
of the sample rate.
• SPI communications must not be attempted
Time–interleaved A/D systems can exhibit non–ideal
artifacts in the frequency domain if the individual core
A/D characteristics are not well matched. Gain, offset
and timing skew mismatches are of primary concern.
Pins 3, 4, and SDO require an external 4.7kΩ pull-up to
OVDD. If these pins are pulled low externally during
power-up, calibration will not be executed properly.
A user-initiated reset can subsequently be invoked in the
event that the above conditions cannot be met at
power-up.
The Intersil Interleave Engine (I2E) performs automatic
interleave calibration for the offset, gain, and sample
time skew mismatch between the core A/Ds. The I2E
circuitry also adjusts in real-time for temperature and
voltage variations.
After the power supply has stabilized the internal POR
releases RESETN and an internal pull-up pulls it high,
which starts the calibration sequence. If a subsequent
user-initiated reset is desired, the RESETN pin should be
connected to an open-drain driver with a drive strength
in its high impedance state of less than 0.5mA.
Residual gain and sample time skew mismatch result in
fundamental image spurs at fNYQUIST ± fIN. Offset
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 26. The over-range output
CLOCK
GENERATION
INP
SHA
INN
1.25V
+
–
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
3-BIT
FLASH
DIGITAL
ERROR
CORRECTION
LVDS/LVCMOS
OUTPUTS
FIGURE 25. A/D CORE BLOCK DIAGRAM
14
FN7565.1
June 4, 2010
ISLA118P50
While RESETN is low, the output clock
(CLKOUTP/CLKOUTN) is set low. Normal operation of the
output clock resumes at the next input clock edge
(CLKP/CLKN) after RESETN is deasserted. At 500MSPS
the nominal calibration time is 200ms, while the
maximum calibration time is 550ms.
CLKN
CLKP
CALIBRATION
TIME
RESETN
the variation of SNR/SFDR across temperature after a
single power on calibration at -40°C, +25°C and +85°C.
Best performance is typically achieved by a user-initiated
power on calibration at the operating conditions, as
stated earlier. However, it can be seen that performance
drift with temperature is not a very strong function of the
temperature at which the power on calibration is
performed. To achieve the performance demonstrated in
the SFDR plot, I2E must be in Track mode.
SNR CHANGE (dBfs)
(OR) is set high once RESETN is pulled low, and remains
in that state until calibration is complete. The OR output
returns to normal operation at that time, so it is
important that the analog input be within the converter’s
full-scale range to observe the transition. If the input is in
an over-range condition the OR pin will stay high, and it
will not be possible to detect the end of the calibration
cycle.
3
CAL DONE AT
+85°C
2
1
0
-1
-2
-3
CALIBRATION
BEGINS
CAL DONE AT
+25°C
CAL DONE AT
-40°C
-4
-40
-15
10
ORP
35
60
85
TEMPERATURE (°C)
CALIBRATION
COMPLETE
CLKOUTP
FIGURE 27. SNR PERFORMANCE vs TEMPERATURE
AFTER +25°C CALIBRATION
User Initiated Reset
Recalibration of the A/D can be initiated at any time by
driving the RESETN pin low for a minimum of one clock
cycle. An open-drain driver with a drive strength in its
high impedance state of less than 0.5mA is
recommended, as RESETN has an internal high
impedance pull-up to OVDD. As is the case during
power-on reset, the SDO, RESETN and DNC pins must be
in the proper state for the calibration to successfully
execute.
The performance of the ISLA118P50 changes with
variations in temperature, supply voltage or sample rate.
The extent of these changes may necessitate
recalibration, depending on system performance
requirements. Best performance will be achieved by
recalibrating the A/D under the environmental conditions
at which it will operate.
A supply voltage variation of less than 100mV will
generally result in an SNR change of less than 0.5dBFS
and SFDR change of less than 3dBc.
In situations where the sample rate is not constant, best
results will be obtained if the device is calibrated at the
highest sample rate. Reducing the sample rate by less
than 80MSPS will typically result in an SNR change of
less than 0.5dBFS and an SFDR change of less than
3dBc.
Figures 27 and 28 show the effect of temperature on
SNR and SFDR performance with power on calibration
performed at -40°C, +25°C, and +85°C. Each plot shows
15
SFDR CHANGE (dBc)
15
FIGURE 26. CALIBRATION TIMING
CAL DONE AT
-40°C
10
5
0
-5
CAL DONE AT
+85°C
-10
-15
-40
-15
CAL DONE AT
+25°C
10
35
TEMPERATURE (°C)
60
85
FIGURE 28. SFDR PERFORMANCE vs TEMPERATURE
AFTER +25°C CALIBRATION
Analog Input
A single fully differential input (VINP/VINN) connects to
the sample and hold amplifier (SHA) of each unit A/D.
The ideal full-scale input voltage is 1.45V, centered at the
VCM voltage of 0.535V as shown in Figure 29.
1.8
1.4
1.0
0.6
INN
0.725V
INP
VCM
0.535V
0.2
FIGURE 29. ANALOG INPUT RANGE
FN7565.1
June 4, 2010
ISLA118P50
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as
shown in Figures 30 through 32. An RF transformer will
give the best noise and distortion performance for
wideband and/or high intermediate frequency (IF)
inputs. Two different transformer input schemes are
shown in Figures 30 and 31.
ADT1-1WT
ADT1-1WT
1000pF
A/D
VCM
0.1µF
A differential amplifier, as shown in Figure 32, can be
used in applications that require DC-coupling. In this
configuration, the amplifier will typically dominate the
achievable SNR and distortion performance.
Clock Input
The clock input circuit is a differential pair (see
Figure 47). Driving these inputs with a high level (up to
1.8VP-P on each input) sine or square wave will provide
the lowest jitter performance. A transformer with 4:1
impedance ratio will provide increased drive levels. The
clock input is functional with AC-coupled LVDS, LVPECL,
and CML drive levels. To maintain the lowest possible
aperture jitter, it is recommended to have high slew rate
at the zero crossing of the differential clock input signal.
The recommended drive circuit is shown in Figure 33. A
duty range of 40% to 60% is acceptable. The clock can
be driven single-ended, but this will reduce the edge rate
and may impact SNR performance. The clock inputs are
internally self-biased to AVDD/2 to facilitate AC coupling.
FIGURE 30. TRANSFORMER INPUT FOR GENERAL
PURPOSE APPLICATIONS
Ω
1kO
Ω
1kO
ADTL1-12
ADTL1-12
1000pF
AVDD
200pF
0.1µF
TC4-1W
A/D
1000pF
CLKP
VCM
1000pF
200pF
Ω
200O
FIGURE 31. TRANSMISSION-LINE TRANSFORMER
INPUT FOR HIGH IF APPLICATIONS
This dual transformer scheme is used to improve
common-mode rejection, which keeps the
common-mode level of the input matched to VCM. The
value of the shunt resistor should be determined based
on the desired load impedance. The differential input
resistance of the ISLA118P50 is 500Ω.
Ω
348O
Ω
69.8O
Ω
25O
Ω
100O
Ω
49.9O
FIGURE 33. RECOMMENDED CLOCK DRIVE
Jitter
In a sampled data system, clock jitter directly impacts
the achievable SNR performance. The theoretical
relationship between clock jitter (tJ) and SNR is shown in
Equation 1 and is illustrated in Figure 34.
1
SNR = 20 log 10 ⎛ --------------------⎞
⎝ 2πf t ⎠
217O
Ω
Ω
100O
100
95
tj = 0.1ps
90
14 BITS
85
80
tj = 1ps
75
Ω
69.8O
Ω
348O
60
VCM
55
0.1µF
12 BITS
70
A/D
25O
Ω
(EQ. 1)
IN J
tj = 10ps
65
CM
0.22µF
200pF
SNR (dB)
The SHA design uses a switched capacitor input stage
(see Figure 46), which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle
before the next sampling point. Lower source impedance
will result in faster settling and improved performance.
Therefore a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
CLKN
50
10 BITS
tj = 100ps
1M
10M
100M
INPUT FREQUENCY (Hz)
1G
FIGURE 34. SNR vs CLOCK JITTER
FIGURE 32. DIFFERENTIAL AMPLIFIER INPUT
16
This relationship shows the SNR that would be achieved
if clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
FN7565.1
June 4, 2010
ISLA118P50
linearity, aperture jitter and thermal noise. Internal
aperture jitter is the uncertainty in the sampling instant
shown in Figure 2. The internal aperture jitter combines
with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this
determines the total jitter in the system. The total jitter,
combined with other noise sources, then determines the
achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides
the reference charges used in the successive
approximation operations. The full-scale range of each
A/D is proportional to the reference voltage. The nominal
value of the voltage reference is 1.25V.
Digital Outputs
Output data is available as a parallel bus in
LVDS-compatible or CMOS modes. In either case, the
data is presented in double data rate (DDR) format.
Figures 2 and 3 show the timing relationships for LVDS
and CMOS modes, respectively.
Additionally, the drive current for LVDS mode can be set
to a nominal 3mA or a power-saving 2mA. The lower
current setting can be used in designs where the receiver
is in close physical proximity to the A/D. The applicability
of this setting is dependent upon the PCB layout,
therefore the user should experiment to determine if
performance degradation is observed.
The output mode and LVDS drive current are selected via
the OUTMODE pin as shown in Table 1.
TABLE 1. OUTMODE PIN SETTINGS
OUTMODE PIN
MODE
AVSS
LVCMOS
Float
LVDS, 3mA
AVDD
LVDS, 2mA
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details
on this are contained in “Serial Peripheral Interface” on
page 22.
An external resistor creates the bias for the LVDS drivers.
A 10kΩ, 1% resistor must be connected from the RLVDS
pin to OVSS.
Over Range Indicator
The over range (OR) bit is asserted when the output code
reaches positive full-scale (e.g. 0xFFF in offset binary
mode). The output code does not wrap around during an
over-range condition. The OR bit is updated at the
sample rate.
Power Dissipation
The power dissipated by the ISLA118P50 is primarily
dependent on the sample rate and the output modes:
LVDS vs. CMOS and DDR vs. SDR. There is a static bias
in the analog supply, while the remaining power
17
dissipation is linearly related to the sample rate. The
output supply dissipation changes to a lesser degree in
LVDS mode, but is more strongly related to the clock
frequency in CMOS mode.
Nap/Sleep
Portions of the device may be shut down to save power
during times when operation of the A/D is not required.
Two power saving modes are available: Nap, and Sleep.
Nap mode reduces power dissipation to less than
164mW and recovers to normal operation in
approximately 2.75µs. Sleep mode reduces power
dissipation to less than 6mW but requires approximately
1ms to recover from a sleep command.
Wake-up time from sleep mode is dependent on the state
of CSB; in a typical application CSB would be held high
during sleep, requiring a user to wait 150µs max after
CSB is asserted (brought low) prior to writing ‘001x’ to
SPI Register 25. The device would be fully powered up, in
normal mode 1ms after this command is written.
Wake-up from Sleep Mode Sequence (CSB high)
• Pull CSB Low
• Wait 150µs
• Write ‘001x’ to Register 25
• Wait 1ms until A/D fully powered on
In an application where CSB was kept low in sleep
mode, the 150µs CSB setup time is not required as the
SPI registers are powered on when CSB is low, the chip
power dissipation increases by ~ 15mW in this case.
The 1ms wake-up time after the write of a ‘001x’ to
register 25 still applies. It is generally recommended to
keep CSB high in sleep mode to avoid any unintentional
SPI activity on the A/D.
All digital outputs (Data, CLKOUT and OR) are placed in a
high impedance state during Nap or Sleep. The input
clock should remain running and at a fixed frequency
during Nap or Sleep, and CSB should be high. Recovery
time from Nap mode will increase if the clock is stopped,
since the internal DLL can take up to 52µs to regain lock
at 250MSPS.
By default after the device is powered on, the operational
state is controlled by the NAPSLP pin as shown in Table 2.
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
The power-down mode can also be controlled through
the SPI port, which overrides the NAPSLP pin setting.
Details on this are contained in “Serial Peripheral
Interface” on page 22. This is an indexed function when
controlled from the SPI, but a global function when
driven from the pin.
FN7565.1
June 4, 2010
ISLA118P50
Data Format
Output data can be presented in three formats: two’s
complement, Gray code and offset binary. The data
format is selected via the OUTFMT pin as shown in
Table 3.
Converting back to offset binary from Gray code must be
done recursively, using the result of each bit for the next
lower bit as shown in Figure 36.
GRAY CODE
11
10
9
••••
1
0
TABLE 3. OUTFMT PIN SETTINGS
OUTFMT PIN
MODE
AVSS
Offset Binary
Float
Two’s Complement
AVDD
Gray Code
••••
The data format can also be controlled through the SPI
port, which overrides the OUTFMT pin setting. Details on
this are contained in “Serial Peripheral Interface” on
page 22.
Offset binary coding maps the most negative input
voltage to code 0x000 (all zeros) and the most positive
input to 0xFFF (all ones). Two’s complement coding
simply complements the MSB of the offset binary
representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current
bit position and the next most significant bit. Figure 35
shows this operation.
••••
BINARY
11
10
9
••••
1
0
FIGURE 36. GRAY CODE TO BINARY CONVERSION
Mapping of the input voltage to the various data formats
is shown in Table 4.
TABLE 4. INPUT VOLTAGE TO OUTPUT CODE MAPPING
BINARY
11
10
9
••••
1
0
••••
GRAY CODE
11
10
9
••••
1
0
FIGURE 35. BINARY TO GRAY CODE CONVERSION
18
INPUT
VOLTAGE
OFFSET
BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full
Scale
000 00 000 00 00 100 00 000 00 00 000 00 000 00 00
–Full
Scale +
1LSB
000 00 000 00 01 100 00 000 00 01 000 00 000 00 01
Mid–Scale 100 00 000 00 00 000 00 000 00 00 110 00 000 00 00
+Full
Scale –
1LSB
111 11 111 11 10 011 11 111 11 10 100 00 000 00 01
+Full
Scale
111 11 111 11 11 011 11 111 111 1 100 00 000 00 00
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ISLA118P50
I2E Requirements and
Restrictions
Overview
I2E is a blind and background capable algorithm,
designed to transparently eliminate interleaving
artifacts. This circuitry eliminates interleave artifacts
due to offset, gain, and sample time mismatches
between unit A/Ds, and across supply voltage and
temperature variations in real-time.
Differences in the offset, gain, and sample times of
time-interleaved A/Ds create artifacts in the digital
outputs. Each of these artifacts creates a unique
signature that may be detectable in the captured
samples. The I2E algorithm optimizes performance by
detecting error signatures and adjusting each unit A/D
using minimal additional power.
The I2E algorithm can be put in Active Run state via SPI.
When the I2E algorithm is in Active Run state, it detects
and corrects for offset, gain, and sample time
mismatches in real time (see Track Mode description).
However, certain analog input characteristics can obscure
the estimation of these mismatches. The I2E algorithm is
capable of detecting these obscuring analog input
characteristics, and as long as they are present I2E will
stop updating the correction in real time. Effectively, this
freezes the current correction circuitry to the last
known-good state (see Hold Mode description). Once the
analog input signal stops obscuring the interleaved
artifacts, the I2E algorithm will automatically start
correcting for mismatch in real time again.
Active Run State
During the Active Run state the I2E algorithm actively
suppresses artifacts due to interleaving based on
statistics in the digitized data. I2E has two modes of
operation in this state (described below), dynamically
chosen in real-time by the algorithm based on the
statistics of the analog input signal.
Track Mode refers to the default state of the algorithm,
when all artifacts due to interleaving are actively being
eliminated. To be in Track Mode the analog input signal to
the device must adhere to the following requirements:
• Posses total power greater than -20dBFS, integrated
from 1MHz to Nyquist but excluding signal energy in
a 100kHz band centered at fS/4
The criteria above assumes 500MSPS operation; the
frequency bands should be scaled proportionally for
lower sample rates. Note that the effect of excluding
energy in the 100kHz band around of fS/4 exists in every
Nyquist zone. This band generalizes to the form
(N*fS/4-50kHz) to (N*fS/4+50kHz), where N is any odd
integer. An input signal that violates these criteria briefly
(approximately 10µs), before and after which it meets
this criteria, will not impact system performance.
19
The algorithm must be in Track Mode for approximately
one second (defined as I2Epost_t in the specification
table on page 7) after power-up before the specifications
apply. Once this requirement has been met, the
specifications of the device will continue to be met while
I2E remains in Track Mode, even in the presence of
temperature and supply voltage changes.
Hold Mode refers to the state of the I2E algorithm when
the analog input signal does not meet the requirements
specified above. If the algorithm detects that the signal
no longer meets the criteria, it automatically enters Hold
Mode. In Hold Mode, the I2E circuitry freezes the
adjustment values based on the most recent set of valid
input conditions. However, in Hold Mode, the I2E circuitry
will not correct for new changes in interleave artifacts
induced by supply voltage and temperature changes. The
I2E circuitry will remain in Hold Mode until such time as
the analog input signal meets the requirements for Track
Mode.
Power Meter
The power meter calculates the average power of the
analog input, and determines if it’s within range to allow
operation in Track Mode. Both AC RMS and total RMS
power are calculated, and there are separate SPI
programmable thresholds and hysteresis values for each.
FS/4 Filter
A digital filter removes the signal energy in a 100kHz
band around fS/4 before the I2E circuitry uses these
samples for estimating offset, gain, and sample time
mismatches (data samples produced by the A/D are
unaffected by this filtering). This allows the I2E algorithm
to continue in Active Run state while in the presence of a
large amount of input energy near the fS/4 frequency.
This filter can be powered down if it’s known that the
signal characteristics won’t violate the restrictions.
Powering down the FS/4 filter will reduce power
consumption by approximately 70mW.
Nyquist Zones
The I2E circuitry allows the use of any one Nyquist zone
without configuration, but requires the use of only one
Nyquist zone. Inputs that switch dynamically between
Nyquist zones will cause poor performance for the I2E
circuitry. For example, I2E will function properly for a
particular application that has fS = 500MSPS and uses
the 1st Nyquist zone (0MHz to 250MHz). I2E will also
function properly for an application that uses
fS = 500MSPS and the 2nd Nyquist zone (250MHz to
500MHz). I2E will not function properly for an application
that uses fS = 500MSPS, and input frequency bands
from 150MHz to 210MHz and 250MHz to 290MHz
simultaneously. There is no need to configure the I2E
algorithm to use a particular Nyquist zone, but no
dynamic switching between Nyquist zones is permitted
while I2E is running.
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Configurability and Communication
I2E can respond to status queries, be turned on and
turned off, and generally configured via SPI
programmable registers. Configuring of I2E is generally
unnecessary unless the application cannot meet the
requirements of Track Mode on or after power up.
Parameters that can be adjusted and read back include
FS/4 filter threshold and status, Power Meter threshold
and status, and initial values for the offset, gain, and
sample time values to use when I2E starts.
Clock Divider Synchronous
Reset
An output clock (CLKOUTP, CLKOUTN) is provided to
facilitate latching of the sampled data. This clock is at
half the frequency of the sample clock, and the absolute
phase of the output clocks for multiple A/Ds is
indeterminate. This feature allows the phase of multiple
A/Ds to be synchronized (refer to Figure 37), which
greatly simplifies data capture in systems employing
multiple A/Ds.
The reset signal must be well-timed with respect to the
sample clock (See “Switching Specifications” on page 9).
Sample Clock
Input
s1
L+td1
Analog Input
s2
tRSTH
CLKDIVRSTP 2
tRSTS
tRSTRT
ADC1 Output Data
s0
s1
s2
s3
s0
s1
s2
s3
ADC1 CLKOUTP
ADC2 Output Data
ADC2 CLKOUTP
(phase 1) 3
ADC2 CLKOUTP
(phase 2) 3
1
2
Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay t d
CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge.
CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP.
3
Either Output Clock Phase (phase 1 or phase 2) equally likely prior to synchronization
FIGURE 37. SYNCHRONOUS RESET OPERATION
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ISLA118P50
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D3
D4
D5
D6
D7
FIGURE 38. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D1
D0
D2
FIGURE 39. LSB-FIRST ADDRESSING
tDSW
CSB
tDHW
tS
tCLK
tHI
tH
tLO
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
SPI WRITE
FIGURE 40. SPI WRITE
tDSW
CSB
tDHW
tS
tCLK
tHI
tH
tDHR
tDVR
tLO
SCLK
WRITING A READ COMMAND
SDIO
R/W
W1
W0
A12
A11
A10
A9
A2
A1
READING DATA (3 WIRE MODE)
A0
D7
SDO
D6
D3
D2
D1 D0
(4 WIRE MODE)
D7
D3
D2
D1 D0
SPI READ
FIGURE 41. SPI READ
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ISLA118P50
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 42. 2-BYTE TRANSFER
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 43. N-BYTE TRANSFER
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to
facilitate configuration of the device and to optimize
performance. The SPI bus consists of chip select (CSB),
serial clock (SCLK) serial data output (SDO), and serial
data input/output (SDIO). The maximum SCLK rate is
equal to the A/D sample rate (fSAMPLE) divided by 32
for write operations and fSAMPLE divided by 132 for
reads. At fSAMPLE = 250MHz, maximum SCLK is
15.63MHz for writing and 3.79MHz for read operations.
There is no minimum SCLK rate.
The following sections describe various registers that
are used to configure the SPI or adjust performance or
functional parameters. Many registers in the available
address space (0x00 to 0xFF) are not defined in this
document. Additionally, within a defined register there
may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values
within defined registers are reserved and should not be
selected. Setting any reserved register or value may
produce indeterminate results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for
the data transfer. By default, all data is presented on the
serial data input/output (SDIO) pin in three-wire mode.
The state of the SDIO pin is set automatically in the
communication protocol (described in the following). A
dedicated serial data output pin (SDO) can be activated
by setting 0x00[7] high to allow operation in four-wire
mode.
The SPI port operates in a half duplex master/slave
configuration, with the ISLA118P50 functioning as a
slave. Multiple slave devices can interface to a single
master in three-wire mode only, since the SDO output of
an unaddressed device is asserted in four wire mode.
22
The chip-select bar (CSB) pin determines when a slave
device is being addressed. Multiple slave devices can be
written to concurrently, but only one slave device can be
read from at a given time (again, only in three-wire
mode). If multiple slave devices are selected for reading
at the same time, the results will be indeterminate.
The communication protocol begins with an
instruction/address phase. The first rising SCLK edge
following a high to low transition on CSB determines the
beginning of the two-byte instruction/address command;
SCLK must be static low before the CSB transition. Data
can be presented in MSB-first order or LSB-first order.
The default is MSB-first, but this can be changed by
setting 0x00[6] high. Figures 38 and 39 show the
appropriate bit ordering for the MSB-first and LSB-first
modes, respectively. In MSB-first mode, the address is
incremented for multi-byte transfers, while in LSB-first
mode it’s decremented.
In the default mode, the MSB is R/W, which determines if
the data is to be read (active high) or written. The next
two bits, W1 and W0, determine the number of data
bytes to be read or written (see Table 5). The lower 13
bits contain the first address for the data transfer. This
relationship is illustrated in Figure 40, and timing values
are given in “Switching Specifications” on page 9.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read
from the A/D (based on the R/W bit status). The data
transfer will continue as long as CSB remains low and
SCLK is active. Stalling of the CSB pin is allowed at any
byte boundary (instruction/address or data) if the
number of bytes being transferred is three or less. For
transfers of four bytes or more, CSB is allowed to stall in
the middle of the instruction/address bytes or before the
first data byte. If CSB transitions to a high state after
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that point the state machine will reset and terminate the
data transfer.
TABLE 5. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
10
3
11
4 or more
Figures 42 and 43 illustrate the timing relationships for
2-byte and N-byte transfers, respectively. The operation
for a 3-byte transfer can be inferred from these
diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register.
Bit order can be selected as MSB to LSB (MSB first) or
LSB to MSB (LSB first) to accommodate various micro
controllers.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret
serial data as arriving in LSB to MSB order.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default
values.
Bit 4 Reserved
This bit should always be set high.
Indexed Device Configuration/Control
ADDRESS 0X10: DEVICE_INDEX_A
Bits 1:0 ADC01, ADC00
Determines which A/D is addressed. Valid states for
this register are 0x01 or 0x10. The two A/D cores
cannot be adjusted concurrently.
A common SPI map, which can accommodate
single-channel or multi-channel devices, is used for all
Intersil A/D products. Certain configuration commands
(identified as Indexed in the SPI map) can be executed
on a per-converter basis. This register determines which
converter is being addressed for an Indexed command. It
is important to note that only a single converter can be
addressed at a time.
This register defaults to 00h, indicating that no A/D is
addressed. Error code ‘AD’ is returned if any indexed
register is read from without properly setting
device_index_A.
ADDRESS 0X20: OFFSET_COARSE
ADDRESS 0X21: OFFSET_FINE
The input offset of the A/D core can be adjusted in fine
and coarse steps. Both adjustments are made via an
8-bit word as detailed in Table 6. The data format is twos
complement.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read
the register value then write the incremented or
decremented value back to the same register.
TABLE 6. OFFSET ADJUSTMENTS
PARAMETER
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
Steps
255
255
ADDRESS 0X02: BURST_END
–Full Scale (0x00)
-133LSB (-47mV)
-5LSB (-1.75mV)
If a series of sequential registers are to be set, burst
mode can improve throughput by eliminating redundant
addressing. In 3-wire SPI mode, the burst is ended by
pulling the CSB pin high. If the device is operated in
2-wire mode the CSB pin is not available. In that case,
setting the burst_end address determines the end of the
transfer. During a write operation, the user must be
cautious to transmit the correct number of bytes based
on the starting and ending addresses.
Mid–Scale (0x80)
0.0LSB (0.0mV)
0.0LSB
Bits 3:0 These bits should always mirror bits 4:7 to
avoid ambiguity in bit ordering.
Bits 7:0 Burst End Address
+Full Scale (0xFF) +133LSB (+47mV) +5LSB (+1.75mV)
Nominal Step Size 1.04LSB (0.37mV) 0.04LSB (0.014mV)
ADDRESS 0X22: GAIN_COARSE
ADDRESS 0X23: GAIN_MEDIUM
ADDRESS 0X24: GAIN_FINE
ADDRESS 0X09: CHIP_VERSION
Gain of the A/D core can be adjusted in coarse, medium
and fine steps. Coarse gain is a 4-bit adjustment while
medium and fine are 8-bit. Multiple Coarse Gain Bits
can be set for a total adjustment range of ±4.2%.
(‘0011’ ≅ -4.2% and ‘1100’ ≅ +4.2%) It is
recommended to use one of the coarse gain settings
(-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and
fine-tune the gain using the registers at 23h and 24h.
The generic die identifier and a revision number,
respectively, can be read from these two registers.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
This register value determines the ending address of
the burst data.
Device Information
ADDRESS 0X08: CHIP_ID
23
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ISLA118P50
incremented or decremented, the user should first read
the register value then write the incremented or
decremented value back to the same register.
TABLE 7. COARSE GAIN ADJUSTMENT
0x22[3:0]
NOMINAL COARSE GAIN ADJUST
(%)
Bit 3
+2.8
Bit 2
+1.4
Bit 1
-2.8
Bit 0
-1.4
TABLE 8. MEDIUM AND FINE GAIN ADJUSTMENTS
achieves sufficient quality to allow the I2E algorithm to
make mismatch estimates again.
Bit 0: 0 = I2E has not detected a low power condition.
1 = I2E has detected a low power condition, and the
analog adjustments for interleave correction are frozen.
Bit 1: 0 = I2E has not detected a low AC power
condition. 1 = I2E has detected a low AC power
condition, and I2E will continue to correct with best
known information but will not update its interleave
correction adjustments until the input signal achieves
sufficient AC RMS power.
Bit 2: When first started, the I2E algorithm can take a
significant amount of time to settle (~1s), dependent on
the characteristics of the analog input signal. 0 = I2E is
still settling, 1 = I2E has completed settling.
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
0.00%
The I2E general control register. This register can be
written while I2E is running to control various
parameters.
+Full Scale (0xFF)
+2%
+0.2%
Bit 0: 0 = turn I2E off, 1= turn I2E on
Nominal Step Size
0.016%
0.0016%
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation, nap or sleep modes (refer to“Nap/Sleep” on
page 17). This functionality can be overridden and
controlled through the SPI. This is an indexed function
when controlled from the SPI, but a global function when
driven from the pin. This register is not changed by a
Soft Reset.
TABLE 9. POWER-DOWN CONTROL
VALUE
0x25[2:0]
POWER DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
ADDRESS 0X30: I2E STATUS
The I2E general status register.
Bits 0 and 1 indicate if the I2E circuitry is in Active Run or
Hold state. The state of the I2E circuitry is dependent on
the analog input signal itself. If the input signal obscures
the interleave mismatched artifacts such that I2E cannot
estimate the mismatch, the algorithm will dynamically
enter the Hold state. For example, a DC mid-scale input
to the A/D does not contain sufficient information to
estimate the gain and sample time skew mismatches,
and thus the I2E algorithm will enter the Hold state. In
the Hold state, the analog adjustments for interleave
correction will be frozen and mismatch estimate
calculations will cease until such time as the analog input
ADDRESS 0X31: I2E CONTROL
Bit 1: 0 = no action, 1 = freeze I2E, leaving all settings
in the current state. Subsequently writing a 0 to this bit
will allow I2E to continue from the state it was left in.
Bit 2-4: Disable any of the interleave adjustments of
offset, gain, or sample time skew.
Bit 5: 0 = bypass notch filter, 1 = use notch filter on
incoming data before estimating interleave mismatch
terms.
ADDRESS 0X32: I2E STATIC CONTROL
The I2E general static control register. This register must
be written prior to turning I2E on for the settings to take
effect.
Bit 1-4: Reserved, always set to 0
Bit 5: 0 = normal operation, 1 = skip coarse adjustment
of the offset, gain, and sample time skew analog controls
when I2E is first turned on. This bit would typically be
used if optimal analog adjustment values for offset, gain,
and sample time skew have been preloaded in order to
have the I2E algorithm converge more quickly.
The system gain of the pair of interleaved core A/Ds can
be set by programming the medium and fine gain of the
reference A/D before turning I2E on. In this case, I2E will
adjust the non-reference A/D’s gain to match the
reference A/D’s gain.
Bit 7: Reserved, always set to 0
ADDRESS 0X4A: I2E POWER DOWN
This register provides the capability to completely power
down the I2E algorithm and the Notch filter. This would
typically be done to conserve power.
BIT 0: Power down the I2E Algorithm
BIT 1: Power down the Notch Filter
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ADDRESS 0X50-0X55: I2E FREEZE THRESHOLDS
This group of registers provides programming access to
configure I2E’s dynamic freeze control. As with any
interleave mismatch correction algorithm making
estimates of the interleave mismatch errors using the
digitized application input signal, there are certain
characteristics of the input signal that can obscure the
mismatch estimates. For example, a DC input to the A/D
contains no information about the sample time skew
mismatch between the core A/Ds, and thus should not be
used by the I2E algorithm to update its sample time
skew estimate. Under such circumstances, I2E enters
Hold state. In the Hold state, the analog adjustments will
be frozen and mismatch estimate calculations will cease
until such time as the analog input achieves sufficient
quality to allow the I2E algorithm to make mismatch
estimates again.
These registers allow the programming of the thresholds
of the meters used to determine the quality of the input
signal. This can be used by the application to optimize
I2E’s behavior based on knowledge of the input signal.
For example, if a specific application had an input signal
that was typically 30dB down from full scale, and was
primarily concerned about analog performance of the
A/D at this input power, lowering the RMS power
threshold would allow I2E to continue tracking with this
input power level, thus allowing it to track over voltage
and temperature changes.
0x50 (LSBs), 0x51 (MSBs) RMS Power Threshold
This 16-bit quantity is the RMS power threshold at which
I2E will enter Hold state. The RMS power of the analog
input is calculated continuously by I2E on incoming data.
A 12-bit number squared produces a 24-bit result (for
A/D resolutions under 12-bits, the A/D samples are
MSB-aligned to 12-bit data). A dynamic number of these
24-bit results are averaged to compare with this
threshold approximately every 1µs to decide whether or
not to freeze I2E. The 24-bit threshold is constructed
with bits 23 through 20 (MSBs) assigned to 0, bits 19
through 4 assigned to this 16-bit quantity, and bits 3
through 0 (LSBs) assigned to 0. As an example, if the
application wanted to set this threshold to trigger near
the RMS analog input of a -20dBFS sinusoidal input, the
calculation to determine this register’s value would be
20⎞
⎛ –---------
⎝ 20 ⎠
12
2
RMS codes = ------- × 10
× 2 ≅ 290codes
2
(EQ. 2)
2
hex ( 290 ) = 0x014884 TruncateMSBandLSBhexdigit = 0x1488
(EQ. 3)
Therefore, programming 0x1488 into these two registers
will cause I2E to freeze when the signal being digitized
has less RMS power than a -20dBFS sinusoid.
The default value of this register is 0x1000, causing I2E
to freeze when the input amplitude is less than -21.2
dBFS.
25
The freezing of I2E by the RMS power meter threshold
affects the gain and sample time skew interleave
mismatch estimates, but not the offset mismatch
estimate.
0x52 RMS Power Hysteresis
In order to prevent I2E from constantly oscillating
between the Hold and Track state, there is hysteresis
in the comparison described above. After I2E enters a
frozen state, the RMS input power must achieve ≥
threshold value + hysteresis to again enter the old.
The hysteresis quantity is a 24-bit value, constructed
with bits 23 through 12 (MSBs) being assigned to 0,
bits 11 through 4 assigned to this register’s value,
and bits 3 through 0 (LSBs) assigned to 0.
AC RMS Power Threshold
Similar to RMS power threshold, there must be sufficient
AC RMS power (or dV/dt) of the input signal to measure
sample time skew mismatch for an arbitrary input. This is
clear from observing the effect when a high voltage (and
therefore large RMS value) DC input is applied to the A/D
input. Without sufficient dV/dt in the input signal, no
information about the sample time skew between the
core A/Ds can be determined from the digitized samples.
The AC RMS Power Meter is implemented as a
high-passed (via DSP) RMS power meter.
The writing of the AC RMS Power Threshold is different
than other SPI registers, and these registers are not
listed in the SPI memory map table. The required
algorithm is documented below.
1. Write the value 0x80 to the Index Register (SPI
address 0x10)
2. Write the MSBs of the 16-bit quantity to SPI Address
0x150
3. Write the LSBs of the 16-bit quantity to SPI Address
0x14F
A 12-bit number squared produces a 24-bit result (for
A/D resolutions under 12-bits, the A/D samples are
MSB-aligned to 12-bit data). A dynamic number of these
24-bit results are averaged to compare with this
threshold approximately every 1µs to decide whether or
not to freeze I2E. The 24-bit threshold is constructed
with bits 23 through 20 (MSBs) assigned to 0, bits 19
through 4 assigned to this 16-bit quantity, and bits 3
through 0 (LSBs) assigned to 0. The calculation
methodology to set this register is identical to the
description in the RMS power threshold description.
The freezing of I2E when the AC RMS power meter
threshold is not met affects the sample time skew
interleave mismatch estimate, but not the offset or gain
mismatch estimates.
0x55 AC RMS Power Hysteresis
In order to prevent I2E from constantly oscillating between
the Hold and Track state, there is hysteresis in the
comparison described above. After I2E enters a frozen
state, the AC RMS input power must achieve ≥ threshold
value + hysteresis to again enter the Track state. The
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hysteresis quantity is a 24-bit value, constructed with bits
23 through 12 (MSBs) being assigned to 0, bits 11 through
4 assigned to this register’s value, and bits 3 through 0
(LSBs) assigned to 0.
ADDRESS 0X60-0X64: I2E INITIALIZATION
These registers provide access to the initialization values
for each of offset, gain, and sample time skew that I2E
programs into the target core A/D before adjusting to
minimize interleave mismatch. They can be used by the
system to, for example, reduce the convergence time of
the I2E algorithm by programming in the optimal values
before turning I2E on. In this case, I2E only needs to
adjust for temperature and voltage-induced changes
since the optimal values were recorded.
Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing
skew between the two A/D cores. The nominal range and
resolution of this adjustment are given in Table 10. The
default value of this register after power-up is 80h.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
ISLA118P50 can present output data in two physical
formats: LVDS or LVCMOS. Additionally, the drive
strength in LVDS mode can be set high (3mA) or low
(2mA). By default, the tri-level OUTMODE pin selects the
mode and drive level (refer to “Digital Outputs” on
page 17). This functionality can be overridden and
controlled through the SPI, as shown in Table 11.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to
“Data Format” on page 18). This functionality can be
overridden and controlled through the SPI, as shown in
Table 12.
This register is not changed by a Soft Reset.
TABLE 11. OUTPUT MODE CONTROL
VALUE
0x93[7:5]
OUTPUT MODE
000
Pin Control
001
LVDS 2mA
010
LVDS 3mA
100
LVCMOS
TABLE 10. DIFFERENTIAL SKEW ADJUSTMENT
PARAMETER
0x70[7:0]
DIFFERENTIAL SKEW
Steps
256
–Full Scale (0x00)
-6.5ps
Mid–Scale (0x80)
0.0ps
+Full Scale (0xFF)
+6.5ps
Nominal Step Size
51fs
TABLE 12. OUTPUT FORMAT CONTROL
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the
A/D input sample clock. Some systems with multiple
A/Ds can more easily latch the data from each A/D by
controlling the phase of the output data clock. This
control is accomplished through the use of the phase_slip
SPI feature, which allows the rising edge of the output
data clock to be advanced by one input clock period, as
shown in the Figure 44. Execution of a phase_slip
command is accomplished by first writing a '0' to bit 0 at
address 0x71, followed by writing a '1' to bit 0 at address
0x71.
ADC Input
Clock (500MHz)
2ns
Output Data
Clock (250MHz)
No clock_slip
4ns
VALUE
0x93[2:0]
OUTPUT FORMAT
000
Pin Control
001
Two’s Complement
010
Gray Code
100
Offset Binary
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default)
or slow.
Internal clock signals are generated by a delay-locked
loop (DLL), which has a finite operating range. Table 13
shows the allowable sample rate ranges for the slow and
fast settings.
2ns
TABLE 13. DLL RANGES
Output Data
Clock (250MHz)
1 clock_slip
DLL RANGE
MIN
MAX
UNIT
Slow
80
200
MSPS
Output Data
Clock (250MHz)
2 clock_slip
Fast
160
500
MSPS
FIGURE 44. PHASE SLIP
26
The output_mode_B and config_status registers are used
in conjunction to enable DDR mode and select the
frequency range of the DLL clock generator. The method
FN7565.1
June 4, 2010
ISLA118P50
of setting these options is different from the other
registers.
ADDRESS 0XC2: USER_PATT1_LSB
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
READ
OUTPUT_MODE_B
0x74
ADDRESS 0XC4: USER_PATT2_LSB
READ
CONFIG_STATUS
0x75
WRITE TO
0x74
DESIRED
VALUE
FIGURE 45. SETTING OUTPUT_MODE_B REGISTER
The procedure for setting output_mode_B is shown in
Figure 45. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with
the desired value for output_mode_B and write that XOR
result to the register.
Device Test
The ISLA118P50 can produce preset or user defined
patterns on the digital outputs to facilitate in-situ testing.
A static word can be placed on the output bus, or two
different words can alternate. In the alternate mode, the
values defined as Word 1 and Word 2 (as shown in
Table 14) are set on the output bus on alternating clock
phases. The test mode is enabled asynchronously to the
sample clock, therefore several sample clock cycles may
elapse before the data is present on the output bus.
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
These bits set the test mode to static (0x00) or
alternate (0x01) mode. Other values are reserved.
The four LSBs in this register (Output Test Mode)
determine the test pattern in combination with registers
0xC2 through 0xC5. Refer to “SPI Memory Map” on
page 28.
TABLE 14. OUTPUT TEST MODES
VALUE
0xC0[3:0]
OUTPUT TEST MODE
0000
Off
0001
WORD 1
WORD 2
Midscale
0x8000
N/A
0010
Positive Full-Scale
0xFFFF
N/A
0011
Negative Full-Scale
0x0000
N/A
0100
Checkerboard
0xAAAA
0x5555
0101
Reserved
N/A
N/A
0110
Reserved
N/A
N/A
0111
One/Zero
0xFFFF
0x0000
1000
User Pattern
ADDRESS 0XC5: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
Digital Temperature Sensor
This set of registers provides digital access to an
IPTAT-based temperature sensor, allowing the system to
estimate the temperature of the die. This information is
of particular interest for applications that do not keep I2E
in Active Run state when in normal use, allowing easy
access to information that can be used to decide when to
recalibrate the A/D as needed. This set of registers is not
included in the SPI memory map table.
The most accurate usage of this information requires
knowledge of the temperature at which the digital value
is first read (time = 0, T(0) = degrees C at time = 0, and
register_value(0) = the digital value of the temperature
registers at time = 0). Any future reading of the registers
indicates temperature change according to Equation 4:
[ register_value(1) ] – [ register_value(0) ]
ΔT = T ( 1 ) – T ( 0 ) = ----------------------------------------------------------------------------------------------------------------[ ( T ( 0 ) – 216 ) ⁄ 256 ]
(EQ. 4)
A less accurate method for evaluating the temperature
change does not require knowledge of the temperature
at time = 0, and is given by Equation 5:
[ register_value(1) ] – [ register_value(0) ]
ΔT = T ( 1 ) – T ( 0 ) = ----------------------------------------------------------------------------------------------------------------( -0.72 )
(EQ. 5)
The digital temperature sensor is a weak function of the
AVDD supply voltage, so to achieve best accuracy the
AVDD supply voltage should be held fairly constant
across the operating temperature range.
The algorithm to access this set of registers is as follows:
27
1. Write the value 0x80 to the Index Register (SPI
address 0x10).
2. Write the value 0x88 to SPI address 0x120 to turn
the temperature sensor on.
3. Read the register_value LSBs at SPI register 0x11E.
4. Read the register_value MSBs at SPI register 0x11F.
5. Write the value 0x60 to SPI address 0x120 to turn
the temperature sensor off.
user_patt1 user_patt2
FN7565.1
June 4, 2010
ISLA118P50
SPI Memory Map
I2E Control and Status
Indexed Device Config/Control
Info
SPI Config
TABLE 15. SPI MEMORY MAP
DEF.
VALUE
(Hex)
INDEXED
/GLOBAL
00h
G
00h
G
Chip ID #
Read only
G
Chip Version #
Read only
G
00h
I
Coarse Offset
cal. value
I
Fine Offset
cal. value
I
cal. value
I
Medium Gain
cal. value
I
Fine Gain
cal. value
I
00h
NOT
affected
by
Soft
Reset
I
ADDR
(Hex)
PARAMETER
NAME
BIT 7
(MSB)
BIT 6
BIT 5
00
port_config
SDO
Active
LSB
First
Soft
Reset
01
reserved
Reserved
02
burst_end
Burst end address [7:0]
03-07
reserved
Reserved
08
chip_id
09
chip_version
10
device_index_A
11-1F
reserved
Reserved
20
offset_coarse
21
offset_fine
22
gain_coarse
23
gain_medium
24
gain_fine
25
modes
26-2F
reserved
30
I2E Status
31
I2E Control
32
I2E Static
Control
33-49
reserved
4A
I2E Power Down
4B-4F
reserved
Reserved
50
I2E RMS Power
Threshold LSBs
RMS Power Threshold, LSBs
00h
G
51
I2E RMS Power
Threshold MSBs
RMS Power Threshold, MSBs
10h
G
52
I2E RMS
Hysteresis
RMS Power Hysteresis
FFh
G
53-54
reserved
Reserved
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
Mirror
(bit5)
Mirror
(bit6)
Mirror
(bit7)
Reserved
ADC01
Reserved
ADC00
Coarse Gain
Reserved
Power-Down Mode
[2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
Reserved
Reserved
Enable
notch
filter
Reserved
must be
set to 0
Skip
coarse
adjustment
Disable
Offset
Disable
Gain
I
I2E
Low AC
Settled
RMS
Power
Disable
Skew
Freeze
Low
RMS
Power
Read only
G
Run
20h
G
00h
G
Reserved, must be set to 0
Reserved
G
Notch
Filter
Power
Down
28
I2E
Power
Down
00h
G
G
G
FN7565.1
June 4, 2010
ISLA118P50
Global DeviceConfig/Control
I2E Control and Status (continued)
TABLE 15. SPI MEMORY MAP (Continued)
BIT 7
(MSB)
INDEXED
/GLOBAL
10h
G
PARAMETER
NAME
55
I2E AC RMS
Hysteresis
AC RMS Power Hysteresis
56-5F
reserved
Reserved
60
Coarse Offset
Init
Coarse Offset Initialization value
80h
G
61
Fine Offset Init
Fine Offset Initialization value
80h
G
62
Medium Gain
Init
Medium Gain Initialization value
80h
G
63
Fine Gain Init
Fine Gain Initialization value
80h
G
64
Sample Time
Skew Init
Sample Time Skew Initialization value
80h
G
65-6F
reserved
Reserved
70
skew_diff
Differential Skew
71
phase_slip
72
Reserved
73
output_mode_A
74
output_mode_B
DLL
Range
0 = fast
1 = slow
00h
NOT
affected
by
Soft
Reset
G
75
config_status
XOR
Result
Read Only
G
76-BF
reserved
BIT 6
BIT 5
BIT 4
BIT 3
Reserved
Reserved
BIT 2
BIT 1
BIT 0
(LSB)
DEF.
VALUE
(Hex)
ADDR
(Hex)
G
G
80h
G
00h
G
00h
NOT
affected
by
Soft Reset
G
00h
Output Format [2:0]
NOT
000 = Pin Control
001 = Twos Complement affected
by
010 = Gray Code
Soft Reset
100 = Offset Binary
Other codes = Reserved
G
Next
Clock
Edge
Reserved (must be 0)
Output Mode [2:0]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
other codes = reserved
Reserved
29
FN7565.1
June 4, 2010
ISLA118P50
TABLE 15. SPI MEMORY MAP (Continued)
PARAMETER
NAME
C0
test_io
Device Test
ADDR
(Hex)
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 0
(LSB)
BIT 1
Output Test Mode [3:0]
User Test Mode
[1:0]
00 = Single
01 = Alternate
10 = Reserved
11 = Reserved
0 = Off
1 = Midscale
Short
2 = +FS Short
3 = -FS Short
4 = Checker
Board
5 = reserved
6 = reserved
DEF.
VALUE
(Hex)
INDEXED
/GLOBAL
00h
G
00h
G
7 = One/Zero
Word Toggle
8 = User Input
9-15 = reserved
C1
Reserved
Reserved
C2
user_patt 1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C3
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C4
user_patt 2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C5
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C6-FF
reserved
Reserved
Equivalent Circuits
AVDD
TO
CLOCKPHASE
GENERATION
AVDD
CLKP
AVDD
CSAMP
1.6pF
INP
Ω
500O
Φ2
F
Φ
F1
CSAMP
1.6pF
AVDD
INN
Φ2
F
Φ
F1
FIGURE 46. ANALOG INPUTS
30
TO
CHARGE
PIPELINE
Φ
F3
TO
CHARGE
PIPELINE
Φ3
F
AVDD
Ω
11kO
AVDD 11kO
Ω
Ω
18kO
Ω
18kO
CLKN
FIGURE 47. CLOCK INPUTS
FN7565.1
June 4, 2010
ISLA118P50
Equivalent Circuits
(Continued)
AVDD
AVDD
(20k PULL-UP
ON RESETN
ONLY)
AVDD
Ω
75kO
AVDD
TO
SENSE
LOGIC
Ω
75kO
Ω
280O
INPUT
OVDD
OVDD
OVDD
20kΩ
INPUT
Ω
75kO
Ω
75kO
TO
LOGIC
280Ω
FIGURE 48. TRI-LEVEL DIGITAL INPUTS
FIGURE 49. DIGITAL INPUTS
OVDD
2mA OR
3mA
OVDD
DATA
DATA
D[7:0]P
OVDD
OVDD
D[7:0]N
OVDD
DATA
DATA
DATA
D[7:0]
2mA OR
3mA
FIGURE 51. CMOS OUTPUTS
FIGURE 50. LVDS OUTPUTS
AVDD
VCM
0.535V
+
–
FIGURE 52. VCM_OUT OUTPUT
31
FN7565.1
June 4, 2010
ISLA118P50
A/D Evaluation Platform
Definitions
Intersil offers an A/D Evaluation platform which can be
used to evaluate any of Intersil’s high speed A/D
products. The platform consists of a FPGA based data
capture motherboard and a family of A/D daughtercards.
This USB based platform allows a user to quickly
evaluate the A/D’s performance at a user’s specific
application frequency requirements. More information is
available at
http://www.intersil.com/converters/adc_eval_platform/
Analog Input Bandwidth is the analog input frequency
at which the spectral output power at the fundamental
frequency (as determined by FFT analysis) is reduced by
3dB from its full-scale low-frequency value. This is also
referred to as Full Power Bandwidth.
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies
require extra care in PC board layout. Many complex
board designs benefit from isolating the analog and
digital sections. Analog supply and ground planes should
be laid out under signal and clock inputs. Locate the
digital planes under outputs and logic pins. Grounds
should be joined under the chip.
Aperture Delay or Sampling Delay is the time
required after the rise of the clock input for the sampling
switch to open, at which time the signal is held for
conversion.
Aperture Jitter is the RMS variation in aperture delay
for a set of samples.
Clock Duty Cycle is the ratio of the time the clock wave
is at logic high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of
any code width from an ideal 1 LSB step.
Clock Input Considerations
Effective Number of Bits (ENOB) is an alternate
method of specifying Signal to Noise-and-Distortion Ratio
(SINAD). In dB, it is calculated as: ENOB = (SINAD 1.76)/6.02
Use matched transmission lines to the transformer inputs
for the analog input and clock signals. Locate
transformers and terminations as close to the chip as
possible.
Gain Error is the ratio of the difference between the
voltages that cause the lowest and highest code
transitions to the full-scale voltage less 2 LSB. It is
typically expressed in percent.
Exposed Paddle
I2E The Intersil Interleave Engine. This highly
configurable circuitry performs estimates of offset, gain,
and sample time skew mismatches between the core
converters, and updates analog adjustments for each to
minimize interleave spurs.
The exposed paddle must be electrically connected to
analog ground (AVSS) and should be connected to a
large copper plane using numerous vias for optimal
thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series
resistance. Tantalum is a good choice. For best
performance, keep ceramic bypass capacitors very close
to device pins. Longer traces will increase inductance,
resulting in diminished dynamic performance and
accuracy. Make sure that connections to ground are
direct and low impedance. Avoid forming ground loops.
LVDS Outputs
Output traces and connections must be designed for 50Ω
(100Ω differential) characteristic impedance. Keep traces
direct and minimize bends where possible. Avoid crossing
ground and power-plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50Ω
characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO)
which will not be operated do not require connection to
ensure optimal A/D performance. These inputs can be
left floating if they are not used. Tri-level inputs (NAPSLP,
OUTMODE, OUTFMT) accept a floating input as a valid
state, and therefore should be biased according to the
desired functionality.
32
Integral Non-Linearity (INL) is the maximum
deviation of the A/D’s transfer function from a best fit line
determined by a least squares curve fit of that transfer
function, measured in units of LSBs.
Least Significant Bit (LSB) is the bit that has the
smallest value or weight in a digital word. Its value in
terms of input voltage is VFS/(2N-1) where N is the
resolution in bits.
Missing Codes are output codes that are skipped and
will never appear at the A/D output. These codes cannot
be reached with any input value.
Most Significant Bit (MSB) is the bit that has the
largest value or weight.
Pipeline Delay is the number of clock cycles between
the initiation of a conversion and the appearance at the
output pins of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of
the observed magnitude of a spur in the A/D FFT, caused
by an AC signal superimposed on the power supply
voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio
of the RMS signal amplitude to the RMS sum of all other
spectral components below one half the clock frequency,
including harmonics but excluding DC.
FN7565.1
June 4, 2010
ISLA118P50
Signal-to-Noise Ratio (without Harmonics) is the ratio
of the RMS signal amplitude to the RMS sum of all other
spectral components below one-half the sampling
frequency, excluding harmonics and DC.
SNR and SINAD are either given in units of dB when the
power of the fundamental is used as the reference, or
dBFS (dB to full scale) when the converter’s full-scale
input power is used as the reference.
Spurious-Free-Dynamic Range (SFDR) is the ratio of
the RMS signal amplitude to the RMS value of the largest
spurious spectral component. The largest spurious
spectral component may or may not be a harmonic.
33
FN7565.1
June 4, 2010
ISLA118P50
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
5/19/10
FN7565.1
-On page 1:
Removed CLKDIV from key feature list (Selectable Clock Divider: ÷1 or ÷2)
Removed CLKDIV pin from “Block Diagram”(was right nexto to CLKDIVRSTP pin)
-On page 3:
Removed CLKDIV pin from “Pin Configuration” diagram, replaced with a DNC pin (pin 16)
-On page 4:
Removed CLKDIV pin from “Pin Descriptions” list, added pin 16 to DNC list
-On page 8:
Under “CMOS INPUTS” in the “Digital Specifications” table, added CSB and SCLK to the CMOS pin list
(in Parameter column) for I_IH, I_IL, V_IH, V_IL
Removed CLKDIV reference from “Input Current High (OUTMODE, NAPSLP, OUTFMT) (Note 14)” and
“Input Current Low (OUTMODE, NAPSLP, OUTFMT)” specs
-On page 16:
Removed text and table describing CLKDIV function
-On page 20:
Removed sentences referencing the “2GSPS” block diagram under the “Clock Divider Synchronous
Reset” section as we no longer support this clock distribution block diagram, nor su/hold times to
support closing timing at 1GHz input clock
-On page 21:
Removed Sync generation block diagram (former FIGURE 38. SYNCHRONIZATION SCHEME) because
we no longer support this architecture
-On page 26:
Updated “Address 0x71: phase_slip” section to reflect functionality in the CLKDIV1 mode. New timing
diagram Figure 44 to show functionality.
Removed the “ADDRESS 0X72: CLOCK_DIVIDE” section and table for SPI address 0x72, clock_divide
feature
-On page 29:
Removed the clock_divide SPI register from Table 15 under ADDR 72, replacing with Reserved (and
indicating which bits must be set to 0)
-On page 32:
Removed the CLKDIV reference in “Unused Inputs” section
3/30/10
FN7565.0
Initial Release of Production Datasheet
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISLA118P50
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
34
FN7565.1
June 4, 2010
ISLA118P50
Package Outline Drawing
L72.10x10C
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN)
Rev 0, 7/07
10.00
A
9.75
X
B
EXPOSED PAD AREA
Z
72
72
1
6
PIN 1
INDEX AREA
9.75
8.50 REF.
(4X)
1
10.00
6
PIN #1 INDEX AREA
68X 0.50
4 0.23
(4X)
0.15
72X 0.50 ±0.1 mm
6.00 REF.
(4X)
TOP VIEW
0.100 M C A B
BOTTOM VIEW
PACKAGE OUTLINE
R0.200
10.00
0.450
6.00
(0
.1
AR 2 5
O )
U
N
D
)
(68X 0.50)
C0.400 X 45°
(4X)
(72X 0.23)
1
TYPICAL RECOMMENDED LAND PATTERN
DETAIL “X”
72
R0.115
TYP.
DETAIL “Z”
11° ±1° ALL AROUND
(A
L
(72X 0.20)
(72X 0.70)
LL
R0.200
TYP.
Y
9.75
10.00
SIDE VIEW
R0.200 MAX
ALL AROUND
0.100 C
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
0.65
0.85
2. Dimensioning and tolerancing conform to JESD-MO220.
3. Unless otherwise specified, tolerance : Decimal ± 0.05;
body tolerance: ±0.1mm
0.19~ 0.245
SEATING
PLANE
0.08 C
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
35
e
0.25 ±0.02
C
b
0.100 M C A B
0.050 M C
DETAIL “Y”
FN7565.1
June 4, 2010
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