Product Folder Sample & Buy Support & Community Tools & Software Technical Documents ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 ISO76x1 Low-Power Triple and Quad-Channels Digital Isolators 1 Features 3 Description • The ISO7631F and ISO7641F devices provide galvanic isolation up to 4242 VPK per VDE. The ISO7631F device has three channels, two of which operate in the forward direction and one which operates in the reverse direction. The ISO7641F device has 4 channels, three of which operate in the forward direction and one of which operates in the reverse direction. Suffix F indicates that output defaults to low-state in fail-safe conditions (see ). MGrade devices are high-speed isolators capable of up to150-Mbps data rates with fast propagation delays, whereas C-Grade devices are capable of up to 25Mbps data rates with low power consumption and integrated filters for noise-prone applications. CGrade devices are recommended for lower-speed applications where input noise pulses of less than 6 ns duration must be suppressed, or when low-power consumption is critical. 1 • • • • • • • • • • • • Signaling Rate: 150 Mbps (M-Grade), 25 Mbps (C-Grade) Robust Design with Integrated Noise Filter (C-Grade) Low Power Consumption, Typical ICC per Channel (3.3-V Supplies): – ISO7631FM: 2 mA at 10 Mbps – ISO7631FC: 1.5 mA at 10 Mbps – ISO7641FC: 1.3 mA at 10 Mbps Extremely-Low ICC_disable (C-Grade) Low Propagation Delay: 7 ns Typical (M-Grade) Output Defaults to Low-State in Fail-Safe Mode Wide Temperature Range: –40°C to 125°C 50 KV/µs Transient Immunity, Typical Long Life With SiO2 Isolation Barrier Operates From 2.7-V (M-Grade), 3.3-V and 5-V Supply and Logic Levels 2.7-V (M-Grade), 3.3-V and 5-V Level Translation Wide Body SOIC-16 Package Safety and Regulatory Approvals – 2500 VRMS Isolation for 1 Minute per UL 1577 – 4242 VPK Basic Insulation per DIN V VDE V 0884-10 and DIN EN 61010-1 – CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 61010-1 End Equipment Standards – CQC Certification per GB4943.1-2011 – TUV 3000 VRMS Reinforced Insulation according to EN/UL/CSA 60950-1 and EN/UL/CSA 61010-1 Each isolation channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. The devices have TTL input thresholds and can operate from 2.7-V (M-Grade), 3.3-V and 5-V supplies. All inputs are 5-V tolerant when supplied from 3.3-V or 2.7-V supplies. Device Information(1) PART NUMBER ISO7631FC Optocoupler Replacement in: – Industrial Fieldbus – Profibus – Modbus – DeviceNet™ Data Buses – Servo Control Interface – Motor Control – Power Supplies – Battery Packs BODY SIZE (NOM) SOIC (16) 10.30 mm × 7.50 mm ISO7641FC (1) For all available packages, see the orderable addendum at the end of the datasheet. 2 Applications • PACKAGE ISO7631FM Simplified Schematic VCCI Isolation Capacitor VCCO INx OUTx ENx GNDI GNDO (1) VCCI and GNDI are supply and ground connections respectively for the input channels. (2) VCCO and GNDO are supply and ground connections respectively for the output channels. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Available Options................................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.17 Switching Characteristics: VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% ................................................ 11 7.18 Switching Characteristics: VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% ................................................... 12 7.19 Switching Characteristics: VCC1 and VCC2 at 3.3 V ± 10% .......................................................................... 12 7.20 Switching Characteristics: VCC1 and VCC2 at 2.7 V ................................................................................. 13 7.21 Typical Characteristics .......................................... 14 1 1 1 2 4 4 5 7.1 7.2 7.3 7.4 7.5 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information ................................................. 6 Electrical Characteristics: VCC1 and VCC2 at 5 V ± 10% ............................................................................ 6 7.6 Electrical Characteristics: VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% .................................................. 6 7.7 Electrical Characteristics: VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% ..................................................... 7 7.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ± 10% ............................................................................ 7 7.9 Electrical Characteristics: VCC1 and VCC2 at 2.7 V (ISO7631FM Only)..................................................... 7 7.10 Power Dissipation Characteristics .......................... 7 7.11 Supply Current Characteristics: VCC1 and VCC2 at 5 V ± 10% ..................................................................... 8 7.12 Supply Current Characteristics: VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% ........................................... 9 7.13 Supply Current Characteristics: VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% .............................................. 9 7.14 Supply Current Characteristics: VCC1 and VCC2 at 3.3 V ± 10% ............................................................. 10 7.15 Supply Current Characteristics: VCC1 and VCC2 at 2.7 V (ISO7631FM Only) ........................................ 10 7.16 Switching Characteristics: VCC1 and VCC2 at 5 V ± 10% .......................................................................... 11 8 9 Parameter Measurement Information ................ 17 Detailed Description ............................................ 19 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 19 19 20 22 10 Application and Implementation........................ 23 10.1 Application Information.......................................... 23 10.2 Typical Application ............................................... 24 11 Power Supply Recommendations ..................... 27 12 Layout................................................................... 27 12.1 Layout Guidelines ................................................. 27 12.2 Layout Example .................................................... 27 13 Device and Documentation Support ................. 28 13.1 13.2 13.3 13.4 13.5 13.6 Documentation Support ........................................ Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 28 28 28 28 28 28 14 Mechanical, Packaging, and Orderable Information ........................................................... 28 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (September 2013) to Revision E Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ............................. 1 • Added 2.7-V (M-Grade), 3.3-V and 5-V Level Translation to Features section ..................................................................... 1 • Deleted marked as column from Available Options table....................................................................................................... 4 • Added Footnote 3 to Absolute Maximum Ratings table. ........................................................................................................ 5 • Changed thermal metric values in the Thermal Information table. ........................................................................................ 6 • Changed VCCX to VCCOin Electrical Characteristics: VCC1 and VCC2 at 5 V ± 10% table. ........................................................ 6 • Added cross-reference to VI = VCCI in the Electrical Characteristics: VCC1 and VCC2 at 5 V ± 10% table. ....................... 6 • Changed Footnote 1 of the Electrical Characteristics: VCC1 and VCC2 at 5 V ± 10% table for clarification. ..................... 6 • Added cross-reference to VI = VCCI in the Electrical Characteristics: VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% table. ....................................................................................................................................................................................... 6 • Added footnote to the Electrical Characteristics: VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% table. .............................. 7 • Changed VCCX to VCCO in the Electrical Characteristics: VCC1 and VCC2 at 3.3 V ± 10% table. ........................................ 7 2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 Revision History (continued) • Changed footnote 1 in the Electrical Characteristics: VCC1 and VCC2 at 3.3 V ± 10% table for clarification. ..................... 7 • Changed VCCX to VCCO in the Electrical Characteristics: VCC1 and VCC2 at 2.7 V table. ................................................... 7 • Deleted IEC and for DW-16 Package from IEC Package Insulation and Safety-Related Specifications for DW-16 Package section. .................................................................................................................................................................. 20 • Changed L(I01) MIN from 8.3 mm to 8 mm, L(IO2) MIN from 8.1 mm to 8 mm, and DIN IEC 60112 / VDE 0303 Part 1 to DIN EN 60112 (VDE 0303-11); IEC 60112 in the Package Insulation and Safety-Related Specifications table. ....... 20 • Deleted footnote 2 from Package Insulation and Safety-Related Specifications IEC and for DW-16 Package from IEC Package Insulation and Safety-Related Specifications for DW-16 Package section.. .................................................. 20 • Changed VDE Standard to DIN V VDE V 0884-10 (VDE V 0084-10): 2006-12. ................................................................ 21 • Changed the value for θJA from 72 °C/W to 77.5 °C/W for the Test Conditions and the values for Safety input, output, or supply current max from 316, 482, and 643 to 293, 448 and 597 in the Safety Limiting Values table. ............. 22 • Changed safety temperature to case temperature in Safety Limiting Values. ..................................................................... 22 • Changed name of DW-16 θJC Thermal Derating Curve per IEC 64747-5-2 to Thermal Derating Curve for Safety Limiting Current per VDE...................................................................................................................................................... 22 • Changed graph in Safety Limiting Values section. .............................................................................................................. 22 • Changed I/O schematics figure in Feature Description section. ......................................................................................... 23 Changes from Revision C (August 2013) to Revision D Page • Deleted 2500 VRMS from Rated Isolation Data ....................................................................................................................... 4 • Changed the REGULATORY INFORMATION table, TUV column From: Certificate Number: U8V 13 07 77311 009 To: Certificate Number: U8V 13 09 77311 010 .................................................................................................................... 21 Changes from Revision B (April 2013) to Revision C Page • Deleted the device image from the top of the page ............................................................................................................... 1 • Deleted device number ISO7640FC....................................................................................................................................... 1 • Changed the Description ........................................................................................................................................................ 1 • Deleted ISO7640FC from the Available Options table ........................................................................................................... 4 • Changed The ISO7631FC Rated Isolation values in the Available Options table ................................................................. 4 • Deleted Graph ISO7640FC Supply Current Per Channel vs Data Rate .............................................................................. 14 • Deleted Graph ISO7640FC Supply Current For All Channels vs Data Rate ....................................................................... 14 • Added the TUV column to the REGULATORY INFORMATION table ................................................................................. 21 • Deleted ISO7640FC from the TYPICAL SUPPLY CURRENT EQUATIONS section .......................................................... 25 • Deleted the ISO7640 circuit from the APPLICATION INFORMATION section.................................................................... 27 Changes from Revision A (September 2012) to Revision B Page • Changed the VIOTM SPECIFICATION From: 4000 VPEAK to 4242 VPEAK............................................................................... 21 • Changed the REGULATORY INFORMATION table: 4242 VPK To: 4000 VPK .................................................................... 21 Changes from Original (September 2012) to Revision A Page • Changed Description text From: "applications where input noise pulses of less than 10 ns duration..." To:"applications where input noise pulses of less than 6 ns duration..."................................................................................ 1 • Added note Product Preview to ISO7640FC in the Available Options table.......................................................................... 4 • Changed Input PU in the Function table From: Z To: 'Undetermined .................................................................................. 22 Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7631FM ISO7631FC ISO7641FC 3 ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com 5 Available Options PRODUCT RATED ISOLATION (1) PACKAGE INPUT THRESHOLD DATA RATE INTEGRATED NOISE FILTER CHANNEL DIRECTION ISO631FM 4242 VPK DW-16 ~1.5 V TTL 150 Mbps No 2 Forward, 1 Reverse ISO7631FC 4242 VPK DW-16 ~1.5 V TTL 25 Mbps Yes 2 Forward, 1 Reverse ISO7641FC 4242 VPK DW-16 ~1.5 V TTL 25 Mbps Yes 3 Forward, 1 Reverse (1) See the Regulatory Information table for detailed isolation ratings. 6 Pin Configuration and Functions ISO7641 DW Package 16-Pin SOIC Top View ISO07631 DW Package 16-Pin SOIC Top View VCC1 GND1 1 16 VCC1 GND1 16 15 VCC2 GND2 1 2 2 15 VCC2 GND2 INA 3 14 OUTA INA 3 14 OUTA INB 4 13 OUTB INB 4 13 OUTB INC OUTD 5 12 OUTC 5 12 INC 6 11 IND OUTC NC 6 11 NC EN1 GND1 7 10 10 9 EN1 GND1 7 8 EN2 GND2 8 9 EN2 GND2 Pin Functions PIN NAME I/O DESCRIPTION 7 I Enables (when input is High or Open) or Disables (when input is Low) OUTD of ISO7641 and OUTC of ISO7631 10 I Enables (when input is High or Open) or Disables (when input is Low) OUTA, OUTB, and OUTC of ISO7641 Enables (when input is High or Open) or Disables (when input is Low) OUTA and OUTB of ISO7631 ISO7641 ISO7631 EN1 7 EN2 10 GND1 2, 8 2, 8 – Ground connection for VCC1 GND2 9, 15 9, 15 – Ground connection for VCC2 INA 3 3 I Input, channel A INB 4 4 I Input, channel B INC 5 12 I Input, channel C IND 11 – I Input, channel D NC – 6,11 – No Connect pins are floating with no internal connection OUTA 14 14 O Output, channel A OUTB 13 13 O Output, channel B OUTC 12 5 O Output, channel C OUTD 6 – O Output, channel D VCC1 1 1 – Power supply, VCC1 VCC2 16 16 – Power supply, VCC2 4 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 7 Specifications 7.1 Absolute Maximum Ratings See (1) VCC1 VCC2 (2) Supply voltage Voltage INx, OUTx, ENx IO Output current TJ Maximum junction temperature TSTG Storage temperature (1) (2) (3) MIN MAX UNIT –0.5 6 V –0.5 (3) 6 –65 V ±15 mA 150 °C 150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values. Maximum voltage must not exceed 6 V. 7.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1500 Machine model (MM), JEDEC JESD22-A115-A ±200 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions MIN VCC1, VCC2 Supply voltage IOH High-level output current IOL Low-level output current VIH High-level input voltage VIL Low-level input voltage tui Input pulse duration NOM MAX M-Grade 2.7 5.5 C-Grade 3 5.5 –4 UNIT V mA 4 mA 2 5.5 V 0 0.8 V M-Grade: ≥3-V Operation 6.67 M-Grade: <3-V Operation 10 C-Grade: ≥3-V Operation 40 M-Grade: ≥3-V Operation 0 150 M-Grade: <3-V Operation 0 100 ns 1 / tui Signaling rate 0 25 TJ Junction temperature –40 136 °C TA Ambient temperature –40 125 °C C-Grade: ≥3-V Operation Copyright © 2012–2015, Texas Instruments Incorporated 25 Submit Documentation Feedback Product Folder Links: ISO7631FM ISO7631FC ISO7641FC Mbps 5 ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com 7.4 Thermal Information ISO76x1Fx THERMAL METRIC (1) DW (SOIC) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 77.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 40.4 °C/W RθJB Junction-to-board thermal resistance 42.2 °C/W ψJT Junction-to-top characterization parameter 15 °C/W ψJB Junction-to-board characterization parameter 41.6 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics: VCC1 and VCC2 at 5 V ± 10% VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS C-Grade MIN TYP IOH = –4 mA; see Figure 16 VCCO (1) – 0.8 IOH = –20 μA; see Figure 16 VCCO – 0.1 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCC at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx CMTI Common-mode transient immunity (1) M-Grade MAX MIN TYP 4.8 VCCO – 0.8 4.7 5 VCCO – 0.1 5 MAX V IOL = 4 mA; see Figure 16 0.2 0.4 0.3 0.5 IOL = 20 μA; see Figure 16 0 0.1 0 0.1 450 VI = VCCI (1) or 0 V; see Figure 19 V 450 mV 10 μA 10 –10 μA -10 25 75 25 UNIT 75 kV/μs VCCI = Input-side supply voltage; VCCO = Output-side supply voltage 7.6 Electrical Characteristics: VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER High-level output voltage VOH TEST CONDITIONS C-Grade MAX MIN TYP OUTx on VCC1 (5 V) side VCC1 – 0.8 4.8 VCC1 – 0.8 4.7 OUTx on VCC2 (3.3 V) side VCC2 - 0.4 3 VCC2 - 0.6 2.9 IOH = –20 μA; see Figure 16 OUTx on VCC1 (5 V) side VCC1 – 0.1 5 VCC1 – 0.1 5 OUTx on VCC2 (3.3 V) side VCC2 – 0.1 3.3 VCC2 – 0.1 3.3 MAX 0.2 0.4 0.3 0.5 IOL = 20 μA; see Figure 16 0 0.1 0 0.1 VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCC at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx CMTI Common-mode transient immunity 430 VI = VCCI (1) or 0 V; see Figure 19 430 10 -10 25 25 V mV 10 μA μA -10 50 UNIT V IOL = 4 mA; see Figure 16 VOL 6 TYP IOH = –4 mA; see Figure 16 Low-level output voltage (1) M-Grade MIN 50 kV/μs VCCI = Input-side supply voltage Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 7.7 Electrical Characteristics: VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER VOH MIN C-Grade TYP MAX MIN TYP IOH = –4 mA; see Figure 16 OUTx on VCC1 (3.3 V) side VCC1–0.4 3 VCC1-0.6 2.9 OUTx on VCC2 (5 V) side VCC2–0.8 4.8 VCC2–0.8 4.7 IOH = –20 μA; see Figure 16 OUTx on VCC1 (3.3 V) side VCC1–0.1 3.3 VCC1–0.1 3.3 OUTx on VCC2 (5 V) side VCC2–0.1 High-level output voltage 5 VCC2–0.1 MAX 5 0.2 0.4 0.3 0.5 IOL = 20 μA; see Figure 16 0 0.1 0 0.1 Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCC at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx CMTI Common-mode transient immunity VI = VCCI 430 (1) 430 or 0 V; see Figure 19 10 50 μA μA -10 25 V mV 10 -10 UNIT V IOL = 4 mA; see Figure 16 VOL (1) M-Grade TEST CONDITIONS 25 50 kV/μs VCCI = Input-side supply voltage 7.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ± 10% VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER MIN IOH = –4 mA; see Figure 16 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCC at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx CMTI Common-mode transient VI = VCCI immunity (1) M-Grade TEST CONDITIONS VCCO IOH = –20 μA; see Figure 16 (1) C-Grade TYP MAX MIN TYP – 0.4 3 VCCO – 0.6 2.9 VCCO – 0.1 3.3 VCCO – 0.1 3.3 V IOL = 4 mA; see Figure 16 0.2 0.4 0.3 0.5 IOL = 20 μA; see Figure 16 0 0.1 0 0.1 425 (1) mV 10 25 V 425 μA 10 -10 or 0 V; see Figure 19 UNIT MAX μA -10 50 25 50 kV/μs VCCI = Input-side supply voltage; VCCO = Output-side supply voltage 7.9 Electrical Characteristics: VCC1 and VCC2 at 2.7 V (ISO7631FM Only) VCC1 and VCC2 at 2.7 V (1) (over recommended operating conditions unless otherwise noted) PARAMETER MIN TYP IOH = –4 mA; see Figure 16 TEST CONDITIONS VCCO (2) – 0.5 2.4 IOH = –20 μA; see Figure 16 VCCO – 0.1 2.7 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCC at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx CMTI (1) (2) IOL = 4 mA; see Figure 16 IOL = 20 μA; see Figure 16 MAX UNIT V 0.2 0.4 0 0.1 V 350 Common-mode transient immunity VI = VCCI (2) mV μA 10 μA -10 or 0 V; see Figure 19 25 50 kV/μs Only M-Grade devices are recommended for operation down to 2.7 V supplies. For 2.7 V-operation, max data rate is 100 Mbps. VCCI = Input-side supply voltage; VCCO = Output-side supply voltage 7.10 Power Dissipation Characteristics PARAMETER PD TEST CONDITIONS Maximum Device Power Dissipation Copyright © 2012–2015, Texas Instruments Incorporated MIN VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF Input a 75 MHz 50% duty cycle square wave TYP MAX UNIT 399 mW Submit Documentation Feedback Product Folder Links: ISO7631FM ISO7631FC ISO7641FC 7 ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com 7.11 Supply Current Characteristics: VCC1 and VCC2 at 5 V ± 10% VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS M-Grade MIN TYP C-Grade MAX MIN TYP MAX UNIT ISO7631F ICC1 Disable ICC2 ICC1 EN1 = EN2 = 0 V DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 ICC1 25 Mbps ICC2 ICC1 DC Signal: VI = VCC or 0 V AC Signal: All channels switching with square wave clock input; CL = 15 pF 150 Mbps ICC2 2.5 4 1.1 1.9 mA 3.7 5.4 1.5 2.6 mA 2.6 4.1 1.8 2.7 mA 3.8 5.5 2.6 3.9 mA 3.3 4.5 2.7 3.7 mA 4.9 6.6 3.9 5.3 mA 4.5 6 4.1 5.4 mA 6.8 9 5.9 7.8 mA 15 19.5 Not Applicable mA 22 30 Not Applicable mA ISO7641F ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 8 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF 25 Mbps Submit Documentation Feedback 1.2 2.1 mA 1.6 2.6 mA 1.8 2.8 mA 3.1 4.2 mA 3 4 mA 4.9 6.1 mA 4.8 6 mA 7.7 9.5 mA Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 7.12 Supply Current Characteristics: VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS M-Grade MIN TYP C-Grade MAX MIN TYP MAX UNIT ISO7631F ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC Signal: VI = VCC or 0 V AC Signal: All channels switching with square wave clock input; CL = 15 pF 150 Mbps 2.5 4 1.1 1.9 mA 2.7 3.7 0.7 1.3 mA 2.6 4.1 1.8 2.7 mA 2.8 3.8 1.8 2.6 mA 3.3 4.5 2.7 3.7 mA 3.5 4.6 2.6 3.5 mA 4.5 6 4.1 5.4 mA 4.7 5.9 3.8 5 mA 15 19.5 Not Applicable mA 14.6 19 Not Applicable mA ISO7641F ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF 25 Mbps 1.2 2.1 mA 0.8 1.3 mA 1.8 2.8 mA 2 2.9 mA 3 4 mA 3.2 4.1 mA 4.8 6 mA 5.1 7 mA 7.13 Supply Current Characteristics: VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS M-Grade MIN C-Grade MIN TYP MAX UNIT TYP MAX 1.8 2.8 0.6 1.1 mA 3.7 5.4 1.5 2.6 mA 1.9 2.9 1.2 1.8 mA 3.8 5.5 2.6 3.9 mA 2.4 3.4 1.8 2.6 mA 4.9 6.6 3.9 5.3 mA 3.2 4.2 2.7 3.6 mA 6.8 9 5.9 7.8 mA 9.3 12.5 Not Applicable mA 22 30 Not Applicable mA ISO7631F ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC Signal: VI = VCC or 0 V AC Signal: All channels switching with square wave clock input; CL = 15 pF 150 Mbps ISO7641F ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF 25 Mbps Copyright © 2012–2015, Texas Instruments Incorporated 0.7 1.1 mA 1.6 2.6 mA 1.2 1.9 mA 3.1 4.2 mA 2 2.8 mA 4.9 6.1 mA 3.1 4 mA 7.7 9.5 mA Submit Documentation Feedback Product Folder Links: ISO7631FM ISO7631FC ISO7641FC 9 ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com 7.14 Supply Current Characteristics: VCC1 and VCC2 at 3.3 V ± 10% VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS M-Grade MIN C-Grade MIN TYP MAX UNIT TYP MAX 1.8 2.8 0.6 1.1 mA 2.7 3.7 0.7 1.3 mA 1.9 2.9 1.2 1.8 mA 2.8 3.8 1.8 2.6 mA 2.4 3.4 1.8 2.6 mA 3.5 4.6 2.6 3.5 mA 3.2 4.2 2.7 3.6 mA 4.7 5.9 3.8 5 mA 9.3 12.5 Not Applicable mA 14.6 19 Not Applicable mA ISO7631F ICC1 Disable ICC2 ICC1 EN1 = EN2 = 0 V DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 ICC1 25 Mbps ICC2 ICC1 DC Signal: VI = VCC or 0 V AC Signal: All channels switching with square wave clock input; CL = 15 pF 150 Mbps ICC2 ISO7641F ICC1 Disable ICC2 ICC1 EN1 = EN2 = 0 V DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 ICC1 DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF 25 Mbps ICC2 0.7 1.1 mA 0.8 1.3 mA 1.2 1.9 mA 2 2.9 mA 2 2.8 mA 3.2 4.1 mA 3.1 4 mA 5.1 7 mA 7.15 Supply Current Characteristics: VCC1 and VCC2 at 2.7 V (ISO7631FM Only) VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted) PARAMETER M-Grade TEST CONDITIONS MIN UNIT TYP MAX 1.5 2.4 mA 2.2 3.2 mA 1.6 2.5 mA 2.3 3.2 mA 2 2.9 mA 3 3.9 mA 2.7 3.7 mA 3.9 4.9 mA 5.7 6.8 mA 8.6 12 mA ISO7631F ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 10 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps DC Signal: VI = VCC or 0 V AC Signal: All channels switching with square wave clock input; CL = 15 pF 25 Mbps 100 Mbps Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 7.16 Switching Characteristics: VCC1 and VCC2 at 5 V ± 10% VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS M-Grade C-Grade MIN TYP MAX MIN TYP MAX 3.5 7 10.5 11 17 UNIT ISO7631F, ISO7641F tPLH, tPHL Propagation delay time See Figure 16 28 ns PWD (1) Pulse width distortion |tPHL – tPLH| See Figure 16 2 3 ns Same-direction Channels 2 3 Opposite-direction Channels 3 4 tsk(o) (2) Channel-to-channel output skew time tsk(pp) (3) Part-to-part skew time tr Output signal rise time See Figure 16 1.6 2.8 ns tf Output signal fall time See Figure 16 1 2.9 ns tPHZ Disable Propagation Delay, high-to-high impedance output See Figure 17 5 16 8 20 ns tPLZ Disable Propagation Delay, low-to-high impedance output See Figure 17 5 16 7 20 ns tPZH Enable Propagation Delay, high impedance-to-high output See Figure 17 4 16 11000 22000 (4) ns tPZL Enable Propagation Delay, high impedance-to-low output See Figure 17 4 16 8 20 ns tfs Fail-safe output delay time from input data or power loss See Figure 18 9.5 (1) (2) (3) (4) 4.5 ns 13 ns μs 9 Also known as Pulse Skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. The enable signal rate for C-grade devices should be ≤ 45 Kbps. 7.17 Switching Characteristics: VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS M-Grade C-Grade MIN TYP MAX MIN TYP 4 8 13 11 18 MAX UNIT ISO7631F, ISO7641F tPLH, tPHL Propagation delay time See Figure 16 PWD (1) Pulse width distortion |tPHL – tPLH| See Figure 16 32 ns 2 3.5 ns Same-direction Channels 2.5 4.5 Opposite-direction Channels 3.5 5.5 tsk(o) (2) Channel-to-channel output skew time tsk(pp) (3) Part-to-part skew time tr Output signal rise time See Figure 16 2 3.6 ns tf Output signal fall time See Figure 16 1.2 3.3 ns tPHZ Disable Propagation Delay, high-tohigh impedance output See Figure 17 6.5 17 9 20 ns tPLZ Disable Propagation Delay, low-tohigh impedance output See Figure 17 6.5 17 8 20 ns tPZH Enable Propagation Delay, high impedance-to-high output See Figure 17 5.5 17 11000 22000 (4) ns tPZL Enable Propagation Delay, high impedance-to-low output See Figure 17 5.5 17 10 30 ns tfs Fail-safe output delay time from input data or power loss See Figure 18 9.5 (1) (2) (3) (4) 6 15 8.5 ns ns μs Also known as Pulse Skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. The enable signal rate for C-grade devices should be ≤ 45 Kbps. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7631FM ISO7631FC ISO7641FC 11 ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com 7.18 Switching Characteristics: VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS M-Grade C-Grade MIN TYP MAX MIN TYP 4 7.5 12.5 11 18.5 MAX UNIT ISO7631F, ISO7641F tPLH, tPHL Propagation delay time See Figure 16 PWD (1) Pulse width distortion |tPHL – tPLH| See Figure 16 32 ns 2 2.5 ns Same-direction Channels 2.5 4.5 Opposite-direction Channels 3.5 5.5 tsk(o) (2) Channel-to-channel output skew time tsk(pp) (3) Part-to-part skew time tr Output signal rise time See Figure 16 1.7 2.9 ns tf Output signal fall time See Figure 16 1.1 2.9 ns tPHZ Disable Propagation Delay, high-to-high impedance output See Figure 17 5.5 17 8 20 ns tPLZ Disable Propagation Delay, low-to-high impedance output See Figure 17 5.5 17 7 20 ns tPZH Enable Propagation Delay, high impedance-to-high output See Figure 17 4.5 17 11000 22000 (4) ns tPZL Enable Propagation Delay, high impedance-to-low output See Figure 17 4.5 17 8 30 ns tfs Fail-safe output delay time from input data or power loss See Figure 18 9.5 (1) (2) (3) (4) 6 15 ns ns μs 7.5 Also known as Pulse Skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. The enable signal rate for C-grade devices should be ≤ 45 Kbps. 7.19 Switching Characteristics: VCC1 and VCC2 at 3.3 V ± 10% VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS M-Grade C-Grade MIN TYP MAX MIN TYP MAX 4 8.5 14 12 23 UNIT ISO7631F, ISO7641F tPLH, tPHL Propagation delay time See Figure 16 35 ns PWD (1) Pulse width distortion |tPHL – tPLH| See Figure 16 2 3 ns Same-direction Channels 3 5 Opposite-direction Channels 4 6 tsk(o) (2) Channel-to-channel output skew time tsk(pp) (3) Part-to-part skew time tr Output signal rise time See Figure 16 2 3.7 ns tf Output signal fall time See Figure 16 1.3 3.4 ns tPHZ Disable Propagation Delay, high-to-high impedance output See Figure 17 6.5 17 9 20 ns tPLZ Disable Propagation Delay, low-to-high impedance output See Figure 17 6.5 17 8 20 ns tPZH Enable Propagation Delay, high impedance-to-high output See Figure 17 5.5 17 11000 22000 (4) ns tPZL Enable Propagation Delay, high impedance-to-low output See Figure 17 5.5 17 10 30 ns tfs Fail-safe output delay time from input data or power loss See Figure 18 9.2 (1) (2) (3) (4) 12 6.5 16 7.5 ns ns μs Also known as Pulse Skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. The enable signal rate for C-grade devices should be ≤ 45 Kbps. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 7.20 Switching Characteristics: VCC1 and VCC2 at 2.7 V VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted) PARAMETER M-Grade TEST CONDITIONS MIN TYP 5 8 MAX UNIT ISO7631F, ISO7641F tPLH, tPHL Propagation delay time See Figure 16 PWD (1) Pulse width distortion |tPHL – tPLH| See Figure 16 16 ns 2.5 ns Same-direction Channels 4 Opposite-direction Channels 5 tsk(o) (2) Channel-to-channel output skew time tsk(pp) (3) Part-to-part skew time tr Output signal rise time See Figure 16 2.3 ns tf Output signal fall time See Figure 16 1.8 ns tPHZ Disable Propagation Delay, high-to-high impedance output See Figure 17 8 18 ns tPLZ Disable Propagation Delay, low-to-high impedance output See Figure 17 8 18 ns tPZH Enable Propagation Delay, high impedance-tohigh output See Figure 17 7 18 ns tPZL Enable Propagation Delay, high impedance-tolow output See Figure 17 7 18 ns tfs Fail-safe output delay time from input data or power loss See Figure 18 8.5 (1) (2) (3) 8 ns ns μs Also known as Pulse Skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7631FM ISO7631FC ISO7641FC 13 ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com 7.21 Typical Characteristics 8 24 ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V 6 5 4 3 2 0 20 40 60 80 100 Data Rate (Mbps) 120 140 12 8 0 160 TA = 25°C CL = 15 pF 0 20 40 G200 Figure 1. ISO7631FM Supply Current Per Channel vs Data Rate 60 80 100 Data Rate (Mbps) Supply Current (mA) 1 5 3 2 0 5 10 15 Data Rate (Mbps) 20 TA = 25°C CL = 15 pF 1 TA = 25°C CL = 15 pF 0 25 0 5 G202 Figure 3. ISO7631FC Supply Current Per Channel vs Data Rate 10 15 Data Rate (Mbps) 20 25 G203 Figure 4. ISO7631FC Supply Current For All Channels vs Data Rate 2.5 8 ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V TA = 25°C CL = 15 pF ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V 7 Supply Current (mA) 2 Supply Current (mA) G201 4 0.5 1.5 1 0.5 6 5 4 3 2 TA = 25°C CL = 15 pF 1 0 5 10 15 Data Rate (Mbps) 20 25 Submit Documentation Feedback 0 0 5 G102 Figure 5. ISO7641FC Supply Current Per Channel vs Data Rate 14 160 ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V 6 1.5 0 140 7 ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V 2 0 120 Figure 2. ISO7631FM Supply Current For All Channels vs Data Rate 2.5 Supply Current (mA) 16 4 TA = 25°C CL = 15 pF 1 0 ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V 20 Supply Current (mA) Supply Current (mA) 7 10 15 Data Rate (Mbps) 20 25 G103 Figure 6. ISO7641FC Supply Current For All Channels vs Data Rate Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 Typical Characteristics (continued) 6 VCC = 5 V VCC = 3.3 V 5 4 3 2 1 0 −70 −60 −50 −40 −30 −20 High−Level Output Current (mA) −10 5 3 2 1 0 0 0 10 G005 20 30 40 50 Low−Level Output Current (mA) 60 70 G006 Figure 8. M-Grade Low-Level Output Voltage vs Low-Level Output Current 6 6 VCC = 3.3 V VCC = 5 V 5 4 3 2 1 0 −30 −25 VCC = 3.3 V VCC = 5 V TA = 25°C Low−Level Output Voltage (V) High−Level Output Voltage (V) TA = 25°C 4 Figure 7. M-Grade High-Level Output Voltage vs High-Level Output Current −20 −15 −10 High−Level Output Current (mA) −5 5 3 2 1 0 0 TA = 25°C 4 0 5 10 15 20 25 30 35 Low−Level Output Current (mA) G104 Figure 9. C-Grade High-Level Output Voltage vs High-Level Output Current 40 45 G105 Figure 10. C-Grade Low-Level Output Voltage vs Low-Level Output Current 2.52 11 2.5 Propagation Delay Time (ns) Power Supply Under Voltage Threshold (V) VCC = 3.3 V VCC = 5 V TA = 25°C Low−Level Output Voltage (V) High−Level Output Voltage (V) 6 2.48 2.46 VCC Rising VCC Falling 2.44 2.42 2.4 tPLH at 3.3 V tPHL at 3.3 V tPHL at 5 V tPLH at 5 V 10 9 8 7 2.38 CL = 15 pF 2.36 −40 −20 0 20 40 60 80 Free−Air Temperature (°C) 100 Figure 11. VCC Undervoltage Threshold vs Free Air Temperature Copyright © 2012–2015, Texas Instruments Incorporated 120 G007 6 −40 −15 10 35 60 85 110 Free−Air Temperature (°C) 135 150 G008 Figure 12. M-Grade Propagation Delay Time vs Free Air Temperature Submit Documentation Feedback Product Folder Links: ISO7631FM ISO7631FC ISO7641FC 15 ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) 1 tPLH at 3.3 V tPHL at 3.3 V tPLH at 5 V tPHL at 5 V 26 0.9 Pk-Pk Output Jitter (ns) Propagation Delay Time (ns) 28 24 22 20 18 −20 0 20 40 60 80 100 Free−Air Temperature (°C) 120 0.7 0.6 0.5 0.4 0.3 0 140 TA = 25°C CL = 15 pF All Channels Switching Typ Jitter on output pin shown 0.2 VCC = 5 V VCC = 3.3 V 0.1 CL = 15 pF 16 −40 0.8 0 20 40 G106 Figure 13. C-Grade Propagation Delay Time vs Free Air Temperature 60 80 100 120 Data Rate (Mbps) 140 160 180 G009 Figure 14. M-Grade Output Jitter vs Data Rate 1.4 Pk-Pk Output Jitter (ns) 1.2 1 0.8 0.6 0.4 0.2 0 VCC = 3.3 V VCC = 5 V 0 5 TA = 25°C CL = 15 pF All Channels Switching Typ Jitter on output pin shown 10 15 Data Rate (Mbps) 20 25 G107 Figure 15. C-Grade Output Jitter vs Data Rate 16 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 ISOLATION BARRIER 8 Parameter Measurement Information IN Input Generator NOTE A 50 W VI VCCI VI VCC/2 OUT VCC/2 0V tPHL tPLH VO CL NOTE B VOH 90% VO 50% 10% tf tr 50% VOL A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 16. Switching Characteristics Test Circuit and Voltage Waveforms VCCO VCC ISOLATION BARRIER 0V R L = 1 k W ± 1% IN Input Generator EN VCC/2 VI OUT VO 0V tPLZ tPZL VO CL VCC/2 VCCO 0.5 V 50% VOL NOTE B VI 50 W 3V ISOLATION BARRIER NOTE A IN Input Generator NOTE A VI VCC OUT VO VCC/2 VI VCC/2 0V EN CL NOTE B 50 W tPZH R L = 1 k W ± 1% VOH 50% VO 0.5 V tPHZ A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. 0V Figure 17. Enable/Disable Propagation Delay Time Test Circuit and Waveform Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7631FM ISO7631FC ISO7641FC 17 ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com Parameter Measurement Information (continued) VI VCCI ISOLATION BARRIER VCCI IN = VCCI 2.7 V VI 0V OUT t fs VO 50% VO CL VOH fs low V OL NOTE A A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 18. Failsafe Delay Time Test Circuit and Voltage Waveforms IN S1 C = 0.1 μ F ±1% Isolation Barrier VCCI GNDI VCCO C = 0.1 μ F ±1% Pass-fail criteria – output must remain stable. OUT + CL Note A GNDO VOH or VOL – + VCM – A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 19. Common-Mode Transient Immunity Test Circuit 18 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 9 Detailed Description 9.1 Overview The isolator in Figure 20 is based on a capacitive, isolation-barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to 150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single-ended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the lowfrequency channel. Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer. 9.2 Functional Block Diagram Isolation Barrier OSC LPF Low t Frequency Channel (DC...100 kbps) PWM VREF 0 OUT 1 S IN DCL High t Frequency Channel (100 kbps...150 Mbps) VREF Figure 20. ISO7631FM Conceptual Block Diagram Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7631FM ISO7631FC ISO7641FC 19 ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com Functional Block Diagram (continued) Isolation Barrier OSC Low t Frequency Channel (DC...100 kbps) PWM VREF LPF 0 Polarity and Threshold Selection IN OUT 1 S High t Frequency Channel (100 kbps...25 Mbps) DCL VREF Polarity and Threshold Selection Figure 21. ISO7631FC and ISO7641FC Conceptual Block Diagram 9.3 Feature Description 9.3.1 Package Insulation and Safety-Related Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (Clearance) Shortest terminal to terminal distance through air 8 mm L(I02) (1) Minimum external tracking (Creepage) Shortest terminal to terminal distance across the package surface 8 mm CTI Tracking resistance (Comparative Tracking Index) DIN EN 60112 (VDE 0303-11); IEC 60112 ≥400 V DTI Minimum Internal Gap (Internal Clearance) Distance through the insulation 0.014 mm Input capacitance VI = VCC/2 + 0.4 sin (2πft), f = 1MHz, VCC = 5 V CI (1) (2) (2) 2 pF Per JEDEC package dimensions. Measured from input pin to ground. spacer NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. 20 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 Table 1. DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics (1) PARAMETER VIORM VPR Input-to-output test voltage VIOTM RIO CIO TEST CONDITIONS Maximum working insulation voltage (2) (2) Maximum transient overvoltage Isolation resistance, Input to Output Barrier capacitance, Input to Output UNIT 1414 VPEAK After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC 1697 Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial Discharge < 5 pC 2262 Method b1, 100% Production test VPR = VIORM x 1.875, t = 1 s Partial discharge < 5 pC 2652 VTEST = VIOTM t = 60 sec (Qualification) t = 1 sec (100% Production) 4242 VIO = 500 V, TA = 25°C >1012 VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 VIO = 500 V at TS = 150°C >109 VI = 0.4 sin (2πft), f = 1MHz VPEAK VPEAK Ω 2 Pollution degree (1) (2) SPECIFICATION pF 2 Climatic Classification 40/125/21 All pins on each side of the barrier tied together creating a two-terminal device. Table 2. IEC 60664-1 Ratings Table PARAMETER TEST CONDITIONS SPECIFICATION Material Group II Installation classification / Overvoltage category for basic insulation Rated mains voltage ≤ 300 VRMS I–IV Rated mains voltage ≤ 600 VRMS I–III Rated mains voltage ≤ 1000 VRMS I–II 9.3.1.1 Regulatory Information VDE TUV CSA Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 610101 (VDE 04111):2011-07 Certified according to EN/UL/CSA 60950-1 and 61010-1 Basic Insulation Maximum Transient Overvoltage, 4242 VPK Maximum Working Voltage, 1414 VPK 3000 VRMS Reinforced Insulation, 400 VRMS maximum working voltage 3000 VRMS Basic Insulation, 600 VRMS maximum working voltage 3000 VRMS Isolation Rating Certificate number: 40016131 Certificate number: U8V 13 09 77311 010 Master contract number: 220991 (1) Approved under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 61010-1 UL CQC Recognized under 1577 Component Recognition Program Single Protection, 2500 VRMS (1) File number: E181974 Certified according to GB4943.1-2011 Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS Maximum Working Voltage Certificate number: CQC14001109542 Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7631FM ISO7631FC ISO7641FC 21 ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com 9.3.1.2 Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER TEST CONDITIONS IS Safety input, output, or supply current TS Maximum safety temperature DW-16 MIN TYP MAX θJA = 77.5 °C/W, VI = 5.5V, TJ = 150°C, TA = 25°C 293 θJA = 77.5 °C/W, VI = 3.6V, TJ = 150°C, TA = 25°C 448 θJA = 77.5 °C/W, VI = 2.7V, TJ = 150°C, TA = 25°C 597 UNIT 150 mA °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 700 VCC1 = VCC2 = 2.7 V VCC1 = VCC2 = 3.6 V VCC1 = VCC2 = 5.5 V Safety Limiting Current - mA 600 500 400 300 200 100 0 0 50 100 Ambient Temperature - (qC) 150 200 D001 D001 Figure 22. Thermal Derating Curve for Safety Limiting Current per VDE 9.4 Device Functional Modes Table 3. Function Table (1) INPUT VCC PU (1) 22 OUTPUT VCC PU INPUT (INx) OUTPUT ENABLE (ENx) OUTPUT (OUTx) H H or Open H L H or Open L X L Z Open H or Open L H or Open L PD PU X PD PU X L Z PU PD X X Undetermined PU = Powered Up(VCC ≥ 2.7 V); PD = Powered Down (VCC ≤ 2.1 V); X = Irrelevant; H = High Level; L = Low Level; Z = High Impedance Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 Input VCCI VCCI Enable Output VCCO VCCO VCCO VCCO 1 MW 8W 500 W IN 500 W OUT EN 13 W 7.5 µA Figure 23. Device I/O Schematics 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information ISO7641FC uses single-ended TTL-logic switching technology. It has a supply voltage range from 3 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to note that due to the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or standard. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7631FM ISO7631FC ISO7641FC 23 ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com 10.2 Typical Application ISO-BARRIER 5VISO 5VISO 0.1 F RTD Bridge Thermo couple Current shunt 0.1 F 5VISO 22 1 0.1 F AVDD DVDD 11 8 AIN1+ A0 12 7 AIN1A1 27 SCLK 18 28 AIN2+ DOUT ADS1234 17 5VISO 5VISO AIN220 REF+ 0.1 F 13 19 AIN3+ REF0.1 F 14 23 AIN3GAIN0 24 GAIN1 16 25 AIN4+ SPEED 15 26 PWDN AIN4AGND DGND 2 21 3.3V 16 10 VCC2 VCC1 0.1 F 1 7 EN2 EN1 3 INA OUTA 13 4 ISO7641 INB OUTB 5 12 OUTC INC 6 11 IND OUTD 9,15 2,8 GND2 GND1 16 14 VCC2 EN VCC1 NC 11 12 13 3.3V P3.0 DVcc 5 XOUT P3.1 6 MSP430 F2132 XIN 18 P3.7 SOMI 17 P3.6 15 16 P3.4 P3.5 DVss 14 1 7 2 0.1 F 14 10 3.3V CLK 0.1 F 4 3 OUTA INA 4 ISO7640 OUTB INB 12 5 OUTC INC 11 6 OUTD IND 9,15 2,8 GND2 GND1 13 Figure 24. Isolated Data Acquisition System for Process Control 10.2.1 Design Requirements Unlike optocouplers, which require external components to improve performance, provide bias, or limit current, the ISO76xx device only requires two external bypass capacitors to operate. 24 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 Typical Application (continued) 10.2.2 Detailed Design Procedure ISO7641 0.1 µF VCC1 0.1 µF VCC2 1 16 2 15 INA 3 14 OUTA INB 4 13 OUTB INC 5 12 OUTD 6 11 7 10 8 9 GND1 GND2 IND EN2 EN1 GND1 OUTC GND2 Figure 25. Typical ISO7641FC Circuit Hookup 10.2.2.1 Typical Supply Current Equations (Calculated based on room temperature and typical Silicon process) ISO7631FM: At VCC1 = VCC2 = 3.3 V ICC1 = 1.8072 + 0.0244 × f + 0.0016 × f × CL ICC2 = 2.4625 + 0.0252 × f + 0.0033 × f × CL (1) (2) At VCC1 = VCC2 = 5 V ICC1 = 2.3183 + 0.04 × f + 0.0025 × f × CL ICC2 = 3.2582 + 0.0403 × f + 0.0049 × f × CL (3) (4) ISO7631FC: At VCC1 = VCC2 = 3.3 V ICC1 = 1.1762 + 0.0325 × f + 0.0017 × f × CL ICC2 = 1.5285 + 0.0299 × f + 0.0033 × f × CL (5) (6) At VCC1 = VCC2 = 5 V ICC1 = 1.6001 + 0.0528 × f + 0.0025 × f × CL ICC2 = 2.2032 + 0.0475 × f + 0.005 × f × CL (7) (8) ISO7641FC: At VCC1 = VCC2 = 3.3 V ICC1 = 1.2162 + 0.0462 × f + 0.0017 × f × CL ICC2 = 1.8054 + 0.0411 × f + 0.005 × f × CL Copyright © 2012–2015, Texas Instruments Incorporated (9) (10) Submit Documentation Feedback Product Folder Links: ISO7631FM ISO7631FC ISO7641FC 25 ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com Typical Application (continued) (Calculated based on room temperature and typical Silicon process) At VCC1 = VCC2 = 5 V ICC1 = 1.6583 + 0.0757 × f + 0.0025 × f × CL ICC2 = 2.5008 + 0.0655 × f + 0.0076 × f × CL (11) (12) ICC1 and ICC2 are typical supply currents measured in mA; f is data rate measured in Mbps; CL is the capacitive load on each channel measured in pF. 10.2.3 Application Curves TA = 25 oC, CL = 15 pF TA = 25 oC, CL = 15 pF VCC1 = V CC2 = 5 V Pattern: NRZ 216-1 VCC1 = V CC2 = 3.3 V Pattern: NRZ 216-1 Figure 26. M-Grade Typical Eye Diagram at 150 Mbps, 5 V Operation Figure 27. M-Grade Typical Eye Diagram at 150 Mbps, 3.3 V Operation TA = 25 oC, CL = 15 pF VCC1 = V CC2 = 5 V Pattern: NRZ 216-1 TA = 25 oC, CL = 15 pF VCC1 = V CC2 = 3.3 V Pattern: NRZ 216-1 Figure 28. C-Grade Typical Eye Diagram at 25 Mbps, 5 V Operation 26 Submit Documentation Feedback Figure 29. C-Grade Typical Eye Diagram at 25 Mbps, 3.3 V Operation Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 11 Power Supply Recommendations To ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For such applications, detailed power supply design and transformer selection recommendations are available in SN6501 data sheet (SLLSEA0). 12 Layout 12.1 Layout Guidelines A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 30). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2. • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. If an additional supply voltage plane or signal layer is needed, add a second power and ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. NOTE For detailed layout recommendations, see Digital Isolator Design Guide, SLLA284. 12.2 Layout Example High-speed traces 10 mils Ground plane 40 mils Keep this space free from planes, traces, pads, and vias FR-4 0r ~ 4.5 Power plane 10 mils Low-speed traces Figure 30. Recommended Layer Stack Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7631FM ISO7631FC ISO7641FC 27 ISO7631FM, ISO7631FC, ISO7641FC SLLSEC3E – SEPTEMBER 2012 – REVISED AUGUST 2015 www.ti.com 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation For related documentation, see the following: • Digital Isolator Design Guide, SLLA284 • Transformer Driver for Isolated Power Supplies, SLLSEA0 • Isolation Glossary, SLLA353 13.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 4. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ISO7631FM Click here Click here Click here Click here Click here ISO7631FC Click here Click here Click here Click here Click here ISO7641FC Click here Click here Click here Click here Click here 13.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.4 Trademarks DeviceNet, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 13.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 28 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO7631FM ISO7631FC ISO7641FC PACKAGE OPTION ADDENDUM www.ti.com 26-Mar-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ISO7631FCDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7631FC ISO7631FCDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7631FC ISO7631FMDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7631FM ISO7631FMDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7631FM ISO7641FCDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7641FC ISO7641FCDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7641FC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 26-Mar-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO7631FCDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7631FMDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7641FCDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7631FCDWR SOIC DW 16 2000 367.0 367.0 38.0 ISO7631FMDWR SOIC DW 16 2000 367.0 367.0 38.0 ISO7641FCDWR SOIC DW 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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