Lattice ISPL1048E-125LQI High-density programmable logic Datasheet

ispLSI 1048E
®
High-Density Programmable Logic
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
— 96 I/O Pins, Twelve Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally and Pin-out Compatible to ispLSI 1048C
Output Routing Pool
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
E7 E6 E5 E4 E3 E2 E1 E0
D7
Output Routing Pool
A0
E2CMOS®
D Q
A1
A2
A3
A4
Logic
Global Routing Pool (GRP)
Array
D6
D5
D Q
D Q
D4
GLB
D3
D2
A5
D Q
A6
D1
A7
TECHNOLOGY
• HIGH PERFORMANCE
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Eraseable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
Output Routing Pool
Features
D0
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
Output Routing Pool
CLK
0139G1A-isp
Description
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The ispLSI 1048E is a High-Density Programmable Logic
Device containing 288 Registers, 96 Universal I/O pins,
12 Dedicated Input pins, four Dedicated Clock Input pins,
two dedicated Global OE input pins, and a Global Routing
Pool (GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1048E features 5V in-system programmability and in-system
diagnostic capabilities. The ispLSI 1048E offers nonvolatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems. A
functional superset of the ispLSI 1048 architecture, the
ispLSI 1048E device adds two new global output enable
pins and two additional dedicated inputs.
The basic unit of logic on the ispLSI 1048E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
• ispLSI DEVELOPMENT TOOLS
ispVHDL™ Systems
— VHDL/Verilog-HDL/Schematic Design Options
— Functional/Timing/VHDL Simulation Options
ispDS+™ VHDL Synthesis-Optimized Logic Fitter
— Supports Leading Third-Party Design Environments
for Schematic Capture, Synthesis and Timing
Simulation
— Static Timing Analyzer
ispDS™ Software
— Lattice HDL or Boolean Logic Entry
— Functional Simulator and Waveform Viewer
ISP Daisy Chain Download Software
Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
1048E_08
1
July 1998
Specifications ispLSI 1048E
Functional Block Diagram
Figure 1. ispLSI 1048E Functional Block Diagram
I/O I/O I/O I/O
95 94 93 92
I/O I/O I/O I/O
91 90 89 88
I/O I/O I/O I/O
87 86 85 84
I/O I/O I/O I/O
83 82 81 80
IN IN
11 10
I/O I/O I/O I/O
79 78 77 76
I/O I/O I/O I/O
75 74 73 72
I/O I/O I/O I/O
71 70 69 68
I/O I/O I/O I/O
67 66 65 64
IN
9
IN
8
RESET
Input Bus
Input Bus
Output Routing Pool (ORP)
Output Routing Pool (ORP)
GOE 0
Generic
Logic Blocks
(GLBs)
GOE 1
F7
F6
F5
F4
F3
F2
F1
F0
E7
E6
E5
E4
E3
E2
E1
IN 7
IN 6
E0
I/O 63
I/O 62
I/O 61
D7
I/O 12
I/O 13
I/O 14
I/O 15
D6
A1
D5
Global
Routing
Pool
(GRP)
A2
A3
A4
D4
D3
D2
A5
D1
A6
D0
I/O 60
I/O 59
I/O 58
I/O 57
lnput Bus
A0
Output Routing Pool (ORP)
I/O 8
I/O 9
I/O 10
I/O 11
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
A7
SDI/IN 0
MODE/IN 1
B0
B1
B2
B3
B4
B5
B6
B7
C0
C1
C2
C3
C4
C5
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
C6
C7
Clock
Distribution
Network
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Megablock
ispEN/NC
IN 2 SDO/
IN 3
I/O I/O I/O I/O
16 17 18 19
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
IN SCLK/ I/O I/O I/O I/O
4 IN 5 32 33 34 35
The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered input, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to minimize overall output switching noise.
I/O I/O I/O I/O
36 37 38 39
I/O I/O I/O I/O
40 41 42 43
I/O I/O I/O I/O
44 45 46 47
Y Y Y Y
0 1 2 3
0139F(2)-48B-isp
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1048E device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0). The logic
of this GLB allows the user to create an internal clock
from a combination of internal signals within the device.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. Each ispLSI
1048E device contains six Megablocks.
2
Specifications ispLSI 1048E
Absolute Maximum Ratings 1
Supply Voltage Vcc. ................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
Commercial
TA = 0°C to + 70°C
4.75
5.25
V
Industrial
TA = -40°C to + 85°C
4.5
5.5
V
Input Low Voltage
0
0.8
V
Input High Voltage
2.0
VCC
Supply Voltage
VIL
VIH
Vcc+1
V
Table 2-0005/1048E
Capacitance (TA=25oC, f=1.0 MHz)
PARAMETER
TYPICAL
UNITS
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
8
pf
VCC = 5.0V, VPIN = 2.0V
Y0 Clock Capacitance
15
pf
VCC = 5.0V, VPIN = 2.0V
SYMBOL
C1
C2
TEST CONDITIONS
Table 2-0006/1048E
Data Retention Specifications
PARAMETER
MINIMUM
MAXIMUM
UNITS
20
–
Years
10000
–
Cycles
Data Retention
Erase/Reprogram Cycles
Table 2-0008/1048E
3
Specifications ispLSI 1048E
Switching Test Conditions
Figure 2. Test Load
GND to 3.0V
Input Pulse Levels
+ 5V
≤ 3 ns 10% to 90%
Input Rise and Fall Time
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
R1
See Figure 2
Device
Output
Table 2-0003/1048E
3-state levels are measured 0.5V from
steady-state active level.
Test
Point
CL*
R2
Output Load Conditions (see Figure 2)
TEST CONDITION
R1
R2
CL
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
A
B
C
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
*CL includes Test Fixture and Probe Capacitance.
0213a
Table 2-0004a
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
CONDITION
PARAMETER
3
MIN.
TYP.
MAX. UNITS
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS1
Output Low Voltage
IOL= 8 mA
–
–
0.4
V
Output High Voltage
IOH = -4 mA
2.4
–
–
V
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
–
–
-10
µA
Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC
–
–
10
µA
ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL
–
–
-150
µA
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
Output Short Circuit Current
VCC = 5V, VOUT = 0.5V
–
–
-200
mA
ICC2, 4
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V Commercial
–
175
–
mA
–
175
–
1.
2.
3.
4.
mA
Industrial
fCLOCK = 1 MHz
Table
2-0007/1048E
One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
Measured using twelve 16-bit counters.
Typical values are at VCC = 5V and TA= 25°C.
Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC .
4
Specifications ispLSI 1048E
External Timing Parameters
Over Recommended Operating Conditions
4
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
tsu3
th3
1.
2.
3.
4.
TEST
COND.
#2
-125
1
DESCRIPTION
-90
-100
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
7.5
–
10.0
–
10.0
ns
A
2
Data Propagation Delay, Worst Case Path
–
10.0
–
12.5
–
12.5
ns
A
3
Clock Frequency with Internal Feedback 3
125.0
–
100.0
–
90.9
–
MHz
91.0
–
71.0
–
71.0
–
MHz
167.0
–
125.0
–
125.0
–
MHz
5.5
–
6.5
–
6.5
–
ns
–
6.5
ns
0.0
–
ns
7.5
–
ns
–
7.5
ns
0.0
–
ns
–
4
Clock Frequency with External Feedback (
(
1
twh + twl
1
tsu2 + tco1
)
)
–
5
Clock Frequency, Max. Toggle
–
6
GLB Reg. Setup Time before Clock,4 PT Bypass
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
4.5
–
6.5
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
0.0
–
–
9
GLB Reg. Setup Time before Clock
6.5
–
7.5
–
–
10 GLB Reg. Clock to Output Delay
–
5.5
–
7.5
–
11 GLB Reg. Hold Time after Clock
0.0
–
0.0
–
A
12 Ext. Reset Pin to Output Delay
–
13 Ext. Reset Pulse Duration
B
14 Input to Output Enable
–
10.0
–
13.5
5.0
–
6.5
–
–
12.0
–
15.0
–
13.5
ns
6.5
–
ns
–
15.0
ns
–
15.0
ns
–
9.0
ns
–
9.0
ns
–
4.0
–
ns
4.0
–
4.0
–
ns
–
3.5
–
4.0
–
ns
–
0.0
–
0.0
–
ns
C
15 Input to Output Disable
–
12.0
–
15.0
B
16 Global OE Output Enable
–
7.0
–
9.0
C
17 Global OE Output Disable
–
7.0
–
9.0
–
18 External Synchronous Clock Pulse Duration, High
3.0
–
4.0
–
19 External Synchronous Clock Pulse Duration, Low
3.0
–
–
20
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0
–
21
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
0.0
USE 104
8E-100 F
OR
NEW DE
SIGNS
PARAMETER
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
5
Table 2-0030A/1048E
Specifications ispLSI 1048E
External Timing Parameters
Over Recommended Operating Conditions
4
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
tsu3
th3
1.
2.
3.
4.
TEST
COND.
-70
1
#2
DESCRIPTION
-50
MIN. MAX. MIN. MAX.
UNITS
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
15.0
–
20.0
ns
A
2
Data Propagation Delay, Worst Case Path
–
18.5
–
24.5
ns
A
3
Clock Frequency with Internal Feedback 3
70.0
–
50.0
–
MHz
56.0
–
42.0
–
MHz
100.0
–
77.0
–
MHz
9.0
–
12.0
–
ns
–
9.5
ns
0.0
–
ns
14.5
–
ns
–
12.0
ns
0.0
–
ns
–
4
Clock Frequency with External Feedback (
(
1
twh + twl
1
tsu2 + tco1
)
)
–
5
Clock Frequency, Max. Toggle
–
6
GLB Reg. Setup Time before Clock,4 PT Bypass
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
7.0
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
–
9
GLB Reg. Setup Time before Clock
11.0
–
–
10 GLB Reg. Clock to Output Delay
–
9.0
–
11 GLB Reg. Hold Time after Clock
0.0
–
A
12 Ext. Reset Pin to Output Delay
–
13 Ext. Reset Pulse Duration
B
–
15.0
10.0
–
14 Input to Output Enable
–
18.0
C
15 Input to Output Disable
–
18.0
B
16 Global OE Output Enable
–
12.0
C
17 Global OE Output Disable
–
–
18 External Synchronous Clock Pulse Duration, High
–
USE 104
8E-70 FO
R
NEW DE
SIGNS
PARAMETER
–
20.5
ns
13.0
–
ns
–
24.0
ns
–
24.0
ns
–
16.0
ns
12.0
–
16.0
ns
5.0
–
6.5
–
ns
19 External Synchronous Clock Pulse Duration, Low
5.0
–
6.5
–
ns
–
20
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
4.0
–
6.5
–
ns
–
21
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
0.0
–
0.0
–
ns
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
6
Table 2-0030B/1048E
Specifications ispLSI 1048E
Internal Timing Parameters1
PARAMETER
#2
-125
DESCRIPTION
-100
-90
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
22 I/O Register Bypass
–
0.3
–
0.3
–
0.5
ns
23 I/O Latch Delay
–
1.9
–
2.3
–
2.5
ns
24 I/O Register Setup Time before Clock
3.0
–
3.5
–
4.0
–
ns
25 I/O Register Hold Time after Clock
0.0
–
0.0
–
-0.5
26 I/O Register Clock to Out Delay
–
4.6
–
5.0
–
27 I/O Register Reset to Out Delay
–
4.6
–
5.0
–
28 Dedicated Input Delay
–
2.3
–
2.7
–
29 GRP Delay, 1 GLB Load
–
1.8
–
1.9
–
30 GRP Delay, 4 GLB Loads
–
2.0
–
2.4
–
31 GRP Delay, 8 GLB Loads
–
2.3
–
2.6
–
32 GRP Delay, 16 GLB Loads
–
2.8
–
3.0
–
33 GRP Delay, 48 GLB Loads
–
4.9
–
5.4
–
34 4 Product Term Bypass Path Delay (Combinatorial)
–
3.9
–
5.3
35 4 Product Term Bypass Path Delay (Registered)
–
4.0
–
5.3
36 1 Product Term/XOR Path Delay
–
3.6
–
4.6
37 20 Product Term/XOR Path Delay
–
5.0
–
5.8
38 XOR Adjacent Path Delay 3
–
5.0
–
6.3
39 GLB Register Bypass Delay
–
0.4
–
1.0
40 GLB Register Setup Time before Clock
0.1
–
0.5
–
41 GLB Register Hold Time after Clock
4.5
–
5.3
–
42 GLB Register Clock to Output Delay
–
2.3
–
2.5
43 GLB Register Reset to Output Delay
–
4.9
–
6.2
44 GLB Product Term Reset to Register Delay
–
3.9
–
4.5
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
ns
5.0
ns
5.0
ns
2.9
ns
2.2
ns
2.4
ns
2.7
ns
3.3
ns
5.7
ns
8E-100 F
tgrp1
tgrp4
tgrp8
tgrp16
tgrp48
–
OR NEW
GRP
DESIGNS
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
USE 104
Inputs
–
5.4
ns
–
6.3
ns
–
6.5
ns
–
6.5
ns
–
7.3
ns
–
0.4
ns
0.1
–
ns
6.4
–
ns
–
2.0
ns
–
6.3
ns
–
5.0
ns
–
5.4
–
7.2
–
5.7
ns
2.9
4.0
3.5
4.7
4.0
5.2
ns
47 ORP Delay
–
1.0
–
1.0
–
1.0
ns
48 ORP Bypass Delay
–
0.0
–
0.0
–
0.0
ns
45 GLB Product Term Output Enable to I/O Cell Delay
46 GLB Product Term Clock Delay
ORP
torp
torpbp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Table 2-0036A/1048E
Specifications ispLSI 1048E
Internal Timing Parameters1
PARAMETER
#2
-70
DESCRIPTION
-50
MIN. MAX. MIN. MAX.
UNITS
Inputs
–
0.6
–
0.7
ns
23 I/O Latch Delay
–
3.6
–
4.7
ns
24 I/O Register Setup Time before Clock
4.1
–
6.5
–
ns
25 I/O Register Hold Time after Clock
-0.6
–
-0.7
–
ns
26 I/O Register Clock to Out Delay
–
6.0
–
7.0
ns
27 I/O Register Reset to Out Delay
–
6.0
–
7.0
ns
28 Dedicated Input Delay
–
4.3
–
6.1
ns
29 GRP Delay, 1 GLB Load
–
3.5
–
5.1
ns
30 GRP Delay, 4 GLB Loads
–
3.7
–
5.4
ns
31 GRP Delay, 8 GLB Loads
–
4.1
–
5.8
ns
32 GRP Delay, 16 GLB Loads
–
4.8
–
33 GRP Delay, 48 GLB Loads
–
7.5
–
34 4 Product Term Bypass Path Delay (Combinatorial)
–
8.5
35 4 Product Term Bypass Path Delay (Registered)
–
7.4
36 1 Product Term/XOR Path Delay
–
8.4
37 20 Product Term/XOR Path Delay
–
8.4
38 XOR Adjacent Path Delay 3
–
9.4
39 GLB Register Bypass Delay
–
1.6
40 GLB Register Setup Time before Clock
0.1
–
41 GLB Register Hold Time after Clock
8.5
–
42 GLB Register Clock to Output Delay
–
2.0
43 GLB Register Reset to Output Delay
–
6.3
44 GLB Product Term Reset to Register Delay
–
6.1
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
45 GLB Product Term Output Enable to I/O Cell Delay
6.6
ns
9.8
ns
–
10.7
ns
–
9.2
ns
–
10.5
ns
–
10.5
ns
–
11.7
ns
USE 104
tgrp1
tgrp4
tgrp8
tgrp16
tgrp48
8E-70 FO
GRP
NS
22 I/O Register Bypass
R NEW D
ESIG
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
–
2.2
ns
0.0
–
ns
11.5
–
ns
–
3.0
ns
–
7.3
ns
–
7.9
ns
–
6.8
–
10.0
ns
5.1
6.4
6.9
8.3
ns
47 ORP Delay
–
2.0
–
2.5
ns
48 ORP Bypass Delay
–
0.0
–
0.0
ns
46 GLB Product Term Clock Delay
ORP
torp
torpbp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
Table 2-0036B/1048E
Specifications ispLSI 1048E
Internal Timing Parameters1
PARAMETER
#
-90
-100
-125
DESCRIPTION
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
Outputs
49 Output Buffer Delay
–
1.3
–
2.0
50 Output Slew Limited Delay Adder
–
10.0
–
10.0
51 I/O Cell OE to Output Enabled
–
4.3
–
5.1
52 I/O Cell OE to Output Disabled
–
4.3
–
5.1
53 Global OE
–
2.7
–
3.9
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
0.9
0.9
2.0
2.0
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
0.9
0.9
2.0
2.0
56 Clock Delay, Clock GLB to Global GLB Clock Line
0.8
1.8
0.8
1.8
57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
0.0
0.0
0.0
0.0
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
0.8
1.8
0.8
1.8
–
2.8
–
4.3
Clocks
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
Global Reset
tgr
59 Global Reset to GLB and I/O Registers
1. Internal timing parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
9
–
1.7
ns
–
12.0
ns
–
6.4
ns
–
6.4
ns
–
2.6
ns
2.8
2.8
ns
2.8
2.8
ns
0.8
1.8
ns
USE 104
8E-100 F
OR
NEW DE
SIGNS
tob
tsl
toen
todis
tgoe
0.0
0.5
ns
0.8
1.8
ns
4.5
ns
–
Table 2-0037A/1048E
Specifications ispLSI 1048E
Internal Timing Parameters1
PARAMETER
#
DESCRIPTION
-50
-70
MIN. MAX. MIN. MAX.
UNITS
Outputs
49 Output Buffer Delay
–
2.2
50 Output Slew Limited Delay Adder
–
12.0
51 I/O Cell OE to Output Enabled
–
6.9
52 I/O Cell OE to Output Disabled
–
6.9
53 Global OE
–
5.1
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
2.8
2.8
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.8
2.8
56 Clock Delay, Clock GLB to Global GLB Clock Line
0.8
1.8
57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
0.1
0.6
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
0.8
1.8
–
4.5
Clocks
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
Global Reset
tgr
59 Global Reset to GLB and I/O Registers
1. Internal timing parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
10
–
3.2
ns
–
12.0
ns
–
7.9
ns
–
7.9
ns
–
8.1
ns
3.3
3.3
ns
3.3
3.3
ns
0.8
1.8
ns
USE 104
8E-70 FO
R
NEW DE
SIGNS
tob
tsl
toen
todis
tgoe
0.0
0.7
ns
0.8
1.8
ns
7.5
ns
–
Table 2-0037B/1048E
Specifications ispLSI 1048E
ispLSI 1048E Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
#34
#28
I/O Reg Bypass
I/O Pin
(Input)
#59
Comb 4 PT Bypass
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#22
#30
#35
#39
#48
Input
D Register Q
RST
#23 - 27
GRP Loading
Delay
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
#29, 31-33
#36 - 38
GRP4
D
Q
#49, 50
#51, 52
#47
RST
#59
Reset
Clock
Distribution
Y1,2,3
#55 - 58
#40 - 43
Control RE
PTs
OE
#44 - 46 CK
0491
#54
Y0
#53
GOE 0,1
Derivations of tsu, th and tco from the Product Term Clock 1
tsu
=
=
=
2.2 ns =
Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min))
(#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
(0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
th
=
=
=
3.5 ns =
Clock (max) + Reg h - Logic
(tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)
tco
=
=
=
10.9 ns =
Clock (max) + Reg co + Output
(tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
(#22 + #30 + #46) + (#42) + (#47 + #49)
(0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
Derivations of tsu, th and tco from the Clock GLB 1
tsu
=
=
=
3.4 ns =
Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))
(#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
(0.3 + 2.0 + 5.0) + (0.1) – (0.9 + 2.3 + 0.8)
th
=
=
=
2.2 ns =
Clock (max) + Reg h - Logic
(tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
(#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
(0.9 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)
tco
=
=
=
9.6 ns =
Clock (max) + Reg co + Output
(tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
(#54 + #42 + #56) + (#42) + (#47 + #49)
(0.9 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
1. Calculations are based upon timing specifications for the ispLSI 1048E-125.
Table 2-0042/1048E
11
I/O Pin
(Output)
Specifications ispLSI 1048E
Maximum GRP Delay vs. GLB Loads
10
ispLSI 1048E-50
9
GRP Delay (ns)
8
ispLSI 1048E-70
7
6
ispLSI 1048E-90/100
ispLSI 1048E-125
5
4
3
2
1
1
4
8
16
32
48
GLB Loads
0127A/1048E
Power Consumption
Power Consumption in the ispLSI 1048E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used. Figure
3 shows the relationship between power and operating
speed.
Figure 3. Typical Device Power Consumption vs fmax
380
ispLSI 1048E
ICC (mA)
340
300
260
220
180
0
20
40
60
80
100
120
140
fmax (MHz)
Notes: Configuration of twelve 16-bit counters,
Typical current at 5V, 25°C
ICC can be estimated for the ispLSI 1048E using the following equation:
ICC = 20 + (# of PTs * 0.42) + (# of nets * Max. freq * 0.010)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 4 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
0127B/1048E
12
Specifications ispLSI 1048E
Pin Description
NAME
PQFP / TQFP PIN NUMBERS
23,
29,
36,
42,
54,
60,
68,
74,
87,
93,
100,
106,
119,
125,
4,
10,
24,
30,
37,
43,
55,
61,
69,
75,
88,
94,
101,
107,
120,
126,
5,
11,
25,
31,
38,
44,
56,
62,
70,
76,
89,
95,
102,
108,
121,
127,
6,
12,
DESCRIPTION
26,
32,
39,
45,
57,
63,
71,
77,
90,
96,
103,
109,
122,
128,
7,
13
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
104,
117,
123,
2,
8,
22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
105,
118,
124,
3,
9,
GOE0, GOE1
64,
114
IN 2, IN 4
IN 6 - IN 11
47,
84,
51
110,
ispEN/NC1
18
SDI/IN 0
20
MODE/IN 1
46
SDO/IN 3
50
SCLK/IN 5
78
RESET
19
Y0
15
Y1
83
Y2
80
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Y3
79
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
GND
1,
97,
17,
112
33,
49,
VCC
16,
48,
82,
113
Global Output Enable input pins.
Dedicated input pins to the device.
111,
115,
116,
14
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. When low, the MODE,
SDI, SDO and SCLK controls become active.
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 also is used as one of the two control pins for the ISP state
machine. When ispEN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When ispEN is logic low, it
functions as pin to control the operation of the isp state machine. When
ispEN is high, it functions as a dedicated input pin.
Output/Input - This pin performs two functions. When ispEN is logic low,
it functions as an output pin to read serial shift register data. When
ispEN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
65,
81,
Ground (GND)
VCC
1. NC pins are not to be connected to any active signals, VCC or GND.
13
Table 2 - 0002C-48E
Specifications ispLSI 1048E
Pin Configuration
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
IN 10
IN 9
GOE 1
VCC
GND
IN 8
IN 7
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
ispLSI 1048E 128-Pin PQFP Pinout Diagram
ispLSI 1048E
Top View
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
Y1
VCC
GND
Y2
Y3
SCLK/IN 5
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
GND
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
MODE/IN 1
IN 2
VCC
GND
SDO/IN 3
IN 4
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
GOE 0
GND
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
IN 11
Y0
VCC
GND
1ispEN/NC
RESET
SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
1. NC pins are not to be connected to any active signals, Vcc or GND.
0124-48C
14
Specifications ispLSI 1048E
Pin Configuration
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
IN 10
IN 9
GOE 1
VCC
GND
IN 8
IN 7
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
ispLSI 1048E 128-Pin TQFP Pinout Diagram
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
ispLSI 1048E
Top View
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
1MODE/IN 1
IN 2
VCC
GND
1SDO/IN 3
IN 4
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
GOE 0
GND
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
IN 11
Y0
VCC
GND
ispEN
RESET
1SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
1. Pins have dual function capability.
0124-48/TQFP
15
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
Y1
VCC
GND
Y2
Y3
SCLK/IN 51
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
GND
Specifications ispLSI 1048E
Package Thermal Characteristics
For the ispLSI 1048E-125LT, it is strongly recommended
that the actual Icc be verified to ensure that the maximum
junction temperature (TJ) with power supplied is not
exceeded. Depending on the specific logic design and
clock speed, airflow may be required to satisfy the maxi-
mum allowable junction temperature (TJ) specification.
Please refer to the Thermal Management section of the
Lattice Semiconductor Data Book or CD-ROM for additional information on calculating TJ.
Part Number Description
ispLSI 1048E – XXX
X
X
X
Device Family
Grade
Blank = Commercial
I = Industrial
Device Number
Package
Q = PQFP
T = TQFP
Speed
125 = 125 MHz fmax
100 = 100 MHz fmax
90 = 90 MHz fmax
70 = 70 MHz fmax
50 = 50 MHz fmax
Power
L = Low
0212/1048E
ispLSI 1048E Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
125
125
7.5
7.5
100
100
10
10
ispLSI 1048E-125LQ
ispLSI 1048E-125LT
ispLSI 1048E-100LQ
ispLSI 1048E-100LT
128-Pin PQFP
128-Pin TQFP
128-Pin PQFP
128-Pin TQFP
90
90
10
10
70
70
50
15
15
20
ispLSI 1048E-90LQ*
ispLSI 1048E-90LT*
ispLSI 1048E-70LQ
ispLSI 1048E-70LT
ispLSI 1048E-50LQ**
128-Pin PQFP
128-Pin TQFP
128-Pin PQFP
128-Pin TQFP
128-Pin PQFP
50
20
ispLSI 1048E-50LT**
128-Pin TQFP
Table 2-0041A/1048E
*Recommend 1048E-100 for new 1048E-90 designs.
**Recommend 1048E-70 for new 1048E-50 designs.
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
70
15
ispLSI 1048E-70LQI
128-Pin PQFP
50
20
ispLSI 1048E-50LQI**
128-Pin PQFP
Table 2-0041B/1048E
**Recommend 1048E-70 for new 1048E-50 designs.
16
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