Lattice ISPLSI1048EA-100LQ128 In-system programmable high density pld Datasheet

ispLSI 1048EA
®
In-System Programmable High Density PLD
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
— 96 I/O Pins, Eight Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally Compatible with ispLSI 1048C and 1048E
Output Routing Pool
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
E7 E6 E5 E4 E3 E2 E1 E0
D7
Output Routing Pool
A0
• NEW FEATURES
— 100% IEEE 1149.1 Boundary Scan Testable
— ispJTAG™ In-System Programmable Via IEEE 1149.1
(JTAG) Test Access Port
— User Selectable 3.3V or 5V I/O supports Mixed
Voltage Systems (VCCIO Pin)
— Open Drain Output Option
D Q
A1
A2
A3
A4
Logic
Global Routing Pool (GRP)
Array
D6
D5
D Q
D Q
D4
GLB
D3
D2
A5
D Q
A6
D1
Output Routing Pool
Features
D0
A7
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
Output Routing Pool
CLK
0139A/1048EA
Description
E2CMOS®
TECHNOLOGY
• HIGH PERFORMANCE
— fmax = 170 MHz Maximum Operating Frequency
— tpd = 5.0 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Eraseable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
The ispLSI 1048EA is a High Density Programmable
Logic Device containing 288 Registers, 96 Universal I/O
pins, eight Dedicated Input pins, four Dedicated Clock
Input pins, two dedicated Global OE input pins, and a
Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 1048EA features 5V in-system programmability
and in-system diagnostic capabilities via IEEE 1149.1
Test Access Port. The ispLSI 1048EA offers non-volatile
reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional
superset of the ispLSI 1048 architecture, the ispLSI
1048EA device adds user selectable 3.3V or 5V I/O and
open-drain output options.
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on the ispLSI 1048EA device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048EA device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP
and dedicated inputs. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1048ea_03
1
June 2000
Specifications ispLSI 1048EA
Functional Block Diagram
Figure 1. ispLSI 1048EA Functional Block Diagram
I/O I/O I/O I/O
95 94 93 92
I/O I/O I/O I/O
91 90 89 88
I/O I/O I/O I/O
87 86 85 84
IN IN
11 10
I/O I/O I/O I/O
83 82 81 80
I/O I/O I/O I/O
79 78 77 76
I/O I/O I/O I/O
75 74 73 72
I/O I/O I/O I/O
71 70 69 68
I/O I/O I/O I/O
67 66 65 64
IN
9
IN
8
RESET
Input Bus
Input Bus
Output Routing Pool (ORP)
Output Routing Pool (ORP)
GOE 0
Generic
Logic Blocks
(GLBs)
GOE 1
VCCIO
F7
F6
F5
F4
F3
F2
F1
F0
E7
E6
E5
E4
E3
E2
E1
IN 7
IN 6
E0
I/O 63
I/O 62
I/O 61
D7
I/O 12
I/O 13
I/O 14
I/O 15
D6
A1
D5
Global
Routing
Pool
(GRP)
A2
A3
A4
D4
D3
D2
A5
D1
A6
D0
I/O 60
I/O 59
I/O 58
I/O 57
lnput Bus
A0
Output Routing Pool (ORP)
I/O 8
I/O 9
I/O 10
I/O 11
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
A7
B0
B1
B2
B3
B4
B5
B6
B7
C0
C1
C2
C3
C4
C5
C6
C7
Clock
Distribution
Network
Megablock
TDI
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
TDO
TMS
TCK
IN 2
I/O I/O I/O I/O
16 17 18 19
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
IN
4
I/O I/O I/O I/O
32 33 34 35
I/O I/O I/O I/O
36 37 38 39
I/O I/O I/O I/O
40 41 42 43
I/O I/O I/O I/O
44 45 46 47
Y Y Y Y
0 1 2 3
0139F/1048EA
The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered
input, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source
2mA or sink 8mA. Each output can be programmed
independently for fast or slow output slew rate to
minimize overall output switching noise. By connecting
the VCCIO pin to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compatible voltages.
Clocks in the ispLSI 1048EA device are selected using
the Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0). The logic
of this GLB allows the user to create an internal clock
from a combination of internal signals within the device.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 1048EA are individually programmable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
Eight GLBs, 16 I/O cells, dedicated inputs (if available)
and one ORP are connected together to make a
Megablock (Figure 1). The outputs of the eight GLBs are
connected to a set of 16 universal I/O cells by the ORP.
Each ispLSI 1048EA device contains six Megablocks.
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
2
Specifications ispLSI 1048EA
Boundary Scan
Figure 2. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
Tbtsu
Tbtch
Tbth
Tbtcl
Tbtcp
TCK
Tbtvo
Tbtco
TDO
Valid Data
Tbtcpsu
Data to be
captured
Tbtoz
Valid Data
Tbtcph
Data Captured
Tbtuov
Tbtuco
Data to be
driven out
Symbol
Valid Data
Parameter
Tbtuoz
Valid Data
Min
Max
Units
tbtcp
TCK [BSCAN test] clock pulse width
100
–
ns
tbtch
TCK [BSCAN test] pulse width high
50
–
ns
tbtcl
TCK [BSCAN test] pulse width low
50
–
ns
tbtsu
TCK [BSCAN test] setup time
20
–
ns
tbth
TCK [BSCAN test] hold time
25
–
ns
trf
TCK [BSCAN test] rise and fall time
50
–
mV/ns
tbtco
TAP controller falling edge of clock to valid output
–
25
ns
tbtoz
TAP controller falling edge of clock to data output disable
–
25
ns
tbtvo
TAP controller falling edge of clock to data output enable
–
25
ns
tbtcpsu
BSCAN test Capture register setup time
40
–
ns
tbtcph
BSCAN test Capture register hold time
25
–
ns
tbtuco
BSCAN test Update reg, falling edge of clock to valid output
–
50
ns
tbtuoz
BSCAN test Update reg, falling edge of clock to output disable
–
50
ns
tbtuov
BSCAN test Update reg, falling edge of clock to output enable
–
50
ns
3
Specifications ispLSI 1048EA
Absolute Maximum Ratings 1
Supply Voltage Vcc. ................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
PARAMETER
SYMBOL
VCC
Supply Voltage
MIN.
MAX.
UNITS
4.75
5.25
V
5V
4.75
5.25
V
3.3V
3.0
3.6
V
0.8
V
Vcc+1
V
Commercial
TA = 0°C to + 70°C
VCCIO
Supply Voltage: Output Drivers
VIL
VIH
Input Low Voltage
0
Input High Voltage
2.0
Table 2-0005/1048EA
Capacitance (TA=25oC, f=1.0 MHz)
PARAMETER
TYPICAL
UNITS
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
8
pf
VCC = 5.0V, VPIN = 2.0V
Y0 Clock Capacitance
10
pf
VCC = 5.0V, VPIN = 2.0V
SYMBOL
C1
C2
TEST CONDITIONS
Table 2-0006/1048EA
Erase/Reprogram Specifications
PARAMETER
MINIMUM
MAXIMUM
UNITS
10000
–
Cycles
Erase/Reprogram Cycles
Table 2-0008/1048EA
4
Specifications ispLSI 1048EA
Switching Test Conditions
Input Pulse Levels
Figure 3. Test Load
GND to 3.0V
Input Rise and Fall Time 10% to 90%
1.5ns
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
+ 5V
R1
See Figure 3
Device
Output
Table 2-0003/1048EA
3-state levels are measured 0.5V from
steady-state active level.
Test
Point
R2
CL*
Output Load Conditions (see Figure 3)
TEST CONDITION
R1
R2
CL
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
A
B
C
*CL includes Test Fixture and Probe Capacitance.
0213a
Table 2-0004a
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
MIN.
TYP.3
—
—
0.4
V
IOH = -2 mA, VCCIO = 3.0V
2.4
—
—
V
IOH = -4 mA, VCCIO = 4.75V
CONDITION
PARAMETER
MAX. UNITS
VOL
Output Low Voltage
VOH
Output High Voltage
IIL
Input or I/O Low Leakage Current
IIH
Input or I/O High Leakage Current
IIL-PU
IOS1
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
—
—
-200
µA
Output Short Circuit Current
VCCIO = 5.0V or 3.3V, VOUT = 0.5V
—
—
-240
mA
ICC2, 4, 5
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V
fTOGGLE = 1 MHz
—
190
—
mA
IOL = 8 mA
2.4
—
—
V
0V ≤ VIN ≤ VIL (Max.)
—
—
-10
µA
(VCCIO - 0.2)V ≤ VIN ≤ VCCIO
—
—
10
µA
VCCIO ≤ VIN ≤ 5.25V
—
—
10
µA
Table 2-0007/1048EA
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Meaured using eight 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25°C.
4. Unused inputs held at 0.0V.
5. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book CD-ROM to estimate maximum ICC.
5
Specifications ispLSI 1048EA
External Timing Parameters
Over Recommended Operating Conditions
4
PARAMETER
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
tsu3
th3
1.
2.
3.
4.
#
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
A
2
A
3
—
4
2
DESCRIPTION
-125
-170
TEST
COND.
1
-100
MIN. MAX. MIN. MAX. MIN. MAX.
—
7.5
7.0
—
—
125
—
222
—
5.0
Data Propagation Delay, Worst Case Path
—
Clock Frequency with Internal Feedback 3
170
Clock Frequency with External Feedback ( tsu2 + tco1) 125
(
)
ns
—
10.0
10.0
—
12.5
ns
—
100
—
MHz
100
—
77
—
MHz
—
167
—
125
—
MHz
3.5
—
4.5
—
6.0
—
ns
1
1
twh + twl
UNITS
—
5
Clock Frequency, Max. Toggle
—
6
GLB Reg. Setup Time before Clock,4 PT Bypass
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
—
3.5
—
4.5
—
6.0
ns
—
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
—
0.0
—
0.0
—
ns
—
9
GLB Reg. Setup Time before Clock
4.5
—
5.5
—
7.0
—
ns
—
10 GLB Reg. Clock to Output Delay
—
4.5
—
5.5
—
7.0
ns
—
11 GLB Reg. Hold Time after Clock
0.0
—
0.0
—
0.0
—
ns
A
12 Ext. Reset Pin to Output Delay
—
7.0
—
10.0
—
13.5
ns
—
13 Ext. Reset Pulse Duration
4.0
—
5.0
—
6.5
—
ns
B
14 Input to Output Enable
—
9.0
—
12.0
—
15.0
ns
C
15 Input to Output Disable
—
9.0
—
12.0
—
15.0
ns
B
16 Global OE Output Enable
—
6.5
—
7.0
—
9.0
ns
C
17 Global OE Output Disable
—
6.5
—
7.0
—
9.0
ns
—
18 External Synchronous Clock Pulse Duration, High
2.25
—
3.0
—
4.0
—
ns
—
19 External Synchronous Clock Pulse Duration, Low
2.25
—
3.0
—
4.0
—
ns
—
20
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0
—
3.0
—
3.5
—
ns
—
21
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
—
0.0
—
0.0
—
ns
0.0
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
6
Table 2-0030A/1048EA
v.2.0
Specifications ispLSI 1048EA
Internal Timing Parameters1
PARAMETER
#2
-170
DESCRIPTION
-125
-100
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
22 I/O Register Bypass
—
0.3
—
0.3
—
0.4
ns
—
4.0
—
4.0
—
4.0
ns
24 I/O Register Setup Time before Clock
3.0
—
3.0
—
3.4
—
ns
25 I/O Register Hold Time after Clock
0.0
—
0.0
—
0.0
—
ns
26 I/O Register Clock to Out Delay
—
4.6
—
4.6
—
5.0
ns
27 I/O Register Reset to Out Delay
—
4.6
—
4.6
—
5.0
ns
28 Dedicated Input Delay
—
1.8
—
1.9
—
2.2
ns
29 GRP Delay, 1 GLB Load
—
1.4
—
1.7
—
2.1
ns
30 GRP Delay, 4 GLB Loads
—
1.6
—
1.9
—
2.3
ns
31 GRP Delay, 8 GLB Loads
—
1.8
—
2.1
—
2.5
ns
32 GRP Delay, 16 GLB Loads
—
2.2
—
2.5
—
2.9
ns
33 GRP Delay, 48 GLB Loads
—
3.8
—
4.1
—
4.5
ns
34 4 Product Term Bypass Path Delay (Combinatorial)
—
2.1
—
3.4
—
4.9
ns
35 4 Product Term Bypass Path Delay (Registered)
—
2.0
—
3.1
—
4.9
ns
36 1 Product Term/XOR Path Delay
—
2.3
—
3.6
—
4.3
ns
37 20 Product Term/XOR Path Delay
—
2.2
—
3.6
—
4.3
ns
38 XOR Adjacent Path Delay 3
—
2.2
—
3.6
—
4.3
ns
39 GLB Register Bypass Delay
—
1.0
—
1.2
—
2.1
ns
40 GLB Register Setup Time before Clock
0.3
—
0.3
—
0.3
—
ns
41 GLB Register Hold Time after Clock
2.0
—
3.5
—
4.8
—
ns
42 GLB Register Clock to Output Delay
—
1.4
—
1.4
—
1.7
ns
43 GLB Register Reset to Output Delay
—
4.7
—
4.9
—
5.0
ns
44 GLB Product Term Reset to Register Delay
—
2.7
—
3.8
—
4.5
ns
45 GLB Product Term Output Enable to I/O Cell Delay
—
3.6
—
5.2
—
7.2
ns
1.7
2.7
2.8
3.9
3.5
4.7
ns
47 GLB Feedback Delay
—
0.1
—
0.6
—
1.4
ns
48 ORP Delay
—
1.0
—
1.3
—
1.4
ns
49 ORP Bypass Delay
—
0.1
—
0.2
—
0.4
ns
23 I/O Latch Delay
GRP
tgrp1
tgrp4
tgrp8
tgrp16
tgrp48
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
tgfb
46 GLB Product Term Clock Delay
ORP
torp
torpbp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Table 2-0036A/1048EA
v.2.0
Specifications ispLSI 1048EA
Internal Timing Parameters1
PARAMETER
#
-170
DESCRIPTION
-125
-100
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
Outputs
tob
tsl
toen
todis
tgoe
50 Output Buffer Delay
—
0.9
—
1.7
—
2.0
ns
51 Output Slew Limited Delay Adder
52 I/O Cell OE to Output Enabled
—
6.0
—
6.0
—
6.0
ns
—
3.3
—
4.0
—
5.1
ns
53 I/O Cell OE to Output Disabled
—
3.3
—
4.0
—
5.1
ns
54 Global OE
—
2.6
—
3.0
—
3.9
ns
55 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
0.9
0.9
1.1
1.1
1.9
1.9
ns
56 Clock Delay, Y1 or Y2 to Global GLB Clock Line
0.9
0.9
0.9
0.9
1.5
1.5
ns
57 Clock Delay, Clock GLB to Global GLB Clock Line
0.8
1.8
0.8
1.8
0.8
1.8
ns
58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
0.0
0.0
0.0
0.0
0.0
0.0
ns
59 Clock Delay, Clock GLB to I/O Cell Global Clock Line
0.8
2.8
0.8
2.8
0.8
2.8
ns
—
0.4
—
2.1
—
5.1
ns
Clocks
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
Global Reset
tgr
60 Global Reset to GLB and I/O Registers
1. Internal timing parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
8
Table 2-0037A/1048EA
v.2.0
Specifications ispLSI 1048EA
ispLSI 1048EA Timing Model
I/O Cell
GRP
GLB
#47
Ded. In
I/O Pin
(Input)
#60
Comb 4 PT Bypass
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#22
#30
#35
#39
#49
Input
D Register Q
RST
#23 - 27
GRP Loading
Delay
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
#29, 31 - 33
#36 - 38
I/O Reg Bypass
GRP4
I/O Cell
Feedback
#34
#28
ORP
D
Q
#50, 51
#52, 53
#48
RST
#60
Reset
Clock
Distribution
Y1,2,3
#56 - 59
#40 - 43
Control RE
PTs
OE
#44 - 46 CK
0491/1048EA
#55
Y0
#54
GOE 0,1
Derivations of tsu, th and tco from the Product Term Clock 1
tsu
=
=
=
0.8 =
Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))
(#22 + #30 + #37) + (#40) - (#22 + #30 + #46)
(0.3 + 1.6 + 2.2) + (0.3) - (0.3 + 1.6 + 1.7)
th
=
=
=
2.5 =
Clock (max) + Reg h - Logic
(tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 1.6 + 2.7) + (2.0) - (0.3 + 1.6 + 2.2)
tco
=
=
=
7.9 =
Clock (max) + Reg co + Output
(tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
(#22 + #30 + #46) + (#42) + (#48 + #50)
(0.3 + 1.6 + 2.7) + (1.4) + (1.0 + 0.9)
Derivations of tsu, th and tco from the Clock GLB 1
tsu
=
=
=
1.3 =
Logic + Reg (setup) - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))
(#22 + #30 + #37) + (#40) - (#55 + #42 + #57)
(0.3 + 1.6 + 2.2) + (0.3) - (0.9 + 1.4 + 0.8)
th
=
=
=
2.0 =
Clock (max) + Reg (hold) - Logic
(tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
(#55 + #42 + #57) + (#41) - (#22 + #30 + #37)
(0.9 + 1.4 + 1.8) + (2.0) - (0.3 + 1.6 + 2.2)
tco
=
=
=
7.4 =
Clock (max) + Reg(clock-to-out) + Output
(tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
(#55 + #42 + #57) + (#42) + (#48 + #50)
(0.9 + 1.4 + 1.8) + (1.4) + (1.0 + 0.9)
1. Calculations are based upon timing specifications for the ispLSI 1048EA-170.
Table 2-0042/1048EA
v.2.0
9
I/O Pin
(Output)
Specifications ispLSI 1048EA
Maximum GRP Delay vs. GLB Loads
5
GRP Delay (ns)
ispLSI 1048EA-100
ispLSI 1048EA-125
4
ispLSI 1048EA-170
3
2
1
1 4 8
16
32
48
GRP/GLB/1048EA
GLB Load
Power Consumption
Power consumption in the ispLSI 1048EA device depends on two primary factors: the speed at which the
device is operating and the number of Product Terms
used. Figure 4 shows the relationship between power
and operating speed.
Figure 4. Typical Device Power Consumption vs fmax
500
ispLSI 1048EA
ICC (mA)
400
300
200
100
0
25
50
75 100 125
fmax (MHz)
150
175
Notes: Configuration of twelve 16-bit counters, Typical current at 5V, 25¡C
Icc can be estimated for the ispLSI 1048EA using the following equation:
Icc = 20mA + (# of PTs * .45) + (# of nets * Max Freq * .0087)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The Icc estimate is based on typical conditions (Vcc = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of Icc is sensitive to operating
conditions and the program in the device, the actual Icc should be verified.
0127/1048EA
Package Thermal Characteristics
For the ispLSI 1048EA-170, it is strongly recommended
that the actual Icc be verified to ensure that the maximum
junction temperature (TJ) with power supplied is not
exceeded. Depending on the specific logic design and
clock speed, airflow may be required to satisfy the maxi-
mum allowable junction temperature (TJ) specification.
Please refer to the Thermal Management section of the
Lattice Semiconductor Data Book or CD-ROM for additional information on calculating TJ.
10
Specifications ispLSI 1048EA
Pin Description
NAME
PQFP / TQFP PIN NUMBERS
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
104,
117,
123,
2,
8,
22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
105,
118,
124,
3,
9,
GOE0, GOE1
64,
114
IN 2, IN 4, IN 6-IN 11 47,
116,
51
14
23,
29,
36,
42,
54,
60,
68,
74,
87,
93,
100,
106,
119,
125,
4,
10,
24,
30,
37,
43,
55,
61,
69,
75,
88,
94,
101,
107,
120,
126,
5,
11,
25,
31,
38,
44,
56,
62,
70,
76,
89,
95,
102,
108,
121,
127,
6,
12,
DESCRIPTION
26,
32,
39,
45,
57,
63,
71,
77,
90,
96,
103,
109,
122,
128,
7,
13
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Global Output Enable input pins.
84,
110,
111,
115,
Dedicated input pins to the device.
TDI
20
Input - Functions as an input pin to load programming data into the
device and also is used as one of the two control pins for the ISP JTAG
state machine.
TMS
46
Input - Controls the operation of the ISP JTAG state machine.
TDO
50
Output - Functions as an output pin to read serial shift register data.
TCK
78
Input - Functions as a clock pin for the Serial Shift Register.
RESET
19
Y0
15
Y1
83
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Y2
80
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Y3
79
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
GND
1,
97,
17,
112
33,
49,
VCC
16,
48,
82,
113
VCCIO
18
65,
81,
Ground (GND)
VCC
Supply voltage for output drivers, 5V or 3.3V.
Table 2-0002C/1048EA
11
Specifications ispLSI 1048EA
Pin Configuration
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
IN 10
IN 9
GOE 1
VCC
GND
IN 8
IN 7
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
ispLSI 1048EA 128-Pin PQFP Pinout Diagram
ispLSI 1048EA
Top View
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
Y1
VCC
GND
Y2
Y3
TCK
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
GND
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
TMS
IN 2
VCC
GND
TDO
IN 4
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
GOE 0
GND
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
IN 11
Y0
VCC
GND
VCCIO
RESET
TDI
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
0124/1048EA
12
Specifications ispLSI 1048EA
Pin Configuration
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
IN 10
IN 9
GOE 1
VCC
GND
IN 8
IN 7
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
ispLSI 1048EA 128-Pin TQFP Pinout Diagram
ispLSI 1048EA
Top View
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
Y1
VCC
GND
Y2
Y3
TCK
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
GND
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
TMS
IN 2
VCC
GND
TDO
IN 4
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
GOE 0
GND
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
IN 11
Y0
VCC
GND
VCCIO
RESET
TDI
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
128TQFP/1048EA
13
Specifications ispLSI 1048EA
Part Number Description
ispLSI 1048EA - XXX
X
XXXX
X
Device Family
Grade
Blank = Commercial
Device Number
Package
Q128 = 128-Pin PQFP
T128 = 128-Pin TQFP
Speed
170 = 170 MHz fmax
125 = 125 MHz fmax
100 = 100 MHz fmax
Power
L = Low
0212/1048EA
ispLSI 1048EA Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
170*
170*
5.0
5.0
ispLSI 1048EA-170LQ128
ispLSI 1048EA-170LT128
128-Pin PQFP
128-Pin TQFP
125
125
7.5
7.5
100
100
10
10
ispLSI 1048EA-125LQ128
ispLSI 1048EA-125LT128
ispLSI 1048EA-100LQ128
ispLSI 1048EA-100LT128
128-Pin PQFP
128-Pin TQFP
128-Pin PQFP
128-Pin TQFP
*Note: Please refer to the Package Thermal Characteristics section of this data sheet for details.
14
Table 2-0041A/1048EA
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