Lattice ISPLSI2032-110LT48 In-system programmable high density pld Datasheet

®
ispLSI 2032/A
In-System Programmable High Density PLD
Features
Functional Block Diagram
• ENHANCEMENTS
GLB
Logic
Array
A6
D Q
D Q
A5
D Q
EW
A4
0139Bisp/2000
R
N
fmax = 180 MHz Maximum Operating Frequency
tpd = 5.0 ns Propagation Delay
Description
FO
• IN-SYSTEM PROGRAMMABLE
A2
D Q
A3
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
TTL Compatible Inputs and Outputs
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
A1
A7
Input Bus
Input Bus
Output Routing Pool (ORP)
1000 PLD Gates
32 I/O Pins, Two Dedicated Inputs
32 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
—
—
—
—
—
—
—
Global Routing Pool
(GRP)
A0
—
—
—
—
—
Output Routing Pool (ORP)
• HIGH DENSITY PROGRAMMABLE LOGIC
D
ES
IG
N
S
— ispLSI 2032A is Fully Form and Function Compatible
to the ispLSI 2032, with Identical Timing
Specifcations and Packaging
— ispLSI 2032A is Built on an Advanced 0.35 Micron
E2CMOS® Technology
The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers,
32 Universal I/O pins, two Dedicated Input Pins, three
Dedicated Clock Input Pins, one dedicated Global OE
input pin and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2032 and 2032A feature 5V insystem programmability and in-system diagnostic
capabilities. The ispLSI 2032 and 2032A offer nonvolatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
03
2E
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
I2
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
LS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
U
SE
is
p
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1 .. A7
(Figure 1). There are a total of eight GLBs in the ispLSI
2032 and 2032A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2032_10
1
January 2002
Specifications ispLSI 2032/A
Functional Block Diagram
Figure 1. ispLSI 2032/A Functional Block Diagram
I/O 12
I/O 13
I/O 14
I/O 15
A2
A5
A4
SDI/IN 0
SDO/IN 1
2E
MODE
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
Y0
*Y1/RESET
SCLK/Y2
03
ispEN
I/O 26
I/O 25
CLK 0
CLK 1
CLK 2
FO
A3
I/O 27
Input Bus
A6
EW
I/O 9
I/O 10
I/O 11
Global Routing Pool
(GRP)
A1
N
I/O 8
I/O 31
I/O 30
I/O 29
I/O 28
A7
R
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
Output Routing Pool (ORP)
A0
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
D
ES
IG
N
S
GOE 0
Notes:
*Y1 and RESET are multiplexed on the same pin
I2
0139B(1)isp/2000
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
pL
S
The devices also have 32 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
SE
is
Clocks in the ispLSI 2032 and 2032A devices are selected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
U
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032 and 2032A device contains one Megablock.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
2
Specifications ispLSI 2032/A
Absolute Maximum Ratings 1
Supply Voltage Vcc ...................................-0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
S
Storage Temperature ................................ -65 to 150°C
D
ES
IG
N
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
SYMBOL
EW
DC Recommended Operating Condition
PARAMETER
VIL
VIH
Input Low Voltage
UNITS
TA = 0°C to + 70°C
4.75
5.25
V
Industrial
TA = -40°C to + 85°C
4.5
5.5
V
0.8
V
0
2.0
FO
Input High Voltage
MAX.
Commercial
N
Supply Voltage
R
VCC
MIN.
Vcc+1
V
2E
Table 2 - 0005/2032
03
Capacitance (TA=25°C, f=1.0 MHz)
TYPICAL
UNITS
6
pf
VCC = 5.0V, VIN = 2.0V
I/O Capacitance
7
pf
VCC = 5.0V, VI/O = 2.0V
Clock Capacitance
10
pf
VCC = 5.0V, VY = 2.0V
SYMBOL
PARAMETER
C1
C2
C3
pL
S
I2
Dedicated Input Capacitance
TEST CONDITIONS
Table 2-0006/2032
SE
is
Data Retention Specifications
PARAMETER
MINIMUM
MAXIMUM
20
–
Years
10000
–
Cycles
Data Retention
U
Erase/Reprogram Cycles
UNITS
Table 2-0008A-isp
3
Specifications ispLSI 2032/A
Switching Test Conditions
Figure 2. Test Load
GND to 3.0V
Input Rise and Fall Time
10% to 90%
-135, -150, -180
≤ 1.5 ns
-80, -110
≤ 3 ns
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
+ 5V
R1
Device
Output
See Figure 2
R2
Output Load Conditions (see Figure 2)
C
R2
CL
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
0213A
EW
B
*CL includes Test Fixture and Probe Capacitance.
R1
N
A
C L*
D
ES
IG
N
Table 2-0003/2032
3-state levels are measured 0.5V from
steady-state active level.
TEST CONDITION
Test
Point
S
Input Pulse Levels
FO
R
Table 2 - 0004A
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS1
Output Low Voltage
ICC2, 4
TYP.
IOL= 8 mA
–
–
0.4
V
IOH = -4 mA
2.4
–
–
V
03
Output High Voltage
CONDITION
Input or I/O Low Leakage Current
3
MIN.
2E
PARAMETER
–
–
-10
µA
Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC
–
–
10
µA
ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL
–
–
-150
µA
pL
S
I2
0V ≤ VIN ≤ VIL (Max.)
MAX. UNITS
0V ≤ VIN ≤ VIL
–
–
-150
µA
Output Short Circuit Current
VCC = 5V, VOUT = 0.5V
–
–
-200
mA
-180, -150
VIL = 0.0V, VIH = 3.0V Comm.
Others
fTOGGLE = 1 MHz
Industrial
–
60
–
mA
Operating Power Supply Current
–
40
–
mA
–
40
–
mA
Table 2-0007/2032
SE
is
I/O Active Pull-Up Current
U
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using two 16-bit counters.
3. Typical values are at VCC = 5V and TA= 25°C.
4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I CC .
4
Specifications ispLSI 2032/A
External Timing Parameters
Over Recommended Operating Conditions
4
-135
-150
MIN. MAX. MIN. MAX. MIN. MAX.
A
1 Data Prop. Delay, 4PT Bypass, ORP Bypass
A
2 Data Prop. Delay
A
3 Clk Frequency with Internal Feedback 3
–
4 Clk Frequency with Ext. Feedback
–
–
5.0
–
5.5
–
7.5
10.0
UNITS
ns
–
7.5
–
8.0
–
180
–
154
–
137
125
–
111
–
100
–
MHz
5 Clk Frequency, Max. Toggle
200
–
167
–
167
–
MHz
ns
S
D
ES
IG
N
( tsu21+ tco1)
–
MHz
–
6 GLB Reg Setup Time before Clk, 4 PT Bypass
3.0
–
3.0
–
4.0
–
ns
A
7 GLB Reg. Clk to Output Delay, ORP Bypass
–
4.0
–
4.5
–
4.5
ns
–
8 GLB Reg. Hold Time after Clk, 4 PT Bypass
0.0
–
0.0
–
0.0
–
ns
–
9 GLB Reg. Setup Time before Clk
4.0
–
4.5
–
5.5
–
ns
–
10 GLB Reg. Clk to Output Delay
–
4.5
–
11 GLB Reg. Hold Time after Clk
A
12 Ext. Reset Pin to Output Delay
–
13 Ext. Reset Pulse Duration
5.0
–
5.5
ns
–
0.0
–
0.0
–
ns
–
7.0
–
8.0
–
10.0
ns
4.0
–
4.5
–
5.0
–
ns
–
10.0
–
11.0
–
12.0
ns
–
10.0
–
11.0
–
12.0
ns
–
5.0
–
5.0
–
6.0
ns
–
5.0
–
5.0
–
6.0
ns
N
EW
–
0.0
14 Input to Output Enable
15 Input to Output Disable
B
16 Global OE Output Enable
C
17 Global OE Output Disable
–
18 Ext. Synchronous Clk Pulse Duration, High
2.5
–
3.0
–
3.0
–
ns
–
19 Ext. Synchronous Clk Pulse Duration, Low
2.5
–
3.0
–
3.0
–
ns
R
B
C
03
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
U
SE
is
pL
S
I2
1.
2.
3.
4.
-180
DESCRIPTION1
FO
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
TEST
#2
COND.
2E
PARAMETER
5
Table 2-0030B-180/2032
Specifications ispLSI 2032/A
External Timing Parameters
Over Recommended Operating Conditions
4
TEST
#2
COND.
UNITS
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
10.0
–
15.0
ns
2
Data Propagation Delay
–
13.0
–
18.5
ns
111
–
84.0
3
Clock Frequency with Internal Feedback
1
tsu2 + tco1
4
Clock Frequency with External Feedback (
–
5
Clock Frequency, Max. Toggle
–
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
–
9
GLB Reg. Setup Time before Clock
–
10 GLB Reg. Clock to Output Delay
–
11 GLB Reg. Hold Time after Clock
A
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
C
15 Input to Output Disable
B
16 Global OE Output Enable
C
17 Global OE Output Disable
–
–
R
N
–
B
)
EW
–
–
D
ES
IG
N
A
3
S
A
A
MHz
77.0
–
57.0
–
MHz
125
–
83.0
–
MHz
5.5
–
7.5
–
ns
–
5.5
–
8.0
ns
0.0
–
0.0
–
ns
7.5
–
9.5
–
ns
–
6.5
–
9.5
ns
0.0
–
0.0
–
ns
–
13.5
–
19.5
ns
6.5
–
10.0
–
ns
–
14.5
–
24.0
ns
–
14.5
–
24.0
ns
–
7.0
–
12.0
ns
–
7.0
–
12.0
ns
18 External Synchronous Clock Pulse Duration, High
4.0
–
6.0
–
ns
19 External Synchronous Clock Pulse Duration, Low
4.0
–
6.0
–
ns
03
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
U
SE
is
pL
S
I2
1.
2.
3.
4.
MIN. MAX. MIN. MAX.
FO
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
-80
-110
DESCRIPTION1
2E
PARAMETER
6
Table 2-0030B-110/2032
Specifications ispLSI 2032/A
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
2
#
-180
DESCRIPTION
-135
-150
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
20 Input Buffer Delay
–
0.6
–
0.6
–
1.1
21 Dedicated Input Delay
–
1.1
–
1.3
–
22 GRP Delay
–
0.7
–
0.7
–
1.3
ns
23 4 Product Term Bypass Path Delay (Combinatorial)
–
2.3
–
2.6
–
3.6
ns
24 4 Product Term Bypass Path Delay (Registered)
–
3.1
–
3.1
–
3.6
ns
25 1 Product Term/XOR Path Delay
–
3.6
–
4.3
–
5.0
ns
26 20 Product Term/XOR Path Delay
–
4.1
–
4.6
–
5.1
ns
GRP
tgrp
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
4.8
–
5.0
–
5.6
ns
–
0.2
–
0.0
–
0.0
ns
0.5
–
0.7
–
0.3
–
ns
1.8
–
1.8
–
3.0
–
ns
–
0.7
–
0.8
–
0.7
ns
–
1.0
–
1.2
–
1.1
ns
33 GLB Product Term Reset to Register Delay
–
2.8
–
2.9
–
4.4
ns
34 GLB Product Term Output Enable to I/O Cell Delay
–
5.9
–
6.9
–
6.4
ns
2.5
3.8
2.5
4.1
2.9
5.2
ns
–
0.7
–
0.8
–
1.3
ns
–
0.2
–
0.3
–
0.3
ns
–
1.2
–
1.3
–
1.2
ns
39 Output Slew Limited Delay Adder
–
10.0
–
10.0
–
10.0
ns
40 I/O Cell OE to Output Enabled
–
2.8
–
2.8
–
3.2
ns
41 I/O Cell OE to Output Disabled
–
2.8
–
2.8
–
3.2
ns
42 Global Output Enable
–
2.2
–
2.2
–
2.8
ns
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
1.9
1.9
2.1
2.1
2.3
2.3
ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
1.9
1.9
2.1
2.1
2.3
2.3
ns
–
4.1
–
4.7
–
6.4
ns
28 GLB Register Bypass Delay
30 GLB Register Hold Time after Clock
FO
32 GLB Register Reset to Output Delay
2E
35 GLB Product Term Clock Delay
03
36 ORP Delay
37 ORP Bypass Delay
I2
is
pL
S
38 Output Buffer Delay
SE
tgy0
tgy1/2
R
31 GLB Register Clock to Output Delay
Outputs
Clocks
N
29 GLB Register Setup Time before Clock
ORP
tob
tsl
toen
todis
tgoe
ns
–
27 XOR Adjacent Path Delay 3
torp
torpbp
ns
EW
GLB
2.4
D
ES
IG
N
tio
tdin
S
Inputs
U
Global Reset
tgr
45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Table 2-0036C-180/2032
Specifications ispLSI 2032/A
Internal Timing Parameters1
Over Recommended Operating Conditions
#2
PARAMETER
-80
-110
DESCRIPTION
MIN. MAX. MIN. MAX.
UNITS
Inputs
–
1.7
–
2.2
21 Dedicated Input Delay
–
3.4
–
4.8
GRP
tgrp
22 GRP Delay
GLB
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay
30 GLB Register Hold Time after Clock
ns
–
1.7
–
2.6
ns
–
4.9
–
7.2
ns
–
4.8
–
7.2
ns
–
6.2
–
8.8
ns
–
6.8
–
9.2
ns
–
7.5
–
10.2
ns
–
0.1
–
0.0
ns
0.5
–
0.1
–
ns
4.0
–
6.0
–
ns
–
0.6
–
0.4
ns
–
1.8
–
2.2
ns
33 GLB Product Term Reset to Register Delay
–
5.9
–
8.8
ns
34 GLB Product Term Output Enable to I/O Cell Delay
–
7.1
–
12.8
ns
4.0
7.0
5.5
9.5
ns
–
1.5
–
2.1
ns
–
0.5
–
0.6
ns
38 Output Buffer Delay
–
1.2
–
2.4
ns
39 Output Slew Limited Delay Adder
–
10.0
–
10.0
ns
40 I/O Cell OE to Output Enabled
–
4.0
–
6.4
ns
41 I/O Cell OE to Output Disabled
–
4.0
–
6.4
ns
42 Global Output Enable
–
3.0
–
5.6
ns
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
3.2
3.2
4.6
4.6
ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
3.2
3.2
4.6
4.6
ns
–
9.0
–
12.8
ns
FO
32 GLB Register Reset to Output Delay
35 GLB Product Term Clock Delay
03
36 ORP Delay
37 ORP Bypass Delay
I2
pL
S
SE
tgy0
tgy1/2
R
31 GLB Register Clock to Output Delay
is
Clocks
N
29 GLB Register Setup Time befor Clock
Outputs
tob
tsl
toen
todis
tgoe
3
28 GLB Register Bypass Delay
ORP
torp
torpbp
EW
26 20 Product Term/XOR Path Delay
2E
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
ns
S
20 Input Buffer Delay
D
ES
IG
N
tio
tdin
U
Global Reset
tgr
45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
Table 2-0036C-110/2032
Specifications ispLSI 2032/A
ispLSI 2032/A Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
GRP
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#20
#22
#24
#28
#37
20 PT
XOR Delays
GLB Reg
Delay
D
#25, 26, 27
ORP
Delay
Q
RST
#45
Reset
#29, 30,
31, 32
EW
Control RE
PTs
OE
#33, 34, CK
35
#43, 44
Y0,1,2
R
N
#42
GOE 0
FO
Derivations of tsu, th and tco from the Product Term Clock 1
=
=
=
2.1 ns =
Logic + Reg su - Clock (min)
(tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
(#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
(0.6 + 0.7 + 4.1) + (0.5) - (0.6 + 0.7 + 2.5)
th
=
=
=
1.5 ns =
Clock (max) + Reg h - Logic
(tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
(#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
(0.6 + 0.7 + 3.8) + (1.8) - (0.6 + 0.7 + 4.1)
tco
=
=
=
7.7 ns =
Clock (max) + Reg co + Output
(tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#20+ #22+ #35) + (#31) + (#36 + #38)
(0.6 + 0.7 + 3.8) + (0.7) + (0.7 + 1.2)
is
pL
S
I2
03
2E
tsu
Note: Calculations are based upon timing specifications for the ispLSI 2032/A-180L
U
SE
Table 2- 0042-16/2032
9
#38,
39
D
ES
IG
N
I/O Pin
(Input)
Comb 4 PT Bypass #23
#21
I/O Delay
S
Ded. In
#36
#40, 41
0491/2000
I/O Pin
(Output)
Specifications ispLSI 2032/A
Power Consumption
used. Figure 4 shows the relationship between power
and operating speed.
Power consumption in the ispLSI 2032 and 2032A devices depends on two primary factors: the speed at which
the device is operating and the number of Product Terms
D
ES
IG
N
S
Figure 4. Typical Device Power Consumption vs fmax
120
110
ispLSI 2032/A (-150, -180)
90
EW
ICC (mA)
100
80
70
N
ispLSI 2032/A (-80, -110, -135)
60
40
20
40
60
2E
1
FO
R
50
80
100 120 140 160 180
fmax (MHz)
03
Notes: Configuration of Two 16-bit Counters
Typical Current at 5V, 25° C
I2
ICC can be estimated for the ispLSI 2032/A using the following equation:
pL
S
For 2032/A -150, -180: ICC(mA) = 30 + (# of PTs * 0.46) + (# of nets * Max freq * 0.012)
For 2032/A -135, -110, -80: ICC(mA) = 21 + (# of PTs * 0.30) + (# of nets * Max freq * 0.012)
SE
is
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
U
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
0127A/2032A
10
Specifications ispLSI 2032/A
Pin Description
44-PIN PLCC
PIN NUMBERS
44-PIN TQFP
PIN NUMBERS
48-PIN TQFP
PIN NUMBERS
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
15,
19,
25,
29,
37,
41,
3,
7,
9,
13,
19,
23,
31
35,
41,
1,
9,
14,
20,
25,
33,
38,
44,
1,
GOE 0
2
40
43
Global Output Enable input pin.
Y0
11
5
5
RESET/Y1
35
29
31
Dedicated Clock input. This clock input is connected to
one of the clock inputs of all the GLBs on the device.
This pin performs two functions:
- Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can optionally
be routed to any GLB and/or I/O cell on the device.
- Active Low (0) Reset pin which resets all of the GLB
and I/O registers in the device.
ispEN
13
7
7
SDI/IN 02
14
8
8
MODE
36
30
SDO/IN 12
24
18
SCLK/Y22
33
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
10,
15,
21,
26,
34,
39,
45,
2,
11,
16,
22,
27,
35,
40,
46,
3,
13,
17,
23,
28,
37,
41,
47,
4
Input — Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The MODE, SDI, SDO and SCLK
controls become active.
23
is
12, 34
FO
2E
Input — When in ISP Mode, controls operation of ISP
state machine.
19
Output/Input — This pin performs two functions. When
ispEN is logic low, it functions as an output pin to read
serial shift register data. When ispEN is high, it
functions as a dedicated input pin.
27
29
Input — This pin performs two functions. When
ispEN is logic low, it functions as a clock pin for the
Serial Shift Register. When ispEN is high, it
functions as a dedicated clock input. This clock input
is brought into the Clock Distribution Network and
can be routed to any GLB and/or I/O cell on the
device.
17, 39
18, 42
Ground (GND)
6,
6,
VCC
28
30
12, 24, 36, 48
SE
NC1
Input — This pin performs two functions. When ispEN
is logic low, it functions as an input pin to load
programming data into the device. SDI/IN0 also is used
as one of the two control pins for the isp state machine.
When ispEN is high, it functions as a dedicated input
pin.
03
VCC
1,
32
I2
pL
S
GND
DESCRIPTION
Input/Output Pins — These are the general purpose
I/O pins used by the logic array.
S
10,
14,
20,
24,
32,
36,
42,
2,
D
ES
IG
N
18,
22,
28,
32,
40,
44,
6,
10
EW
17,
21,
27,
31,
39,
43,
5,
9,
N
16,
20,
26,
30,
38,
42,
4,
8,
R
NAME
U
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
11
No Connect.
Table 2-0002A-08isp/2032
Specifications ispLSI 2032/A
Pin Configuration
I/O 21
I/O 20
I/O 19
I/O 22
GND
I/O 23
GOE 0
I/O 24
I/O 26
I/O 25
I/O 27
ispLSI 2032/A 44-Pin PLCC Pinout Diagram
I/O 29
7
8
I/O 30
9
I/O 31
10
11
Y0
VCC
ispEN
13
0
14
I/O 0
I/O 1
I/O 2
15
16
17
Top View
39
I/O 18
38
37
I/O 17
I/O 16
36
MODE
35
34
RESET/Y1
VCC
33
SCLK/Y21
32
I/O 15
31
30
29
I/O 14
I/O 13
I/O 12
EW
1SDI/IN
ispLSI 2032/A
12
D
ES
IG
N
I/O 28
S
6 5 4 3 2 1 44 43 42 41 40
N
I/O 9
I/O 10
I/O 11
R
I/O 8
1
1SDO/IN
GND
I/O 7
I/O 6
I/O 4
I/O 5
I/O 3
18 19 20 21 22 23 24 25 26 27 28
FO
0123B/2032/A
2E
1. Pins have dual function capability.
I2
pL
S
I/O 28
I/O 29
I/O 30
Y0
VCC
ispEN
1SDI/IN
0
I/O 0
I/O 1
I/O 2
I/O 21
I/O 20
I/O 19
I/O 22
GND
I/O 23
GOE 0
I/O 24
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5
33
I/O 18
32
31
I/O 17
I/O 16
30
MODE
RESET/Y1
VCC
6
ispLSI 2032/A
29
28
7
Top View
27
SCLK/Y21
8
26
I/O 15
9
10
11
25
24
23
I/O 14
I/O 13
I/O 12
12
I/O 9
I/O 10
I/O 11
1
1. Pins have dual function capability.
I/O 8
1SDO/IN
GND
I/O 7
I/O 6
I/O 4
I/O 5
12 13 14 15 16 17 18 19 20 21 22
I/O 3
U
SE
is
I/O 31
I/O 26
I/O 25
I/O 27
03
ispLSI 2032/A 44-Pin TQFP Pinout Diagram
0851/2032/A
Specifications ispLSI 2032/A
Pin Configuration
I/O 21
I/O 20
I/O 19
I/O 22
GND
I/O 23
GOE 0
I/O 24
I/O 26
I/O 25
I/O 27
NC1
ispLSI 2032/A 48-Pin TQFP Pinout Diagram
I/O 29
I/O 30
I/O 31
Y0
VCC
ispEN
1
2
36
NC1
35
I/O 18
34
33
3
4
5
6
ispLSI 2032/A
7
Top View
32
31
30
8
29
I/O 0
I/O 1
I/O 2
1NC
9
28
10
11
12
27
26
25
EW
0
2SDI/IN
D
ES
IG
N
I/O 28
I/O 17
I/O 16
MODE
RESET/Y12
VCC
SCLK/Y22
I/O 15
I/O 14
I/O 13
I/O 12
FO
N
I/O 9
I/O 10
I/O 11
1NC
R
I/O 8
I/O 7
GND
2SDO/IN 1
I/O 6
I/O 4
I/O 5
I/O 3
13 14 15 16 17 18 19 20 21 22 23 24
48-Pin TQFP-2032/A
U
SE
is
pL
S
I2
03
2E
1. NC pins are not to be connected to any active signal, Vcc or GND.
2. Pins have dual function capability.
13
S
48 47 46 45 44 43 42 41 40 39 38 37
Specifications ispLSI 2032/A
Part Number Description
ispLSI XXXX —XXX X XXX X
Device Family
Grade
Blank = Commercial
I = Industrial
Package
J = PLCC
T44 = TQFP
T48 = TQFP
Power
L = Low
D
ES
IG
N
S
Device Number
2032
2032A
Speed
180 = 180 MHz fmax
150 = 154 MHz fmax
135 = 137 MHz fmax
110 = 111 MHz fmax
80 = 84 MHz fmax
0212A/2032
EW
ispLSI 2032/A Ordering Information
COMMERCIAL
tpd (ns)
ispLSI
180
180
180
154
154
154
137
137
137
111
111
111
84
84
84
5.0
5.0
5.0
5.5
5.5
5.5
7.5
7.5
7.5
10
10
10
15
15
15
U
ispLSI
FO
2E
03
I2
pL
S
is
SE
FAMILY
ORDERING NUMBER
PACKAGE
ispLSI 2032A-180LJ44
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
N
fmax (MHz)
R
FAMILY
ispLSI 2032A-180LT44
ispLSI 2032A-180LT48
ispLSI 2032A-150LJ44
ispLSI 2032A-150LT44
ispLSI 2032A-150LT48
ispLSI 2032A-135LJ44
ispLSI 2032A-135LT44
ispLSI 2032A-135LT48
ispLSI 2032A-110LJ44
ispLSI 2032A-110LT44
ispLSI 2032A-110LT48
ispLSI 2032A-80LJ44
ispLSI 2032A-80LT44
ispLSI 2032A-80LT48
Table 2-0041A/2032A
INDUSTRIAL
fmax (MHz)
tpd (ns)
84
84
84
15
15
15
ORDERING NUMBER
PACKAGE
ispLSI 2032A-80LJ44I
ispLSI 2032A-80LT44I
ispLSI 2032A-80LT48I
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
Table 2-0041B/2032A
14
Specifications ispLSI 2032/A
COMMERCIAL
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
ispLSI
180
180
180
154
154
154
137
137
137
111
111
111
84
84
84
5.0
5.0
5.0
5.5
5.5
5.5
7.5
7.5
7.5
10
10
10
15
15
15
ispLSI 2032-180LJ
ispLSI 2032-180LT44
ispLSI 2032-180LT48
ispLSI 2032-150LJ
ispLSI 2032-150LT44
ispLSI 2032-150LT48
ispLSI 2032-135LJ
ispLSI 2032-135LT44
ispLSI 2032-135LT48
ispLSI 2032-110LJ
ispLSI 2032-110LT44
ispLSI 2032-110LT48
ispLSI 2032-80LJ
ispLSI 2032-80LT44
ispLSI 2032-80LT48
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
EW
D
ES
IG
N
S
FAMILY
N
INDUSTRIAL
Table 2-0041A/2032
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
ispLSI
84
84
84
15
15
15
ispLSI 2032-80LJI
ispLSI 2032-80LT44I
ispLSI 2032-80LT48I
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
U
SE
is
pL
S
I2
03
2E
FO
R
FAMILY
15
Table 2-0041C/2032
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