Lattice ISPLSI2032E-135LJ44 In-system programmable superfast high density pld Datasheet

®
ispLSI 2032E
In-System Programmable
SuperFAST™ High Density PLD
Functional Block Diagram
Input Bus
®
• HIGH PERFORMANCE E CMOS TECHNOLOGY
— fmax = 225 MHz Maximum Operating Frequency
— tpd = 3.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG™ In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O (48-Pin Package Only)
Supports Mixed Voltage Systems
— PCI Compatible Outputs (48-Pin Package Only)
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
Output Routing Pool (ORP)
2
Global Routing Pool
(GRP)
A0
A1
A2
D Q
GLB
Logic
Array
A7
A6
D Q
D Q
A5
D Q
A3
Input Bus
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functionally and JEDEC Upward Compatible
with ispLSI 2032 Devices
Output Routing Pool (ORP)
Features
A4
0139Bisp/2000
Description
The ispLSI 2032E is a High Density Programmable Logic
Device. The device contains 32 Registers, 32 Universal
I/O pins, two Dedicated Input Pins, three Dedicated
Clock Input Pins, one dedicated Global OE input pin and
a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.
The ispLSI 2032E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI
2032E offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on the ispLSI 2032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
Copyright © 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2032e_05
1
November 2003
Specifications ispLSI 2032E
Functional Block Diagram
Figure 1. ispLSI 2032E Functional Block Diagram
GOE 0
I/O 12
I/O 13
I/O 14
I/O 15
A1
I/O 31
I/O 30
I/O 29
I/O 28
A7
Global Routing Pool
(GRP)
A2
A6
A5
A4
A3
I/O 27
Input Bus
I/O 9
I/O 10
I/O 11
Output Routing Pool (ORP)
I/O 8
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
A0
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
CLK 0
CLK 1
CLK 2
TDI/IN 0
TDO/IN 1
TMS
BSCAN
Y0
Y1*
TCK/Y2
Notes:
*Y1 and RESET are multiplexed on the same pin
0139/2032E
Clocks in the ispLSI 2032E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
programmed to be a combinatorial input, output or bidirectional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate
to minimize overall output switching noise. By connecting
the VCCIO pins to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compatible voltages. When connected to a 5V supply, the I/O
pins provide PCI-compatible output drive (48-pin device
only).
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2032E are individually programmable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the Lattice software tools.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032E device contains one Megablock.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
2
Specifications ispLSI 2032E
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
4.75
5.25
V
5V
4.75
5.25
V
3.3V
3.0
3.6
V
V
VCC
Supply Voltage: Logic Core, Input Buffers
VCCIO1
Supply Voltage: Output Drivers
VIL
VIH
Input Low Voltage
0
0.8
Input High Voltage
2.0
Vcc+1
TA = 0°C to +70°C
V
Table 2-0005/2032E
1. 3.3V I/O operation not available for 44-pin packages.
Capacitance (TA=25°C, f=1.0 MHz)
TYP
UNITS
Dedicated Input Capacitance
6
pf
VCC = 5.0V, VIN = 2.0V
I/O Capacitance
7
pf
VCC = 5.0V, VI/O = 2.0V
Clock Capacitance
10
pf
VCC = 5.0V, VY = 2.0V
SYMBOL
C1
C2
C3
PARAMETER
TEST CONDITIONS
Table 2-0006/2032E
Erase/Reprogram Specification
PARAMETER
Erase/Reprogram Cycles
MINIMUM
MAXIMUM
UNITS
10,000
–
Cycles
Table 2-0008/2032E
3
Specifications ispLSI 2032E
Switching Test Conditions
Input Pulse Levels
Figure 2. Test Load
GND to 3.0V
+ 5V
1.5 ns
Input Rise and Fall Time 10% to 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
R1
Device
Output
See Figure 2
Table 2-0003/2032E
3-state levels are measured 0.5V from
steady-state active level.
Test
Point
R2
CL*
Output Load Conditions (see Figure 2)
TEST CONDITION
R1
R2
CL
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
A
B
C
*CL includes Test Fixture and Probe Capacitance.
0213A
5pF
Table 2 - 0004A
DC Electrical Characteristics
Over Recommended Operating Conditions1
SYMBOL
VOL
VOH
IIL
IIH
IIL-PU
IOS1
ICC2,4,6
1.
2.
3.
4.
5.
6.
PARAMETER
CONDITION
MIN.
TYP.3
MAX. UNITS
Output Low Voltage
IOL = 8 mA
–
–
0.4
V
Output High Voltage
IOH = -4 mA
2.4
–
–
V
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
I/O Active Pull-Up Current, non-PCI
5
I/O Active Pull-Up Current, PCI
0V ≤ VIN ≤ VIL (Max.)
–
–
-10
µA
(VCCIO - 0.2)V ≤ VIN ≤ VCCIO
–
–
10
µA
VCCIO ≤ VIN ≤ 5.25V
–
–
10
µA
0V ≤ VIN ≤ 2.0V
-10
–
-150
µA
0V ≤ VIN ≤ 2.0V
-10
–
-250
µA
–
–
-200
mA
Output Short Circuit Current, non-PCI VCCIO = 5V, VOUT = 0.5V
Output Short Circuit Current, PCI5
Operating Power Supply Current
VCCIO = 5.0V or 3.3V, VOUT = 0.5V
VIL = 0.0V, VIH = 3.0V
fTOGGLE = 1 MHz
–
–
-240
mA
-225/-200
–
85
–
mA
Others
–
65
–
mA
Table 2-0007/2032E
One output at a time for a maximum duration of one second (VOUT = 0.5V). Characterized, but not 100% tested.
Meaured using two 16-bit counters.
Typical values are at VCC = 5V and TA = 25°C.
Unused inputs held at 0.0V.
Available in 48-pin package only.
Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book or CD-ROM to estimate maximum ICC.
4
Specifications ispLSI 2032E
External Timing Parameters
Over Recommended Operating Conditions
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
1.
2.
3.
4.
TEST
2
4 #
COND.
-225
DESCRIPTION1
-180
-200
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
A
1 Data Prop. Delay, 4PT Bypass, ORP Bypass
–
3.5
–
3.5
–
5.0
ns
A
2 Data Prop. Delay
–
5.5
–
5.5
–
7.5
ns
A
3 Clk Frequency with Int. Feedback3
225
–
200
–
180
–
MHz
167
–
167
–
125
–
MHz
250
–
200
–
MHz
2.5
–
3.0
–
ns
–
2.5
–
4.0
ns
0.0
–
0.0
–
ns
3.5
–
4.0
–
ns
–
3.5
–
4.5
ns
0.0
–
0.0
–
ns
–
5.0
–
6.5
ns
3.5
–
4.0
–
ns
–
7.0
–
10.0
ns
–
7.0
–
10.0
ns
–
3.5
–
5.0
ns
1
tsu2 + tco1
–
4 Clk Frequency with Ext. Feedback (
)
–
5 Clk Frequency, Max. Toggle
250
–
–
6 GLB Reg. Setup Time before Clk, 4 PT Bypass
2.5
–
A
7 GLB Reg. Clk to Output Delay, ORP Bypass
–
2.5
–
8 GLB Reg. Hold Time after Clk, 4 PT Bypass
0.0
–
–
9 GLB Reg. Setup Time before Clk
3.5
–
–
10 GLB Reg. Clk to Output Delay
–
3.5
–
11 GLB Reg. Hold Time after Clk
0.0
–
A
12 Ext. Reset Pin to Output Delay, ORP Bypass
–
5.0
USE 2032E-22
5 FOR
NEW DESIGNS
PARAMETER
–
13 Ext. Reset Pulse Duration
3.5
–
B
14 Input to Output Enable
–
7.0
C
15 Input to Output Disable
–
7.0
B
16 Global OE Output Enable
–
3.5
C
17 Global OE Output Disable
–
3.5
–
3.5
–
5.0
ns
–
18 Ext. Synch. Clk Pulse Duration, High
2.0
–
2.0
–
2.5
–
ns
–
19 Ext. Synch. Clk Pulse Duration, Low
2.0
–
2.0
–
2.5
–
ns
Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
5
Table 2-0030A/2032E
Specifications ispLSI 2032E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
1.
2.
3.
4.
TEST
2
4 #
COND.
-110
-135
DESCRIPTION1
MIN. MAX. MIN. MAX.
UNITS
A
1 Data Propagation Delay, 4PT Bypass, ORP Bypass
–
7.5
–
10.0
ns
A
2 Data Propagation Delay
–
10.0
–
13.0
ns
A
3 Clock Frequency with Internal Feedback3
137
–
111
–
MHz
100
–
77.0
–
MHz
1
tsu2 + tco1
–
4 Clock Frequency with External Feedback (
)
–
5 Clock Frequency, Max. Toggle
167
–
125
–
MHz
–
6 GLB Register Setup Time before Clock, 4 PT Bypass
4.0
–
5.5
–
ns
A
7 GLB Register Clock to Output Delay, ORP Bypass
–
4.5
–
5.5
ns
–
8 GLB Register Hold Time after Clock, 4 PT Bypass
0.0
–
0.0
–
ns
–
9 GLB Register Setup Time before Clock
5.5
–
7.5
–
ns
–
10 GLB Register Clock to Output Delay
–
5.5
–
6.5
ns
–
11 GLB Register Hold Time after Clock
0.0
–
0.0
–
ns
A
12 External Reset Pin to Output Delay, ORP Bypass
–
9.0
–
12.5
ns
–
13 External Reset Pulse Duration
5.0
–
6.5
–
ns
B
14 Input to Output Enable
–
12.0
–
14.5
ns
C
15 Input to Output Disable
–
12.0
–
14.5
ns
B
16 Global OE Output Enable
–
6.0
–
7.0
ns
C
17 Global OE Output Disable
–
6.0
–
7.0
ns
–
18 External Synchronous Clock Pulse Duration, High
3.0
–
4.0
–
ns
–
19 External Synchronous Clock Pulse Duration, Low
3.0
–
4.0
–
ns
Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
6
Table 2-0030B/2032E
Specifications ispLSI 2032E
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
2
#
-225
DESCRIPTION
-180
-200
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
20 Input Buffer Delay
–
0.6
–
0.4
–
0.6
ns
21 Dedicated Input Delay
–
1.3
–
1.3
–
1.3
ns
22 GRP Delay
–
0.7
–
0.7
–
0.7
ns
23 4 Product Term Bypass Path Delay (Combinatorial)
–
1.2
–
1.8
–
1.8
ns
24 4 Product Term Bypass Path Delay (Registered)
–
1.2
–
1.8
–
2.8
ns
25 1 Product Term/XOR Path Delay
–
2.2
–
2.8
–
3.8
ns
26 20 Product Term/XOR Path Delay
–
2.2
–
SIGNS
tio
tdin
2.8
–
3.8
ns
–
2.2
–
2.8
–
3.8
ns
–
0.0
–
0.0
–
0.0
ns
29 GLB Register Setup Time before Clock
0.8
–
0.8
–
0.3
–
ns
30 GLB Register Hold Time after Clock
1.7
–
1.7
–
2.7
–
ns
31 GLB Register Clock to Output Delay
–
0.7
–
0.7
–
0.7
ns
32 GLB Register Reset to Output Delay
–
1.3
–
2.9
–
1.1
ns
33 GLB Product Term Reset to Register Delay
–
2.5
–
2.5
–
2.9
ns
34 GLB Product Term Output Enable to I/O Cell Delay
–
4.2
–
4.4
–
5.9
ns
0.3
2.8
0.7
3.2
1.5
3.7
ns
36 ORP Delay
–
1.0
37 ORP Bypass Delay
–
0.0
38 Output Buffer Delay
–
1.0
39 Output Slew Limited Delay Adder
–
1.5
40 I/O Cell OE to Output Enabled
–
1.5
41 I/O Cell OE to Output Disabled
–
1.5
42 Global Output Enable
–
2.0
USE 2032E-22
Inputs
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
0.8
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
GRP
tgrp
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
27 XOR Adjacent Path Delay
3
28 GLB Register Bypass Delay
35 GLB Product Term Clock Delay
ORP
torp
torpbp
Outputs
tob
tsl
toen
todis
tgoe
5 FOR NEW DE
GLB
–
1.0
–
1.1
ns
–
0.0
–
0.6
ns
–
0.6
–
1.3
ns
–
1.5
–
1.5
ns
–
1.5
–
2.8
ns
–
1.5
–
2.8
ns
–
2.0
–
2.2
ns
0.8
1.2
1.2
1.4
1.4
ns
1.0
1.0
1.4
1.4
1.6
1.6
ns
–
2.7
–
2.7
–
3.5
ns
Clocks
tgy0
tgy1/2
Global Reset
tgr
45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Table 2-0036A/2032E
Specifications ispLSI 2032E
Internal Timing Parameters1
PARAMETER
2
#
-110
-135
DESCRIPTION
MIN. MAX. MIN. MAX.
UNITS
Inputs
tio
tdin
20 Input Buffer Delay
–
1.1
–
1.7
ns
21 Dedicated Input Delay
–
2.4
–
3.4
ns
22 GRP Delay
–
1.3
–
1.7
ns
23 4 Product Term Bypass Path Delay (Combinatorial)
–
3.6
–
4.9
ns
24 4 Product Term Bypass Path Delay (Registered)
–
3.6
–
4.8
ns
25 1 Product Term/XOR Path Delay
–
5.0
–
6.2
ns
26 20 Product Term/XOR Path Delay
–
5.1
–
6.8
ns
GRP
tgrp
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
27 XOR Adjacent Path Delay
3
–
5.6
–
7.5
ns
–
0.0
–
0.1
ns
29 GLB Register Setup Time before Clock
0.3
–
0.5
–
ns
30 GLB Register Hold Time after Clock
3.0
–
4.0
–
ns
31 GLB Register Clock to Output Delay
–
0.7
–
0.6
ns
32 GLB Register Reset to Output Delay
–
1.1
–
1.8
ns
33 GLB Product Term Reset to Register Delay
–
4.4
–
5.9
ns
34 GLB Product Term Output Enable to I/O Cell Delay
–
6.4
–
7.1
ns
2.9
5.2
4.0
7.0
ns
36 ORP Delay
–
1.3
–
1.5
ns
37 ORP Bypass Delay
–
0.3
–
0.5
ns
38 Output Buffer Delay
–
1.2
–
1.2
ns
39 Output Slew Limited Delay Adder
–
10.0
–
10.0
ns
40 I/O Cell OE to Output Enabled
–
3.2
–
4.0
ns
41 I/O Cell OE to Output Disabled
–
3.2
–
4.0
ns
42 Global Output Enable
–
2.8
–
3.0
ns
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
2.3
2.3
3.2
3.2
ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.3
2.3
3.2
3.2
ns
–
6.4
–
9.0
ns
28 GLB Register Bypass Delay
35 GLB Product Term Clock Delay
ORP
torp
torpbp
Outputs
tob
tsl
toen
todis
tgoe
Clocks
tgy0
tgy1/2
Global Reset
tgr
45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
Table 2-0036B/2032E
Specifications ispLSI 2032E
ispLSI 2032E Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
I/O Pin
(Input)
Comb 4 PT Bypass #23
#21
I/O Delay
GRP
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#20
#22
#24
#28
#37
20 PT
XOR Delays
#25, 26, 27
GLB Reg
Delay
D
#38,
#39
ORP
Delay
Q
#36
RST
#45
Reset
#29, 30,
31, 32
Control RE
PTs
OE
#33, 34, CK
35
#40, 41
#43, 44
Y0,1,2
#42
GOE 0
0491/2032E
Derivations of tsu, th and tco from the Product Term Clock
tsu
=
=
=
2.7 =
Logic + Reg su - Clock (min)
(tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.6 + 0.7 + 2.2) + (0.8) - (0.6 + 0.7 + 0.3)
th
=
=
=
2.3 =
Clock (max) + Reg h - Logic
(tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.6 + 0.7 + 2.8) + (1.7) - (0.6 + 0.7 + 2.2)
tco
=
=
=
6.8 =
Clock (max) + Reg co + Output
(tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.6 + 0.7 + 2.8) + (0.7) + (1.0 + 1.0)
Note: Calculations are based upon timing specifications for the ispLSI 2032E-225L
Table 2-0042/2032E
9
I/O Pin
(Output)
Specifications ispLSI 2032E
Power Consumption
Figure 3 shows the relationship between power and
operating speed.
Power consumption in the ispLSI 2032E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
Figure 3. Typical Device Power Consumption vs fmax
ispLSI 2032E-225 and -200
150
140
130
120
ICC (mA)
110
ispLSI 2032E-180
and Slower
100
90
80
70
60
50
40
1
20
40
60
80
100 120 140 160 180 200 220 240
fmax (MHz)
Notes: Configuration of two 16-bit counters
Typical current at 5V, 25°C
ICC can be estimated for the ispLSI 2032E using the following equation:
For 2032E-225 and -200: ICC = 4.5 + (# of PTs * 1.3) + (# of nets * Max freq * 0.0035)
For 2032E-180 and Slower: ICC = 4.5 + (# of PTs * 1.02) + (# of nets * Max freq * 0.0035)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB
loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating
conditions and the program in the device, the actual ICC should be verified.
0127A/2032E
10
Specifications ispLSI 2032E
Pin Description
44-PIN PLCC
PIN NUMBERS
44-PIN TQFP
PIN NUMBERS
48-PIN TQFP
PIN NUMBERS
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
15,
19,
25,
29,
37,
41,
3,
7,
9,
13,
19,
23,
31
35,
41,
1,
9,
14,
20,
25,
33,
38,
44,
1,
GOE 0
2
40
43
Global Output Enable input pin.
Y0
11
5
5
RESET/Y1
35
29
31
Dedicated Clock input. This clock input is connected to
one of the clock inputs of all the GLBs on the device.
This pin performs two functions:
- Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can optionally
be routed to any GLB and/or I/O cell on the device.
- Active Low (0) Reset pin which resets all of the GLB
and I/O registers in the device.
BSCAN
13
7
7
Input — Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The TMS, TDI, TDO and TCK
controls become active.
TDI/IN 01
14
8
8
Input — This pin performs two functions. When
BSCAN is logic low, it functions as an input pin to load
programming data into the device. TDI/IN0 also is used
as one of the two control pins for the ISP state
machine. When BSCAN is high, it functions as a
dedicated input pin.
TMS/NC2
36
30
32
Input — When in ISP mode, controls operation of ISP
state machine.
TDO/IN 11
24
18
19
Output/Input — This pin performs two functions. When
BSCAN is logic low, it functions as an output pin to
read serial shift register data. When BSCAN is high, it
functions as a dedicated input pin.
TCK/Y21
33
27
29
Input — This pin performs two functions. When
BSCAN is logic low, it functions as a clock pin for the
Serial Shift Register. When BSCAN is high, it
functions as a dedicated clock input. This clock input
is brought into the Clock Distribution Network and
can be routed to any GLB and/or I/O cell on the
device.
GND
1,
17, 39
12, 18, 36, 42
Ground (GND)
VCC
12, 34
6,
VCC
NAME
VCCIO
16,
20,
26,
30,
38,
42,
4,
8,
23
17,
21,
27,
31,
39,
43,
5,
9,
18,
22,
28,
32,
40,
44,
6,
10
6,
10,
14,
20,
24,
32,
36,
42,
2,
28
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
10,
15,
21,
26,
34,
39,
45,
2,
30
24, 48
11,
16,
22,
27,
35,
40,
46,
3,
13,
17,
23,
28,
37,
41,
47,
4
DESCRIPTION
Input/Output Pins — These are the general purpose
I/O pins used by the logic array.
Supply voltage for output drivers, 5V or 3.3V. All
VCCIO pins must be connected to the same voltage
level.
Table 2-0002/2032E
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, VCC or GND.
11
Specifications ispLSI 2032E
Pin Configuration
I/O 21
I/O 20
I/O 19
I/O 22
GND
I/O 23
GOE 0
I/O 24
I/O 26
I/O 25
I/O 27
ispLSI 2032E 44-Pin PLCC Pinout Diagram
6 5 4 3 2 1 44 43 42 41 40
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
BSCAN
7
8
9
10
11
39
I/O 18
38
37
I/O 17
I/O 16
36
TMS/NC2
RESET/Y11
VCC
12
ispLSI 2032E
35
34
13
Top View
33
TCK/Y21
0
14
32
I/O 15
I/O 0
I/O 1
I/O 2
15
16
17
31
30
29
I/O 14
I/O 13
I/O 12
1TDI/IN
I/O 9
I/O 10
I/O 11
I/O 8
GND
1TDO/IN 1
I/O 7
I/O 6
I/O 4
I/O 5
I/O 3
18 19 20 21 22 23 24 25 26 27 28
44PLCC/2032E
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, VCC or GND.
I/O 19
I/O 21
I/O 20
I/O 22
GND
I/O 23
GOE 0
I/O 24
I/O 26
I/O 25
I/O 27
ispLSI 2032E 44-Pin TQFP Pinout Diagram
44 43 42 41 40 39 38 37 36 35 34
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
BSCAN
1TDI/IN
0
I/O 0
I/O 1
I/O 2
1
2
33
I/O 18
32
31
I/O 17
I/O 16
30
TMS/NC2
ispLSI 2032E
29
28
RESET/Y11
VCC
Top View
3
4
5
6
27
TCK/Y21
8
26
I/O 15
9
10
11
25
24
23
I/O 14
I/O 13
I/O 12
7
I/O 10
I/O 11
I/O 9
I/O 8
GND
1TDO/IN 1
I/O 7
I/O 6
I/O 4
I/O 5
I/O 3
12 13 14 15 16 17 18 19 20 21 22
44TQFP/2032E
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, VCC or GND.
12
Specifications ispLSI 2032E
Pin Configuration
I/O 21
I/O 20
I/O 19
I/O 22
GND
I/O 23
GOE 0
I/O 24
I/O 26
I/O 25
I/O 27
VCCIO
ispLSI 2032E 48-Pin TQFP Pinout Diagram
48 47 46 45 44 43 42 41 40 39 38 37
I/O 28
1
36
GND
I/O 29
2
35
I/O 18
I/O 30
3
I/O 31
4
5
34
33
I/O 17
I/O 16
32
TMS/NC2
31
30
RESET/Y11
VCC
8
29
TCK/Y21
I/O 0
I/O 1
9
10
28
I/O 15
I/O 2
GND
11
12
27
26
25
I/O 14
I/O 13
Y0
VCC
BSCAN
1TDI/IN
0
6
ispLSI 2032E
7
Top View
I/O 12
I/O 9
I/O 10
I/O 11
VCCIO
I/O 8
1
1TDO/IN
I/O 7
GND
I/O 6
I/O 4
I/O 5
I/O 3
13 14 15 16 17 18 19 20 21 22 23 24
48TQFP/2032E
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, VCC or GND.
13
Specifications ispLSI 2032E
Part Number Description
ispLSI 2032E – XXX X XXX X
Device Family
Grade
Blank = Commercial
Device Number
Package
J44 = PLCC
T44 = TQFP
T48 = TQFP
Speed
225 = 225 MHz fmax
200 = 200 MHz fmax
180 = 180 MHz fmax
135 = 135 MHz fmax
110 = 110 MHz fmax
Power
L = Low
0212/2032E
ispLSI 2032E Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
225
3.5
ispLSI 2032E-225LJ44
44-Pin PLCC
225
3.5
ispLSI 2032E-225LT44
44-Pin TQFP
225
3.5
ispLSI 2032E-225LT48
48-Pin TQFP
200
3.5
ispLSI 2032E-200LT48*
48-Pin TQFP
180
5.0
ispLSI 2032E-180LJ44
44-Pin PLCC
180
5.0
ispLSI 2032E-180LT44
44-Pin TQFP
180
5.0
ispLSI 2032E-180LT48
48-Pin TQFP
135
7.5
ispLSI 2032E-135LJ44
44-Pin PLCC
135
7.5
ispLSI 2032E-135LT44
44-Pin TQFP
135
7.5
ispLSI 2032E-135LT48
48-Pin TQFP
110
10.0
ispLSI 2032E-110LJ44
44-Pin PLCC
110
10.0
ispLSI 2032E-110LT44
44-Pin TQFP
110
10.0
ispLSI 2032E-110LT48
48-Pin TQFP
*2032E-225 recommended for new designs.
Table 2-0041/2032E
14
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