Lattice ISPLSI2096E-180LT128 In-system programmable superfastâ ¢ high density pld Datasheet

®
ispLSI 2096E
In-System Programmable
SuperFAST™ High Density PLD
Features
Functional Block Diagram
Output Routing Pool (ORP)
Output Routing Pool (ORP)
C7
C5
C4
Output Routing Pool (ORP)
C3
C2
C1
C0
A0
B7
D Q
A1
A2
GLB
Logic
Array
B6
D Q
Global Routing Pool
(GRP)
D Q
B5
D Q
A3
B4
A4
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 180 MHz Maximum Operating Frequency
— tpd = 5.0 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG™ In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O Supports MixedVoltage Systems
— PCI Compatible Outputs
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
C6
A5
A6
A7
Output Routing Pool (ORP)
B0
B1
B2
Output Routing Pool (ORP)
• SUPERFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional/JEDEC Upward Compatible with
ispLSI 2096 Devices
B3
Output Routing Pool (ORP)
0919/2096E
Description
The ispLSI 2096E is a High Density Programmable Logic
Device. The device contains 96 Registers, 96 Universal
I/O pins, six Dedicated Input pins, three Dedicated Clock
Input pins, two dedicated Global OE input pins and a
Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 2096E features 5V in-system programmability
and in-system diagnostic capabilities. The ispLSI 2096E
offers non-volatile reprogrammability of all logic, as well
as the interconnect to provide truly reconfigurable systems.
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
The basic unit of logic on the ispLSI 2096E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or
registered.Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bidirectional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate
to minimize overall output switching noise. By connecting
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2096e_04
1
January 2002
Specifications ispLSI 2096E
Functional Block Diagram
Megablock
Generic Logic
Blocks (GLBs)
TDI/IN 0
TMS/IN 1
TDO
C4
C1
C2
C3
IN 5
IN 4
I/O 67
I/O 66
I/O 65
I/O 64
I/O 71
I/O 70
I/O 69
I/O 68
I/O 75
I/O 74
I/O 73
I/O 72
I/O 79
I/O 78
I/O 77
I/O 76
I/O 83
I/O 82
I/O 81
I/O 80
I/O 87
I/O 86
I/O 85
I/O 84
C5
C6
C7
C0
I/O 63
I/O 62
I/O 61
I/O 60
Global
Routing
Pool
(GRP)
A1
A2
B6
B5
A3
Input Bus
B7
A6
A5
A7
Output Routing Pool (ORP)
RESET
B2
B1
B0
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
B4
A4
I/O 59
I/O 58
I/O 57
I/O 56
B3
Output Routing Pool (ORP)
CLK 0
CLK 1
CLK 2
I/O 12
I/O 13
I/O 14
I/O 15
Output Routing Pool (ORP)
I/O 8
I/O 9
I/O 10
I/O 11
Input Bus
Output Routing Pool (ORP)
A0
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
Input Bus
Output Routing Pool (ORP)
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 91
I/O 90
I/O 89
I/O 88
I/O 95
I/O 94
I/O 93
I/O 92
GOE 1
GOE 0
Figure 1. ispLSI 2096E Functional Block Diagram
Input Bus
Input Bus
the VCCIO pins to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compatible voltages. When connected to a 5V supply, the I/O
pins provide PCI-compatible output drive.
0917/2096E
Y0
Y1
Y2
I/O 44
I/O 45
I/O 46
I/O 47
I/O 40
I/O 41
I/O 42
I/O 43
I/O 36
I/O 37
I/O 38
I/O 39
I/O 32
I/O 33
I/O 34
I/O 35
IN 2
TCK/IN 3
I/O 28
I/O 29
I/O 30
I/O 31
I/O 24
I/O 25
I/O 26
I/O 27
I/O 20
I/O 21
I/O 22
I/O 23
I/O 16
I/O 17
I/O 18
I/O 19
BSCAN
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2096E are individually programmable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the Lattice software tools.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096E device contains three Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2096E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
2
Specifications ispLSI 2096E
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
MIN.
MAX.
UNITS
4.75
5.25
V
5V
4.75
5.25
V
3.3V
3.0
3.6
V
V
PARAMETER
SYMBOL
VCC
Supply Voltage: Logic Core, Input Buffers
VCCIO
Supply Voltage: Output Drivers
VIL
VIH
Input Low Voltage
0
0.8
Input High Voltage
2.0
Vcc+1
TA = 0°C to +70°C
V
Table 2-0005/2096E
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
C1
C2
C3
TYP
UNITS
Dedicated Input Capacitance
PARAMETER
8
pf
VCC = 5.0V, VIN = 2.0V
TEST CONDITIONS
I/O Capacitance
8
pf
VCC = 5.0V, VI/O = 2.0V
Clock Capacitance
10
pf
VCC = 5.0V, VY = 2.0V
Table 2-0006/2096E
Erase/Reprogram Specification
PARAMETER
Erase/Reprogram Cycles
MINIMUM
MAXIMUM
UNITS
10,000
–
Cycles
Table 2-0008/2096E
3
Specifications ispLSI 2096E
Switching Test Conditions
GND to 3.0V
Input Pulse Levels
Figure 2. Test Load
1.5 ns
Input Rise and Fall Time 10% to 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
+ 5V
See Figure 2
R1
Table 2-0003/2128E
3-state levels are measured 0.5V from
steady-state active level.
Device
Output
Output Load Conditions (see Figure 2)
TEST CONDITION
A
B
C
R1
R2
CL
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
Test
Point
C L*
R2
*CL includes Test Fixture and Probe Capacitance.
0213A
Table 2 - 0004A/2000
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
CONDITION
PARAMETER
MIN.
TYP.3
MAX. UNITS
VOL
VOH
IIL
Output Low Voltage
IOL = 8 mA
–
–
Output High Voltage
IOH = -4 mA
2.4
–
–
V
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
–
–
-10
µA
IIH
Input or I/O High Leakage Current
(VCCIO - 0.2)V ≤ VIN ≤ VCCIO
–
–
10
µA
VCCIO ≤ VIN ≤ 5.25V
–
–
10
µA
IIL-PU
IOS1
I/O Active Pull-Up Current
0V ≤ VIN ≤ 2.0V
-10
–
-250
µA
Output Short Circuit Current
VCCIO = 5.0V or 3.3V, VOUT = 0.5V
–
–
-240
mA
ICC3,4
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V
fTOGGLE = 1 MHz
–
130
–
mA
0.4
V
Table 2-0007/2096E
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Meaured using six 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25°C.
4. Unused inputs held at 0.0V.
5. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book or CD-ROM to estimate maximum ICC.
4
Specifications ispLSI 2096E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
1.
2.
3.
4.
TEST
2
4 #
COND.
-135
-180
DESCRIPTION1
-100
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
A
1 Data Prop Delay, 4PT Bypass, ORP Bypass
–
5.0
–
7.5
–
10.0
ns
A
2 Data Prop Delay
–
7.5
–
10.0
–
13.0
ns
A
3 Clk Freq with Internal Feedback3
180
–
135
–
100
–
MHz
125
–
100
–
77
–
MHz
1
tsu2 + tco1
–
4 Clk Freq with External Feedback (
)
–
5 Clk Frequency, Max. Toggle
200
–
143
–
100
–
MHz
–
6 GLB Reg Setup Time before Clk, 4 PT Bypass
4.0
–
5.0
–
6.5
–
ns
A
7 GLB Reg Clk to Output Delay, ORP Bypass
–
3.0
–
4.0
–
5.0
ns
–
8 GLB Reg Hold Time after Clk, 4 PT Bypass
0.0
–
0.0
–
0.0
–
ns
–
9 GLB Reg Setup Time before Clk
5.0
–
6.0
–
8.0
–
ns
–
10 GLB Reg Clk to Output Delay
–
3.5
–
4.5
–
6.0
ns
–
11 GLB Reg Hold Time after Clk
0.0
–
0.0
–
0.0
–
ns
A
12 External Reset Pin to Output Delay
–
7.0
–
10.0
–
13.5
ns
–
13 External Reset Pulse Duration
4.0
–
5.0
–
6.5
–
ns
B
14 Input to Output Enable
–
10.0
–
12.0
–
15.0
ns
C
15 Input to Output Disable
–
10.0
–
12.0
–
15.0
ns
B
16 Global OE Output Enable
–
5.0
–
7.0
–
9.0
ns
C
17 Global OE Output Disable
–
5.0
–
7.0
–
9.0
ns
–
18 External Synch Clk Pulse Duration, High
2.5
–
3.5
–
5.0
–
ns
–
19 External Synch Clk Pulse Duration, Low
2.5
–
3.5
–
5.0
–
ns
Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
5
Table 2-0030A/2096E
Specifications ispLSI 2096E
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
2
#
-180
DESCRIPTION
-100
-135
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
Inputs
tio
tdin
20 Input Buffer Delay
–
0.5
–
0.5
–
0.5
ns
21 Dedicated Input Delay
–
1.1
–
1.7
–
2.2
ns
22 GRP Delay
–
0.6
–
1.2
–
1.7
ns
23 4 Product Term Bypass Path Delay (Combinatorial)
–
1.9
–
3.7
–
5.8
ns
4.2
–
5.8
ns
6.8
ns
GRP
tgrp
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
24 4 Product Term Bypass Path Delay (Registered)
–
2.9
–
25 1 Product Term/XOR Path Delay
–
3.9
–
5.2
–
26 20 Product Term/XOR Path Delay
–
3.9
–
5.2
–
7.3
ns
27 XOR Adjacent Path Delay 3
–
3.9
–
5.2
–
8.0
ns
28 GLB Register Bypass Delay
–
0.0
–
0.5
–
0.5
ns
–
ns
29 GLB Register Setup Time before Clock
0.7
–
0.7
–
1.2
30 GLB Register Hold Time after Clock
3.3
–
4.3
–
4.0
–
ns
31 GLB Register Clock to Output Delay
–
0.3
–
0.3
–
0.3
ns
32 GLB Register Reset to Output Delay
–
0.6
–
1.1
–
1.3
ns
6.1
ns
33 GLB Product Term Reset to Register Delay
–
4.8
–
6.0
–
34 GLB Product Term Output Enable to I/O Cell Delay
–
5.9
–
6.9
–
8.6
ns
1.0
4.0
2.5
5.5
4.1
7.1
ns
36 ORP Delay
–
0.9
–
1.0
–
1.4
ns
37 ORP Bypass Delay
–
0.4
–
0.5
–
0.4
ns
38 Output Buffer Delay
–
1.6
–
1.6
–
1.6
ns
39 Output Slew Limited Delay Adder
–
1.5
–
1.5
–
1.0
ns
40 I/O Cell OE to Output Enabled
–
3.0
–
3.4
–
4.2
ns
41 I/O Cell OE to Output Disabled
–
3.0
–
3.4
–
4.2
ns
4.8
ns
35 GLB Product Term Clock Delay
ORP
torp
torpbp
Outputs
tob
tsl
toen
todis
tgoe
–
2.0
–
3.6
–
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
0.7
0.7
1.6
1.6
2.7
2.7
ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
0.9
0.9
1.8
1.8
2.7
2.7
ns
–
4.4
–
6.3
–
9.2
ns
42 Global Output Enable
Clocks
tgy0
tgy1/2
Global Reset
tgr
45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
6
Table 2-0036A/2096E
Specifications ispLSI 2096E
ispLSI 2096E Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
I/O Pin
(Input)
Comb 4 PT Bypass #23
#21
I/O Delay
GRP
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#20
#22
#24
#28
#37
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
#25 - 27
D
Q
#38,
#39
#36
RST
#45
Reset
#29 - 32
Control RE
PTs
OE
#33 - 35 CK
Y0,1,2
GOE0, 1
#40, 41
#43, 44
#42
0491/2096E
Derivations of tsu, th and tco from the Product Term Clock
tsu
=
=
=
3.6 =
Logic + Reg su - Clock (min)
(tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.5 + 0.6 + 3.9) + (0.7) - (0.5 + 0.6 + 1.0)
th
=
=
=
3.4 =
Clock (max) + Reg h - Logic
(tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.5 + 0.6 + 4.0) + (3.3) - (0.5 + 0.6 + 3.9)
tco
=
=
=
7.9 =
Clock (max) + Reg co + Output
(tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 1.6)
Table 2-0042/2096E
Note: Calculations are based upon timing specifications for the ispLSI 2096E-180L.
7
I/O Pin
(Output)
Specifications ispLSI 2096E
Power Consumption
Figure 3 shows the relationship between power and
operating speed.
Power consumption in the ispLSI 2096E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
Figure 3. Typical Device Power Consumption vs fmax
350
ispLSI 2096E
325
300
ICC (mA)
275
250
225
200
175
150
125
0
20
40
60
80
100 120 140 160 180
fmax (MHz)
Notes: Configuration of six 16-bit counters
Typical current at 5V, 25° C
ICC can be estimated for the ispLSI 2096E using the following equation:
ICC = 5.5 + (# of PTs * 0.67) + (# of nets * max freq * 0.0047)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
0127/2096E
8
Specifications ispLSI 2096E
Pin Description
NAME
PQFP & TQFP PIN NUMBERS
23,
29,
36,
42,
54,
60,
68,
74,
87,
93,
100,
106,
119,
125,
4,
10,
24,
30,
37,
43,
55,
61,
69,
75,
88,
94,
101,
107,
120,
126,
5,
11,
25,
31,
38,
44,
56,
62,
70,
76,
89,
95,
102,
108,
121,
127,
6,
12,
DESCRIPTION
26
32
39
45
57
63
71
77
90
96
103
109
122
128
7
13
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
104,
117,
123,
2,
8,
22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
105,
118,
124,
3,
9,
GOE 0, GOE 1
64,
114
IN 2, IN 4, IN 5
51,
84,
BSCAN
18
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The TMS, TDI, TDO and
TCK options become active.
TDI/IN 01
20
Input - This pin performs two functions. When BSCAN is logic low, it
functions as an input pin to load programming data into the device.
TDI/IN0 also is used as one of the two control pins for the isp state
machine. When BSCAN is high, it functions as a dedicated input pin.
TMS/IN 11
46
Input - This pin performs two functions. When BSCAN is logic low, it
functions as a pin to control the operation of the isp state machine.
When BSCAN is high, it functions as a dedicated input pin.
TDO1
50
Output - When BSCAN is logic low, it functions as an output pin to read
serial shift register data.
TCK/IN 31
78
Input - This pin performs two functions. When BSCAN is logic low, it
functions as a clock pin for the Serial Shift Register. When BSCAN is
high, it functions as a dedicated input pin.
RESET
19
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Y0, Y1, Y2
15
83,
80
GND
1,
97,
17,
112,
33,
115,
49,
116
VCC
16,
48,
82,
113
VCC
VCCIO
14,
47,
79,
111
Supply voltage for output drivers, 5V or 3.3V. All VCCIO pins must be
connected to the same voltage level
Global Output Enables input pins.
Dedicated input pins to the device.
110
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
65,
81,
Ground (GND)
Table 2-0002/2096E
1. Pins have dual function capability.
9
Specifications ispLSI 2096E
Pin Configuration
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
GND
GND
GOE 1
VCC
GND
VCCIO
IN 5
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
ispLSI 2096E 128-pin PQFP and TQFP Pinout Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ispLSI 2096E
Top View
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 4
Y1
VCC
GND
Y2
VCCIO
TCK/IN 31
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
GND
GND
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
1TMS/IN 1
VCCIO
VCC
GND
TDO
IN 2
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
GOE 0
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GND
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
VCCIO
Y0
VCC
GND
BSCAN
RESET
1TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
1. Pins have dual function capability.
0124/2096E
10
Specifications ispLSI 2096E
Part Number Description
ispLSI 2096E – XXX X XXXX X
Device Family
Grade
Blank = Commercial
Device Number
Package
T128 = TQFP
Q128 = PQFP
Speed
180 = 180 MHz fmax
135 = 135 MHz fmax
100 = 100 MHz fmax
Power
L = Low
0212/2096E
ispLSI 2096E Ordering Information
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
180
5.0
ispLSI 2096E-180LT128
128-Pin TQFP
180
5.0
ispLSI 2096E-180LQ128
128-Pin PQFP
135
7.5
ispLSI 2096E-135LT128
128-Pin TQFP
135
7.5
ispLSI 2096E-135LQ128
128-Pin PQFP
100
10.0
ispLSI 2096E-100LT128
128-Pin TQFP
100
10.0
ispLSI 2096E-100LQ128
128-Pin PQFP
Table 2-0041/2096E
11
Similar pages