IK Semicon IW4043B Quad 3-state r/s latches high-voltage silicon-gate cmo Datasheet

TECHNICAL DATA
IW4043B
Quad 3-State R/S Latches
High-Voltage Silicon-Gate CMOS
The IW4043B types are quad cross-coupled 3-state CMOS NOR
latces. Each latch has a separate Q output and individual SET and RESET
inputs. The Q outputs are controlled by a common ENABLE input. A
logic “1” or high on the ENABLE input connects the latch states to the Q
outputs. A logic “0” or low on the ENABLE input disconnects the latch
states from the Q outputs, resulting in an open circuit condition on the Q
outputs. The open circuit feature allows common busing of the outputs.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 μA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4043BN Plastic
IW4043BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
PIN 13 = NO CONNECTION
PIN 16=VCC
PIN 8= GND
Outputs
S
R
OE
Q
X
X
L
High
Impedance
L
L
H
No change
L
H
H
L
H
L
H
H
H
H
H
H
X = don’t care
Rev. 00
IW4043B
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +20
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
VOUT
IIN
DC Input Current, per Pin
±10
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
PD
Power Dissipation per Output Transistor
100
mW
-65 to +150
°C
260
°C
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
TA
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min
Max
Unit
3.0
18
V
0
VCC
V
-55
+125
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
Rev. 00
IW4043B
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Guaranteed Limit
V
≥-55°C
25°C
≤125
°C
Unit
VOUT= 0.5 V or VCC - 0.5V
VOUT= 1.0 V or VCC - 1.0 V
VOUT= 1.5 V or VCC - 1.5V
5.0
10
15
3.5
7
11
3.5
7
11
3.5
7
11
V
Maximum Low Level Input Voltage
VOUT= 0.5 V or VCC - 0.5V
VOUT= 1.0 V or VCC - 1.0 V
VOUT= 1.5 V or VCC - 1.5V
5.0
10
15
1.5
3
4
1.5
3
4
1.5
3
4
V
VOH
Minimum High-Level
Output Voltage
VIN=GND or VCC
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
V
VOL
Maximum Low-Level
Output Voltage
VIN=GND or VCC
5.0
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
IIN
Maximum Input
Leakage Current
VIN= GND or VCC
18
±0.1
±0.1
±1.0
μA
IOZ
Maximum Three State Output in High-Impedance
Leakage Current
State
VIN= GND or VCC
VOUT= GND or VCC
18
±0.4
±0.4
±12.0
μA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN= GND or VCC
5.0
10
15
20
1
2
4
20
1
2
4
20
30
60
120
600
μA
IOL
Minimum Output
Low (Sink) Current
VIN= GND or VCC
UOL=0.4 V
UOL=0.5 V
UOL=1.5 V
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
Minimum Output
VIN= GND or VCC
High (Source) Current UOH=2.5 V
UOH=4.6 V
UOH=9.5 V
UOH=13.5 V
5.0
5.0
10
15
-2
-0.64
-1.6
-4.2
-1.6
-0.51
-1.3
-3.4
-1.15
-0.36
-0.9
-2.4
Symbol
Parameter
VIH
Minimum High-Level
Input Voltage
VIL
IOH
Test Conditions
mA
mA
Rev. 00
IW4043B
AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200kΩ, Input tr=tf=20 ns)
VCC
Symbol
Parameter
Guaranteed Limit
V
≥-55°C
25°C
≤125°C
Unit
tPHL, tPLH
Maximum Propagation Delay, SET or RESET
to Q (Figure 1)
5.0
10
15
300
140
100
300
140
100
600
280
200
ns
tPHZ, tPZH
Maximum Propagation Delay, Output Enable
to Q (Figures 2,4)
5.0
10
15
230
110
80
230
110
80
460
220
160
ns
tPLZ, tPZL
Maximum Propagation Delay, Output Enable
to Q (Figures 2,4)
5.0
10
15
180
100
70
180
100
70
360
200
140
ns
tTHL, tTLH
Maximum Output Transition Time, Any Output
(Figure 1)
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
CIN
Maximum Input Capacitance
-
7.5
pF
TIMING REQUIREMENTS (CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
≥-55°C
25°C
≤125°C
Unit
tw
Minimum Pulse Width, SET or RESET (Figure
3)
5.0
10
15
160
80
40
160
80
40
320
160
80
ns
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Rev. 00
IW4043B
TEST
IN
IN
A
tPHZ
VCC
GND
GND
tPLZ
GND
VCC
VCC
tPZH
VCC
GND
GND
tPZL
GND
VCC
VCC
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
( 1/4 of the Device)
Rev. 00
IW4043B
N SUFFIX PLASTIC
(MS - 001BB)
A
9
16
Dimensions, mm
B
1
8
F
C
-T- SEATING
PLANE
N
K
M
J
H
D
MIN
MAX
A
18.67
19.69
B
6.10
7.11
C
L
G
Symbol
0.25 (0.010) M T
NOTES:
1. imensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
5.33
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.20
0.36
N
0.38
D SUFFIX SOIC
(MS - 012AC)
A
16
9
H
Dimensions, mm
B
1
G
P
8
R x 45
C
-TK
D
SEATING
PLANE
J
F
0.25 (0.010) M T C M
NOTES:
1.Dimensions A and B do not include mold flash or protrusion.
2.Maximum mold flash or protrusion 0.15 mm (0.006) per side for A, for
B - 0.25 mm (0.010) per side.
M
Symbol.
MIN
MAX
A
9.80
10.0
B
3.80
4.00
C
1.35
1.75
D
0.33
0.51
F
0.40
1.27
G
1.27
H
5.72
J
0°
8°
K
0.10
0.25
M
0.19
0.25
P
5.80
6.20
R
0.25
0.50
Rev. 00
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