TI1 JM38510/65553BSA Octal bus transceivers with 3-state output Datasheet

SN54HCT245, SN74HCT245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS020E – MARCH 1984 – REVISED AUGUST 2003
D
D
D
D
D
D
D
Operating Voltage Range of 4.5 V to 5.5 V
High-Current 3-State Outputs Drive Bus
Lines Directly or Up To 15 LSTTL Loads
Low Power Consumption, 80-µA Max ICC
Typical tpd = 14 ns
±6-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
SN54HCT245 . . . J OR W PACKAGE
SN74HCT245 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
description/ordering information
These octal bus transceivers are designed for
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
SN54HCT245 . . . FK PACKAGE
(TOP VIEW)
A2
A1
DIR
VCC
OE
The ’HCT245 devices allow data transmission
from the A bus to the B bus or from the B bus to the
A bus, depending upon the logic level at the
direction-control (DIR) input. The output-enable
(OE) input can be used to disable the device so
that the buses are effectively isolated.
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
B1
B2
B3
B4
B5
A8
GND
B8
B7
B6
A3
A4
A5
A6
A7
ORDERING INFORMATION
PACKAGE†
TA
PDIP – N
SN74HCT245N
Tube of 25
SN74HCT245DW
Reel of 2000
SN74HCT245DWR
SOP – NS
Reel of 2000
SN74HCT245NSR
HCT245
SSOP – DB
Reel of 2000
SN74HCT245DBR
HT245
Tube of 70
SN74HCT245PW
Reel of 2000
SN74HCT245PWR
TSSOP – PW
–55°C
125°C
–55 C to 125
C
TOP-SIDE
MARKING
Tube of 20
SOIC – DW
–40 C to 85
–40°C
85°C
C
ORDERABLE
PART NUMBER
SN74HCT245N
HCT245
HT245
Reel of 250
SN74HCT245PWT
CDIP – J
Tube of 20
SNJ54HCT245J
SNJ54HCT245J
CFP – W
Tube of 85
SNJ54HCT245W
SNJ54HCT245W
LCCC – FK
Tube of 55
SNJ54HCT245FK
SNJ54HCT245FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54HCT245, SN74HCT245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS020E – MARCH 1984 – REVISED AUGUST 2003
FUNCTION TABLE
INPUTS
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
logic diagram (positive logic)
DIR
1
19
A1
OE
2
18
B1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54HCT245, SN74HCT245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS020E – MARCH 1984 – REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HCT245
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
∆t/∆v
Output voltage
0
High-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
SN74HCT245
MIN
2
2
Input transition rise/fall time
V
V
0.8
VCC
VCC
UNIT
0
0
500
0.8
V
VCC
VCC
V
500
ns
V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VOH
VI = VIH or VIL
IOH = –20 µA
IOH = –6 mA
4.5 V
VOL
VI = VIH or VIL
IOL = 20 µA
IOL = 6 mA
4.5 V
II
IOZ
DIR or OE
A or B
ICC
∆ICC†
Ci‡
MIN
TA = 25°C
TYP
MAX
SN54HCT245
MIN
MAX
SN74HCT245
MIN
4.4
4.499
4.4
4.4
3.98
4.3
3.7
3.84
MAX
UNIT
V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
0.33
±1000
±1000
nA
V
VI = VCC or 0
VO = VCC or 0
5.5 V
±0.1
±100
5.5 V
±0.01
±0.5
±10
±5
µA
VI = VCC or 0,
IO = 0
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
5.5 V
8
160
80
µA
1.4
2.4
3
2.9
mA
3
10
10
10
pF
5.5 V
4.5 V
to 5.5 V
DIR or OE
† This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
‡ Parameter Ci does not apply to transceiver I/O ports.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
ten
OE
A or B
tdis
OE
A or B
tt
A or B
VCC
MIN
TA = 25°C
TYP
MAX
SN54HCT245
MIN
MAX
SN74HCT245
MIN
MAX
4.5 V
16
22
33
28
5.5 V
14
20
30
25
4.5 V
25
46
69
58
5.5 V
22
41
62
52
4.5 V
26
40
60
50
5.5 V
23
36
54
45
4.5 V
9
12
18
15
5.5 V
8
11
16
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
3
SN54HCT245, SN74HCT245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS020E – MARCH 1984 – REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
B or A
ten
OE
A or B
tt
A or B
VCC
MIN
TA = 25°C
TYP
MAX
SN54HCT245
MIN
MAX
SN74HCT245
MIN
MAX
4.5 V
20
30
45
38
5.5 V
18
27
41
34
4.5 V
36
59
89
74
5.5 V
30
53
80
67
4.5 V
17
42
63
53
5.5 V
14
38
57
48
UNIT
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
4
TEST CONDITIONS
Power dissipation capacitance per transceiver
POST OFFICE BOX 655303
No load
• DALLAS, TEXAS 75265
TYP
40
UNIT
pF
SN54HCT245, SN74HCT245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCLS020E – MARCH 1984 – REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
CL
(see Note A)
PARAMETER
S1
Test
Point
tPZH
ten
RL
S2
1 kΩ
tPZL
tPHZ
tdis
––
LOAD CIRCUIT
2.7 V
2.7 V
S1
S2
50 pF
or
150 pF
Open
Closed
Closed
Open
1 kΩ
tPLZ
tpd or tt
Input 1.3 V
0.3 V
CL
RL
50 pF
50 pF
or
150 pF
Open
Closed
Closed
Open
Open
Open
3V
1.3 V
0.3 V 0 V
tr
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
3V
Input
1.3 V
1.3 V
0V
tPLH
In-Phase
Output
1.3 V
10%
tPHL
90%
90%
tr
tPHL
Out-ofPhase
Output
90%
VOH
1.3 V
10% V
OL
tf
tPLH
1.3 V
10%
1.3 V
10%
tf
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
Output
Control
(Low-Level
Enabling)
3V
1.3 V
1.3 V
0V
tPZL
Output
Waveform 1
(See Note B)
tPLZ
≈VCC
1.3 V
10%
tPZH
Output
Waveform 2
(See Note B)
VOL
tPHZ
1.3 V
90%
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-8550601VRA
ACTIVE
CDIP
J
20
20
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8550601VR
A
SNV54HCT245J
5962-8550601VSA
ACTIVE
CFP
W
20
25
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8550601VS
A
SNV54HCT245W
85506012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
85506012A
SNJ54HCT
245FK
8550601RA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8550601RA
SNJ54HCT245J
JM38510/65553BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65553BRA
JM38510/65553BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65553BSA
M38510/65553BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65553BRA
M38510/65553BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65553BSA
SN54HCT245J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54HCT245J
SN74HCT245DBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
-40 to 85
SN74HCT245DBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT245
SN74HCT245DBRG4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT245
SN74HCT245DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT245
SN74HCT245DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT245
SN74HCT245DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT245
SN74HCT245DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT245
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
17-Dec-2015
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74HCT245DWRE4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT245
SN74HCT245DWRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT245
SN74HCT245N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT245N
SN74HCT245N3
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
-40 to 85
SN74HCT245NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT245N
SN74HCT245NSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT245
SN74HCT245NSRG4
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT245
SN74HCT245PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT245
SN74HCT245PWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT245
SN74HCT245PWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
-40 to 85
SN74HCT245PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
HT245
SN74HCT245PWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT245
SN74HCT245PWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT245
SN74HCT245PWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT245
SNJ54HCT245FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
85506012A
SNJ54HCT
245FK
SNJ54HCT245J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8550601RA
SNJ54HCT245J
SNJ54HCT245W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SNJ54HCT245W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HCT245, SN54HCT245-SP, SN74HCT245 :
• Catalog: SN74HCT245, SN54HCT245
• Military: SN54HCT245
• Space: SN54HCT245-SP
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Dec-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74HCT245DBR
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
SN74HCT245DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74HCT245NSR
SO
NS
20
2000
330.0
24.4
9.0
13.0
2.4
4.0
24.0
Q1
SN74HCT245PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74HCT245PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74HCT245PWT
TSSOP
PW
20
250
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Dec-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HCT245DBR
SN74HCT245DWR
SSOP
DB
20
2000
367.0
367.0
38.0
SOIC
DW
20
2000
367.0
367.0
45.0
SN74HCT245NSR
SO
NS
20
2000
367.0
367.0
45.0
SN74HCT245PWR
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74HCT245PWR
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74HCT245PWT
TSSOP
PW
20
250
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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