Samsung K3P7VU1000B-YC 64m-bit (8mx8 /4mx16) cmos mask rom Datasheet

K3P7V(U)1000B-YC
CMOS MASK ROM
64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
• Switchable organization
8,388,608 x 8(byte mode)
4,194,304 x 16(word mode)
• Fast access time
Random Access Time/Page Access Time
3.3V Operation : 100/30ns(Max.)@CL=50pF,
120/40ns(Max.)@C L=100pF
3.0V Operation : 120/40ns(Max.)@CL=100pF
8 Words / 16 Bytes page access
• Supply voltage : single +3.0V/ single +3.3V
• Current consumption
Operating : 60mA(Max.)
Standby : 50µA(Max.)
• Fully static operation
• All inputs and outputs TTL compatible
• Three state outputs
• Package
K3P7V(U)1000B-YC : 48-TSOP1-1218
The K3P7V(U)1000B-YC is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 8,388,608 x 8 bit(byte mode) or as
4,194,304 x 16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device includes page read mode function, page read mode
allows 8 words (or 16 bytes) of data to read fast in the same
page, CE and A3 ~ A21 should not be changed.
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3P7V(U)1000B-YC is packaged in a 48-TSOP1.
FUNCTIONAL BLOCK DIAGRAM
Pin Name
A21
X
.
.
.
.
.
.
.
.
A0 - A2
Page Address Inputs
BUFFERS
MATRIX
A3 - A21
Address Inputs
AND
(4,194,304x16/
Q0 - Q14
Data Outputs
DECODER
8,388,608x8)
Q15 /A-1
Output 15(Word mode)/
LSB Address(Byte mode)
Y
MEMORY CELL
BHE
SENSE AMP.
BUFFERS
AND
A3
DECODER
A0~A2
A-1
DATA OUT
BUFFERS
. . .
CE
OE
BHE
Pin Function
CONTROL
LOGIC
Q0/Q 8
Q7/Q15
Word/Byte selection
CE
Chip Enable
OE
Output Enable
VCC
Power
Vss
Ground
N.C
No Connection
K3P7V(U)1000B-YC
CMOS MASK ROM
PIN CONFIGURATION
BHE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
A21
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TSOP1
VSS
VSS
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
VCC
N.C
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
VSS
VSS
K3P7V(U)1000B-YC
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to VSS
Symbol
Rating
Unit
VIN
-0.3 to +4.5
V
Temperature Under Bias
TBIAS
-10 to +85
°C
Storage Temperature
TSTG
-55 to +150
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Symbol
Min
Typ
Max
Unit
Supply Voltage
Item
VCC
2.7/3.0
3.0/3.3
3.3/3.6
V
Supply Voltage
VSS
0
0
0
V
DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Operating Current
ICC
Cycle=5MHZ, all outputs open, CE=OE=VIL,
VIN=0.45V to 2.4V (AC Test Condition)
Standby Current(TTL)
ISB1
CE=VIH, all outputs open
Standby Current(CMOS)
ISB2
CE=VCC, all outputs open
Input Leakage Current
ILI
VIN=0 to VCC
VOUT=0 to VCC
VCC=3.3V±0.3V
Min
Max
Unit
-
60
mA
VCC=3.0V±0.3V
-
50
mA
500
µA
50
µA
10
µA
Output Leakage Current
ILO
-
10
µA
Input High Voltage, All Inputs
VIH
2.0
VCC+0.3
V
Input Low Voltage, All Inputs
VIL
-0.3
0.6
V
Output High Voltage Level
VOH
IOH=-400µA
2.4
-
V
Output Low Voltage Level
VOL
IOL=2.1mA
-
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH ) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
K3P7V(U)1000B-YC
CMOS MASK ROM
MODE SELECTION
CE
OE
BHE
Q15/A-1
Mode
Data
Power
H
X
X
X
Standby
High-Z
Standby
L
H
L
L
X
X
Operating
High-Z
Active
H
Output
Operating
Q0~Q15 : Dout
Active
L
Input
Operating
Q0~Q7 : Dout
Q8~Q14 : Hi-Z
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
Min
Max
Unit
COUT
VOUT=0V
-
12
pF
CIN
VIN=0V
-
12
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
AC CHARACTERISTICS (TA=0°C to +70°C,VCC=3.3V/3.0V±0.3V, unless otherwise noted.)
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
10ns
Input and Output timing Levels
1.5V
Output Loads
1 TTL Gate and CL=50pF or 100pF
READ CYCLE
Item
Symbol
K3P7V1000B-YC10
(CL=50pF)
Min
Max
Min
Max
Min
Unit
Max
tRC
Chip Enable Access Time
tACE
100
120
120
ns
Address Access Time
tAA
100
120
120
ns
Page Address Access Time
tPA
30
40
40
ns
Output Enable Access Time
tOE
30
40
40
ns
Output or Chip Disable to
Output High-Z
tDF
20
20
20
ns
Output Hold from Address Change
tOH
0
120
K3P7U1000B-YC12
(CL=100pF)
Read Cycle Time
NOTE : Page Address is determined as below.
Word mode (BHE=VIH ) : A0 , A1, A2
Byte mode (BHE=VIL) : A-1, A0, A1, A2
100
K3P7V1000B-YC12
(CL=100pF)
0
120
0
ns
ns
K3P7V(U)1000B-YC
CMOS MASK ROM
TIMING DIAGRAM
READ
ADD
A0~A21
A-1(*1)
ADD1
ADD2
tRC
tDF(*3)
tACE
CE
tOE
tAA
OE
tOH
DOUT
D0~D7
D8~D15(*2)
VALID DATA
VALID DATA
PAGE READ
≈
CE
tDF(*3)
≈
≈
OE
≈
≈
ADD
A3~A21
ADD
A0,A1,A2
A -1(*1)
1 st
tAA
≈
tPA
VALID DATA
VALID DATA
VALID DATA
VALID DATA
≈
DOUT
D0~D7
D8~D15(*2)
3 rd
≈
2 nd
NOTES :
*1.Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)
*2. Word Mode only.(BHE = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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