SAMSUNG K4D553238F-JC36

256M GDDR SDRAM
K4D553238F-JC
256Mbit GDDR SDRAM
2M x 32Bit x 4 Banks
Graphic Double Data Rate
Synchronous DRAM
with Bi-directional Data Strobe and DLL
(144-Ball FBGA)
Revision 1.0
March 2004
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
Revision History
Revision 1.0 (March 8, 2004)
• DC Specification finalized
Revision 0.1 (March 2 , 2004) - Target Spec
Revision 0.0 (October 28, 2003) - Target Spec
• Defined Target Specification
- 2 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 2.5V + 5% power supply for device operation
• 4 DQS’s ( 1DQS / Byte )
• 2.5V + 5% power supply for I/O interface
• Data I/O transactions on both edges of Data strobe
• SSTL_2 compatible inputs/outputs
• DLL aligns DQ and DQS transitions with Clock transition
• 4 banks operation
• Edge aligned data & data strobe output
• MRS cycle with address key programs
• Center aligned data & data strobe input
-. Read latency 3, 4 (clock)
• DM for write masking only
-. Burst length (2, 4 and 8)
• Auto & Self refresh
-. Burst type (sequential & interleave)
• 32ms refresh period (4K cycle)
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• 144-Ball FBGA
• Maximum clock frequency up to 350MHz
• Differential clock input
• Maximum data rate up to 700Mbps/pin
• No Wrtie-Interrupted by Read Function
ORDERING INFORMATION
Part NO.
Max Freq.
Max Data Rate
K4D553238F-JC2A
350MHz
700Mbps/pin
K4D553238F-JC33
300MHz
600Mbps/pin
K4D553238F-JC36
275MHz
550Mbps/pin
K4D553238F-JC40
250MHz
500Mbps/pin
K4D553238F-JC50
200MHz
400Mbps/pin
Interface
Package
SSTL_2
144-Ball FBGA
1. K4D553238F-EC is the Lead Free package part number
2. For the K4D553238F-JC2A, VDD & VDDQ =2.8V + 0.1V
GENERAL DESCRIPTION
FOR 2M x 32Bit x 4 Bank GDDR SDRAM
The K4D553238F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by
32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 2.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
PIN CONFIGURATION (Top View)
2
3
4
5
6
7
8
9
10
11
12
13
B
DQS0
DM0
VSSQ
DQ3
DQ2
DQ0
DQ31
DQ29
DQ28
VSSQ
DM3
DQS3
C
DQ4
VDDQ
NC
VDDQ
DQ1
VDDQ
VDDQ
DQ30
VDDQ
NC
VDDQ
DQ27
D
DQ6
DQ5
VSSQ
VSSQ
VSSQ
VDD
VDD
VSSQ
VSSQ
VSSQ
DQ26
DQ25
E
DQ7
VDDQ
VDD
VSS
VSSQ
VSS
VSS
VSSQ
VSS
VDD
VDDQ
DQ24
F
DQ17
DQ16
VDDQ
VSSQ
VSS
VSS
Thermal Thermal
VSS
VSS
Thermal Thermal
VSSQ
VDDQ
DQ15
DQ14
G
DQ19
DQ18
VDDQ
VSSQ
VSS
VSS
Thermal Thermal
VSS
VSS
Thermal Thermal
VSSQ
VDDQ
DQ13
DQ12
H
DQS2
DM2
NC
VSSQ
VSS
VSS
Thermal Thermal
VSS
VSS
Thermal Thermal
VSSQ
NC
DM1
DQS1
J
DQ21
DQ20
VDDQ
VSSQ
VSS
VSS
Thermal Thermal
VSS
VSS
Thermal Thermal
VSSQ
VDDQ
DQ11
DQ10
K
DQ22
DQ23
VDDQ
VSSQ
VSS
VSS
VSS
VSS
VSSQ
VDDQ
DQ9
DQ8
L
CAS
WE
VDD
VSS
A10
VDD
VDD
RFU1
VSS
VDD
NC
NC
M
RAS
NC
NC
BA1
A2
A11
A9
A5
RFU2
CK
CK
MCL
N
CS
NC
BA0
A0
A1
A3
A4
A6
A7
A8/AP
CKE
VREF
NOTE:
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. VSS Thermal balls are optional
PIN DESCRIPTION
CK,CK
Differential Clock Input
BA0, BA1
Bank Select Address
CKE
Clock Enable
A0 ~A11
Address Input
CS
Chip Select
DQ0 ~ DQ31
Data Input/Output
RAS
Row Address Strobe
VDD
Power
CAS
Column Address Strobe
VSS
Ground
WE
Write Enable
VDDQ
Power for DQ’s
DQS
Data Strobe
VSSQ
Ground for DQ’s
DM
Data Mask
NC
No Connection
RFU
Reserved for Future Use
MCL
Must Connect Low
- 4 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ’s and DM’s that are sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS
Input
CS enables the command decoder when low and disabled the command decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE
Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Input/Output
Data input and output are synchronized with both edge of DQS.
DQS0 for DQ0 ~ DQ7, DQS1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ23,
DQS3 for DQ24 ~ DQ31.
DM0 ~ DM3
Input
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for
DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.
DQ0 ~ DQ31
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA0, BA1
Input
Selects which bank is to be active.
A0 ~ A11
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7,CA9
Column address CA8 is used for auto precharge.
VDD/VSS
Power Supply
Power and ground for the input buffers and core logic.
VDDQ/VSSQ
Power Supply
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VREF
Power Supply
Reference voltage for inputs, used for SSTL interface.
No connection/
Reserved for future use
This pin is recommended to be left "No connection" on the device
Must Connect Low
Must connect low
DQS0 ~ DQS3
NC/RFU
MCL
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
- 5 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
BLOCK DIAGRAM (2Mbit x 32I/O x 4 Bank)
32
Intput Buffer
I/O Control
CK, CK
Data Input Register
Serial to parallel
Bank Select
LWE
LDMi
64
2Mx32
32
Output Buffer
2Mx32
64
2-bit prefetch
Sense AMP
Row Decoder
Refresh Counter
Row Buffer
ADDR
Address Register
CK,CK
2Mx32
x32
DQi
2Mx32
Column Decoder
Col. Buffer
LCBR
LRAS
Latency & Burst Length
LRAS LCBR
Strobe
Gen.
Programming Register
LCKE
Data Strobe
(DQS0~DQS3)
DLL
LWE
LCAS
LWCBR
CK,CK
LDMi
Timing Register
CK,CK
CKE
CS
RAS
CAS
WE
- 6 -
DMi
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
FUNCTIONAL DESCRIPTION
• Power-Up Sequence
GDDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*1,2 7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
Power up & Initialization Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
~
precharge
ALL Banks
EMRS
MRS
DLL Reset
1st Auto
Refresh
precharge
ALL Banks
~
tRP
tRFC
tRFC
200 Clock min.
Inputs must be
stable for 200us
2nd Auto
Refresh
~ ~
~
2 Clock min.
2 Clock min.
Mode
Register Set
Any
Command
~
~
2 Clock min.
~
~ ~
tRP
Command
~
~
CK,CK
* When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
- 7 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of GDDR SDRAM. It programs CAS
latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make GDDR SDRAM
useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register
must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS
and WE(The GDDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The
state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode
register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register
contents can be changed using the same command and clock cycle requirements during operation as long as all banks are
in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,
addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is
used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
BA1
BA0
RFU
0
A11
A10
A9
RFU
DLL
A8
A8
A7
DLL
TM
A6
A5
A3
CAS Latency
A2
BT
A1
A0
Burst Length
Address Bus
Mode Register
Burst Type
Test Mode
DLL Reset
A4
A7
mode
A3
Type
0
No
0
Normal
0
Sequential
1
Yes
1
Test
1
Interleave
0
Burst Length
CAS Latency
BA0
A1
A0
Sequential
Interleave
Reserved
0
0
0
Reserve
Reserve
Reserved
0
0
1
2
2
1
0
4
4
A6
A5
A4
Latency
0
MRS
0
0
0
1
EMRS
0
0
1
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
Burst Type
A2
An ~ A0
0
1
0
Reserved
0
0
1
1
3
0
1
1
8
8
1
0
0
4
1
0
0
Reserve
Reserve
1
0
1
Reserved
1
0
1
Reserve
Reserve
1
1
0
Reserved
1
1
0
Reserve
Reserve
Reserved
1
1
1
Reserve
Reserve
1
1
1
MRS Cycle
0
1
2
3
4
5
6
7
8
CK, CK
Command
NOP
Precharge
All Banks
NOP
NOP
MRS
NOP
Any
Command
NOP
NOP
tMRD=2 tCK
tRP
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum tRP is required to issue MRS command.
- 8 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
EXTENDED MODE REGISTER SET(EMRS)
The extended mode register stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore the extened mode register
must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11
and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1
and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific
codes.
BA1
BA0
RFU
1
BA0
A11
A10
A9
A8
A7
RFU
A6
A5
A4
D.I.C
An ~ A0
A6
A1
0
MRS
0
1
1
EMRS
1
A3
A2
RFU
Output Driver Impedence Control
1
A1
A0
D.I.C
DLL
A0
Address Bus
Extended
Mode Register
DLL Enable
Weak
0
Enable
Matched
1
Disable
*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.
Figure 7. Extended Mode Register set
- 9 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to Vss
VDD
-1.0 ~ 3.6
V
Voltage on VDD supply relative to Vss
VDDQ
-0.5 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
2.0
W
Short circuit current
IOS
50
mA
Voltage on any pin relative to Vss
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Device Supply voltage
VDD
2.375
2.5
2.625
V
1, 7
Output Supply voltage
VDDQ
2.375
2.5
2.625
V
1, 7
Reference voltage
VREF
0.49*VDDQ
-
0.51*VDDQ
V
2
Termination voltage
Vtt
VREF-0.04
VREF
VREF+0.04
V
3
Input logic high voltage
VIH(DC)
VREF+0.15
-
VDDQ+0.30
V
4
Input logic low voltage
VIL(DC)
-0.30
-
VREF-0.15
V
5
Output logic high voltage
VOH
Vtt+0.76
-
-
V
IOH=-15.2mA
Output logic low voltage
VOL
-
-
Vtt-0.76
V
IOL=+15.2mA
Input leakage current
IIL
-5
-
5
uA
6
Output leakage current
IOL
-5
-
5
uA
6
Note : 1. Under all conditions VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to
peak noise on the VREF may not exceed + 2% of the DC value.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.
7. For the K4D553238F-JC2A, VDD & VDDQ = 2.8V + 0.1V
- 10 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)
Version
Parameter
Symbol
Test Condition
Unit Note
-2A
-33
-36
-40
-50
340
320
300
280
Operating Current
(One Bank Active)
ICC1
Burst Lenth=2 tRC ≥ tRC(min)
IOL=0mA, tCC= tCC(min)
400
Precharge Standby Current
in Power-down mode
ICC2P
CKE ≤ VIL(max), tCC= tCC(min)
120
Precharge Standby Current
in Non Power-down mode
ICC2N
Active Standby Current
power-down mode
ICC3P
Active Standby Current in
in Non Power-down mode
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
CKE ≤ VIL(max), tCC= tCC(min)
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
mA
90
mA
190
150
140
130
120
mA
170
130
120
110
100
mA
250
220
210
200
190
mA
Operating Current
( Burst Mode)
ICC4
IOL=0mA ,tCC= tCC(min),
Page Burst, All Banks activated.
650
550
520
460
430
mA
Refresh Current
ICC5
tRC ≥ tRFC(min)
470
415
395
365
335
mA
Self Refresh Current
ICC6
CKE ≤ 0.2V
Operating Current
(4Bank interleaving)
ICC7
Burst Length=4 tRC ≥ tRC(min)
IOL=0mA, tCC= tCC(min)
8
840
6
680
630
1
2
mA
590
550
mA
Note : 1. Measured with outputs open.
2. Refresh period is 32ms.
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.5V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65°C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Input High (Logic 1) Voltage; DQ
VIH
VREF+0.35
-
-
V
Input Low (Logic 0) Voltage; DQ
VIL
-
-
VREF-0.35
V
Clock Input Differential Voltage; CK and CK
VID
0.7
-
VDDQ+0.6
V
1
Clock Input Crossing Point Voltage; CK and CK
VIX
0.5*VDDQ-0.2
-
0.5*VDDQ+0.2
V
2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
- 11 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
AC OPERATING TEST CONDITIONS (VDD=2.5V±5%, TA= 0 to 65°C)
Parameter
Value
Unit
Input reference voltage for CK(for single ended)
0.50*VDDQ
V
1.5
V
CK and CK signal maximum peak swing
CK signal minimum slew rate
Input Levels(VIH/VIL)
1.0
V/ns
VREF+0.35/VREF-0.35
V
VREF
V
Vtt
V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Note
See Fig.1
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
(Fig. 1) Output Load Circuit
CAPACITANCE (VDD=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance( CK, CK )
CIN1
5.0
10.0
pF
Input capacitance(A0~A11, BA0~BA1)
CIN2
5.0
9.0
pF
Input capacitance
( CKE, CS, RAS,CAS, WE )
CIN3
5.0
9.0
pF
Data & DQS input/output capacitance(DQ0~DQ31)
COUT
4.0
8.0
pF
Input capacitance(DM0 ~ DM3)
CIN4
4.0
8.0
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Symbol
Value
Unit
Decoupling Capacitance between VDD and VSS
Parameter
CDC1
0.1 + 0.01
uF
Decoupling Capacitance between VDDQ and VSSQ
CDC2
0.1 + 0.01
uF
Note : 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
- 12 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
AC CHARACTERISTICS
Symbol
Parameter
CL=3
CL=4
CK cycle time
tCK
DQ and DM hold time to DQS
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
tIH
tDS
tDH
Clock half period
tHP
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
Data output hold time from DQS tQH
-2A
-33
Min
2.86
0.45
Max
0.55
Min
3.3
0.45
0.45
0.55
0.45
-0.6
0.6
-0.6
-36
-40
Max
0.55
Min
3.6
0.45
0.55
0.45
-0.6
0.6
0.6
-0.6
-
0.35
0.9
1.1
10
Max
0.55
Min
4.0
0.45
0.55
0.45
-0.6
0.6
0.6
-0.6
-
0.35
0.9
1.1
10
-50
Unit
Max
0.55
Min
5.0
0.45
0.55
ns
ns
tCK
0.55
0.45
0.55
tCK
-0.6
0.6
-0.7
0.7
ns
0.6
-0.6
0.6
-0.7
0.7
ns
-
0.40
-
0.40
-
0.45
ns
0.9
1.1
0.9
1.1
0.9
1.1
tCK
10
Max
10
10
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
0.85
1.15
0.85
1.15
0.85
1.15
0.85
1.15
0.8
1.2
tCK
Note
1
0
-
0
-
0
-
0
-
0
-
ns
0.35
-
0.35
-
0.35
-
0.35
-
0.3
-
tCK
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
0.9
-
0.9
-
0.9
-
0.9
-
1.0
-
ns
0.9
-
0.9
-
0.9
-
0.9
-
1.0
-
ns
0.35
-
0.35
-
0.40
-
0.40
-
0.45
-
ns
0.35
tCLmin
or
tCHmin
tHP
-0.35
-
0.35
tCLmin
or
tCHmin
tHP
-0.35
-
0.40
tCLmin
or
tCHmin
tHP
-0.4
-
0.40
tCLmin
or
tCHmin
tHP
-0.4
-
0.45
tCLmin
or
tCHmin
tHP0.45
-
ns
-
ns
1
-
ns
1
-
-
-
-
Simplified Timing @ BL=2, CL=4
tCH
tCL
tCK
0
1
2
3
5
4
6
8
7
CK, CK
tIS
CS
tIH
tDQSCK
tDQSS
DQS
tRPST
tRPRE
tWPRES
tDQSQ
tDQSH
tDQSL
tWPREH
tDS tDH
tAC
DQ
Qa1
Db0
Qa2
Db1
DM
WRITEB
COMMAND READA
- 13 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
Note 1 :
- The JEDEC GDDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL4, BL2)
tHP
0
1
3
2
4
5
CK, CK
CS
DQS
tDQSQ(max)
tQH
tDQSQ(max)
Qa0
DQ
COMMAND
Qa1
READA
- 14 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
AC CHARACTERISTICS (I)
Parameter
-2A
Symbol
-33
-36
-40
-50
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tRC
tRFC
tRAS
tRCDRD
tRCDW
16
-
16
-
16
-
13
-
12
-
17
-
17
-
17
-
15
-
14
-
tCK
11
100K
11
100K
11
100K
9
100K
8
100K
tCK
5
-
5
-
4
-
4
-
4
-
tCK
3
-
3
-
2
-
2
-
2
-
tCK
tRP
tRRD
5
-
5
-
5
-
4
-
4
-
tCK
3
-
3
-
3
-
3
-
3
-
tCK
tWR
4
-
4
-
4
-
3
-
3
-
tCK
1
tWR_A
4
-
4
-
4
-
3
-
3
-
tCK
1
tCDLR
tCCD
tMRD
3
-
3
-
2
-
2
-
2
-
tCK
1
1
-
1
-
1
-
1
-
1
-
tCK
2
-
2
-
2
-
2
-
2
-
tCK
tDAL
9
-
9
-
9
-
7
-
7
-
tCK
tXSR
200
-
200
-
200
-
200
-
200
-
tCK
Power down exit time
tPDEX
3tCK
+tIS
-
3tCK
+tIS
-
3tCK
+tIS
-
3tCK
+tIS
-
3tCK
+tIS
-
ns
Refresh interval time
tREF
7.8
-
7.8
-
7.8
-
7.8
-
7.8
-
us
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
Row active to Row active
Last data in to Row precharge
@Normal Precharge
Last data in to Row precharge
@Auto Precharge
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Auto precharge write recovery +
Precharge
Exit self refresh to read command
tCK
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
(Unit : Number of Clock)
AC CHARACTERISTICS (II)
(Unit : Number of Clock)
K4D553238F-JC2A
Frequency
Cas Latency
350MHz ( 2.86ns )
4
300MHz ( 3.3ns )
4
275MHz ( 3.6ns )
4
250MHz ( 4.0ns )
3
200MHz ( 5.0ns )
3
tRC
16
16
16
13
12
tRFC
17
17
17
15
14
tRAS
11
11
11
9
8
tRCDRD tRCDWR
5
3
5
3
4
2
4
2
4
2
tRP
5
5
5
4
4
tRRD
3
3
3
3
3
tDAL
9
9
9
7
7
Unit
K4D553238F-JC33
Frequency
Cas Latency
300MHz ( 3.3ns )
4
275MHz ( 3.6ns )
4
250MHz ( 4.0ns )
3
200MHz ( 5.0ns )
3
tRC
16
16
13
12
tRFC
17
17
15
14
tRAS
11
11
9
8
tRCDRD tRCDWR
5
3
4
2
4
2
4
2
tRP
5
5
4
4
tRRD
3
3
3
3
tDAL
9
9
7
7
Unit
- 15 -
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
K4D553238F-JC36
Frequency
Cas Latency
275MHz ( 3.6ns )
4
250MHz ( 4.0ns )
3
200MHz ( 5.0ns )
3
tRC
16
13
12
tRFC
17
15
14
tRAS
11
9
8
tRCDRD tRCDWR
4
2
4
2
4
2
tRP
5
4
4
tRRD
3
3
3
tDAL
9
7
7
Unit
K4D553238F-JC40
Frequency
Cas Latency
250MHz ( 4.0ns )
3
200MHz ( 5.0ns )
3
tRC
13
12
tRFC
15
14
tRAS
9
8
tRCDRD tRCDWR
4
2
4
2
tRP
4
4
tRRD
3
3
tDAL
7
7
Unit
K4D553238F-JC50
Frequency
Cas Latency
200MHz ( 5.0ns )
3
tRC
12
tRFC
14
tRAS
8
tRCDRD tRCDWR
4
2
tRP
4
tRRD
3
tDAL
7
Unit
tCK
tCK
tCK
tCK
tCK
tCK
Simplified Timing(2) @ BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BAa
BAb
BAa
BAb
Ra
Rb
Ra
Rb
Ca
Cb
17
18
19
20
21
22
CK, CK
BA[1:0] BAa
BAa
BAa
Ra
A8/AP Ra
ADDR
(A0~A7, Ra
A9,A10)
Ca
WE
DQS
DQ
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3
DM
COMMAND
ACTIVEA
PRECH
WRITEA
ACTIVEA
ACTIVEB WRITEA
WRITEB
tRCD
tRAS
tRP
tRC
Normal Write Burst
(@ BL=4)
tRRD
Multi Bank Interleaving Write Burst
(@ BL=4)
- 16 -
Rev 1.0 (Mar. 2004)
256M GDDR SDRAM
K4D553238F-JC
PACKAGE DIMENSIONS (144-Ball FBGA)
A1 INDEX MARK
12.0
12.0
<Top View>
0.8x11=8.8
A1 INDEX MARK
0.10 Max
0.8
B
C
D
E
F
G
H
J
K
L
M
N
0.40
0.8x11=8.8
0.45 ± 0.05
0.8
13 12 11 10 9 8 7 6 5 4 3 2
0.35 ± 0.05
0.40
1.40 Max
<Bottom View>
Unit : mm
- 17 -
Rev 1.0 (Mar. 2004)