Samsung K6R4004V1D-KC08 256kx16 bit high speed static ram(5.0v operating). operated at commercial and industrial temperature ranges. Datasheet

PRELIMPreliminaryPPPPPPPPPINARY
CMOS SRAM
K6R4016C1D
Document Title
256Kx16 Bit High Speed Static RAM(5.0V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev No.
History
Draft Data
Remark
Rev. 0.0
Initial release with Preliminary.
September. 7. 2001
Preliminary
Rev. 0.1
Package dimension modify on page 11.
Septermber.28. 2001
Preliminary
Rev. 0.2
Change Icc, Isb and Isb1
November, 3, 2001
Preliminary
November, 23, 2001
Preliminary
December, 18, 2001
Preliminary
Item
ICC(Commercial)
ICC(Industrial)
10ns
12ns
15ns
10ns
12ns
15ns
ISB
ISB1(Normal)
Previous
90mA
80mA
70mA
115mA
100mA
85mA
30mA
10mA
Current
65mA
55mA
45mA
85mA
75mA
65mA
20mA
5mA
Rev. 0.3
1. Correct AC parameters : Read & Write Cycle
2. Corrrect Power part : Delete "P-Industrial,Low Power" part
3. Delete Data Retention Characteristics
Rev. 0.4
1. Delete 15ns speed bin.
2. Change Icc for Industrial mode.
Item
10ns
ICC(Industrial)
12ns
Previous
85mA
75mA
Current
75mA
65mA
Rev. 1.0
1. Final datasheet release.
2. Delete 12ns speed bin.
July, 09, 2002
Final
Rev. 2.0
1. Add the Lead Free Package type.
June. 20, 2003
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.0
June 2003
PRELIMPreliminaryPPPPPPPPPINARY
CMOS SRAM
K6R4016C1D
4Mb Async. Fast SRAM Ordering Information
Org.
1M x4
512K x8
256K x16
Part Number
VDD(V)
Speed ( ns )
5
10
K6R4004V1D-J(K)C(I) 08/10
3.3
8/10
K6R4008C1D-J(K,T,U)C(I) 10
5
10
K6R4008V1D-J(K,T,U)C(I) 08/10
3.3
8/10
K6R4016C1D-J(K,T,U,E)C(I) 10
5
10
3.3
8/10
K6R4004C1D-J(K)C(I) 10
K6R4016V1D-J(K,T,U,E)C(I,L,P) 08/10
-2-
PKG
J : 32-SOJ
K : 32-SOJ(LF)
J : 36-SOJ
K : 36-SOJ(LF)
T : 44-TSOP2
U : 44-TSOP2(LF)
J : 44-SOJ
K : 44-SOJ(LF)
T : 44-TSOP2
U: 44-TSOP2(LF)
E : 48-TBGA
Temp. & Power
C : Commercial Temperature
,Normal Power Range
I : Industrial Temperature
,Normal Power Range
L : Commercial Temperature
,Low Power Range
P : Industrial Temperature
,Low Power Range
Rev 2.0
June 2003
PRELIMPreliminaryPPPPPPPPPINARY
CMOS SRAM
K6R4016C1D
256K x 16 Bit High-Speed CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 10ns(Max.)
• Low Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating K6R4016C1D-10 : 65mA(Max.)
• Single 5.0V±10 % Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16
• Standard Pin Configuration
K6R4016C1D-J : 44-SOJ-400
K6R4016C1D-K : 44-SOJ-400(Lead-Free)
K6R4016C1D-T : 44-TSOP2-400BF
K6R4016C1D-U : 44-TSOP2-400BF (Lead-Free)
K6R4016C1D-E : 48-TBGA with 0.75 Ball pitch
(7mm X 9mm)
• Operating in Commercial and Industrial Temperature range.
The K6R4016C1D is a 4,194,304-bit high-speed Static Random Access Memory organized as 262,144 words by 16 bits.
The K6R4016C1D uses 16 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. Also it allows that lower and upper
byte access by data byte control(UB, LB). The device is fabricated using SAMSUNG′s advanced CMOS process and
designed for high-speed circuit technology. It is particularly well
suited for use in high-density high-speed system applications.
The K6R4016C1D is packaged in a 400mil 44-pin plastic SOJ
or TSOP(II) forward or 48 T BGA.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
Pre-Charge Circuit
A2
A3
A4
A5
A6
A7
A8
A9
Row Select
A0
A1
I/O1 ~I/O 8
Data
Cont.
I/O9 ~I/O 16
Data
Cont.
Memory Array
1024 Rows
256 x 16 Columns
I/O Circuit &
Column Select
Gen.
CLK
A10 A11 A1 2 A13 A 14 A 15 A16 A1 7
WE
OE
UB
LB
CS
-3-
Rev 2.0
June 2003
PRELIMPreliminaryPPPPPPPPPINARY
CMOS SRAM
K6R4016C1D
PIN CONFIGURATION
(Top View)
A0
1
4 4 A 17
A1
2
4 3 A 16
A2
3
4 2 A 15
A3
4
4 1 OE
A4
5
4 0 UB
CS
6
3 9 LB
I/O1
7
3 8 I/O 16
I/O2
8
3 7 I/O 15
I/O3
9
3 6 I/O 14
SOJ/
TSOP2
I/O4 10
Vcc 11
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
N.C
B
I/O1
UB
A3
A4
CS
I/O9
C
I/O2
I/O3
A5
A6
I/O11
I/O10
D
Vss
I/O4
A17
A7
I/O12
Vcc
E
Vcc
I/O5
N.C
A16
I/O13
Vss
F
I/O7
I/O6
A14
A15
I/O14
I/O15
G
I/O8
N.C
A12
A13
WE
I/O16
H
N.C
A8
A9
A10
A11
N.C
3 5 I/O 13
3 4 Vss
Vss 12
3 3 Vcc
I/O5 13
3 2 I/O 12
I/O6 14
3 1 I/O 11
I/O7 15
3 0 I/O 10
I/O8 16
2 9 I/O 9
WE 17
2 8 N.C
A5 18
2 7 A 14
A6 19
2 6 A 13
A7 20
2 5 A 12
A8 21
2 4 A 11
A9 22
2 3 A 10
48-TBGA
PIN FUNCTION
Pin Name
A 0 - A17
Pin Function
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
LB
Lower-byte Control(I/O 1~I/O 8)
UB
Upper-byte Control(I/O 9~I/O 16)
I/O1 ~ I/O 16
Data Inputs/Outputs
V CC
Power(+5.0V)
V SS
Ground
N.C
No Connection
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V SS
Voltage on V CC Supply Relative to V SS
Symbol
Rating
Unit
V IN, V OUT
-0.5 to V CC+0.5
V
V CC
-0.5 to 7.0
V
Power Dissipation
Storage Temperature
Operating Temperature
PD
1.0
W
TSTG
-65 to 150
°C
Commercial
TA
0 to 70
°C
Industrial
TA
-40 to 85
°C
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
-4-
Rev 2.0
June 2003
PRELIMPreliminaryPPPPPPPPPINARY
CMOS SRAM
K6R4016C1D
RECOMMENDED DC OPERATING CONDITIONS* (T A=0 to 70°C)
Symbol
Min
Typ
Max
Unit
Supply Voltage
Parameter
V CC
4.5
5.0
5.5
V
Ground
V SS
0
0
0
V
Input High Voltage
V IH
2.2
-
V CC+0.5***
V
Input Low Voltage
V IL
-0.5**
-
0.8
V
* The above parameters are also guaranteed at industrial temperature range.
** VIL (Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.
*** VIH (Max) = V C C + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.
DC AND OPERATING CHARACTERISTICS* (TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Min
Max
Unit
Input Leakage Current
Parameter
ILI
V IN=VSS to V CC
-2
2
µA
Output Leakage Current
ILO
CS = VIH or O E=VIH or WE=V IL
V OUT=VSS to V CC
-2
2
µA
Operating Current
ICC
Min. Cycle, 100% Duty
CS = VIL, V IN=V I H or V IL, IOUT=0mA
mA
Standby Current
Symbol
Test Conditions
Com.
10ns
-
65
Ind.
10ns
-
75
ISB
Min. Cycle, CS=V I H
-
20
ISB1
f=0MHz, CS ≥V CC-0.2V,
V IN≥V CC-0.2V or V IN≤0.2V
-
5
mA
Output Low Voltage Level
V OL
IOL =8mA
-
0.4
V
Output High Voltage Level
V OH
IOH=-4mA
2.4
-
V
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA =25°C, f=1.0MHz)
Item
Symbol
Test Conditions
TYP
Max
Unit
Input/Output Capacitance
CI/O
V I/O=0V
-
8
pF
Input Capacitance
CIN
V IN=0V
-
6
pF
* Capacitance is sampled and not 100% tested.
-5-
Rev 2.0
June 2003
PRELIMPreliminaryPPPPPPPPPINARY
CMOS SRAM
K6R4016C1D
AC CHARACTERISTICS (T A=0 to 70°C, V CC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
* The above test conditions are also applied at industrial temperature range.
Output Loads(B)
for tHZ, t LZ, tWHZ, tOW , tOLZ & tOHZ
Output Loads(A)
+5.0V
R L = 50Ω
DOUT
480Ω
VL = 1.5V
D OUT
30pF*
Z O = 50Ω
255Ω
* Capacitive Load consists of all components of the
test environment.
5pF*
* Including Scope and Jig Capacitance
READ CYCLE*
K6R4016C1D-10
Parameter
Symbol
Min
Max
Unit
Read Cycle Time
tRC
10
-
ns
Address Access Time
tAA
-
10
ns
Chip Select to Output
tCO
-
10
ns
Output Enable to Valid Output
tOE
-
5
ns
Chip Enable to Low-Z Output
tLZ
3
-
ns
Output Enable to Low-Z Output
tOLZ
0
-
ns
Chip Disable to High-Z Output
tHZ
0
5
ns
Output Disable to High-Z Output
tOHZ
0
5
ns
Output Hold from Address Change
tOH
3
-
ns
Chip Selection to Power Up Time
tPU
0
-
ns
Chip Selection to Power DownTime
tPD
-
10
ns
* The above parameters are also guaranteed at industrial temperature range.
-6-
Rev 2.0
June 2003
PRELIMPreliminaryPPPPPPPPPINARY
CMOS SRAM
K6R4016C1D
WRITE CYCLE*
K6R4016C1D-10
Parameter
Symbol
Min
Max
Unit
Write Cycle Time
tWC
10
-
ns
Chip Select to End of Write
tCW
7
-
ns
Address Set-up Time
tAS
0
-
ns
Address Valid to End of Write
tAW
7
-
ns
Write Pulse Width(O E High)
tWP
7
-
ns
Write Pulse Width(O E Low)
tWP1
10
-
ns
Write Recovery Time
tWR
0
-
ns
Write to Output High-Z
tWHZ
0
5
ns
Data to Write Time Overlap
tDW
5
-
ns
Data Hold from Write Time
tDH
0
-
ns
End of Write to Output Low-Z
tOW
3
-
ns
* The above parameters are also guaranteed at industrial temperature range.
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled , CS=OE=VIL , WE=VIH , UB, LB =VIL )
tRC
Address
tAA
tOH
Data Out
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2)
Valid Data
(WE=VIH )
tRC
Address
tAA
tCO
CS
tHZ(3,4,5)
tBHZ(3,4,5)
tBA
UB, LB
tBLZ(4,5)
tOHZ
tOE
OE
tOLZ
Data out
High-Z
tOH
tLZ(4,5)
Valid Data
-7-
Rev 2.0
June 2003
PRELIMPreliminaryPPPPPPPPPINARY
CMOS SRAM
K6R4016C1D
NOTES (READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.
4. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) ( O E Clock)
tWC
Address
tAW
tWR(5)
OE
tCW(3)
CS
tBW
UB, LB
tAS(4)
tWP(2)
WE
tDW
Data in
High-Z
tDH
High-Z
Valid Data
tOHZ(6)
Data out
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE=Low fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tBW
UB, LB
tWP1(2)
tAS(4)
WE
tDW
Data in
High-Z
tDH
Valid Data
tWHZ(6)
tOW
(10)
(9)
High-Z
Data out
-8-
Rev 2.0
June 2003
PRELIMPreliminaryPPPPPPPPPINARY
CMOS SRAM
K6R4016C1D
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tBW
UB, LB
tAS(4)
tWP(2)
WE
tDW
Data in
High-Z
High-Z
Valid Data
tLZ
Data out
tDH
tWHZ(6)
High-Z
High-Z(8)
TIMING WAVEFORM OF WRITE CYCLE(4) ( UB, L B Controlled)
tWC
Address
tAW
tCW(3)
tWR(5)
CS
tBW
UB, LB
tAS(4)
tWP(2)
WE
tDW
Data in
Valid Data
tBLZ
Data out
tDH
High-Z
tWHZ(6)
High-Z(8)
High-Z
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE
going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write
to the end of write.
3. t CW is measured from the later of CS going low to end of write.
4. t AS is measured from the address valid to the beginning of write.
5. t WR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high.
6. If OE , CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not . be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
-9-
Rev 2.0
June 2003
PRELIMPreliminaryPPPPPPPPPINARY
CMOS SRAM
K6R4016C1D
FUNCTIONAL DESCRIPTION
CS
WE
OE
LB
UB
I/O Pin
Mode
Supply Current
I/O1 ~I/O8
I/O9 ~I/O16
H
X
X*
X
X
Not Select
High-Z
High-Z
ISB , ISB1
L
H
H
X
X
Output Disable
High-Z
High-Z
ICC
L
X
X
H
H
L
H
L
L
H
DOUT
High-Z
ICC
H
L
High-Z
D OUT
L
L
X
L
L
L
H
H
L
Read
DOUT
D OUT
D IN
High-Z
L
High-Z
D IN
L
D IN
D IN
Write
ICC
* X means Don ′t Care.
- 10
Rev 2.0
June 2003
PRELIMPreliminaryPPPPPPPPPINARY
K6R4016C1D
CMOS SRAM
PACKAGE DIMENSIONS
Units:millimeters/Inches
44-SOJ-400
#23
9.40 ± 0.25
0.370 ±0.010
10.1 6
0.40 0
#44
11.18 ± 0.12
0.440 ± 0.005
0.20 +0.10
-0.05
0.008 +0.004
- 0.002
#1
#22
28.98
MAX
1.141
0.69 MIN
0.027
25.58 ± 0.12
1.125 ± 0.005
1.19
)
0.047
3.76
1.27
MAX
( 0.050 ) 0.148
0.10 MAX
0.004
(
0.43
0.017
( 0.95 )
0.0375
+0.10
-0.05
+0.004
- 0.002
1.27
0.050
0.71
+0.10
-0.05
0.028 +0.004
-0.002
44-TSOP2-400BF
Units:millimeters/Inches
0~8°
0.25
0.010 TYP
#23
#44
11.76 ±0.20
0.463 ±0.008
1 0.1 6
0.400
0.45 ~0.75
0.018 ~ 0.030
( 0.50 )
0.020
#1
#22
18.81
MAX
0.741
18.41
0.725
0.075
0.125+- 0.035
0.005 +- 0.003
0.001
± 0.10
±0.004
1.00 ± 0.10
0.039 ±0.004
( 0.805 )
0.032
0.30 +0.10
−0.05
0.012 +− 0.004
0.002
0.05
0.002 MIN
0.80
0.0315
- 11
1.20
MAX
0.047
0.10
0.004 MAX
Rev 2.0
June 2003
PRELIMPreliminaryPPPPPPPPPINARY
CMOS SRAM
K6R4016C1D
PACKAGE DIMENSIONS
Units : millimeter.
Top View
Bottom View
B
B
A1 INDEX MARK
0.50
B1
6
5
4
3
2
0.50
1
A
B
#A1
C
C
C1
C
D
C1/2
E
F
G
H
B/2
Detail A
Side View
Y
0.55/Typ.
E1
E
0.35/Typ.
E2
0.30
A
D
C
Min
Typ
Max
A
-
0.75
-
B
6.90
7.00
7.10
B1
-
3.75
-
C
8.90
9.00
9.10
C1
-
5.25
-
D
0.40
0.45
0.50
E
0.80
0.90
1.00
E1
-
0.55
-
E2
0.30
0.35
0.40
Y
-
-
0.08
Notes.
1. Bump counts: 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ : Typical
5. Y is coplanarity: 0.08(Max)
- 12
Rev 2.0
June 2003
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