Samsung K6T1008C2E-DL55 128kx8 bit low power cmos static ram Datasheet

K6T1008C2E Family
CMOS SRAM
Document Title
128Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No.
History
Draft Data
Remark
0.0
Design target
October 12, 1998
Preliminary
1.0
Finalize
- Improve tWP form 55ns to 50ns for 70ns product.
- Remove 55ns speed bin from industrial product.
August 30, 1999
Final
1.01
Errata correction
December 1, 1999
2.0
Revise
February 14, 2000
Final
3.0
Revise
- Add 55ns parts to industrial products.
March 3, 2000
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
128Kx8 bit Low Power CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: TFT
• Organization: 128Kx8
• Power Supply Voltage: 4.5~5.5V
• Low Data Retention Voltage: 2V(Min)
• Three state output and TTL Compatible
• Package Type: 32-DIP-600, 32-SOP-525,
32-TSOP1-0820F/R
The K6T1008C2E families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
various operating temperature ranges and have various package types for user flexibility of system design. The families
also support low data retention voltage for battery back-up
operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
K6T1008C2E-L
Vcc Range
Speed
Standby
(ISB1, Max)
50µA
Commercial(0~70°C)
K6T1008C2E-B
4.5~5.5V
K6T1008C2E-P
Operating
(ICC2, Max)
10µA
551)/70ns
32-DIP-600, 32-SOP-525
32-TSOP1-0820F/R
50mA
50µA
Industrial(-40~85°C)
K6T1008C2E-F
PKG Type
32-SOP -525
32-TSOP1-0820F/R
15µA
1. The parameters are tested with 50pF test load
PIN DESCRIPTION
N.C
1
32
A16
2
31
A14
3
30
A12
4
29
A7
5
28
A6
6
A5
7
A4
8
25
A11
A9
A8
A13
WE
VCC
CS2
A15 A15
VCC
CS2 NC
WE A16
A14
A13 A12
A7
A8
A6
A5
A9
A4
A11
A3
9
24
OE
A2
10
23
A1
11
22
32-SOP
32-DIP
27
26
A0
12
21
I/O1
13
20
I/O2
14
19
I/O3
15
18
VSS
16
17
A4
A5
CS1 A6
A7
I/O8 A12
A14
I/O7 A16
I/O6 NC
VCC
I/O5 A15
CS2
I/O4
WE
A13
A8
A9
A11
A10
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-TSOP
Type1-Forward
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
32-TSOP
Type1-Reverse
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS1
A10
OE
Clk gen.
Raw
Address
I/O1
I/O8
Row
select
Data
cont
Precharge circuit.
Memory array
1024 rows
128×8 columns
I/O Circuit
Column select
Data
cont
Column Address
Name
CS 1, CS2
Function
Chip Select Input
CS 1
OE
Output Enable Input
WE
Write Enable Input
WE
Data Inputs/Outputs
OE
CS 2
I/O1~I/O8
A0~A16
Control
logic
Address Inputs
Vcc
Power
Vss
Ground
N.C.
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Part Name
Industrial Temperature Products(-40~85°C)
Function
Part Name
Function
K6T1008C2E-DL55
K6T1008C2E-DL70
K6T1008C2E-DB55
K6T1008C2E-DB70
32-DIP, 55ns, Low Power
32-DIP, 70ns, Low Power
32-DIP, 55ns, Low Low Power
32-DIP, 70ns, Low Low Power
K6T1008C2E-GP55
K6T1008C2E-GP70
K6T1008C2E-GF55
K6T1008C2E-GF70
32-SOP, 55ns, Low Power
32-SOP, 70ns, Low Power
32-SOP, 55ns, Low Low Power
32-SOP, 70ns, Low Low Power
K6T1008C2E-GL55
K6T1008C2E-GL70
K6T1008C2E-GB55
K6T1008C2E-GB70
32-SOP, 55ns, Low Power
32-SOP, 70ns, Low Power
32-SOP, 55ns, Low Low Power
32-SOP, 70ns, Low Low Power
K6T1008C2E-TF55
K6T1008C2E-TF70
K6T1008C2E-RF55
K6T1008C2E-RF70
32-TSOP F, 55ns, Low Low Power
32-TSOP F, 70ns, Low Low Power
32-TSOP R, 55ns, Low Low Power
32-TSOP R, 70ns, Low Low Power
K6T1008C2E-TB55
K6T1008C2E-TB70
K6T1008C2E-RB55
K6T1008C2E-RB70
32-TSOP F, 55ns, Low Low Power
32-TSOP F, 70ns, Low Low Power
32-TSOP R, 55ns, Low Low Power
32-TSOP R, 70ns, Low Low Power
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O
Mode
Power
1)
1)
H
X
X
X
High-Z
Deselected
Standby
X1)
L
X1)
X1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disabled
Active
L
H
L
H
Dout
Read
Active
L
H
L
Din
Write
Active
1)
1)
X
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
Ratings
Unit
Remark
VIN,VOUT
-0.5 to 7.0
V
-
VCC
-0.5 to 7.0
V
-
PD
1.0
W
-
TSTG
-65 to 150
°C
-
0 to 70
°C
K6T1008C2E-L/-B
-40 to 85
°C
K6T1008C2E-P/-F
TA
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Product
Min
Typ
Max
Unit
V
Supply voltage
Vcc
K6T1008C2E Family
4.5
5.0
5.5
Ground
Vss
All Family
0
0
0
Input high voltage
VIH
K6T1008C2E Family
2.2
-
Input low voltage
VIL
K6T1008C2E Family
-0.5
3)
V
Vcc+0.5
-
V
2)
0.8
V
Note:
1. Commercial Product: TA=0 to 70°C
Industrial Product: TA=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+3.0V in case of pulse width≤30ns.
3. Undershoot: -3.0V in case of pulse width≤30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
6
pF
Input/Output capacitance
CIO
VIO=0V
-
8
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min Typ Max Unit
Input leakage current
ILI
VIN=Vss to Vcc
-1
-
1
µA
Output leakage current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
-1
-
1
µA
Operating power supply current
ICC
IIO=0mA, CS1=VIL, CS 2=VIH, VIN=VIH or VIL, Read
-
-
10
mA
ICC1
Cycle time=1µs, 100%duty, I IO=0mA, CS1 ≤0.2V, CS2 ≥Vcc-0.2V, V IN≤0.2V
or VIN≥VCC-0.2V
-
-
7
mA
ICC2
Cycle time=Min, 100% duty, IIO=0mA, CS1 =VIL, CS2=VIH, VIN=VIH or VIL
-
-
50
mA
Output low voltage
VOL
IOL=2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH=-1.0mA
2.4
-
-
V
Standby Current(TTL)
ISB
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
-
-
3
Standby Current(CMOS)
ISB1
CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V, Other inputs=0~Vcc
-
-
Average operating current
50
1)
mA
µA
1. 50µA for Low power product, in case of Low Low power products are comercial=10µA, industrial=15µA.
4
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL=50pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS (VCC=4.5~5.5V, Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
55ns
Min
Read
Write
Units
70ns
Max
Min
Max
Read Cycle Time
tRC
55
-
70
-
ns
Address Access Time
tAA
-
55
-
70
ns
Chip Select to Output
tCO
-
55
-
70
ns
Output Enable to Valid Output
tOE
-
25
-
35
ns
Chip Select to Low-Z Output
tLZ
10
-
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
5
-
ns
Chip Disable to High-Z Output
tHZ
0
20
0
25
ns
Output Disable to High-Z Output
tOHZ
0
20
0
25
ns
Output Hold from Address Change
tOH
10
-
10
-
ns
Write Cycle Time
tWC
55
-
70
-
ns
Chip Select to End of Write
tCW
45
-
60
-
ns
Address Set-up Time
tAS
0
-
0
-
ns
Address Valid to End of Write
tAW
45
-
60
-
ns
Write Pulse Width
tWP
40
-
50
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
20
0
25
ns
Data to Write Time Overlap
tDW
20
-
25
-
ns
Data Hold from Write Time
tDH
0
-
0
-
ns
End Write to Output Low-Z
tOW
5
-
5
-
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Symbol
VDR
IDR
Data retention set-up time
tSDR
Recovery time
tRDR
Test Condition
CS1≥Vcc-0.2V1)
Vcc=3.0V, CS1≥Vcc-0.2V1)
See data retention waveform
Min
Typ
Max
Unit
2.0
-
5.5
V
K6T1008C2E-L
-
-
20
K6T1008C2E-B
-
-
10
K6T1008C2E-P
-
-
25
K6T1008C2F-F
-
-
10
0
-
-
5
-
-
µA
ms
1. CS1 ≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or CS2≤0.2V(CS2 controlled)
5
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
Data out
High-Z
tOHZ
tOLZ
tLZ
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to device
interconnection.
6
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS 1
tAW
CS 2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1
Controlled)
tWC
Address
tCW(2)
tAS(3)
tWR(4)
CS 1
tAW
CS 2
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
7
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1 , a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. t WR1 applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC
tSDR
Data Retention Mode
tRDR
4.5V
2.2V
VDR
CS≥VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
4.5V
CS 2
tSDR
tRDR
VDR
CS2≤0.2V
0.4V
GND
8
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
32 DUAL INLINE PACKAGE (600mil)
0.25
+0.10
-0.05
+0.004
0.010-0.002
#17
15.24
0.600
#32
13.60±0.20
0.535±0.008
#1
#16
0~15°
3.81±0.20
0.150±0.008
42.31
1.666 MAX
5.08
0.200 MAX
41.91±0.20
1.650±0.008
3.30±0.30
0.130±0.012
0.46±0.10
0.018±0.004
1.52±0.10
0.060±0.004
( 1.91 )
0.075
2.54
0.100
0.38 MIN
0.015
32 PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#17
14.12±0.30
0.556±0.012
#1
#16
2.74±0.20
0.108±0.008
3.00
0.118 MAX
20.87 MAX
0.822
20.47±0.20
0.806±0.008
11.43±0.20
0.450±0.008
0.20 +0.10
-0.05
0.008+0.004
-0.002
13.34
0.525
#32
0.80±0.20
0.031±0.008
0.10 MAX
0.004 MAX
( 0.71 )
0.028
+0.100
-0.050
+0.004
0.016 -0.002
0.41
1.27
0.050
0.05 MIN
0.002
9
Revision 3.0
March 2000
K6T1008C2E Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
20.00±0.20
0.787±0.008
+0.10
-0.05
+0.004
0.008-0.002
0.20
#1
#32
8.40
0.331 MAX
0.50
0.0197
#17
#16
0.25
0.010 TYP
0.25
)
0.010
8.00
0.315
(
1.00±0.10
0.039±0.004
1.20
0.047 MAX
18.40±0.10
0.724±0.004
+0.10
-0.05
0.006+0.004
-0.002
0.05
0.002 MIN
0~8°
0.45 ~0.75
0.018 ~0.030
(
0.10 MAX
0.004 MAX
0.15
0.50
)
0.020
32 THIN SMALL OUTLINE PACKAGE TYPE I (0820R)
+0.10
-0.05
0.008+0.004
-0.002
0.20
20.00±0.20
0.787±0.008
#16
#17
0.50
0.0197
#1
0.25
)
0.010
8.00
0.315
8.40
0.331 MAX
(
#32
1.00±0.10
0.039±0.004
0.05
0.002 MIN
1.20
0.047 MAX
18.40±0.10
0.724±0.004
+0.10
-0.05
+0.004
0.006 -0.002
0.15
0~8°
0.45 ~0.75
0.018 ~0.030
(
10
0.10 MAX
0.004 MAX
0.25
0.010 TYP
0.50
)
0.020
Revision 3.0
March 2000
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