Samsung K6T1008V2C-D 128k x8 bit low power and low voltage cmos static ram Datasheet

K6T1008V2C, K6T1008U2C Family
CMOS SRAM
Document Title
128K x8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No. History
Draft Data
Remark
0.0
Initial draft
July 3, 1996
Preliminary
1.0
Finalize
- Increased ISB, IDR
Commercial part = 10µA
Industrial part = 20µA
December 16, 1996
Final
2.0
Revise
- Change speed bin
KM68V1000C Family: 70/85ns → 70/100ns
KM68U1000C Family: 70/100ns → 85/100ns
- Improved operating current: 40mA → 35mA
- Improved power dissipation
PD: 0.7W → 1.0W
- Improved standby current
Extended/Industrial: 20 → 10µA
- VIL: 0.4V → 0.6V
November 25, 1997
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 2.0
November 1997
K6T1008V2C, K6T1008U2C Family
CMOS SRAM
128K x8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: 0.4µm CMOS
• Organization: 128K x8
• Power Supply Voltage:
K6T1008V2C family: 3.0~3.6V
K6T1008U2C family: 2.7~3.3V
• Low Data Retention Voltage: 2V(Min)
• Three state output and TTL Compatible
• Package Type: 32-SOP-525, 32-TSOP1-0820F/R,
32-TSOP1-0813.4F/R
The K6T1008V2C and K6T1008U2C families are fabricated by
SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and have
various package types for user flexibility of system design. The
families also supports low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed
3.0~3.6V
70/100ns
K6T1008U2C-B
2.7~3.3V
85/100ns
K6T1008V2C-D
3.0~3.6V
70/100ns
K6T1008U2C-D
2.7~3.3V
85/100ns
K6T1008V2C-F
3.0~3.6V
70/100ns
2.7~3.3V
85/100ns
K6T1008V2C-B
Commercial(0~70°C)
Extended(-25~85°C)
Industrial(-40~85°C)
K6T1008U2C-F
PIN DESCRIPTION
26
A11
A9
A8
A13
WE
VCC CS2
A15
A15 VCC
CS2 NC
A16
WE A14
A12
A13 A7
A6
A8
A5
A9
A4
25
A11
9
24
OE
A2
10
23
A10
A1
11
22
A0
12
21
I/O1
13
20
N.C
1
32
A16
2
31
A14
3
30
A12
4
29
A7
5
28
A6
6
A5
7
A4
8
A3
27
32-SOP
I/O2
14
19
I/O3
15
18
VSS
16
17
A4
A5
A6
CS1 A7
I/O8 A12
A14
I/O7 A16
NC
I/O6
VCC
I/O5 A15
CS2
I/O4 WE
A13
A8
A9
A11
Standby
(ISB1, Max)
Operating
(ICC2, Max)
10µA
35mA
32-SOP
32-TSOP1-F/R
32-sTSOP1-F/R
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-TSOP
32-STSOP
Type1-Forward
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS1
A10
OE
Clk gen.
Precharge circuit.
VCC
VSS
A4
A5
A6
A7
A8
A12
Row
select
Memory array
1024 rows
128×8 columns
Data
cont
Column select
A13
A14
A15
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
32-TSOP
32-STSOP
Type1-Reverse
A16
I/O1
I/O8
I/O Circuit
A10 A0
Name
CS1 , CS 2
A2 A3 A9
A11
Chip Select Inputs
CS1
Output Enable Input
WE
Write Enable Input
WE
Address Inputs
OE
CS2
A0 ~A16
A1
Function
OE
I/O1 ~I/O8
PKG Type
Control
logic
Data Inputs/Outputs
Vcc
Power
Vss
Ground
N.C
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 2.0
November 1997
K6T1008V2C, K6T1008U2C Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products
(0~70°C)
Part Name
Extended Temperature Products
(-25~85°C)
Industrial Temperature Products
(-40~85°C)
Part Name
Part Name
Function
Function
Function
K6T1008V2C-GB70
K6T1008V2C-GB10
K6T1008V2C-TB70
K6T1008V2C-TB10
K6T1008V2C-RB70
K6T1008V2C-RB10
32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-TSOP R, 70ns, 3.3V
32-TSOP R, 100ns, 3.3V
K6T1008V2C-GD70
K6T1008V2C-GD10
K6T1008V2C-TD70
K6T1008V2C-TD10
K6T1008V2C-RD70
K6T1008V2C-RD10
32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-TSOP R, 70ns, 3.3V
32-TSOP R, 100ns, 3.3V
K6T1008V2C-GF70
K6T1008V2C-GF10
K6T1008V2C-TF70
K6T1008V2C-TF10
K6T1008V2C-RF70
K6T1008V2C-RF10
32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-TSOP R, 70ns, 3.3V
32-TSOP R, 100ns, 3.3V
K6T1008U2C-GB85
K6T1008U2C-GB10
K6T1008U2C-TB85
K6T1008U2C-TB10
K6T1008U2C-RB85
K6T1008U2C-RB10
32-SOP, 85ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 85ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-TSOP R, 85ns, 3.0V
32-TSOP R, 100ns, 3.0V
K6T1008U2C-GD85
K6T1008U2C-GD10
K6T1008U2C-TD85
K6T1008U2C-TD10
K6T1008U2C-RD85
K6T1008U2C-RD10
32-SOP, 85ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 85ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-TSOP R, 85ns, 3.0V
32-TSOP R, 100ns, 3.0V
K6T1008U2C-GF85
K6T1008U2C-GF10
K6T1008U2C-TF85
K6T1008U2C-TF10
K6T1008U2C-RF85
K6T1008U2C-RF10
32-SOP, 85ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 85ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-TSOP R, 85ns, 3.0V
32-TSOP R, 100ns, 3.0V
K6T1008V2C-YB70
K6T1008V2C-YB10
K6T1008V2C-NB70
K6T1008V2C-NB10
32-sTSOP F, 70ns, 3.3V
32-sTSOP F, 100ns, 3.3V
32-sTSOP R, 70ns, 3.3V
32-sTSOP R, 100ns, 3.3V
K6T1008V2C-YD70
K6T1008V2C-YD10
K6T1008V2C-ND70
K6T1008V2C-ND10
32-sTSOP F, 70ns, 3.3V
32-sTSOP F, 100ns, 3.3V
32-sTSOP R, 70ns, 3.3V
32-sTSOP R, 100ns, 3.3V
K6T1008V2C-YF70
K6T1008V2C-YF10
K6T1008V2C-NF70
K6T1008V2C-NF10
32-sTSOP F, 70ns, 3.3V
32-sTSOP F, 100ns, 3.3V
32-sTSOP R, 70ns, 3.3V
32-sTSOP R, 100ns, 3.3V
K6T1008U2C-YB85
K6T1008U2C-YB10
K6T1008U2C-NB85
K6T1008U2C-NB10
32-sTSOP F, 85ns, 3.0V
32-sTSOP F, 100ns, 3.0V
32-sTSOP R, 85ns, 3.0V
32-sTSOP R, 100ns, 3.0V
K6T1008U2C-YD85
K6T1008U2C-YD10
K6T1008U2C-ND85
K6T1008U2C-ND10
32-sTSOP F, 85ns, 3.0V
32-sTSOP F, 100ns, 3.0V
32-sTSOP R, 85ns, 3.0V
32-sTSOP R, 100ns, 3.0V
K6T1008U2C-YF85
K6T1008U2C-YF10
K6T1008U2C-NF85
K6T1008U2C-NF10
32-sTSOP F, 85ns, 3.0V
32-sTSOP F, 100ns, 3.0V
32-sTSOP R, 85ns, 3.0V
32-sTSOP R, 100ns, 3.0V
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O Pin
Mode
Power
1)
H
X
X
X
High-Z
Deselected
Standby
X1)
L
X1)
X1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disabled
Active
L
H
L
H
Dout
Read
Active
L
H
L
Din
Write
Active
1)
1)
1)
X
1. X means don′t care(Must be in high or low status.)
ABSOLUTE MAXIMUM RATINGS1)
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
Item
VIN,VOUT
-0.5 to VCC+0.5
V
-
Voltage on Vcc supply relative to
VCC
-0.3 to 4.6
V
-
Power Dissipation
Storage temperature
Operating Temperature
Soldering temperature and time
PD
1.0
W
-
TSTG
-65 to 150
°C
-
0 to 70
°C
K6T1008V2C-B/K6T1008U2C-B
TA
-25 to 85
°C
K6T1008V2C-D/K6T1008U2C-D
-40 to 85
°C
K6T1008V2C-F/K6T1008U2C-F
TSOLDER
260°C, 10sec (Lead Only)
-
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 2.0
November 1997
K6T1008V2C, K6T1008U2C Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Product
Min
Typ
Max
Unit
Supply voltage
Vcc
K6T1008V2C Family
K6T1008U2C Family
3.0
2.7
3.3
3.0
3.6
3.3
V
Ground
Vss
All Family
0
0
0
V
Input high voltage
VIH
K6T1008V2C, K6T1008U2C Family
2.2
-
Vcc+0.32)
V
Input low voltage
VIL
K6T1008V2C, K6T1008U2C Family
-
0.6
V
-0.3
3)
1. Commercial Product: TA=0 to 70°C, unless otherwise specified
Extended Product: TA=-25 to 85°C, unless otherwise specified
Industrial Product: T A=-40 to 85°C, unless otherwise specified
2. Overshoot: VCC+3.0V in case of pulse width ≤30ns
3. Undershoot: -3.0V in case of pulse width ≤30ns
4. Overshoot and undershoot is sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
6
pF
Input/Output capacitance
CIO
VIO=0V
-
8
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Min
Typ
Max
Unit
Input leakage current
Item
ILI
VIN=Vss to Vcc
-1
-
1
µA
Output leakage current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
-1
-
1
µA
Operating power supply
ICC
IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH, Read
-
2
5
mA
ICC1
Cycle time=1µs, 100% duty, IIO=0mA,
CS1≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V
-
1.5
5
10
15
-
25
35
mA
Average operating current
Symbol
ICC2
Test Conditions
Read
Write
Cycle time=Min, 100% duty, IIO=0mA, CS1 =VIL, CS2 =VIH, VIN =VIL or V IH
mA
Output low voltage
VOL
IOL=2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH=-1.0mA
2.2
-
-
V
Standby Current(TTL)
ISB
CS1=VIH, CS2=VIL, Other inputs=VIL or VIH
-
-
0.3
mA
Standby Current(CMOS)
ISB1
CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V, Other inputs=0~Vcc
-
0.3
10
µA
4
Revision 2.0
November 1997
K6T1008V2C, K6T1008U2C Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C L=100pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS (Commercial product:TA=0 to 70°C, Extended product:TA=-25 to 85°C, Industrial product: TA=-40 to 85°C
K6T1008V2C Family: Vcc=3.0~3.6V, K6T1008U2C Family: Vcc=2.7~3.3V)
Speed Bins
Parameter List
Symbol
Units
100ns
Min
Max
Min
Max
Min
Max
tRC
70
-
85
-
100
-
ns
Address access time
tAA
-
70
-
85
-
100
ns
Chip select to output
tCO1, tCO2
-
70
-
85
-
100
ns
tOE
-
35
-
40
-
50
ns
tLZ
10
-
10
-
10
-
ns
tOLZ
5
-
5
-
5
-
ns
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
tHZ
0
25
0
25
0
30
ns
tOHZ
0
25
0
25
0
30
ns
Output hold from address change
tOH
10
-
15
-
15
-
ns
Write cycle time
tWC
70
-
85
-
100
-
ns
Chip select to end of write
tCW
60
-
70
-
80
-
ns
Address set-up time
tAS
0
-
0
-
0
-
ns
Address valid to end of write
tAW
60
-
70
-
80
-
ns
Write pulse width
tWP
55
-
60
-
70
-
ns
Write recovery time
tWR
0
-
0
-
0
-
ns
Write to output high-Z
tWHZ
0
25
0
30
0
30
ns
Data to write time overlap
tDW
30
-
35
-
40
-
ns
Data hold from write time
tDH
0
-
0
-
0
-
ns
End write to output low-Z
tOW
5
-
5
-
5
-
ns
Output disable to high-Z output
Write
85ns
Read cycle time
Output enable to valid output
Read
70ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Symbol
Test Condition1)
VDR
CS11)≥Vcc-0.2V
Vcc=3.0V, CS1≥Vcc-0.2V, CS2≥VCC-0.2V, or CS2≤0.2V
Data retention current
IDR
Data retention set-up time
tSDR
Recovery time
tRDR
See data retention waveform
Min
Typ
Max
Unit
2.0
-
3.6
V
µA
-
0.3
5
0
-
-
5
-
-
ms
1. CS1≥Vcc-0.2V, CS2 ≥VCC-0.2V, or CS2 ≤0.2V
5
Revision 2.0
November 1997
K6T1008V2C, K6T1008U2C Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
Data out
High-Z
tOHZ
tOLZ
tLZ
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to device
interconnection.
6
Revision 2.0
November 1997
K6T1008V2C, K6T1008U2C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS 1
tAW
CS 2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
tCW(2)
tAS(3)
tWR(4)
CS 1
tAW
CS 2
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
7
Revision 2.0
November 1997
K6T1008V2C, K6T1008U2C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1 , a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. t WR(1) applied in case a write ends as CS1 or WE going high tWR(2)
applied in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC
tSDR
Data Retention Mode
tRDR
3.0/2.7V 1)
2.2V
VDR
CS1≥VCC-0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
3.0/2.7V1)
CS 2
tSDR
tRDR
VDR
CS2≤0.2V
0.4V
GND
1. 3.0V for K6T1008V2C Family, 2.7V for K6T1008U2C Family
8
Revision 2.0
November 1997
K6T1008V2C, K6T1008U2C Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeter(inch)
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#17
14.12±0.30
0.556±0.012
#1
11.43±0.20
0.450±0.008
#16
2.74±0.20
0.108±0.008
3.00
0.118 MAX
20.87
0.822 MAX
20.47±0.20
0.806±0.008
0.20 +0.10
-0.05
0.008+0.004
-0.002
13.34
0.525
#32
0.80±0.20
0.031±0.008
0.10 MAX
0.004 MAX
(
0.71
)
0.028
+0.100
-0.050
+0.004
0.016 -0.002
0.41
1.27
0.050
0.05
MIN
0.002
9
Revision 2.0
November 1997
K6T1008V2C, K6T1008U2C Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeter(inch)
0.20
0.008
+0.10
-0.05
+0.004
-0.002
0.10
MAX
0.004
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
13.40±0.20
0.528±0.008
#1
#32
0.50
0.0197
#16
0.25
)
0.010
8.00
0.315
8.40
0.331 MAX
(
#17
1.00±0.10
0.039±0.004
0.25
TYP
0.010
11.80±0.10
0.465±0.004
0.05
0.002 MIN
+0.10
-0.05
0.006 +0.004
-0.002
0.15
1.20
0.047 MAX
0~8°
0.45~0.75
0.018~0.030
(
0.50
)
0.020
0.10
MAX
0.004
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)
0.20
0.008
+0.10
-0.05
+0.004
-0.002
13.40±0.20
0.528±0.008
#16
#17
0.50
0.0197
#1
0.25
TYP
0.010
0.25
)
0.010
8.00
0.315
8.40
0.331 MAX
(
#32
1.00±0.10
0.039±0.004
11.80±0.10
0.465±0.004
+0.10
-0.05
0.006 +0.004
-0.002
0.15
0.05
0.002 MIN
1.20
0.047 MAX
0~8°
0.45~0.75
0.018~0.030
(
10
0.50
)
0.020
Revision 2.0
November 1997
K6T1008V2C, K6T1008U2C Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeter(inch)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
+0.10
-0.05
0.008+0.004
-0.002
0.20
20.00±0.20
0.787±0.008
#1
#32
8.40
0.331 MAX
0.50
0.0197
#17
#16
0.25
0.010 TYP
0.25
)
0.010
8.00
0.315
(
1.00±0.10
0.039±0.004
1.20
0.047 MAX
18.40±0.10
0.724±0.004
+0.10
-0.05
0.006+0.004
-0.002
0.05
0.002 MIN
0~8°
0.45 ~0.75
0.018 ~0.030
(
0.10 MAX
0.004 MAX
0.15
0.50
)
0.020
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820R)
+0.10
-0.05
0.008+0.004
-0.002
0.20
20.00±0.20
0.787±0.008
#16
#17
0.50
0.0197
#1
0.25
)
0.010
8.00
0.315
8.40
0.331 MAX
(
#32
1.00±0.10
0.039±0.004
0.05
0.002 MIN
1.20
0.047 MAX
18.40±0.10
0.724±0.004
+0.10
-0.05
0.006 +0.004
-0.002
0.15
0~8°
0.45 ~0.75
0.018 ~0.030
(
11
0.10 MAX
0.004 MAX
0.25
0.010 TYP
0.50
)
0.020
Revision 2.0
November 1997
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