Agere L9312 Line interface and line access circuit forward battery slic and ringing relay for tr-57 application Datasheet

Data Sheet
July 2001
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Introduction
Description
The Agere Systems Inc. L9312 is a combination fullfeature, ultralow-power SLIC, and solid-state ringing
access relay. It is part of a pin-for-pin compatible
family of devices designed to serve a wide variety of
applications. The L9312 is optimized for TR-57
access, forward battery only, applications.
The L9312 electronic line interface and line access
circuit (LILAC) provides all the functions that are necessary to interface a codec to the tip and ring of a
subscriber loop, integrating the battery feed and ringing access relay in one low-power, low-cost package.
Features
SLIC
■
5 V and battery operation
■
Optional automatic battery switch
■
Four operational modes
■
Appropriate for 58 dB longitudinal balance applications
■
Minimal external components required at all interfaces
■
Ultralow power dissipation
■
Software/hardware adjustable dc parameters and
supervision thresholds
Solid-State Ring Relay
■
Low impulse noise
■
Current-limited switches/thermal protection
Applications
■
Pair Gain
■
Digital Loop Carrier (DLC)
■
Central Office (CO)
■
Fiber-in-the-Loop (FITL)
The L9312 requires a 5 V and battery supply to operate. Included is an automatic battery switch. The
battery feed offers forward battery and on-hook
transmission. It also has a low-power scan and a disconnect mode.
In all operating states, this IC is designed for minimal
power dissipation. This device is designed to minimize the number of external components required at
all interfaces.
The dc template, current limit, and overhead voltage
and loop supervision threshold are programmable via
an applied voltage source. The voltage source may
be an external programmable voltage source or
derived from the VREF SLIC output.
The integrated solid-state switch offers power ringing
access. Impulse noise is minimized, thus eliminating
the need for external zero-cross switching circuitry.
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Table of Contents
Contents
Page
Introduction..................................................................1
Features ....................................................................1
SLIC .......................................................................1
Solid-State Relay....................................................1
Applications...............................................................1
Description ................................................................1
Features ......................................................................4
Description...................................................................4
Architecture .................................................................7
Pin Information ............................................................8
Operating States........................................................10
Input State Coding ..................................................10
State Definitions ........................................................11
Primary Control Modes ...........................................11
Powerup, Forward Battery....................................11
Scan .....................................................................11
Ringing .................................................................11
Disconnect—Break Before Make .........................11
Reset ....................................................................11
Special States .........................................................11
Thermal Shutdown ...............................................11
Battery Out of Range ...........................................12
Absolute Maximum Ratings ......................................12
Electrical Characteristics ...........................................13
Ring Trip Detector ...................................................14
SLIC Two-Wire Port ................................................15
Analog Pin Characteristics ......................................16
ac Feed Characteristics ..........................................17
Logic Inputs and Outputs, VDD = 5.0 V ...................18
Timing Requirements ..............................................18
Switch Characteristics.............................................19
On-State Switch I-V Characteristics........................20
Test Configurations ...................................................21
Applications ...............................................................23
dc Characteristics ...................................................23
Power Control.......................................................23
Power Derating.....................................................23
Automatic Battery Switch .....................................24
2
Contents
Page
Power Control Resistor ....................................... 24
Overhead Voltage ............................................... 25
dc Loop Current Limit .......................................... 26
Loop Range......................................................... 26
Battery Feed ........................................................ 26
Longitudinal to Metallic Balance.......................... 27
Supervision ............................................................... 27
Loop Closure.......................................................... 27
Ring Trip ................................................................ 28
Switching Behavior................................................. 28
Make-Before-Break Operation ............................... 28
Break-Before-Make Operation ............................... 29
Protection ................................................................. 29
External Protection................................................. 29
Active Mode Response at PT/PR........................... 29
Ring Mode Response at PT/PR ............................. 30
Internal Tertiary Protection..................................... 31
Diode Bridge........................................................ 31
Battery Out of Range Detector: High
(Magnitude) ................................................. 31
Battery Out of Range Detector: Low
(Magnitude) ................................................. 31
ac Applications ......................................................... 32
ac Parameters........................................................ 32
Codec Types .......................................................... 32
ac Interface Network .............................................. 32
Design Tools .......................................................... 33
First-Generation Codec ac Interface Network........ 33
First-Generation Codec ac Interface
Network: Resistive Termination ............................ 34
Example 1, Real Termination .............................. 35
Third-Generation Codec ac Interface
Network: Complex Termination ............................ 38
Outline Diagram........................................................ 40
Ordering Information................................................. 40
Agere Systems Inc.
Data Sheet
July 2001
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Table of Contents (continued)
Figures
Page
Figure 1. Architecture Diagram................................... 7
Figure 2. 44-Pin PLCC ............................................... 8
Figure 3. Timing Requirements ................................ 18
Figure 4. On-State Switch I-V Characteristics .......... 20
Figure 5. Basic Test Circuit ...................................... 21
Figure 6. Metallic PSRR ........................................... 22
Figure 7. Longitudinal PSRR .................................... 22
Figure 8. Longitudinal Balance ................................. 22
Figure 9. Longitudinal Impedance ............................ 22
Figure 10. ac Gains .................................................. 22
Figure 11. L9312 Loop/Battery Current (with Battery
Switch) vs. Loop Resistance ................... 24
Figure 12. Tip/Ring Voltage ..................................... 26
Figure 13. L9312 Loop Current vs. Loop Voltage..... 27
Figure 14. ac Equivalent Circuit................................ 34
Figure 15. Agere T7504 First-Generation
Codec Resistive Termination, Single
Battery Operation .................................... 36
Figure 16. L9312 for Agere T8536 Third-Generation
Codec, Dual Battery Operation, ac and dc
Parameters, Fully Programmable............ 38
Agere Systems Inc.
Tables
Page
Table 1. Pin Descriptions ........................................... 8
Table 2. Control States ............................................. 10
Table 3. Supervision Coding..................................... 10
Table 4. Device Operating Conditions and
Powering ..................................................... 13
Table 5. Ring Trip Detector ....................................... 14
Table 6. SLIC Two-Wire Port .................................... 15
Table 7. Analog Pin Characteristics .......................... 16
Table 8. ac Feed Characteristics .............................. 17
Table 9. Logic Inputs and Outputs ............................ 18
Table 10. Timing Requirements ................................ 18
Table 11. Break Switches (SW1, 2) .......................... 19
Table 12. Ring Return Switch (SW3) ........................ 19
Table 13. Ringing Access Switch (SW4) .................. 20
Table 14. Typical Active Mode On- to Off-Hook
Tip/Ring Current-Limit Transient
Response .................................................. 26
Table 15. Break-Before-Make Logic Control
Sequence Device Switching...................... 29
Table 16. L9312 Parts List for Agere T7504
First-Generation Codec Resistive Termination, Single Battery Operation ................... 37
Table 17. L9312 Parts List for Agere T8536
Third-Generation Codec, Dual Battery
Operation, ac and dc Parameters, Fully
Programmable........................................... 39
3
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Features
Data Sheet
July 2001
■
Integrated 2 Form C ring relay:
— Low impulse noise
— Current-limited switches
— Break-before-make and make-before-break
switching
■
SLIC and solid-state ring relay integrated into a single package
■
5 V and battery operation
■
■
User-defined power control options:
— Automatic battery switch
— Power control resistor
— Package thermal capabilities
Meets Telcordia Technologies* GR1089 requirements with external protection device
■
44-pin, surface-mount plastic package (PLCC)
■
Minimal external components required
Description
■
Operating states:
— Forward active
— Scan
— All-off or disconnect
— Ring
■
Ultralow power:
— Scan, 15 mW
— Active states, on-hook, 75 mW
— Ring mode, on-hook, 90 mW
— Disconnect, 10 mW
■
Adjustable overhead voltage:
— Default overhead adequate for 3.14 dB into
900 Ω overload
— Controlled rate of overhead adjustment
The L9312 electronic line interface and line access circuit (LILAC) provides all the functions that are necessary to interface a codec to the tip and ring of a
subscriber loop, integrating the battery feed and ringing
access relay in one low-power, low-cost package. The
physical construction of the device is two chips. The
first chip is manufactured in Agere 90 V complementary bipolar integrated circuit (CBIC-S) technology. This
chip contains the SLIC functionality:
■
ac transmission path
■
dc feedback and functions
■
Active dc current limit
■
Latched parallel input data interface with reset
■
Active mode loop supervision
■
Adjustable current limiter:
— 10 mA to 45 mA programming range
■
Thermal shutdown
■
Adjustable loop closure detector with hysteresis:
— 4 mA detect, 2.5 mA no detect minimum, upper
limit of 15 mA detect
— Hysteresis, typical 20% of programmed on-hook
to off-hook threshold
■
Ring trip detector:
— Single-pole filtering
■
Thermal shutdown protection with hysteresis
■
Line break switch will foldover into a low-current
state under high-voltage fault conditions
■
Battery out-of-range monitor circuit:
— All-off upon loss of battery (low battery condition)
— All-off upon high battery (fault condition)
■
Longitudinal balance:
— TR-57 balance
■
RFI/EMC-CISP-22
The second chip is manufactured in Agere dielectrically
isolated 320 V bipolar CMOS diffused metal oxide
semiconductor (BCDMOS III) technology. This chip
contains the following:
■
Ring access relay
■
Scan clamp circuitry
■
Logic control
■
Ring trip
■
Thermal shutdown
■
Battery monitor circuit
The LILAC family requires a +5 V and battery supply to
operate. No –5 V supply is required. A battery switch is
included that automatically, based on subscriber loop
length, will apply either the primary higher-voltage battery or an optional lower-voltage auxiliary battery. Use
of this feature will minimize off-hook power dissipation.
* Telcordia Technologies is a trademark of Bell Communications
Research, Inc.
4
Agere Systems Inc.
Data Sheet
July 2001
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Description (continued)
Switching Behavior section of this data sheet for more
details on switching behavior.
The switch point is a function of the user-programmed
dc current limit and the magnitude of the auxiliary battery. Switching from the high-voltage to low-voltage
battery is quiet, without interruption of the dc loop current, thus preventing any impulse noise generation at
the switch point. Design equations for the switch point
and a graph showing loop/battery current versus loop
resistance are given in the dc Characteristics in the
Applications section of this data sheet.
Voltage transients or impulse noise associated with
ring cadence or ring trip are minimized or eliminated
with the L9312, thus possibly eliminating the need for
external zero-cross switching circuitry.
If the user does not want to provide an auxiliary battery,
the design of the L9312 battery switch allows use of a
power control resistor at the auxiliary battery input. This
scheme will not reduce short-loop, off-hook power dissipation, but it will control power dissipation on the
SLIC by sharing power among the SLIC, power resistor, and dc loop. However, in most cases, without the
auxiliary battery, the power dissipation capabilities of
the 44-pin PLCC package are adequate so that the
power control resistor will not be needed. Design equations for power control options are given in the dc Characteristics section of this data sheet.
The L9312 is a forward battery only SLIC that supports
on-hook transmission.
A low-power scan mode is available to reduce idle
mode on-hook power. This mode is realized by using a
scan clamp circuit. In low-power scan mode:
■
The scan clamp circuitry is active.
■
Loop closure is active.
■
All ac transmission, dc feed, and other supervision
circuits, including ring trip, are shut down.
■
Thermal shutdown is active.
■
Low battery sense shutdown is on.
■
On-hook transmission is disabled.
A forward disconnect mode, where all circuits are
turned off and power is denied to the loop, is also provided. During this mode, the NSTAT supervision output
will read on-hook.
In the ring mode, the line break switches are opened
and the power ring access switches are closed. In this
mode, the ring trip detector in the SLIC is active and all
other detectors and the tip/ring drive amplifiers are
turned off to conserve power.
Make-before-break or break-before-make switching is
achievable during ring cadence or ring trip. Toggling
directly into or directly out of the ring mode table will
give make-before-break switching. To achieve breakbefore-make switching, go to an intermediate all-off
state (use forward disconnect state) before entering the
ring mode or before leaving the ring mode. See the
Agere Systems Inc.
Both the ring trip and loop closure supervision functions are included. Loop closure threshold is set by
applying a voltage source to the LCTH input. The voltage source may be an external voltage source or
derived from the SLIC VREF output. A programmable
external voltage source may be used to provide software control of the loop closure threshold. Design
equations for the loop closure threshold are given in
the Supervision section of this data sheet. Hysteresis is
included.
The ring trip detector requires only a single-pole filter at
the input. This will minimize the required number of
external components. To help minimize device power
dissipation, the ring trip detector is active only during
the power ring mode.
Ring trip and loop supervision status outputs appear in
a common output pin, NSTAT. NSTAT is an unlatched
supervision output; thus, an interrupt-based control
scheme may be used.
The dc current limit is set in the active modes via an
applied voltage source. The voltage source may be an
external voltage source. The voltage may be derived
via a resistor divider network from the V REF SLIC output. A programmable external voltage source may be
used to provide software control of the loop closure
threshold. Design equations for this feature are given in
the dc Characteristics section of this data sheet. Programming range is 10 mA to 45 mA.
Overhead is programmable in the active modes via an
applied voltage source. The voltage source may be an
external voltage source or derived via a resistor divider
network from the VREF SLIC output.
A programmable external voltage source may be used
to provide software control of the overhead voltage.
The rate of change of the overhead voltage may be
controlled by use of a single external capacitor at the
CF1 node. If the rate of change is uncontrolled, there
may be audible noise associated with this transition.
Design equations for this feature are given in the dc
Characteristics section of this data sheet.
If the overhead is not programmed via a resistor, the
device develops a default overhead adequate for a
3.14 dBm overload into 900 Ω. For the default overhead, OVH is connected to ground.
5
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Description (continued)
Data control is via a parallel latched data control
scheme. Data latches are edge-level sensitive. Data is
latched in when the LATCH control input goes low.
While LATCH is low, the user cannot change the data
control inputs. The data control inputs may only be
changed when LATCH is high.
Incorporation of data latches allows for data control
information and loop supervision information to be
passed to and from the SLIC via data buses rather than
on a per-line basis, thus minimizing routing complexity
and board routing area.
A device RESET pin is included. When this pin is low,
the logic inputs are overridden and the device will be
reset into SLIC forward disconnect state and the switch
into the all-off state. NSTAT is forced to the on-hook
condition when RESET is low.
The overall device protection is achieved through a
combination of an external secondary protector, along
with an integrated thermal shutdown feature, a battery
voltage window comparator, the break switch foldback
characteristic, and the dc/dynamic current-limit
response of the break and tip return switches.
For protection against long duration fault conditions,
such as power cross and tip/ring shorts, a thermal shutdown mechanism is integrated into the device. Upon
reaching the thermal shutdown temperature, the device
will enter an all-off mode. Upon cooling, the device will
re-enter the state it was in prior to thermal shutdown.
Hysteresis is built in to prevent oscillation. During this
mode, the NSTAT supervision output overrides the
actual loop status and forces an off-hook.
The line break switches and tip return switch are
current-limited switches. The current-limit mechanism
limits current through the switch to the specified dc current limit under low frequency or dc faults (power cross
and/or tip/ring to ground short) and limits the current to
the specified dynamic current-limit response under
transient faults, such as lightning.
A foldover characteristic is incorporated into the line
break switches within their I-V curve. Under voltage
conditions higher than the normal operating range,
such as may be seen under an extreme lightning or
power cross fault condition, the line break switch will
fold over into a low-current state. This feature allows for
more relaxed specifications on the ring side protector,
thus allowing for higher-voltage ringing signals. (Tip
side protector is limited by the requirements on the tip
return switch.) This feature is part of the overall device
protection scheme.
6
Data Sheet
July 2001
This device uses a window comparator to force an alloff condition if the battery drops below, or rises above,
a specified threshold.
Upon loss of VBAT1, the L9312 will automatically enter
an all-off mode. The device will enter this mode if the
magnitude of the battery drops below a nominal 15 V
and will remain in this mode until the magnitude of the
battery rises above a typical 20 V. During this mode,
the NSTAT supervision output will override the actual
hook status and force an off-hook or logic low.
When the device is in the scan mode, because of the
design of the scan clamp circuit, common-mode current can be forced into or out of the battery supply.
Because of this, and depending upon power supply
design, the magnitude of the battery may rise above
the maximum operating condition during extended longitudinal currents or during a power cross fault condition. To prevent excess current from being forced into
or out of the battery, if the magnitude of the battery
rises typically above 75 V to 80 V, the device will enter
an all-off state. The device will remain in the all-off state
until the magnitude of the battery drops into the normal
operating range. During this mode, the NSTAT supervision output will override the actual hook status and
force an off-hook or logic low.
See the Protection section of this data sheet for more
details on device protection. Please contact your Agere
Account Representative for a recommended secondary
protection device.
Longitudinal balance is consistent with North American
TR-57 requirements.
Transmit and receive gains have been chosen to minimize the number of external components required in
the SLIC-codec ac interface, regardless of the choice
of codec.
The L9312 uses a voltage feed, current sense architecture; thus, the transmit gain is a transconductance. The
L9312 transconductance is set via a single external
resistor, and this device is designed for optimal performance with a transconductance set at 300 V/A.
The L9312 offers an option for a single-ended to differential receive gain of either 8 or 2. These options are
mask programmable at the factory and are selected by
choice of part number.
A receive gain of 8 is more appropriate when choosing
a first-generation type codec where termination impedance, hybrid balance, and overall gains are set by
external analog filters. The higher gain is typically
required for synthesization of complex termination
impedance.
Agere Systems Inc.
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Description (continued)
The RCVP/RCVN SLIC inputs are floating inputs. If
there is not feedback from RCVP/RCVN to VITR,
RCVP/RCVN may be directly coupled to the codec output. If there is feedback, RCVP/RCVN must be ac-coupled to the codec output.
A receive gain of 2 is more appropriate when choosing
a third-generation type codec. Third-generation codecs
will synthesize termination impedance, set hybrid balance, and set overall gains. To accomplish these functions, third-generation codecs typically have both
analog and digital gain filters. For optimal signal-tonoise performance, it is best to operate the codec at a
higher gain level. If the SLIC then provides a high gain,
the SLIC output may be saturated causing clipping distortion of the signal at tip and ring. To avoid this situation, with a higher-gain SLIC, external resistor dividers
are used. These external components are not necessary with the lower gain offered by the L9312.
This device is packaged in a 44-pin PLCC surfacemount package.
Architecture
VITR
LCF
LCTH
RESET NSTAT LATCH
B2 B1 B0 VPROG VDD DGND
SWITCHHOOK
+5VD
PARALLEL DATA INTERFACE
WINDOW
COMPARATOR
VREF
IN
REF
–
AAC
+
TXI
RT
FB
CURRENT LIMITER
AND
INRUSH CONTROL
ILC
RB
+
VTX
VTX
AX
(1 V/50 mA)
–
2.35 V
BANDGAP
REFERENCE
ITR
IN
ITR/325
SW1
18 Ω
VBAT
TIP/RING
CURRENT
SENSE
ITR
ac
RCVP
–
ITR
BGND
SCAN
DETECTOR
ac
INTERFACE
VBAT
BGND
ac
RCVN
dc
CF2
+
OUT AR
RFR
PR
SW2
18 Ω
BGND
+
OUT AT
RFT
PT
CF2
CF2
ILC
BGND
REF
2.35 V
VREF
TRNG
SW3
60 Ω
CONTROL
CF1
–
VBAT
OVH
VBAT
RTS
RING TRIP
DETECTOR
RT
SCAN
VBAT
BGND
RSW
SCAN
CLAMP
SW4
15 Ω
RRING
VBAT
+5VA
VCC AGND
VBAT2 /PWR
VBAT1
VBAT1
BGND
BGND
12-3523e (F)
Figure 1. Architecture Diagram
Agere Systems Inc.
7
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
VREF
LCTH
3
2
1 44 43 42 41 40
39
VITR
OVH
4
RCVP
VPROG
5
RCVN
CF2
6
VCC
CF1
AGND
Pin Information
NC
7
TXI
NC
8
38
NC
LCF
9
37
ITR
BGND
10
36
VTX
RPWR
11
35
AGND
VBAT1
12
34
NC
VBAT1
13
33
DGND
BGND
14
32
VDD
TIE B′
15
31
LATCH
TIE A′
16
30
RESET
B0
B1
B2
DGND
NSTAT
PT
TRING
PR
RSW
RRING
NC
17
29
18 19 20 21 22 23 24 25 26 27 28
RTS
NC
L9312AP
12-3522f (F)
Figure 2. 44-Pin PLCC
Table 1. Pin Descriptions
8
Pin
Symbol
Type
Name/Function
1
LCTH
I
2
3
VREF
OVH
O
I
4
VPROG
I
5
6
CF2
CF1
—
—
7,
8,
17,
18,
34
NC
—
Loop Closure Program Input. Connect a voltage source to this point to program the
loop closure threshold. Voltage source may be external and must be connected
through a resistor, or derived via a resistor divider from VREF. A programmable external voltage source may be used to provide software control of the loop closure
threshold.
SLIC Internal Reference Voltage. Output of internal 2.35 V SLIC reference voltage.
Overhead Voltage Program Input. Connect a voltage source to this point to program the overhead voltage. Voltage source may be external or derived via a resistor
divider from VREF. A programmable external voltage source may be used to provide
software control of the overhead voltage. If a resistor or voltage source is not connected, the overhead voltage will default to approximately 5.5 V (sufficient to pass
3.14 dBm in to 900 Ω). If the default overhead is desired, connect this pin to ground.
Current-Limit Program Input. Connect a voltage source to this point to program the
dc current limit. Voltage source may be external or derived via a resistor divider from
VREF. A programmable external voltage source may be used to provide software control of the loop closure threshold.
Filter Capacitor. Connect a capacitor from this node for filtering.
Filter Capacitor. Connect a capacitor from this node to OVH to control the rate of
change of the overhead voltage. If controlled overhead is not desired, leave this node
open.
No Connect. May not be used as a tie point.
Agere Systems Inc.
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
9
Symbol
LCF
10
11
BGND
RPWR
12
13
14
15
16
19
20
VBAT1
VBAT1
BGND
TIE B’
TIE A’
RTS
RSW
21
RRING
22
PR
23
PT
24
TRING
25
NSTAT
26
27
28
29
30
DGND
B2
B1
B0
RESET
31
32
33
35
36
LATCH
VDD
DGND
AGND
VTX
Type
Name/Function
— Loop Closure Filter Capacitor. PPM injection can cause false loop closure indication.
Connect a capacitor from this node to VCC to filter the loop closure detector. If loop closure filtering is not required, leave this node open.
G
Battery Ground. Ground return for the battery supply.
P
Auxiliary Battery. If a lower-voltage auxiliary battery is used, connect the auxiliary battery supply to this node. If a power control resistor is used, connect the power control
resistor from this node to VBAT1. If no power control technique is used, connect this node
to VBAT1.
P
Office Battery Supply. Negative high-voltage power supply.
P
Office Battery Supply. Negative high-voltage power supply.
G
Battery Ground. Ground return for the battery supply.
— Connect to VREF.
— Connect to VREF.
I
Ring Trip Sense. Sense input for the ring trip detector.
O
Ring Lead Ringing Access Switch. Ringing relay connects this pin to pin RRING. Connect this pin to pin PR through a 400 Ω current-limiting resistor.
I
Ringing Access. Input to solid-state ringing access switch. Connect to ringing generator.
I/O Protected Ring. The output of the ring driver amplifier and input to loop sensing connected through solid-state break switch. Connect to subscriber loop through overvoltage/current protection.
I/O Protected Tip. The output of the tip driver amplifier and input to loop sensing connected
through solid-state break switch. Connect to subscriber loop through overvoltage/current protection.
O
Tip Ringing Return. Ring relay connects this pin to PT. Connect to ringing supply
return.
O
Loop Status. The output of the loop status detector (loop start detector wired-OR with
ring trip detector). This loop status supervision output is not controlled by the data latch.
G
Digital Ground. Ground return for VDD current.
I
Data Control Input. See Table 2, Control States, for details.
I
Data Control Input. See Table 2, Control States, for details.
I
Data Control Input. See Table 2, Control States, for details.
I
Reset. A logic low will override the B[0:3] and LATCH inputs and reset the state of the
SLIC to the disconnect state and the switch to the all-off state.
I
Latch Control Input. Edge-level sensitive control for data latches.
P
5 V Digital Power Supply. 5 V supply for digital circuitry.
G
Digital Ground. Ground return for VDD current.
G
Analog Ground.
O
Tip/Ring Voltage Output. This output is a voltage that is directly proportional to the differential tip/ring current. A resistor from this node to ITR sets the device transimpedance. Gain shaping for termination impedance with a COMBO I codec is also achieved
with a network from this node to ITR.
Agere Systems Inc.
9
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
37
Symbol
ITR
Type
I
38
39
NC
TXI
—
I
40
VITR
O
41
RCVP
I
42
RCVN
I
43
44
AGND
VCC
G
P
Name/Function
Transmit Gain. A current output which is proportional to the differential current flowing from tip to ring. Input to AX amplifier. Connect a resistor from this node to VITR to
set transmit gain to 300 Ω. Gain shaping for termination impedance with a COMBO I
codec is also achieved with a network from this node to VITR.
No Connect. May not be used as a tie point.
Transmit ac Input (Noninverting). Connect a 0.1 µF capacitor from this pin to VTX
for dc blocking.
Transmit ac Output Voltage. The output is a voltage that is directly proportional to
the differential ac tip/ring current. This output is connected via a proper interface network to the codec.
Receive ac Signal Input (Noninverting). This high-impedance input controls the ac
differential voltage on tip and ring.
Receive ac Signal Input (Inverting). This high-impedance input controls the ac differential voltage on tip and ring.
Analog Ground. Ground return for VCC current.
5 V Analog Power Supply. 5 V supply for analog circuitry.
Operating States
Input State Coding
Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in
when the LATCH control input goes low. Data must be set up 200 ns before LATCH goes low and held 50 ns after
LATCH goes high. While LATCH is low, the user should not change the data control inputs at B0, B1, and B2. The
data control inputs at B0, B1, and B2 may only be changed when LATCH is high. NSTAT supervision output is not
controlled by the LATCH control input.
Table 2. Control States
B2
B1
B0
RESET
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
1
1
1
1
1
1
1
1
0
State
Scan
Powerup, forward battery
Unassigned
Unassigned
Ring
Unassigned
Unassigned
Disconnect, break before make
Disconnect, break before make
Table 3. Supervision Coding
Pin NSTAT
0 = off-hook or ring trip
1 = on-hook and no ring trip
10
Pin TRGDET
0 = ring ground
1 = no ring ground
Agere Systems Inc.
Data Sheet
July 2001
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
State Definitions
Ringing
Primary Control Modes
■
Switch break switches (SW1 and SW2) are open,
and ring access switches (SW3 and SW4) are
closed.
Powerup, Forward Battery
■
Tip/ring drive amplifiers are powered down.
■
Normal talk and battery feed state.
■
Ring trip circuit is active.
■
Pin PT is positive with respect to pin PR.
■
■
All ac transmission and dc feed circuits are powered
up.
Loop supervision and common-mode current detectors are powered down.
■
NSTAT represents the ring trip detector status.
■
On-hook transmission is enabled.
■
Thermal shutdown is active.
■
Battery window comparator sense shutdown is on.
■
■
Switch break switches (SW1 and SW2) are closed,
and ring access switches (SW3 and SW4) are open.
The tip and ring amplifiers are turned off to conserve
power.
■
Break switches (SW1 and SW2) are open, and ring
access switches (SW3 and SW4) are open. This
mode is also used as a transitional mode to achieve
break-before-make switching from the power ring to
active or scan mode.
■
All supervision circuits are powered down; NSTAT
overrides the actual loop condition and is forced high
(on-hook).
■
VBAT1 is applied to tip and ring during on-hook conditions.
■
Automatic battery switch selects VBAT1 or VBAT2 during off-hook conditions.
■
All supervision circuits except for ring trip detector
are active.
■
NSTAT represents the loop closure detector status.
Disconnect—Break Before Make
Reset
Scan
■
■
Scan clamp circuitry is active.
■
Loop closure is active.
■
All ac transmission, dc feed, and other supervision
circuits, including ring trip, are shut down.
Selection of device reset via the RESET pin will set
the device into the disconnect break-before-make
state.
Special States
■
Thermal shutdown is active.
■
Battery window comparator sense shutdown is on.
■
On-hook transmission is disabled.
■
Not controlled via truth table inputs.
■
Pin PT is positive with respect to PR, and VBAT1 is
applied to tip/ring.
■
This mode is caused by excessive heating of the
device, such as may be encountered in an extended
power cross situation.
■
Switch break switches (SW1 and SW2) are closed,
and ring access switches (SW3 and SW4) are open.
■
Upon reaching the thermal shutdown temperature,
the device will enter an all-off mode.
■
Upon cooling, the device will re-enter the state it was
in prior to thermal shutdown.
■
Hysteresis is built in to prevent oscillation. In this
mode, supervision output NSTAT is forced low
(off-hook) regardless of loop status or if the disconnect logic state is selected.
■
Thermal Shutdown
NSTAT represents the loop closure detector status.
Agere Systems Inc.
11
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
State Definitions (continued)
Special States (continued)
Battery Out of Range
■
Not controlled via truth table inputs.
■
This mode is caused by a battery out of range; that is, the battery voltage rising above or below a specified
threshold.
■
Upon reaching the specified high or low battery voltage, the device will enter an all-off mode.
■
Upon the battery returning to the specified normal operating range, the device will re-enter the state it was in
prior to the low battery shutdown.
■
Hysteresis is built in to prevent oscillation. In this mode, supervision output NSTAT is forced low (off-hook)
regardless of loop status or if the disconnect logic state is selected.
Absolute Maximum Ratings (at TA = 25 °C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
5 V dc Supplies (VCC)
High Office Battery Supply (VBAT1)
Auxiliary Office Battery Supply (VBAT2)
Ringing Voltage
Logic Input Voltage
Maximum Junction Temperature
Storage Temperature Range
Relative Humidity Range
Switch 1, 2, 3; Pole to Pole
Switch 4; Pole to Pole
Switch Input to Output
Symbol
Min
Max
Unit
—
—
—
—
—
—
—
—
—
—
—
–0.5
–75
—
—
–0.5
—
–40
5
—
—
—
7.0
0.5
VBAT1 to 0.5 V
110
VCC + 0.5 V
165
125
95
320
465
320
V
V
V
Vrms
V
°C
°C
%
V
V
V
Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when
powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the
device ratings. For example, inductance in a supply lead could resonate with the supply filter capacitor to cause a destructive overvoltage.
12
Agere Systems Inc.
Data Sheet
July 2001
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Electrical Characteristics
In general, minimum and maximum values are testing requirements. However, some parameters may not be
tested in production because they are guaranteed by design and device characterization. Typical values reflect the
design center or nominal value of the parameter; they are for information only and are not a requirement. Minimum
and maximum values apply across the entire temperature range (–40 °C to +85 °C) and entire battery range
(–36 V to –70 V). Unless otherwise specified, typical is defined as 25 °C, V CC = VDD = 5.0, VBAT1 = –48 V
VBAT2 = –25 V. Positive currents flow into the device.
Table 4. Device Operating Conditions and Powering
Parameter
Temperature Range
Humidity Range
VBAT1 Operational Range
VBAT2 Operational Range
5 V dc Supplies (VCC, VDD)
Supply Currents, Scan State
No Loop Current, VBAT = –48 V, VCC = VDD = 5 V:
IVCC
IVBAT1
Power Dissipation
Supply Currents, Forward Active
No Loop Current, with On-hook Transmission, VBAT = –48 V,
VCC = VDD = 5 V:
IVCC
IVBAT1
Power Dissipation
Supply Currents, Forward Disconnect, VBAT = –48 V, VCC = VDD = 5 V:
IVCC
IVBAT1
Power Dissipation
Supply Currents, Ring State, No Loop Current,
VBAT = –48 V, VCC = VDD = 5 V, VRING = 80 Vrms:
IVCC
IVBAT1
IRING Generator
Power Dissipation
PSRR 500 Hz—3000 Hz:
VBAT1, VBAT2
VCC
Thermal Protection Shutdown (TTSD)
Min
Typ
Max
Unit
–40
5
–36
–19
4.75
—
—
–48
–25
5.0
85
95*
–72
VBAT1
5.25
°C
%RH
V
V
V
—
—
—
2
100
15
2.5
200
22
mA
µA
mW
—
—
—
6
1.1
83
6.5
1.4
100
mA
mA
mW
—
—
—
1.2
65
9
1.85
275
22.5
mA
µA
mW
—
—
—
—
4
200
500
70
—
—
—
—
mA
µA
µA
mW
45
30
150
—
—
165
—
—
—
dB
dB
°C
* Not to exceed 26 grams of water per kilogram of dry air.
Agere Systems Inc.
13
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Electrical Characteristics (continued)
Ring Trip Detector
Table 5. Ring Trip Detector
Parameter
Min
Typ
Max
Unit
Voltage at Input that will Cause Ring Trip After Appropriate
Zero Crossings
Voltage at Input that will Cause Immediate Ring Trip
±2.5
±3
±3.5
V
±12
±15
±18
V
Ringing Source :
Frequency (f)
dc Voltage
ac Voltage
19
–39.5
60
20
—
—
28
–57
105
Hz
V
Vrms
Ring Trip (NDET = 0)2, 3:
Loop Resistance
Trip Time
NDET Valid
2000
—
—
—
—
—
—
200
80
Ω
ms
ms
1
1. The ringing source may be either of the following:
a.) The ringing source consists of the ac and dc voltages added together (battery-backed ringing); the ringing return is ground.
b.) The ringing source consists of only the ac voltage (earth-backed ringing); the ringing return is the dc voltage.
2. NDET must also indicate ring trip when the ac ringing voltage is absent (<5 Vrms) from the ringing source.
3. Pretrip ringing must not be tripped by a 10 kΩ resistor in parallel with an 8 µF capacitor applied across tip and ring.
14
Agere Systems Inc.
Data Sheet
July 2001
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Electrical Characteristics (continued)
SLIC Two-Wire Port
Table 6. SLIC Two-Wire Port
Parameter
PT and PR Drive Current = dc + Longitudinal + Signal Currents
Signal Current
Longitudinal Current Capability per Wire (longitudinal current is independent of dc loop current)
dc Active Mode Loop Current – ILIM (RLOOP = 100 Ω):
Programming Range (5 Vrms max into 200 Ω ac)
Voltage at VPROG
dc Current-limit Variation:
VPROG = 0.8 V (ILIMIT = 40 mA)
Loop Resistance Range (from PT/PR) (3.17 dBm overload into 600 Ω):
ILOOP = 20 mA at VBAT1 = –48 V
VREF
Offset at VPROG
dc Feed Resistance (includes internal SLIC dc resistance and break
switch resistance)
dV/dT Sensitivity at PT/PR
Powerup Open Loop Voltages (VBAT1 = –48 V):
Forward/Reverse Active Mode |PT – PR| – VBAT1
Voltage at OVH
Forward/Reverse Active Mode |PT – PR| – VBAT1, VOVH = 0
Common Mode
Powerup Open Loop Voltages:
Scan Mode |PT – PR| – VBAT1
Loop Closure Threshold:
Voltage at LCTH
Loop Closure Threshold Hysteresis
Longitudinal to Metallic Balance at PT/PR
(Test Method: IEEE* Std. 455):
200 Hz to 3.4 kHz
Metallic to Longitudinal (harm) Balance:
200 Hz to 4000 Hz
Min
Typ
Max
Unit
70
10
8.5
—
—
15
—
—
—
mApeak
mArms
mArms
10
0.2
—
0
45
0.9
mA
V
—
5
—
%
1900
2.23
–40
50
—
2.35
—
75
—
2.47
40
110
Ω
V
mV
Ω
—
200
—
V/µs
5.5
0
5.5
—
—
—
6.1
(VBAT1 + 1)/2
15
1.9
—
—
V
V
V
V
0
—
13.5
V
0
—
—
20
VREF
—
V
%
61
—
—
dB
40
—
—
dB
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Agere Systems Inc.
15
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Electrical Characteristics (continued)
Analog Pin Characteristics
Table 7. Analog Pin Characteristics
Parameter
TXP (input impedance)
VPROG Input Bias Current* (current flow out of pin)
LCTH Input Bias Current* (+ current flows into pin)
VTX:
Output Offset
Output Drive Current
Output Voltage Swing (±1 mA load):
Maximum
Minimum
Output Short-circuit Current
Output Load Resistance
Output Load Capacitance
VITR:
Output Offset
Output Drive Current
Output Voltage Swing (±1 mA load):
Maximum
Minimum
Output Short-circuit Current
Output Load Resistance
Output Load Capacitance
RCVN and RCVP:
Input Voltage Range (VCC = 5.0 V)
Input Bias Current
Min
Typ
Max
Unit
75
—
—
105
–50
50
—
–250
250
kΩ
nA
nA
—
±1
—
—
±40
—
mV
mA
AGND
AGND + 0.35
—
10
—
—
—
—
—
50
VCC
VCC – 0.4
±50
—
—
V
V
mA
kΩ
pF
—
±1
—
—
±100
—
mV
mA
AGND
AGND + 0.35
—
10
—
—
—
—
—
50
VCC
VCC – 0.4
±50
—
—
V
V
mA
kΩ
pF
0
—
—
—
VCC – 0.5
±1.5
V
µA
* This parameter is not tested in production. It is guaranteed by design and device characterization.
16
Agere Systems Inc.
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Electrical Characteristics (continued)
ac Feed Characteristics
Table 8. ac Feed Characteristics
Parameter
ac Termination Impedance1
Total Harmonic Distortion (200 Hz—4 kHz)2:
Off-hook
On-hook
Transmit Gain 3 f = 1004 Hz, 1020 Hz:
PT/PR Current to VITR
Receive Gain, f = 1004 Hz, 1020 Hz Open Loop:
RCVP or RCVN to PT—PR (gain = 8)
RCVP or RCVN to PT—PR (gain = 2)
ac Feed Resistance (includes internal SLIC ac resistance and
break switch resistance)
Gain vs. Frequency (transmit and receive)2 900 Ω = 2.16 µF Termination, 1004 Hz Reference:
200 Hz—300 Hz
300 Hz—3.4 kHz
3.4 kHz—20 kHz
20 kHz—266 kHz
Gain vs. Level (transmit and receive)2 0 dBV Reference:
–55 dB to +3.0 dB
Idle-channel Noise (tip/ring) 600 Ω Termination:
Psophometric
C-Message
3 kHz Flat
Idle-channel Noise (VTX) 600 Ω Termination:
Psophometric
C-Message
3 kHz Flat
Min
Typ
Max
Unit
150
600
1400
Ω
—
—
—
—
0.3
1.0
%
%
–291
–300
–309
V/A
7.76
1.94
50
8
2
75
8.24
2.06
110
—
—
Ω
–0.3
–0.05
–3.0
—
0
0
0
—
0.05
0.05
0.05
2.0
dB
dB
dB
dB
–0.05
0
0.05
dB
—
—
—
–82
8
—
–77
13
20
dBmp
dBrnC
dBrn
—
—
—
–82
8
—
–77
13
20
dBmp
dBrnC
dBrn
1. Set externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance R1 + R2 || C between
150 Ω and 1400 Ω can be synthesized.
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. VITR transconductance depends on the resistor from ITR to VTX. This gain assumes an ideal 6.34 kΩ, the recommended value. Positive current is defined as the differential current flowing from PT to PR.
Agere Systems Inc.
17
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Electrical Characteristics (continued)
Logic Inputs and Outputs, VDD = 5.0 V
Table 9. Logic Inputs and Outputs
Parameter
Symbol
Min
Typ
Max
Unit
VIL
VIH
–0.5
2.0
0.4
2.4
0.7
VDD
V
V
IIL
IIH
—
—
—
—
±50
±50
µA
µA
VOL
VOH
0
2.4
0.2
—
0.4
VCC
V
V
Symbol
Min
Typ
Max
Unit
tSU
tHL
200
50
—
—
—
—
ns
ns
Input Voltages:
Low Level
High Level
Input Current:
Low Level (VDD = 5.25 V, VI = 0.4 V)
High Level (VDD = 5.25 V, VI = 2.4 V)
Output Voltages (CMOS):
Low Level (VDD = 4.75 V, IOL = 180 µA)
High Level (VDD = 4.75 V, IOH = –20 µA)
Timing Requirements
Table 10. Timing Requirements
Parameter
Minimum Setup Time from B0, B1, B2 to LATCH
Minimum Hold Time from LATCH to B0, B1, B2
Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in
when the LATCH control input goes low. Data must be set up t SU ns before LATCH goes low and held tHL ns after
LATCH goes high. While LATCH is low, the user should not change the data control inputs at B0, B1, and B2. The
data control inputs at B0, B1, and B2, may only be changed when LATCH is high. NSTAT supervision output is not
controlled by the LATCH control input.
LATCH
tSU
tHL
B0, B1,
B2, B3
12-3526(F)
Figure 3. Timing Requirements
18
Agere Systems Inc.
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Electrical Characteristics (continued)
Switch Characteristics
Table 11. Break Switches (SW1, 2)
Parameter
Off State:
Maximum Differential Voltage
dc Leakage Current (Vsw = ±320 V)
On State (see On-State I-V Switch Characteristics section):
Resistance
Maximum Differential Voltage (VMAX)2
Foldback Voltage Breakpoint 1 (V1)
Foldback Voltage Breakpoint 2 (V2)
dc Current Limit 1 (ILIMIT1)
dc Current Limit 2 (ILIMIT2)
Dynamic Current Limit
10 x 700 µs, 1000 V Applied Surge T < 0.5 µs
dV/dT Sensitivity2, 3
Min
Typ
Max
Unit
—
—
—
—
±3201
±20
V
µA
—
—
72
V1 + 0.5
105
2
18
—
—
—
250
—
28
320
—
—
450
—
Ω
V
V
V
mA
mA
—
—
2.5
200
—
—
A
V/µs
Min
Typ
Max
Unit
—
—
—
—
±3201
±20
V
µA
—
—
—
60
—
200
100
130
—
Ω
V
mA
—
—
2.5
200
—
—
A
V/µs
1. At 25 °C, maximum voltage rating has a temperature coefficient of 0.167 V/°C.
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dT sensitivity.
Table 12. Ring Return Switch (SW3)
Parameter
Off State:
Maximum Differential Voltage
dc Leakage Current (Vsw = ±320 V)
On State (see On-State Switch I-V Characteristics section):
Resistance
Maximum Differential Voltage (VMAX)2
dc Current Limit
Dynamic Current Limit
10 x 700 µs, 1000 V Applied Surge T = 0.5 µs
dV/dT Sensitivity2, 3
1. At 25 °C, maximum voltage rating has a temperature coefficient of 0.167 V/°C.
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dT sensitivity.
Agere Systems Inc.
19
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Electrical Characteristics (continued)
Switch Characteristics (continued)
Table 13. Ringing Access Switch (SW4)
Parameter
Off State:
Maximum Differential Voltage
dc Leakage Current (Vsw = ±475 V) (pole to pole)
Isolation
On State (see On-State Switch I-V Characteristics section):
Resistance
Voltage
Steady-state Current1
Surge Current (10 x 700 µs pulse)2
Release Current
dV/dT Sensitivity2, 3
Min
Typ
Max
Unit
—
—
—
—
—
—
±475
±20
±320
V
µA
V
—
—
—
—
—
—
—
—
—
—
500
200
15
3
150
2
—
—
Ω
V
mA
A
µA
V/µs
1. Choice of secondary protector and feed resistor should ensure these ratings are not exceeded. A minimum 400 Ω feed resistor is recommended.
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. Applied voltage is 100 Vp-p square wave at 100 Hz to measure dV/dT sensitivity.
On-State Switch I-V Characteristics
ISW
ISW
ISW
CURRENT
LIMITING
+ILIMIT
ILIM1
2/3 RON
–VMAX –V2 –V 1
–ILIM2
–1.5
RON
+1.5
RON
ILIM2
VSW
+V1 +V2 +VMAX
2/3 RON
–VMAX
VSW
RON
–1.5 V
+1.5 V
–VOS
+VMAX
VSW
+VOS
–ILIM1
2/3 R ON
RON
–ILIMIT
CURRENT
LIMITING
5-5990.c(F)
A. Line Break Switch SW1, SW2
12-3291.a(F)
B. Ring Return SW3
12-3292.a(F)
C. Ring Access SW4
Figure 4. On-State Switch I-V Characteristics
20
Agere Systems Inc.
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Test Configurations
TRING
TRING
RING
RRING
RSW
RSW
RTS
RTS
RING
RLOOP
TIP
50 Ω
20 kΩ
RCVP
4.13 kΩ
(GAIN = 2)
46.4 kΩ
(GAIN = 8)
VREF
VITR
VITR
0.1 µF
TXI
VTX
6.34 kΩ
PT
VPROG
VPROG
LCTH
LCTH
VREF
VREF
ITR
L9312
BASIC
TEST
CIRCUIT
OVH
0.1 µF
VCC
20 kΩ
RCVN
PR
100 Ω/600 Ω
50 Ω
RCV
RESET
RESET
LATCH
LATCH
LCF
B2
B2
B1
B1
B0
B0
CF1
CF2
0.1 µF
PWR/
VBAT2
VBAT1 BGND
0.1 µF
VCC
A GND
0.1 µF
VDD
DGND
NSTAT
0.1 µF
0.1 µF
VBAT2 /PWR
VBAT1
VCC
VDD
NSTAT
12-3524f (F)
Figure 5. Basic Test Circuit
Agere Systems Inc.
21
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Test Configurations (continued)
100 µF
PT
VBAT OR VCC
VS
368 Ω
+
100 Ω
VS
BASIC
TEST CIRCUIT
VM
DISCONNECT
BYPASS
CAPACITOR
4.7 µF
368 Ω
–
PR
100 µF
VBAT OR
VCC
LONGITUDINAL BALANCE = 20 log
PT
+
900 Ω
VS
VM
ANSI*/IEEE STANDARD 455-1985
BASIC
TEST CIRCUIT
VT/R
12-2584 (F)
–
Figure 8. Longitudinal Balance
PR
ILONG
VS
PSRR = 20 log ---------V T/R
PT
+
12-2582 (F)
VPT
–
BASIC
TEST CIRCUIT
Figure 6. Metallic PSRR
–
ILONG
VPR
+
VBAT OR VCC
100 Ω
VS
4.7 µF
PR
DISCONNECT
BYPASS
CAPACITOR
ZLONG =
∆ VPR
∆ VPT
OR
∆ ILONG
∆ ILONG
12-2585 (F)
Figure 9. Longitudinal Impedance
VBAT OR
VCC
67.5 Ω
PT
10 µF
BASIC
TEST CIRCUIT
+
VM
–
PT
VITR
+
67.5 Ω
PR
56.3 Ω
VITR
600 Ω
10 µF
VT/R
–
BASIC
TEST CIRCUIT
PR
RCV
RCV
VS
VS
PSRR = 20 log ------VM
12-2583 (F)
Figure 7. Longitudinal PSRR
GXMT =
VITR
VT/R
GRCV =
VT/R
VRCV
12-2587.g (F)
* ANSI is a registered trademark of the American National Standards Institute, Inc.
22
Figure 10. ac Gains
Agere Systems Inc.
Data Sheet
July 2001
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Applications
Total PD = maximum battery x (maximum current limit)
(current limit accuracy) + SLIC quiescent power.
dc Characteristics
For the L9312, the worst-case SLIC on-hook active quiescent power is 100 mW. Thus,
Power Control
Under normal device operating conditions, thermal
design must ensure that the device temperature does
not rise above the thermal shutdown. Power dissipation
is highest with higher battery voltages, with higher current limit, and under shorter dc loop conditions. Higher
ambient temperature will reduce thermal margin.
Power control may be done in several ways, by use of
the integrated automatic battery switch and a lowervoltage auxiliary battery or by use of a power control
resistor with single battery operation. The thermal
capability of the 44-pin PLCC package is sufficient to
allow for single battery operation without the power
control resistor when the device is used under lowerpower operating conditions.
Power Derating
Operating temperature range, maximum current limit,
maximum battery voltage, minimum dc loop length, and
protection resistors’ values, number of PCB board layers, and airflow, will influence the overall thermal performance. The still-air thermal resistance of the 44-pin
PLCC package is typically 38 °C/W for a two-layer
board with 0 LFPM airflow.
The L9312 will enter thermal shutdown at a temperature of 150 °C. The thermal design should ensure that
the SLIC does not reach this temperature under normal
operating conditions.
For this example, assume a maximum ambient operating temperature of 85 °C, a maximum current limit of
30 mA, and a maximum battery of –56 V. Further
assume a (worst-case) minimum dc loop of 20 Ω for
wire resistance, 50 Ω protection resistors, and 200 Ω
for the handset. Include the effects of parameter tolerance in these calculations.
TTSD – TAMBIENT(max) = allowed thermal rise
150 °C – 85 °C = 65 °C
Allowed thermal rise =
package thermal impedance x SLIC power dissipation
65 °C = 38 °C/W x SLIC power dissipation
Allowed SLIC power dissipation (PD) = 1.71 W
Thus, in this example, if the total power dissipated on
the SLIC is less than 1.71 W, it will not enter thermal
shutdown. Total SLIC power is calculated:
Agere Systems Inc.
Total off-hook power = (ILOOP)(1.05) x (VBATAPPLIED) +
SLIC quiescent power
Total off-hook power = (0.030 A)(1.05) x (52) + 100 mW
Total off-hook power = 1.864 W
The power dissipated in the SLIC is the total power dissipation less the power that is dissipated in the loop.
SLIC PD = total power – loop power
Loop off-hook power = (ILOOP x 1.05)2 x (RLOOPdcmin +
2RP + RHANDSET)
Loop off-hook power = {(0.030 A)(1.05)}2 x
(20 Ω + 100 Ω + 200 Ω)
Loop off-hook power = 317.5 mW
SLIC off-hook power = total off-hook power – loop offhook power
SLIC off-hook power = 1.864 W – 0.3175 W
SLIC off-hook power = 1.5465 W < 1.71 W
Thus, under the operating conditions of this example,
the thermal capability of the 44-pin PLCC package is
adequate to ensure that the L9312 will not be driven
into thermal shutdown and no additional power control
measures are needed. If, however, for a given set of
operating conditions, the thermal capabilities of the
package are not adequate to ensure the SLIC is driven
into thermal shutdown, then one of the power control
techniques described below should be used. Additionally, even if the thermal capability of the 44-pin PLCC
package is adequate to ensure that the L9312 will not
be driven into thermal shutdown, the battery switch
technique described below can be used to reduce total
short-loop power dissipation.
Automatic Battery Switch
Use of the automatic battery switch controls power dissipation by automatically switching to the lower-voltage
auxiliary battery under short dc loop conditions, thus
reducing the short-loop power that is generated. This
has the advantage of not only controlling device temperature rise, but reducing overall power dissipation.
The switch will automatically apply the appropriate battery to support the dc loop. No logic control is needed
to control the switch. Switching is quiet, and the dc loop
current will not be interrupted when switching between
batteries. The lower-voltage auxiliary battery is connected to the VBAT2/PRW package pin.
23
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Applications (continued)
0.030
ILOOPdc
dc Characteristics (continued)
0.026
The equation governing the switch point is as follows:
0.024
V BAT2 – 3.0
RLOOP = ----------------------------------- – 2RP – Rdc
I LIM
0.022
The VBAT2 voltage must be chosen properly so that the
power dissipation is minimized. When the voltage at
pin PR equals VBAT2 + 1 V + (50 Ω x ILOOP), at least
98% of the loop current minus 2.5 mA flows into VBAT2
and 2.5 mA + 2% of the loop current plus quiescent
current flows into VBAT1.
BATTERY/LOOP CURRENT (mA)
Automatic Battery Switch (continued)
A graph showing loop and battery current versus loop
resistance with use of the battery switch is shown in
Figure 11.
IBAT2
0.020
0.018
0.016
0.014
0.012
0.010
0.008
To choose VBAT2, add:
0.006
1. Maximum tip overhead voltage (2 V for V OVH = 0).
0.004
2. Maximum loop voltage (maximum loop resistance,
protection resistance, and dc feed resistance
[100 Ω] times the maximum loop current limit).
0.002
0.000
0
200
3. 1 V for the soft switch.
Thus, for a 40 mA current limit, 640 Ω loop, 30 Ω protection resistors, and 3.17 dBm signal (VOVH = 0):
IBAT1
0.028
400
600
800
1000
RLOOP (Ω)
12-3470a (F)
VBAT2 = –(2 + 0.042 x (100 + 60 + 640) + 1) = –36.6 V
Figure 11. L9312 Loop/Battery Current (with Battery
Switch) vs. Loop Resistance
Then, for any loop resistance from 0 Ω to 640 Ω, the
worst-case VBAT1 and VBAT2 currents will be:
Power Control Resistor
IBAT1 = 1.39 mA + 2.5 mA + 0.02 x (42 mA – 2.5 mA) =
4.68 mA
IBAT2 = (0.98) x 42 mA = 38.71 mA
Total max power = 1.641 W (V BAT = –48 V)
Note that to minimize power statistically, this may not
be the best choice for VBAT2. Over a large number of
lines, power is minimized according to the statistical
distribution of loop resistance.
Device temperature rise may be controlled with use of
a single battery voltage by use of a power control resistor. This technique will reduce power dissipation on the
chip, by sharing the total power not dissipated in the
loop between the L9312 and the power control resistor.
It does not, however, reduce the total power consumed, as does use of the auxiliary battery. The power
control resistor is connected from the primary battery to
the VBAT2/PWR node of the device.
The magnitude of the power control resistor must be
low enough to ensure that sufficient power is dissipated
on the resistor to ensure the L9312 does not exceed its
thermal shutdown temperature. At the same time, the
more power that is dissipated by the power control
resistor, the higher the resistor’s power rating must be,
and thus, the more costly the resistor. The following
equations are used to optimize the choice (magnitude
and power rating) of the power control resistor.
24
Agere Systems Inc.
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Applications (continued)
Power Control Resistor (continued)
Since this device is dc unbalanced, the tip side overhead will remain typically at –2 V and the ring side overhead will vary with the voltage at VOH. For the total tip/
ring default overhead of 5.5 V, the ring overhead is typically 3.5 V.
Again assume:
Overhead Voltage
TTSD – TAMBIENT(max) = allowed thermal rise
150 °C – 85 °C = 65 °C
Overhead is programmable in the active mode via an
applied voltage source at the device’s OVH control
input. The voltage source may be an external voltage
source or derived via a resistor divider network from
the VREF SLIC output or an external voltage source. A
programmable external voltage source may be used to
provide software control of the overhead voltage.
dc Characteristics (continued)
Allowed thermal rise =
package thermal impedance x SLIC power dissipation
65 °C = 38 °C/W x SLIC power dissipation
Allowed SLIC power dissipation (PD) = 1.71 W
This time, assume a maximum ambient operating temperature of 85 °C, a maximum current limit of 45 mA
(including tolerance), and a maximum battery of –56 V.
Again, assume a (worst-case) minimum dc loop of 0 Ω
and that 50 Ω protection resistors are used. Assume
the handset is 200 Ω:
Total PD = (56 V x 45 mA) + 0.100 W
Total PD = 2.34 W + 0.100 W
Total PD = 2.4375 W
Again, the power dissipated in the SLIC is the total
power dissipation less the power that is dissipated in
the loop.
SLIC PD = total power – loop power
Loop power = (ILIM)2 x (RLOOPdcmin + 2R P + RHANDSET)
Loop power = (45 mA)2 x (0 Ω + 100 Ω + 200 Ω)
Loop power = 0.6075 W
SLIC power = 2.4375 W – 0.6075 W
SLIC power = 1.83 W > 1.5 W
Under these extreme conditions, thermal margin is
increased via an external power control resistor.
The power dissipated in the power control resistor is
calculated by:
PPRW =
V LOOP ) 2
( V BAT – V ROH –
---------------------------------------------------------------------R PWR
where in this example:
PPRW is power in the resistor
VBAT = –52 V
VLOOP = ILIM * (R LOOP + RPROT)
VROH is the ring-side overhead voltage of the SLIC.
Agere Systems Inc.
The overhead voltage (VOH) is related to the OVH voltage by:
VOH = 5.5 V + 5 x VOVH (V)
Overall accuracy is determined by the accuracy of the
voltage source and the accuracy of any external resistor divider network used and voltage offsets due to the
specified input bias current. If a resistor divider from
VREF is used, lower magnitude resistor will give a more
accurate result due to a lower offset associated with
the input bias current; however, lower value resistors
will also draw more power from VREF. The sum of programming resistors should be between 75 kΩ and
200 kΩ.
Note that a default overhead voltage of 5.5 V is
achieved by shorting input pin OVH to analog ground.
Internally, the SLIC needs typically 2 V from each supply rail to bias the amplifier circuitry. This can be
thought of as an internal saturation voltage.
The default overhead provides sufficient headroom for
on-hook transmission of a 3.14 dBm signal into 900 Ω.
2
V
3.14 = 10 log --------0.9
V = 1.36 V, which is required over and above the internal saturation voltage for signal swing.
1.36 V + 4 V = 5.36 V < 5.5 V default overhead; thus, a
3.14 dBm into 900 Ω signal is passed without clipping
distortion.
The overhead voltage accuracy achieved will not only
be affected by the accuracy of the internal SLIC circuitry, but also by the accuracy of the voltage source
and the accuracy of any external resistor divider network used.
25
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Applications (continued)
dc Characteristics (continued)
dc Loop Current Limit
In the active modes, dc current limit is programmable
via an applied voltage source at the device’s VPROG
control input. The voltage source may be an external
voltage source or derived via a resistor divider network
from the VREF SLIC output or an external voltage
source. A programmable external voltage source may
be used to provide software control of the loop current
limit. The loop current limit (ILIM) is related to the VPROG
voltage by:
Data Sheet
July 2001
The current limit with the SLIC set in an active mode
will be different from the current limit with the SLIC set
in the scan mode. This is due to differences in the scan
clamp circuit versus the active tip/ring drive amplifiers.
The scan mode current limit is fixed and is a function of
the internal design of the scan clamp circuit. The
steady-state scan mode current limit will be a typical
40 mA to 50 mA and may, over temperature and process, vary typically from 30 mA to 110 mA. The scan
clamp current limit will typically settle to its steady-state
value within 300 ms.
Loop Range
The dc loop range is calculated using:
V BAT – V OH
---------------------------------I LOOP
ILIM (mA) = 50 x VPROG (V)
RL =
Note that the overall current-limit accuracy achieved
will not only be affected by the specified accuracy of
the internal SLIC current-limit circuit (accuracy associated with the 50 term), but also by the accuracy of the
voltage source and the accuracy of any external resistor divider network used and voltage offsets due to the
specified input bias current. If a resistor divider from
VREF is used, a lower magnitude resistor will give a
more accurate result due to a lower offset associated
with the input bias current; however, lower value resistors will also draw more power from VREF. The sum of
the two resistors in the resistor divider should be
between 75 kΩ and 200 kΩ. Offset at VPROG and VREF
accuracies are specified in Table 6.
VBAT1 is used because we are calculating the maximum
loop range. The loop resistance value where the device
automatically switches to VBAT2 is calculated in the
Automatic Battery Switch section of this data sheet.
The above equation describes the active mode steadystate current-limit response. There will be a transient
response of the current-limit circuit (with the device in
the active mode) upon an on- to off-hook transition.
Typical active mode transient current-limit response is
given in Table 14.
Table 14. Typical Active Mode On- to Off-Hook Tip/
Ring Current-Limit Transient Response
Parameter
dc Loop Current:
Active Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 5 ms
dc Loop Current:
Active Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 50 ms
dc Loop Current:
Active Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 300 ms
26
Value
Unit
ILIM + 60
mA
– 2RP – Rdc
Battery Feed
The L9312 operates in a dc unbalanced mode. In the
forward active state, under open circuit (on-hook) conditions, with the default overhead chosen, the tip to ring
voltage will be a nominal 5.5 V less than the battery.
This is the overhead voltage. The tip and ring overhead
is achieved by biasing ring a nominal 3.5 V above battery and by biasing tip a nominal 2.0 V below ground.
During off-hook conditions, some dc resistance will be
applied to the subscriber loop as a function of the physical loop length, protection, and telephone handset. As
the dc resistance decreases from infinity (on-hook) to
some finite value (off-hook), the tip to ring voltage will
decrease as shown in Figure 12.
VTIP TO GND
(1/2)Rdc
BEGIN CURRENT LIMITING
ILIM + 20
(1/2)Rdc + RLIM
mA
(1/2)Rdc
VRING TO GND
ILIM
mA
VBAT
DECREASING LOOP LENGTH
12-3431a (F)
Figure 12. Tip/Ring Voltage
Agere Systems Inc.
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Applications (continued)
Refer to Figure 12 and Figure 13 in this section and to
Figure 11 in the Automatic Battery Switch section.
dc Characteristics (continued)
Starting from the on-hook condition and going through
to a short circuit, the curve passes through two regions:
Battery Feed (continued)
As illustrated in Figure 12, as loop length decreases,
the tip to ground voltage will decrease with a slope corresponding to one-half the internal dc feed resistance
of the SLIC (typical 75 Ω). The ring to ground voltage
will also decrease with a slope corresponding to onehalf the internal dc feed resistance of the SLIC, until the
SLIC reaches the current-limit region of operation. At
that point, the slope of the ring to ground voltage will
increase to the sum of one half the internal dc feed
resistance plus approximately 10 kΩ.
The dc feed characteristic can be described by:
Region 1: on-hook and low loop currents: the slope corresponds to the dc feed resistance of the SLIC (plus
any series resistance). The open-circuit voltage is the
battery voltage less the overhead voltage of the device.
Region 2: current limit: the dc current is limited to a
value determined by VPROG. This region of the dc template has a high resistance (10 kΩ).
Notice that the I-V curve is uninterrupted when the
power is shifted from the high-voltage battery to the
low-voltage battery (if auxiliary battery option is used).
This is shown in Figure 11 in the Automatic Battery
Switch section.
V BAT – V OH
ILOOP = -----------------------------------------------------R LOOP + 2R P + R dc
Longitudinal to Metallic Balance
VT/R
( V BAT – V OH ) • R LOOP
= ---------------------------------------------------------------R LOOP + 2R P + R dc
Longitudinal to metallic balance at PT/PR is specified in
the Electrical Characteristics section of this data sheet.
Where:
ILOOP = dc loop current.
VT/R = dc loop voltage.
VBAT = battery voltage magnitude.
VOH = overhead voltage.
RLOOP = loop resistance, including wire and handset
resistance.
RP = protection resistance.
Rdc = SLIC internal dc feed resistance.
50
LOOP CURRENT (mA)
1
10 kΩ
40
1
Rdc
10
0
10
15
20
25
30
35
40
Loop closure supervision threshold is programmed via
an applied voltage source or ground, through a resistor
at the LCTH input. Loop closure status is presented at
the NSTAT output. NSTAT is an unlatched output that
represents either the loop closure or ring trip status,
depending on the device state. See Table 2 for more
details. Loop closure threshold current (I LCTH) is set by:
where:
RLCTH is a resistor from the LCTH node to ground or a
voltage source.
VLCTH is ground or an external voltage source.
20
5
Loop Closure
250 ( V REF – V LC TH )
--------------------------------------------------- = ILCTH (mA)
R LCT H ( kΩ )
30
0
Supervision
45
LOOP VOLTAGE (V)
12-3050.g (F)
Notes:
VBAT1 = –48 V.
There is a built-in hysteresis associated with the loop
closure detector. The above equation describes the onhook to off-hook threshold. To help prevent false
glitches, the off-hook to on-hook threshold will be a typical 20% lower than the corresponding on-hook to offhook threshold.
VBAT2 = –24 V.
ILIM = 40 mA (R PROG = 66.5 kΩ).
Figure 13. L9312 Loop Current vs. Loop Voltage
Agere Systems Inc.
27
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Supervision (continued)
Ring Trip
Ring trip is set by the value of RS1.
The ring trip threshold at the ring trip inputs is ±2.5 V
minimum, ±3.5 V maximum.
A resistor value of 400 Ω, as shown in Figure 4, will set
the ring trip current threshold to ±7.5 mA typical.
Ring trip is asserted upon entering the ringing mode
until the second zero crossing of ringing. This is either
a positive-going zero crossing (between –40 V and
–30 V at –50 V VBAT) or a negative-going zero crossing
(between –10 V and –20 V at –50 V VBAT). The different
threshold for positive-going and negative-going zero
crossings is the result of hysteresis of approximately
20 V. The act of turning on the switch may or may not
produce a ringing zero crossing, therefore, there may
be a delay of up to almost one cycle of ringing or 50 ms
until NSTAT is high.
Ring trip will not be asserted unless the ring trip threshold is exceeded for two zero crossings. This is either a
positive-going zero crossing (between –40 V and –30 V
at –50 V VBAT) or a negative-going zero crossing
(between –10 V and –20 V at –50 V VBAT). The different
threshold for positive-going and negative-going zero
crossings is the result of hysteresis of approximately
20 V.
Note that since the ringing voltage is monitored at
RSW, one zero crossing can occur at switch turn-on
depending on initial conditions.
Ring trip is asserted immediately if the ring trip input is
15 V ± 3 V.
Switching Behavior
The solid-state ring relay in the L9312 device is able to
provide either make-before-break or break-beforemake timing with respect to switching into and out of
the ring mode. If switching is done directly into and out
of the ring mode, the design of the L9312 will give
make-before-break switching with respect to both the
ring and tip side switches. To achieve break-beforemake switching, the user should via software control
enter an intermediate all-off mode when switching into
and out of the ring mode. The all-off state should be
held a minimum of 8 ms.
Make-Before-Break Operation
The break switches are constructed from DMOS transistors. The tip side ring return is also a DMOS transis-
28
Data Sheet
July 2001
tor. Because the on resistance of the break switches is
less than the tip side ring return switch, the break
switches are physically bigger. This implies a larger
gate to source capacitance, with inherently slower
switching speeds since it will take longer to charge or
discharge the gate to source capacitance of the break
switches (to change the state of the switch). The ring
access switch is a pnpn type device. The pnpn device
has inherently faster switching speeds than any of the
DMOS type switches.
Going from the active to ring mode, the smaller tip side
ring return switch and the pnpn ring access switch will
change states before the larger break switches. Thus,
the ring contacts are made before the line break
switches are broken: make-before-break operation.
Going from the ring mode to active or scan, the natural
tendency is for the smaller tip side ring return DMOS to
break or open, before the larger DMOS can turn on.
This would not be make-before-break operation on the
tip side. Thus, circuitry is added to speed up charging
of the tip break switch, to speed up the turn on of that
switch to give make-before-break operation on the tip
side.
On the ring side, going from the ring mode to the active
or scan mode, the pnpn will not turn off until the ring
current drops below the hold current of the pnpn device
(which is typically 500 µA); this is effectively zero current for zero current turn off. This can take up to onehalf cycle of ringing to occur. With this inherent delay in
switching by the pnpn ring access switch, the break
switches will make contact before the ring access
switch breaks contact; so again, make-before-break
switching is achieved.
With the make-before-break switch, there will be a
period of time (depending on ring signal frequency but
measured in tens of microseconds) where all four
switch contacts will be on. This means that the ring
generator will be connected through the current-limited
break switches to the input of the SLIC device. Current
will be limited by the break switch current limit, and this
will not damage the SLIC. This current may, however,
cause a false glitch at the NSTAT supervision output
that will need to be digitally filtered. The board designer
should consider any ramifications of this state on the
overall system or ring generator and battery design.
The major benefit of make-before-break switching is
that it will minimize any impulse noise generated during
ringing cadence. In many cases when operating the
switch in the make-before-break mode, no special
design to switch at zero current and voltage crossing is
required. Impulse noise generation when using solidstate relays is documented in the Impulse Noise and
the L758X Series of Solid State Switches Application
Note.
Agere Systems Inc.
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Supervision (continued)
Break-Before-Make Operation
To achieve break-before-make, use the logic control
sequence device switching as shown below.
Table 15. Break-Before-Make Logic Control
Sequence Device Switching
State
Break
Switches
Ring
Switches
closed
open
open
open
open
open
closed
open
closed
open
Active/Scan
Disconnect
(all-off)
Ring
Disconnect
(all-off)
Active/Scan
Comment
—
hold
>8 ms
—
hold
>8 ms
—
The advantage of break-before-make operation is that
it eliminates the current spike when the ring access
relay changes state. The disadvantage is that it forces
an all-off state. Under inductive ringing loads, due to
Ldi/dt effects, it may cause a reduction in the impulse
noise performance compared to make-before-break
switching.
ally, the break switches have a foldback characteristic
that enables them to survive a higher on-state voltage
(320 V) than the tip ring return switch (130 V), which
does not have the foldback characteristic. (See OnState Switch I-V Characteristics section.) The ring
access switch is a pnpn type device. Additionally, the
ring side will see the full power ring voltage, and the tip
side switch will see the power ringing voltage that is
attenuated by the ringing load, subscriber loop, feed
resistor, and protection resistors. Because of these differences, the protection requirements on the tip side
are different from the protection requirements on the
ring side. Thus, it is recommended that an asymmetrical (with respect to tip and ring) overvoltage protection
scheme be used.
Please contact your Agere Account Representative for
a recommended protection device.
Additionally, a series protection resistor with a fusible
characteristic or a PTC resistor is recommended to
limit current during lightning and power cross faults. A
minimum 50 Ω is recommended in tip and ring.
The overall device protection is achieved through a
combination of the external overvoltage and overcurrent devices, along with the integrated thermal shutdown feature, the integrated window comparator,
the break switch foldback characteristic, and the
dc/dynamic current-limit response of the break and tip
return switches.
Protection
Active Mode Response at PT/PR
External Protection
An external overvoltage clamp is required to ensure
that the off-state and on-state ratings of the solid-state
break switch and solid-state ring access switch are not
exceeded. The solid-state switches in the L9312 are
constructed in a dielectrically isolated high-voltage
technology. Because of the high device-to-device isolation that is inherent in the dielectric isolation, only a tip
to ground and a ring to ground clamp is required. A tip
to ring overvoltage clamp is not needed. A foldback or
crowbar type device is recommended to minimize
power across the solid-state switches under a fault
condition.
The break switches and tip return switch are constructed from DMOS transistors. Because the on resistance of the break switches is less than the tip side ring
return switch, the break switches are physically bigger
and have a higher current handling capability. Addition-
Agere Systems Inc.
The line break switches and tip return switch are current-limited switches. The current-limit mechanism limits current through the switch to the specified dc current
limit under low frequency or dc faults (power cross
and/or tip-ring to ground short) and limits the current to
the specified dynamic current-limit response under
transient faults, such as lightning.
During a lightning fault (typical 1000 V 10 x 700 µs
applied surge), the current-limited line break switches
will pass typically 2.5 A for 0.5 µs before forcing the
break switches off. Once in the off state, the external
protection device must ensure that the off-state voltage
rating of 320 V is not exceeded. Note that the maximum differential voltage is the positive zener rating of
the protection device less the battery voltage, which
will appear on the line feed side of the switch.
29
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Protection (continued)
Active Mode Response at PT/PR (continued)
For a lower-voltage power cross, whose maximum
peak voltage is below the foldback voltage breakpoint 1
(V1), the current-limited break switch will pass the current equal to the dc current limit. The current limit has a
negative temperate coefficient, so as the device continues to pass current, the current limit will reduce with
increasing device temperature. Ultimately, the device
will reach the thermal shutdown temperature and the
thermal shutdown mechanism will force an all-off state,
which will stop current flow and begin device cooling. In
the all-off state, the external protection device ensures
that the switch off-state voltage rating is not exceeded.
Once the device cools significantly, the break switches
will turn on, and current will begin to flow again, until
temperature forces the all-off state. This will continue
until the fault condition is gone.
Sneak-under surge is a voltage surge that is just below
the clamping threshold of the secondary protection
device. For this type of surge, when the surge voltage
is below the foldback voltage breakpoint 1, operation is
as described above. When the surge voltage rises
above the foldback voltage breakpoint 1 (V1), but is still
less than the secondary protector clamping voltage, the
line break switch will crowbar into the high-impedance
region of its I-V characteristic and reduce current to the
specified ILIMIT2 value.
For surges whose magnitude range above the trigger
of the external secondary protector, the device will
operate as described above for the portion of the surge
below the secondary protector trigger voltage. When
the voltage rises above the external secondary protector’s trigger voltage, the secondary protector will crowbar on shunting fault current to ground and reducing
the tip/ring voltage seen at the device.
In the active mode, the external secondary protector
must ensure that the off-state voltage ratings of the ring
access and ring return switch are not exceeded. Normally, the ring return switch is connected to ground on
the TRING side and to the protector on the PT side;
thus, the protector on the tip side in the active mode
must clamp at less than 320 V. As will be seen in the
Ring Mode Response at PT/PR section, during the
power ringing mode, this clamp voltage on the tip side
is significantly less than 320 V.
Data Sheet
July 2001
and on the PR side, the maximum turn-on voltage of
the secondary protector. The ring access switch is of
pnpn construction. Thus, if the off-state voltage rating
of the ring access switch is exceeded, the device will
crowbar into a low-impedance state. This will cause a
surge into the ring generator and can cause the onstate current rating of the switch to be exceeded.
The difference of the battery plus peak negative ring
signal voltage less the maximum turn on of the secondary protector must not exceed the off-state voltage rating of the ring access switch. Additionally, as the
secondary protector will see the power ring signal, the
minimum turn-on rating of the secondary protector
must be high enough to not clamp the ring signal and
cause clipping distortion. The ring side will see the fullpower ring voltage, and the tip side switch will see the
power ringing voltage that is attenuated by the ringing
load, subscriber loop, feed resistor, and protection
resistors; thus, the ring side secondary protector
requires a higher clamping voltage than the tip side.
Ring Mode Response at PT/PR
In this mode, the line break switches are off and the
ring access and ring return switch is on. The secondary
protectors must ensure that the minimum off-state voltage rating of the line break switches is not exceeded.
Note that the maximum differential voltage is the positive zener rating of the protection device less the battery voltage which will appear on the line feed side of
the switch.
The ring access switch is a pnpn type switch. This
switch has no internal current limiting. Thus, through
external current limit, the user must ensure that the
surge ratings (both dynamic and dc for lightning and
power cross faults) are not exceeded. A minimum
400 Ω ring feed resistor is recommended. This resistor
also will set the ring trip threshold. See the Ring Trip
section within the Supervision section of this data sheet.
During a lightning fault (typical 1000 V 10 x 700 µs
applied surge), the current-limited tip return switch will
pass, typically 2.5 A for 0.5 µs before forcing the switch
off. Once in the off state, the external protection device
must ensure that the off-state voltage rating of 320 V is
not exceeded.
Normally, the ring access switch is connected to the
ring generator on the RRING side and to the protector
on the PR side; thus, on one side of the switch there is
the battery voltage and the peak negative ring signal,
30
Agere Systems Inc.
Data Sheet
July 2001
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Protection (continued)
Ring Mode Response at PT/PR (continued)
For power cross for lower-voltage faults, the ring return
switch will behave like the line break switches. However, tip return switch does not have the foldback
clamping feature that is included in the line break
switches; thus, in the on state, the voltage seen by the
ring return switch before damage is less than the line
break switches. The on-state voltage of the line break
switches can go up to the off-state voltage rating. The
ring return voltage should see less than 130 V in the on
state. Thus, the secondary protector on the ring side
should have a maximum crowbar voltage of 130 V.
With typical protection device tolerance, this implies a
minimum clamping voltage of 100 V. The users should
ensure, based on minimum loop length, ringing load,
and peak ring signal voltage, that the ring signal is not
distorted by the (lower) voltage rating of the tip-side
protector.
Internal Tertiary Protection
The external secondary protector and switch current
limit protect the 320 V high-voltage switches from lightning and power cross conditions. Integrated into the
LILAC IC is an internal tertiary protection scheme that
is meant to protect the 90 V SLIC portion of the device
from residue fault current and voltages that may be
passed through the switches to the actual SLIC inputs.
This scheme includes an internal diode bridge voltage
clamp and a battery out of range detector that forces
an all-off condition if the battery voltage falls high or low
out of the specified operating range.
Diode Bridge
High common-mode currents, as may be seen under a
fault condition, will be sensed and reduced to zero by
the battery monitor circuit (see Battery Out of Range
Detector: High [Magnitude] section). However, this
detector will not prevent longitudinal current from flowing into battery. The battery supply must have the ability to sink longitudinal currents as specified in the
longitudinal current capability requirement in Table 6.
Battery Out of Range Detector: High (Magnitude)
This feature is useful in remote power applications
where a dc-dc converter with limited ability to sink current is used as the primary battery supply. Under a fault
condition, the diode bridge will want to sink current into
the battery. As a function of the dc-dc converter input
capacitance and design, this current may cause the
magnitude of supply voltage to rise and ultimately
cause damage to the supply. To prevent damage to the
supply, the LILAC device will monitor the battery supply
voltage. If the magnitude of the battery rises above the
maximum specified operating battery, the battery out of
range detector will force the line break switches and
ring access switches into an all-off state, and will also
force the SLIC into the disconnect state. This will stop
the current flow into the battery, preventing damage to
the battery fault conditions. NSTAT is forced low during
this mode of operation.
Battery Out of Range Detector: Low (Magnitude)
The LILAC device will monitor the battery supply voltage. If the magnitude of the battery drops below the
minimum specified operating battery, the battery out of
range detector will force the line break switches and
ring access switches into an all-off state, and will also
force the SLIC into the disconnect state. NSTAT is
forced low during this mode of operation.
The internal inputs of the actual SLIC chip are clamped
to ground and to VBAT1 by an integrated diode bridge.
Residual positive fault currents are clamped to ground
and residual negative fault currents are clamped to battery. This implies that the battery have some current
sinking capability.
Agere Systems Inc.
31
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
ac Applications
ac Parameters
There are four key ac design parameters. Termination
impedance is the impedance looking into the 2-wire
port of the line card. It is set to match the impedance of
the telephone loop in order to minimize echo return to
the telephone set. Transmit gain is measured from the
2-wire port to the PCM highway, while receive gain is
done from the PCM highway to the transmit port.
Transmit and receive gains may be specified in terms
of an actual gain, or in terms of a transmission level
point (TLP), that is, the actual ac transmission level in
dBm. Finally, the hybrid balance network cancels the
unwanted amount of the receive signal that appears at
the transmit port.
Codec Types
At this point in the design, the codec needs to be
selected. The interface network between the SLIC and
codec can then be designed. Below is a brief codec
feature summary.
First-Generation Codecs. These perform the basic
filtering, A/D (transmit), D/A (receive), and µ-law/A-law
companding. They all have an op amp in front of the
A/D converter for transmit gain setting and hybrid balance (cancellation at the summing node). Depending
on the type, some have differential analog input stages,
differential analog output stages, +5 V only or ±5 V
operation, and µ-law/A-law selectability. These are
available in single and quad designs. This type of
codec requires continuous time analog filtering via
external resistor/capacitor networks to set the ac
design parameters. An example of this type of codec is
the Agere T7504 quad 5 V only codec.
Data Sheet
July 2001
Third-Generation Codecs. This class of devices
includes all ac parameters set digitally under microprocessor control. Depending on the device, it may or may
not have data control latches. Additional functionality
sometimes offered includes tone plant generation and
reception, PPM generation, test algorithms, and echo
cancellation. Again, this type of codec may be +5 V
only or ±5 V operation, single quad or 16-channel, and
µ-law/A-law or 16-bit linear coding selectable. Examples of this type of codec are the Agere T8536/7 (5 V
only, quad, standard features), T8533/4 (5 V only, quad
with echo cancellation), and the T8531/36 (5 V only,
16-channel with self-test).
ac Interface Network
The ac interface network between the L9312 and the
codec will vary depending on the codec selected. With
a first-generation codec, the interface between the
L9312 and codec actually sets the ac parameters. With
a third-generation codec, all ac parameters are set digitally, internal to the codec; thus, the interface between
the L9312 and this type of codec is designed to avoid
overload at the codec input in the transmit direction,
and to optimize signal to noise ratio (S/N) in the receive
direction.
Because the design requirements are very different
with a first- or third-generation codec, the L9312 is
offered with two different receive gains. Each receive
gain was chosen to optimize, in terms of external components required, the ac interface between the L9312
and codec.
This type of codec tends to be the most economical in
terms of piece part price, but tends to require more
external components than a third-generation codec.
Further ac parameters are fixed by the external R/C
network so software control of ac parameters is difficult.
32
Agere Systems Inc.
Data Sheet
July 2001
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
ac Applications (continued)
ac Interface Network (continued)
With a first-generation codec, the termination impedance is set by providing gain shaping through a feedback network from the SLIC VITR output to the SLIC
RCVN/RCVP inputs. The L9312 provides a transconductance from T/R to VITR in the transmit direction and
a single ended to differential gain in the receive direction, from either RCVN or RCVP to T/R. Assuming a
short from VITR to RCVN or RCVP, the maximum
impedance that is seen looking into the SLIC is the
product of the SLIC transconductance times the SLIC
receive gain, plus the protection resistors. The various
specified termination impedance can range over the
voiceband as low as 300 Ω up to over 1000 Ω. Thus, if
the SLIC gains are too low, it will be impossible to synthesize the higher termination impedances. Further, the
termination that is achieved will be far less than what is
calculated by assuming a short for SLIC output to SLIC
input. In the receive direction, in order to control echo,
the gain is typically a loss, which requires a loss network at the SLIC RCVN/RCVP inputs, which will
reduce the amount of gain that is available for termination impedance. For this reason, a high-gain SLIC is
required with a first-generation codec.
Thus, it appears the solution is to have a SLIC with a
low gain, especially in the receive direction. This will
allow the codec to operate near its maximum output
signal (to optimize S/N), without an external resistor
divider (to minimize cost).
Note also that some third-generation codecs require
the designer to provide an inherent resistive termination via external networks. The codec will then provide
gain shaping, as a function of frequency, to meet the
return loss requirements. Further stability issues may
add external components or excessive ground plane
requirements to the design.
To meet the unique requirements of both types of
codecs, the L9312 offers two receive gain choices.
These receive gains are mask programmable at the
factory and are offered as two different code variations.
For interface with a first-generation codec, the L9312 is
offered with a receive gain of 8. For interface with a
third-generation codec, the L9312 is offered with a
receive gain of 2. In either case, the transconductance
in the transmit direction, or the transmit gain, is 300 Ω.
This selection of receive gain gives the designer the
flexibility to maximize performance and minimize external components, regardless of the type of codec chosen.
With a third-generation codec, the line card designer
has different concerns. To design the ac interface, the
designer must first decide upon all termination impedance, hybrid balances, and TLP requirements that the
line card must meet. In the transmit direction, the only
concern is that the SLIC does not provide a signal that
is too large and overloads the codec input. Thus, for
the highest TLP that is being designed to, given the
SLIC gain, the designer, as a function of voiceband frequency, must ensure the codec is not overloaded. With
a given TLP and a given SLIC gain, if the signal will
cause a codec overload, the designer must insert some
sort of loss, typically a resistor divider, between the
SLIC output and codec input.
The following examples illustrate the design techniques/equations followed to design the ac interface
with a first- or third-generation codec for both a resistive and complex design. To aid the line circuit design,
Agere has available Windows*-based spreadsheets to
do the individual component calculations. Further,
Agere has available PSPICE † models for circuit simulation and verification. Consult your Agere Account Representative to obtain these design tools.
In the receive direction, the issue is to optimize the
S/N. Again, the designer must consider all the considered TLPs. The idea, for all desired TLPs, is to run the
codec at or as close as possible to its maximum output
signal, to optimize the S/N. Remember, noise floor is
constant, so the larger the signal from the codec, the
better the S/N. The problem is if the codec is feeding a
high-gain SLIC, either an external resistor divider is
needed to knock the gain down to meet the TLP
requirements, or the codec is not operated near maximum signal levels, thus compromising the S/N.
Termination impedance may be specified as purely
resistive or complex, that is, some combination of
resistors and capacitors that causes the impedance to
vary with frequency. The design for a pure resistive termination, such as 600 Ω, does not vary with frequency,
so it is somewhat more straightforward than a complex
termination design. For this reason, the case of a resistive design and complex design will be shown separately.
Design Tools
First-Generation Codec ac Interface Network
* Windows is a registered trademark of Microsoft Corporation.
† PSPICE is a registered trademark of MicroSim Corporation.
Agere Systems Inc.
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L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
ac Applications (continued)
Data Sheet
July 2001
Also, this example illustrates the device with a single
battery operation, fixed current limit, and fixed loop closure threshold. This is a lower feature application
example.
First-Generation Codec ac Interface Network: Resistive Termination
The following reference circuit shows the complete
SLIC schematic for interface to the Agere T7504 firstgeneration codec for a resistive termination impedance. For this example, the ac interface was designed
for a 600 Ω resistive termination and hybrid balance
with transmit gain and receive gain set to 0 dBm.
Resistor RGN is optional. It compensates for any mismatch of input bias voltage at the RCVN/RCVP inputs.
If it is not used, there may be a slight offset at tip and
ring due to mismatch of input bias voltage at the
RCVN/RCVP inputs. It is very common to simply tie
RCVN directly to ground in this particular mode of operation. If used, to calculate RGN, the impedance from
RCVN to ac ground should equal the impedance from
RCVP to ac ground.
RX
VGSX
–0.300 V/mA
RT6
VITR
ZT/R
RP TIP
BREAK
SWITCH
18 Ω
–
20 Ω
AV = 1
VS
ZT
IT/R
+
VT/R
–
RP
BREAK
SWITCH
AV = 4
+
CURRENT
SENSE
18 Ω
RT3
RHB1
V REF
RRCV
VFXIP
+
2.4 V
VFR
RCVP
RGP
AV = –1
RING
RCVN
VFXIN –
VREF
20 Ω
L9312
1/4 T7504 CODEC
12-3580 (F)
Figure 14. ac Equivalent Circuit
34
Agere Systems Inc.
Data Sheet
July 2001
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
ac Applications (continued)
First-Generation Codec ac Interface Network: Resistive Termination (continued)
Example 1, Real Termination
The following design equations refer to the circuit in Figure 14. Use these to synthesize real termination impedance.
Termination Impedance:
V T/R
ZT = -----------– I T/R
2400
Z T = 76 Ω
+ 2 R P + ----------------------------------RT3
R T3
1 + --------- + -----------RGP
RRCV
Receive Gain:
V T/R
g rcv = -----------V FR
g rcv =
8
-----------------------------------------------------------------ZT 
RCV
R R C V 
1 + R
 ----------- + ------------  1 + ---------
RT3
RGP
Z T/R
Transmit Gain:
gtx =
gtx =
V GSX
----------V T/R
– R X × -------300
--------RT6
Z T/R
Hybrid Balance:
RX
hbal = 20 log  --------------- – g t x × g rcv
R H B1
V GSX
hbal = 20 log  ---------------
V FR
To optimize the hybrid balance, the sum of the currents at the VFX input of the codec op amp should be set to 0.
The expression for ZHB becomes:
R H B ( kΩ ) =
Agere Systems Inc.
RX
-----------------g t x × g rcv
35
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
ac Applications (continued)
First-Generation Codec ac Interface Network: Resistive Termination (continued)
Example 1, Real Termination (continued)
VCC
VBAT1
CVBAT1
0.1 µF
VBAT2 /
PWR
VDD
CCC
0.1 µF
VBAT1 BGND
AGND
VCC
CDD
0.1 µF
A
VDD
D
DGND
TRING
VBAT
ITR
RRING
RINGING
SOURCE R G1
FUSIBLE
OR PTC
VTX
400 Ω CRTI
RRTF 0.1 µF
RSW
RGX
6.34 kΩ
CTX
0.15 µF
TXI
RX
100 kΩ
RTS
1 MΩ
RT6
49.9 kΩ
PR
50 Ω
VITR
180 V—330 V
SECONDARY
PROTECTOR
L9312
RCVP
100 V—130 V
SECONDARY
PROTECTOR
RLCTH
59 kΩ
VFXIN
RHB1
100 kΩ
PCM
HIGHWAY
+2.4 V
VFRO
CC2
0.1 µF
DX
+
DR
FSE
FSEP
MCLK
SYNC
AND
CLOCK
ASEL
CONTROL
INPUTS
PT
VREF
RCVN
LCTH (10 mA)
RGN
28.3 kΩ
OVH (5.5 VOH)
RVPROG
23.2 kΩ
LCF
VPROG (ILIMIT = 25 mA)
RVREF
86.7 kΩ
RRCV
100 kΩ
RGP
43.2 kΩ
50 Ω
FUSIBLE
OR PTC
–
RT3
140 kΩ
(GAIN OF 8)
GSX
CC1
0.33 µF
1/4 T7504
CODEC
VREF
VREF
CF2 CF1 B2
CF2
0.015 µF
B1
B0
MULTIPLEXED
DATA BUS
TO/FROM
MICROPROCESSOR
NSTAT
RESET
LATCH
PER-LINE
TO/FROM
MICROPROCESSOR
12-3521h (F)
Notes:
Termination impedance = 600 Ω.
Hybrid balance = 600 Ω.
Tx = 0 dBm.
Rx = 0 dBm.
Figure 15. Agere T7504 First-Generation Codec Resistive Termination, Single Battery Operation
36
Agere Systems Inc.
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
ac Applications (continued)
First-Generation Codec ac Interface Network: Resistive Termination (continued)
Example 1, Real Termination (continued)
Table 16. L9312 Parts List for Agere T7504 First-Generation Codec Resistive Termination, Single Battery
Operation
Name
Value
Tolerance
Rating
Fault Protection
50 Ω
RPR
1%
50 Ω
1%
—
—
Fusible
or PTC
Fusible
or PTC
—
—
20%
20%
20%
20%
100 V
10 V
10 V
100 V
1%
1%
1/16 W With RVREF fix dc current limit.
1/16 W With RVPROG fix dc current limit.
RPT
Function
Protection resistor.
Protection resistor.
Protector*
180 V to 320 V
Protector*
100 V to 130 V
Power Supply
CBAT1
0.1 µF
CCC
0.1 µF
CDD
0.1 µF
CF2
0.015 µF
dc Profile
RVPROG
23.2 kΩ
RVREF
86.7 kΩ
Supervision
CRTF
0.1 µF
RRTF
1 MΩ
RRS1
400 Ω
RLCTH
59 kΩ
ac Interface
RGX
6.34 kΩ
CTX
0.15 µF
CC1
0.33 µF
CC2
0.1 µF
RT3
140 kΩ
Ring-side secondary protector.
Tip-side secondary protector.
20%
1%
5%
1%
100 V
1/16 W
2W
1/16 W
Ring trip filter capacitor.
Ring trip filter resistor.
Sets ring trip threshold.
With RVREF, fix loop supervision threshold.
1%
20%
20%
20%
1%
1/16 W
10 V
10 V
10 V
1/16 W
RT6
RX
RHB
RRCV
49.9 kΩ
100 kΩ
100 kΩ
100 kΩ
1%
1%
1%
1%
1/16 W
1/16 W
1/16 W
1/16 W
RGP
43.2 kΩ
1%
1/16 W
RGN
Optional
28.3 kΩ
1%
1/16 W
Sets T/R to VITR transconductance.
ac/dc separation.
dc blocking capacitor.
dc blocking capacitor.
With RGP and RRCV, sets termination impedance and
receive gain.
With RX, sets transmit gain.
With RT6, sets transmit gain.
With RX, sets hybrid balance.
With RGP and RT3, sets termination impedance and
receive gain.
With RRCV and RT3, sets termination impedance and
receive gain.
Optional. Compensates for input offset at RCVN/RCVP.
Filter capacitor.
Filter capacitor.
Filter capacitor.
Filter capacitor.
* See your Agere Account Representative for a recommended secondary protection device.
Agere Systems Inc.
37
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
ac Applications (continued)
Third-Generation Codec ac Interface Network: Complex Termination
The following reference circuit shows the complete SLIC schematic for interface to the Agere T8536 third-generation. All ac parameters are programmed by the T8536. Note that this codec differentiates itself in that no external
components are required in the ac interface to provide a dc termination impedance or for stability. Also, this example illustrates the device using the battery switch with multiple battery operation, programmable current limit, and
programmable loop closure threshold. Please see the T8535/6 data sheet for information on coefficient programming.
VBAT2
CVBAT2
0.1 µF
VBAT2 /
PWR
VCC
VBAT1
CVBAT1
0.1 µF
VDD
CCC
0.1 µF
VBAT1 BGND
VCC
A
AGND
CDD
0.1 µF
VDD
D
DGND
TRING
ITR
VBAT
RGX
6.34 kΩ
RRING
RINGING
SOURCE
RS1
FUSIBLE
OR PTC
400 Ω CRTS
RRTF 0.1 µF
VTX
CTX
0.15 µF
TXI
RSW
CC1
0.33 µF
RTS
1 MΩ
50 Ω
PR
180 V—330 V
SECONDARY
PROTECTOR
VITR
VFXIN
RCVP
RCVN
VFROP
VFRON
NSTAT
RESET
100 V—130 V
SECONDARY
PROTECTOR
LATCH
B2
50 Ω
B1
PT
FROM
PROGRAMMABLE
VOLTAGE
SOURCE
B0
OVH
DR0
DX1
DR1
PCM
HIGHWAY
SLIC0a
SLIC1a
SLIC5a
FS
BCLK
SLIC4a
SLIC3a
SYNC
AND
CLOCK
DGND
CVDD
0.1 µF
SLIC2a
VDD
VPROG (ILIMIT = 25 mA)
LCTH (THRESHOLD = 11 mA)
DX0
T8536
L9312
(GAIN OF 2)
FUSIBLE
OR PTC
RCIN
20 MΩ
VDD
LCF
VREF
CF2
CF1
CF2
0.015 µF
12-3527i (F)
Figure 16. L9312 for Agere T8536 Third-Generation Codec, Dual Battery Operation, ac and dc Parameters,
Fully Programmable
38
Agere Systems Inc.
Data Sheet
July 2001
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
ac Applications (continued)
Third-Generation Codec ac Interface Network: Complex Termination (continued)
Table 17. L9312 Parts List for Agere T8536 Third-Generation Codec, Dual Battery Operation, ac and dc
Parameters, Fully Programmable
Name
Value
Tolerance
Fault Protection
RPR
50 Ω
1%
RPT
50 Ω
1%
180 V to 320 V
100 V to 130 V
—
—
1N4004
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.015 µF
—
20%
20%
20%
20%
20%
—
100 V
50 V
10 V
10 V
100 V
Reverse battery current.
Filter capacitor.
Filter capacitor.
Filter capacitor.
Filter capacitor.
Filter capacitor.
0.1 µF
1 MΩ
400 Ω
20%
1%
5%
100 V
1/16 W
2W
Ring trip filter capacitor.
Ring trip filter resistor.
Sets ring trip threshold.
6.34 kΩ
20 MΩ
0.15 µF
0.33 µF
1%
5%
20%
20%
1/16 W
1/16 W
10 V
10 V
Sets T/R to VITR transconductance.
dc bias.
ac/dc separation.
dc blocking capacitor.
Protector*
Protector*
Power Supply
Diode
CBAT1
CBAT2
CCC
CDD
CF2
Supervision
CRTF
RRTF
RRS1
ac Interface
RGX
RCIN
CTX
CC1
Rating
Function
Fusible or Protection resistor.
PTC
Fusible or Protection resistor.
PTC
—
Ring-side secondary protector.
—
Tip-side secondary protector.
* See your Agere Account Representative for a recommended secondary protection device.
Agere Systems Inc.
39
L9312 Line Interface and Line Access Circuit
Forward Battery SLIC and Ringing Relay for TR-57 Applications
Data Sheet
July 2001
Outline Diagram
17.65 MAX
16.66 MAX
PIN #1 IDENTIFIER
ZONE
6
1
40
39
7
16.66
MAX
17.65
MAX
29
17
18
28
4.57
MAX
1.27 TYP
0.53
MAX
0.51 MIN
TYP
SEATING PLANE
0.10
5-2506F
Ordering Information
Device Part Number
LUCL9312AP-D
LUCL9312AP-DT
LUCL9312GP-D
LUCL9312GP-DT
Package
44-Pin PLCC, Dry-bagged
44-Pin PLCC, Dry-bagged, Tape and Reel
44-Pin PLCC, Dry-bagged
44-Pin PLCC, Dry-bagged, Tape and Reel
Comcode
108698127
108698135
108698200
108698218
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
http://www.agere.com
E-MAIL:
[email protected]
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA:
Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC
Tel. (86) 21 50471212, FAX (86) 21 50472266
JAPAN:
Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE:
Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
July 2001
DS01-192ALC (Replaces DS01-170ALC)