Sanyo LC35256FT-70U 256k (32768 words x 8 bits) sram control pins: oe and ce Datasheet

Ordering number : ENN*6302
CMOS IC
LC35256FM, FT-55U/70U
256K (32768 words × 8 bits) SRAM
Control Pins: OE and CE
Preliminary
Overview
Package Dimensions
The LC35256FM and LC35256FT are asynchronous
silicon-gate CMOS SRAMs with a 32K-word by 8-bit
structure. These are full-CMOS devices with 6 transistors
per memory cell, and feature low-voltage operation, a low
operating current drain, and an ultralow standby current.
Control inputs include OE for fast memory access and CE
(chip enable) for power saving and device selection. This
makes these devices optimal for systems that require low
power or battery backup, and makes memory expansion
easy. The ultralow standby current allows these devices to
be used with capacitor backup as well.
unit: mm
3187A-SOP28D
[LC35256FM]
1
14
0.15
11.8
15
1.0
9.8
8.4
28
18.0
0.4
1.27
SANYO: SOP28D
unit: mm
3221-TSOP28 (Type I)
[LC35256FT]
21
8
0.5
13.4
11.8
• Supply voltage range: 4.5 to 5.5 V
• Access time at 5 V operation:
LC35256FM, FT-55U: 55 ns (maximum)
LC35256FM, FT-70U: 70 ns (maximum)
• Standby current: 3.0 µA (Ta ≤ 70°C)
5.0 µA (Ta ≤ 85°C)
• Operating temperature: –40 to +85°C
• Data retention voltage: 2.0 to 5.5 V
• All I/O levels: TTL compatible
• Input/output shared function pins, 3-state output pins
• No clock required
• Package
28-pin SOP (450 mil) plastic package: LC35256FM
28-pin TSOP (8 × 13.4 mm) plastic package: LC35256FT
0.1
2.3
Features
7
0.2
1.27max
28 1
0.55
8.1
0.125
0.08
22
SANYO: TSOP28 (Type I)
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
52600RM (OT) No. 6302-1/7
LC35256FM, FT-55U/70U
Pin Assignment (Top view)
SOP28D
TSOP28
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
LC35256FT
A14 1
28 VCC
A12 2
27 WE
A7 3
26 A13
A6 4
25 A8
A5 5
24 A9
A4 6
23 A11
A3 7
22 OE
A2 8
21 A10
A1 9
20 CE
A0 10
19 I/O8
I/O1 11
18 I/O7
I/O2 12
17 I/O6
I/O3 13
16 I/O5
GND 14
15 I/O4
LC35256FM
Block Diagram
A6
A9
A10
A11
A12
Row decoder
A8
Address buffer
A7
VCC
Memory cell array
512 × 512
GND
A13
I/O8
Input data
control circuit
I/O1
Input data buffer
A14
Column I/O
circuit
Output
data
buffer
Column decoder
Address buffer
A0 A1 A2 A3 A4 A5
CE
WE
OE
No. 6302-2/7
LC35256FM, FT-55U/70U
Pin Functions
A0 to A14
Address input
WE
Read/write control input
OE
Output enable input
CE
Chip enable input
I/O1 to I/O8
Data I/O
VCC, GND
Power supply, ground
Function Table
CE
OE
WE
I/O
Read cycle
Mode
L
L
H
Data output
Supply current
ICCA
Write cycle
L
X
L
Data input
ICCA
Output disable
L
H
H
High impedance
ICCA
Unselected
H
X
X
High impedance
ICCS
Specifications
Absolute Maximum Ratings
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
VCC max
Unit
7.0
V
V
Input pin voltage
VIN
–0.3* to VCC + 0.3
I/O pin voltage
VI/O
–0.3 to VCC + 0.3
V
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Note: * The minimum value is –3.0 V for pulse widths under 30 ns.
I/O Capacitances at Ta = 25°C, f = 1 MHz
Parameter
I/O pin capacitance
Input pin capacitance
Symbol
Conditions
Ratings
min
typ
Unit
max
CI/O
VI/O = 0 V
6
10
pF
CI
VIN = 0 V
6
10
pF
Note: All units are not tested; only samples are tested.
DC Allowable Operating Ranges at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V
Parameter
Supply voltage
Input voltage
Symbol
Conditions
Ratings
min
typ
Unit
max
VCC
4.5
5.5
V
VIH
2.2
VCC + 0.3
V
VIL
–0.3*
+0.8
V
5.0
Note: * The minimum value is –3.0 V for pulse widths under 30 ns.
No. 6302-3/7
LC35256FM, FT-55U/70U
DC Electrical Characteristics at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V
Parameter
Symbol
Input leakage current
Ratings
Conditions
min
typ*
Unit
max
ILI
VIN = 0 to VCC
–1.0
+1.0
µA
Output leakage current
ILO
VCE = VIH or VOE = VIH or VWE = VIL,
VI/O = 0 to VCC
–1.0
+1.0
µA
Output high-level voltage
VOH
IOH = –1.0 mA
Output low-level voltage
VOL
IOL = 2.0 mA
0.4
V
5.0
mA
ICCA2
Operating current drain
TTL inputs
ICCA3
2.4
VCE = VIL, II/O = 0 mA, VIN = VIH or VIL
VCE = VIL, VIN = VIH Min. LC35256FM, FT-55U
cycle LC35256FM, FT-70U
or VIL, II/O = 0 mA,
Duty 100 %
1 µs cycle
40
Ta ≤ 25°C
Standby mode
VCC – 0.2 V/
0.2 V inputs
ICCS1
TTL inputs
ICCS2
current drain
V
VCE ≥ VCC – 0.2 V,
VIN = 0 to VCC
45
35
40
3.5
6.0
mA
0.05
Ta ≤ 60°C
1.5
Ta ≤ 70°C
3.0
Ta ≤ 85°C
µA
5.0
VCE = VIH, VIN = 0 to VCC
1.0
mA
Note: * Reference values when VCC = 5 V and Ta = 25°C.
AC Electrical Characteristics at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V
AC test conditions
Input pulse voltage levels: VIH = 2.4 V, VIL = 0.6 V
Input rise and fall times: 5 ns
Input and output timing levels: 1.5 V
Output load: 30 pF + 1 TTL gate (including the jig capacitance)
Read Cycle
LC35256FM, FT
Parameter
Symbol
-55U
min
-70U
max
min
55
Unit
max
70
ns
Read cycle time
tRC
Address access time
tAA
55
70
ns
CE access time
tCA
55
70
ns
OE access time
tOA
30
35
ns
Output hold time
tOH
10
10
ns
CE output enable time
tCOE
5
10
ns
OE output enable time
tOOE
5
CE output disable time
tCOD
20
30
ns
OE output disable time
tOOD
20
25
ns
5
ns
Write Cycle
LC35256FM, FT
Parameter
Symbol
-55U
min
-70U
max
min
Unit
max
Write cycle time
tWC
55
70
Address setup time
tAS
0
0
ns
Write pulse width
tWP
40
50
ns
CE setup time
tCW
50
60
ns
Write recovery time
tWR
0
0
ns
CE write recovery time
tWR1
0
0
ns
tDS
25
30
ns
Data hold time
tDH
0
0
ns
CE data hold time
tDH1
0
0
ns
WE output enable time
tWOE
5
5
WE output disable time
tWOD
Data setup time
20
ns
ns
30
ns
No. 6302-4/7
LC35256FM, FT-55U/70U
Timing Charts
[Read cycle] *1
tRC
A0 to A14
tAA
tOH
tCA
CE
tCOD
tCOE
tOA
OE
tOOE
tOOD
*5
DOUT1 to DOUT8
Output data valid
[Write cycle 1] (WE write) *6
tWC
A0 to A14
tCW *4
CE
tWP *3
tAS
tWR
WE
tWOE
tWOD
*5
DOUT1 to DOUT8
*7
tDS
DIN1 to DIN8
tDH
Data in stable
*2
*2
[Write cycle 2] (CE write) *6
tWC
A0 to A14
tCW *4
tAS
CE
tWR1
tWP *3
WE
*5
DOUT1 to DOUT8
High impedance
tDS
DIN1 to DIN8
tDH1
Data in stable
No. 6302-5/7
LC35256FM, FT-55U/70U
Notes:1. WE must be held at the high level during the read cycle.
2. Do not apply reverse phase signals to the DOUT pins when those pins are in the output state.
3. The time tWP is the period when both CE and WE are low. It is defined as the time from the fall of WE to the rise of CE or WE, whichever occurs
first.
4. The time tCW is the period when both CE and WE are low. It is defined as the time from the fall of CE to the rise of CE or WE, whichever occurs first.
5. The DOUT pins will be in the high-impedance state if any one of the following hold: OE is at the high level, CE is at the high level, or WE is at the low
level.
6. The OE pin must be either held high or held low during the write cycle.
7. DOUT has the same phase as the write data during this write cycle.
Circuit Design Notes
When designing application circuits, always take the following into consideration and design the circuits so that the
absolute maximum ratings are never exceeded.
• Supply voltage fluctuations
• Sample-to-sample variations in the electrical characteristics of the electronic components used, including
semiconductor devices, resistors, and capacitors.
• Ambient temperature
• Variations in the input and clock signals
• The application of abnormal pulses
Furthermore, be sure to operate this device within the stipulated ranges of all parameters for which an allowable
operating range is specified.
When CMOS IC input pins are left in the open state, through currents may occur in internal circuits to which
intermediate voltage levels are applied, and this can result in incorrect circuit operation. Be sure to handle all unused
input pins as specified in the device documentation.
Data Retention Conditions at Ta = –40 to +85°C
Parameter
Symbol
Data retention supply voltage
VDR
Conditions
min
VCE ≥ VCC – 0.2 V
typ*
2.0
Ta ≤ 25°C
Data retention supply current
ICCDR
Chip enable setup time
tCDR
Chip enable hold time
tR
max
Unit
5.5
V
0.02
VCC = 3.0 V
Ta ≤ 60°C
1.0
VCE ≥ VCC – 0.2 V
Ta ≤ 70°C
2.0
Ta ≤ 85°C
µA
3.5
0
ns
tRC**
ns
Note: * Reference values for VCC = 3 V, Ta = 25°C.
** tRC: Read cycle time
Data Retention Waveforms
tCDR
Data retention mode
tR
VCC
VCCL*
VIH
VDR
VCE
GND
VCE ≥ VCC – 0.2 V
Note: * VCCL 5 V operation: 4.5 V
No. 6302-6/7
LC35256FM, FT-55U/70U
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of May, 2000. Specifications and information herein are subject to
change without notice.
PS No. 6302-7/7
Similar pages