Sanyo LC651152F Four-bit cmos microcontrollers for small-scale control application Datasheet

Ordering number : ENN*6728
CMOS IC
LC651154N, 651154F, 651154L, LC651152N, 651152F, 651152L
Four-Bit CMOS Microcontrollers for
Small-Scale Control Applications
Preliminary
Overview
The LC651154N/F/L and the LC651152N/F/L are the
small-scale control application versions of Sanyo’s
LC6500 series of 4-bit single-chip CMOS
microcontrollers, and feature the same basic architecture
and instruction set. These microcontrollers include an 8input 8-bit A/D converter and are appropriate for use in a
wide range of applications, from applications with a small
number of circuits and controls that were previously
implemented in standard logic to applications with a larger
scale such as home appliances, automotive equipment,
communications equipment, office equipment, and audio
equipment such as decks and players. Also note that since
these ICs provide the same basic functions (certain
functions and specifications do differ) as, and are pin
compatible with the earlier LC651104N/F/L and
LC651102N/F/L, they can replace those ICs in most cases.
•
Features
• Fabricated in a CMOS process for low power (A
standby function that can be invoked under program
control is also provided.)
• ROM/RAM
LC651154N/F/L — ROM: 4K × 8 bits,
RAM: 256 × 4 bits
LC651152N/F/L — ROM: 2K × 8 bits,
RAM: 256 × 4 bits
• Instruction set: The 80-instruction set common to the
LC6500 family
• Wide operating supply voltage range: 2.2 to 6.0 V
(L versions)
• Instruction cycle time: 0.92 µs (F versions)
• On-chip serial I/O function
• Flexible I/O ports
— Number of ports: 6 ports with a total of 22 pins
•
•
•
•
•
•
— All ports:
· Are I/O ports
· I/O voltage handling capacity: 15 V (maximum)
(Open-drain specification C, D, E, and F ports
only)
· Output current: 20 mA (maximum) sink current
(Are capable of directly driving an LED.)
— Support options to match application system
specifications
A. Open-drain output, internal pull-up resistor
specification: All ports, in bit units
B. Output level at reset specification: Ports C and D
can be specified to go to the high or low level in
4-bit units.
Interrupt function
— Timer interrupts through an interrupt vector (Can be
tested under program control)
— INT pin and serial I/O full/empty interrupts through
an interrupt vector (Can be tested under program
control)
Stack levels: 8 (Shared with the interrupt system.)
Timers: 4-bit variable prescaler and 8-bit programmable
timers
Clock oscillator options that match a wide range of
system specifications
— Oscillator circuit options:
Two-pin RC oscillator (N and L versions)
Two-pin ceramic oscillator (N, F, and L versions)
— Clock divider circuit options:
No divider, built-in divide-by-3, built-in divide-by-4
(N and L versions)
Continuous square wave output (with a period 64 times
the cycle time)
A/D converter (successive approximation)
— 8-bit precision with 8 input channels
Watchdog timer
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
91799RM (OT) No. 6278-1/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
— RC circuit time constant
— Optional watchdog timer reset function from an
external pin
Function Table
Parameter
Memory
Instructions
LC651154N/1152N
LC651154F/1152F
LC651154L/1152L
ROM
4096 × 8 bits (1154N)
2048 × 8 bits (1152N)
4096 × 8 bits (1154F)
2048 × 8 bits (1152F)
4096 × 8 bits (1154L)
2048 × 8 bits (1152L)
RAM
256 × 4 bits (1154/1152N)
256 × 4 bits (1154/1152F)
256 × 4 bits (1154/1152L)
80
80
80
Supported
Supported
Supported
Instruction set
Table reference
Interrupts
Timers
On-chip functions
Stack levels
Standby function
Number of ports
Serial port
I/O voltage handling capability
I/O ports
Output current
I/O circuit types
Output level at reset
Characteristics
1 external, 1 internal
4-bit variable prescaler
+ 8-bit timers
8
8
8
Standby mode entered by the
HALT instruction supported
Standby mode entered by the
HALT instruction supported
Standby mode entered by the
HALT instruction supported
22 I/O port pins
22 I/O port pins
22 I/O port pins
Input and output in 4 or 8 bit units
Input and output in 4 or 8 bit units
Input and output in 4 or 8 bit units
15 V max.
15 V max.
15 V max.
10 mA typ. 20 mA max.
10 mA typ. 20 mA max.
10 mA typ. 20 mA max.
Open drain (n-channel) and pull-up resistor output options can be specified in 1-bit units
A high or low level output can be selected in port units (ports C and D only)
Supported
Supported
Supported
Minimum cycle time
2.77 µs (VDD ≥ 3 V)
0.92 µs (VDD ≥ 2.5 V)
3.84 µs (VDD ≥ 2.2 V)
Supply voltage
Oscillator element
Divider circuit option
Other items
1 external, 1 internal
4-bit variable prescaler
+ 8-bit timers
Square wave output
Current drain
Oscillator
1 external, 1 internal
4-bit variable prescaler
+ 8-bit timers
Package
3 to 6 V
2.5 to 6 V
2.2 to 6 V
1.5 mA typ.
2 mA typ.
1.5 mA typ.
RC (800/400 kHz typ.)
Ceramic (400 k, 800 k, 1 MHz, 4 MHz)
Ceramic 4 MHz
RC (400 kHz typ.)
Ceramic (400 k, 800 k, 1 MHz, 4 MHz)
1/1, 1/3, 1/4
1/1
1/1, 1/3, 1/4
DIP30S-D, MFP30S, SSOP30
DIP30S-D, MFP30S, SSOP30
DIP30S-D, MFP30S, SSOP30
Note: Recommendations for oscillator elements and oscillator circuit constants will be announced as the recommended circuits for these ICs are determined.
Verify the progress of these developments periodically.
No. 6278-2/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Differences between the LC651154N/1152N and the LC651104N/1102N.
The table below lists the points that require care when converting an existing product that uses the LC651104N/1102N to
use the LC651154N/1152N.
Parameter
Allowable power dissipation
LC651154N/1152N
LC651104N/1102N
Pdmax (1) : DIP
310 mW
250 mW
Pdmax (2) : MFP
220 mW
150 mW
Pdmax (3) : SSOP
160 mW
(No corresponding package)
fCFOSC
[OSC1, OSC2]
Oscillator characteristics
Ceramic oscillator
Oscillator frequency
2-pin RC oscillator
fMOSC
Oscillator frequency
[OSC1, OSC2]
Pull-up resistors
Ru [RES]
Serial clock input clock cycle time
tCKCY (1) [ SCK]
A/D converter characteristics
Operating voltage
AV+ = VDD
Reference input current
AV– = VSS
IRIF [AV+, AV–]
Watchdog timer
Cw = 0.047 ±5% µF
Rw = 680 ±1% kΩ
RI = 100 ±1% Ω
Package
Oscillator frequency precision: within ±2%
Changes in the recommended oscillator
constants (See table 1.)
Oscillator frequency precision: within ±4%
800 kHz typ. (VDD = 3 to 6 V)
900 kHz typ. (VDD = 4 to 6 V)
Constants changed: Rext = 5.6 kΩ ±1 %
Constants changed: Rext = 4.7 kΩ ±1 %
Frequency variability (sample to sample):
587 to 1298 kHz
Frequency variability (sample to sample):
634 to 1278 kHz
400 kHz typ. (VDD = 3 to 6 V)
400 kHz typ. (VDD = 3 to 6 V)
Frequency variability (sample to sample):
290 to 616 kHz
Frequency variability (sample to sample):
276 to 742 kHz
200 to 800 kΩ (500 kΩ typ.)
300 to 700 kΩ (500 kΩ typ.)
min. 2.0 µs
min. 3.0 µs
VDD = 3 to 6 V
VDD = 4 to 6 V
200 to 800 µA (500 µA typ.)
75 to 300 µA (150 µA typ.)
VDD = 3 to 6 V
VDD = 4 to 6 V
DIP30S-D, MFP30S
An SSOP30 version was added.
DIP30S-D, MFP30S
Differences between the LC651154F/1152F and the LC651104F/1102F.
The table below lists the points that require care when converting an existing product that uses the LC651104F/1102F to
use the LC651154F/1152F.
Parameter
Allowable power dissipation
Operating supply voltage
Low-level input voltage
Oscillator characteristics
Ceramic oscillator
LC651154F/1152F
LC651104F/1102F
Pdmax (1) : DIP
310 mW
250 mW
Pdmax (2) : MFP
220 mW
150 mW
Pdmax (3) : SSOP
160 mW
(No corresponding package)
2.5 to 6 V
4 to 6 V
VDD
VIL(n)
fCFOSC
[OSC1, OSC2]
Specifications for VDD = 4 to 6 V
The specifications for VDD = 2.5 to 6 V
were added.
Specifications for VDD = 4 to 6 V
Oscillator frequency precision: within ±2 %
Oscillator frequency precision: within ±4 %
Oscillator frequency
Pull-up resistors
A/D converter characteristics
Ru [RES]
Operating voltage
AV+ = VDD
AV– = VSS
Reference input current
IRIF [AV+, AV–]
Package
200 to 800 kΩ (500 kΩ typ.)
300 to 700 kΩ (500 kΩ typ.)
AD speed 1/1 : VDD = 3.5 to 6 V
AD speed 1/1 : VDD = 4.5 to 6 V
AD speed 1/2 : VDD = 3 to 6 V
AD speed 1/2 : VDD = 4 to 6 V
200 to 800 µA (500 µA typ.)
75 to 300 µA (150 µA typ.)
DIP30S-D, MFP30S
An SSOP30 version was added.
DIP30S-D, MFP30S
No. 6278-3/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Differences between the LC651154L/1152L and the LC651104L/1102L.
The table below lists the points that require care when converting an existing product that uses the LC651104L/1102L to
use the LC651154L/1152L.
Parameter
Allowable power dissipation
Operating supply voltage
Oscillator characteristics
Ceramic oscillator
LC651154L/1152L
LC651104L/1102L
Pdmax (1) : DIP
310 mW
250 mW
Pdmax (2) : MFP
220 mW
150 mW
Pdmax (3) : SSOP
160 mW
(No corresponding package)
2.2 to 6 V
2.5 to 6 V
VDD
fCFOSC
[OSC1, OSC2]
Oscillator frequency precision: within ±2%
Changes in the recommended oscillator
constants (See table 1.)
Oscillator frequency precision: within ±4%
400 kHz typ. (VDD = 2.2 to 6 V)
400 kHz typ. (VDD = 2.5 to 6 V)
Frequency variability (sample to sample):
290 to 841 kHz
Frequency variability (sample to sample):
276 to 742 kHz
200 to 800 kΩ (500 kΩ typ.)
300 to 700 kΩ (500 kΩ typ.)
Oscillator frequency
2-pin RC oscillator
fMOSC
Oscillator frequency
[OSC1, OSC2]
Pull-up resistors
Ru [RES]
Serial clock input clock cycle time
tCKCY (1) [ SCK]
A/D converter characteristics
Operating voltage
AV+ = VDD
Reference input current
AV– = VSS
IRIF [AV+, AV–]
Watchdog timer
Package
min. 2.0 µs
min. 6.0 µs
VDD = 3 to 6 V
VDD = 4 to 6 V
200 to 800 µA (500 µA typ.)
75 to 300 µA (150 µA typ.)
VDD = 2.2 to 6.0 V
VDD = 2.5 to 6.0 V
DIP30S-D, MFP30S
An SSOP30 version was added.
DIP30S-D, MFP30S
Caution: Perform a full system evaluation and inspection after replacing the microcontroller.
No. 6278-4/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Pin Assignment
The pin assignment is the same for the DIP, MFP, and SSOP packages.
No. 6278-5/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Pin Functions
OSC1, OSC2: Connections for the oscillator capacitor and resistor or ceramic element
TEST:
IC testing.
RES:
Reset
INT:
Interrupt request input
PA0 to PA3:
Common I/O ports A0 to A3
SI:
Serial input
PC0 to PC3:
Common I/O ports C0 to C3
SO:
Serial output
PD0 to PD3:
Common I/O ports D0 to D3
SCK:
Serial clock input output
PE0 to PE3:
Common I/O ports E0 to E3
AD0 to AD7: A/D converter analog inputs
PF0 to PF3:
Common I/O ports F0 to F3
AV+, AV–:
A/D converter reference voltage inputs
PG0 to PG3:
Common I/O ports G0 to G3
WDR:
Watchdog timer reset input
Note: Pins SI, SO, SCK, and INT are shared function pins also used as PF0:3.
Shared with port F
System Block Diagram
RAM:
Data memory
ROM:
Program memory
F:
Flag
PC:
Program counter
WR:
Working register
INT:
Interrupt control
AC:
Accumulator
IR:
Instruction register
ALU:
Arithmetic and logic unit
I.DEC:
Instruction decoder
DP:
Data pointer
CF, CSF:
Carry flag and carry save flag
E:
E register
ZF, ZSF:
Zero flag and zero save flag
CTL:
Control register
EXTF:
External interrupt request flag
OSC:
Oscillator circuit
TMF:
Internal interrupt request flag
TM:
Timer
STS:
Status register
No. 6278-6/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Development Support
The following are provided for development with the LC651154 and LC651152.
• User’s manual
See the “LC651104/1102 User’s Manual.”
• Development tools manual
See the “Four-Bit Microcontroller EVA86000 Development Tools Manual.”
• Software manual
“LC65/66 Series Software Manual”
• Development tools
— Program development (EVA86000 System)
— On-chip EPROM microcontroller <LC65E1104> for program evaluation
Pin Functions
Symbol
VDD
VSS
OSC1
OSC2
PA0 to
PA3/
AD0 to
AD3
PC0 to
PC3
PD0 to
PD3
Number
of pins
1
1
1
4
4
4
I/O
—
—
Function
Power supply
Input
• Connection for the RC circuit or ceramic oscillator
element used for the system clock oscillator
• Leave OSC2 open when an external clock input is
used.
Output
I/O
• I/O port A0 to A3
Input in 4-bit units (IP instruction)
Output in 4-bit units (OP instruction)
Testing in 1-bit units (BP and BNP instructions)
Set and reset in 1-bit units (SPB and RPB
instructions)
• PA3 is used for standby mode control
• Application must assure that chattering does not
occur on the PA3 input during HALT instruction
execution.
• All four pins have shared functions
PA0/AD0 - A/D converter input AD0
PA1/AD1 - A/D converter input AD1
PA2/AD2 - A/D converter input AD2
PA3/AD3 - A/D converter input AD3
I/O
• I/O port C0 to C3
The port functions are identical to those of PA0 to
PA3. (See note.)
• The output during a reset can be selected to be
either high or low as an option.
Note: This port has no standby mode control
function.
I/O
• I/O port D0 to D3
The port functions and options are identical to
those of PC0 to PC3.
Option
At reset
Handling when
unused
—
—
—
(1) Two-pin RC oscillator or
external clock
(2) Two-pin ceramic oscillator
(3) Divider option
1. No divider
2. Divide-by-3
3. Divide-by-4
—
—
(1) Open-drain output
(2) Pull-up resistor
Options (1) and (2) can be
specified in bit units
High-level
output (The
output nchannel
transistors in
the off state.)
Select the
open-drain
output option
and connect
to VSS.
(1)
(2)
(3)
(4)
Open-drain output
Pull-up resistor
High-level output during reset
Low-level output during reset
• Options (1) and (2) can be
specified in bit units
• Options (3) and (4) are
specified 4 bits at a time
The same as PC0 to PC3
• High-level
output
• Low-level
output
(Depending
on option
selected.)
The same as
PC0 to PC3
The same as
for PA0 to
PA3
The same as
for PA0 to
PA3
Continued on next page.
No. 6278-7/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Symbol
Number
of pins
I/O
Function
Option
At reset
Handling when
unused
• I/O port E0 to E1
PE0-PE1/
WDR
2
I/O
Input in 4-bit units (IP instruction)
(1) Open-drain output
Output in 4-bit units (OP instruction)
(2) Pull-up resistor
• Options (1) and (2) can be
specified in bit units
Set and reset in 1-bit units (SPB and RPB
instructions)
Testing in 1-bit units (BP and BNP instructions)
• PE0 also has a continuous pulse (64·Tcyc) output
function.
(3) Normal port PE1
(4) Watchdog reset WDR
High-level
output (The
output nchannel
transistors in
the off state.)
Identical to
those for PA0
to PA3
• Either options (3) and (4)
may be specified.
• PE1 becomes the watchdog reset pin WDR when
selected for such as an option.
• I/O port F0 to F3
The port functions and options are identical to
those of PE0 to PE1 (See note.)
• PF0 to PF3 have shared functions as the serial
interface pins and the INT input.
PF0/SI
PF1/SO
PF2/SCK
Identical to
those for PA0
to PA3
The function can be selected under program
control.
4
I/O
SI ... Serial input pin
Identical to those for PA0 to PA3
SO ... Serial output pin
PF3/INT
The serial port Identical to
functions are
those for PA0
disabled.
to PA3
The interrupt
source is set
to INT.
SCK ... Input and output of the serial clock signal
INT ... Interrupt request input
The serial I/O function can be switched between 4bit and 8-bit transfers under program control.
Note: There is no continuous pulse output function.
• I/O port G0 to G3
The port functions and options are identical to
those of PE0 to PE1 (See note.)
Note: There is no continuous pulse output function.
PG0-PG3/
AD4-AD7
4
I/O
• All four pins have shared functions.
Identical to those for PA0 to PA3
Identical to
those for PA0
to PA3
Identical to
those for PA0
to PA3
—
—
Connect to
VSS.
—
—
—
—
—
This pin must
be connected
to VSS.
PG0/AD4 - A/D converter input AD4
PG1/AD5 - A/D converter input AD5
PG2/AD6 - A/D converter input AD6
PG3/AD7 - A/D converter input AD7
AV+
1
—
AV–
1
—
A/D converter reference voltage input
• System reset input
RES
1
Input
• Applications must provide an external capacitor for
the power-on reset.
• Apply a low level to this pin for 4 clock cycles to
effect and reset start.
• IC test pin
TEST
1
Input
This pin must be connected to VSS during normal
operation.
No. 6278-8/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Oscillator Circuit Options
Option
Circuit
Conditions and other notes
External clock
The OSC2 pin must be left open.
Two-pin RC oscillator
Ceramic oscillator
Ceramic
oscillator element
Divider Circuit Options
Oscillator circuit
Built-in divide-by-three circuit
Divide-by-3
Built-in divide-by-four circuit
Divide-by-4
Conditions and other notes
Timing
generator
• This option can be used with any of the three oscillator
options.
• The oscillator frequency or external clock frequency must
not exceed 1444 kHz. (LC651154N, LC651152N)
• The oscillator frequency or external clock frequency must
not exceed 4330 kHz. (LC651154F, LC651152F)
• The oscillator frequency or external clock frequency must
not exceed 1040 kHz. (LC651154L, LC651152L)
• This option can only be used with the external clock and the
ceramic oscillator options.
• The oscillator frequency or external clock frequency must
not exceed 4330 kHz.
Timing
generator
Timing
generator
No divider
Oscillator circuit
Circuit
Oscillator circuit
Option
• This option can only be used with the external clock and the
ceramic oscillator options.
• The oscillator frequency or external clock frequency must
not exceed 4330 kHz.
Caution: The following tables summarize the oscillator and divider circuit options. Use care when selecting these options.
No. 6278-9/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Oscillator Options
LC651154N, LC651152N
Circuit type
Frequency
400 kHz
800 kHz
Ceramic oscillator
1 MHz
4 MHz
External clock used with the 2-pin RC oscillator circuit
Divider option
(cycle time)
VDD range
1/1 (10 µs)
3 to 6 V
1/1 (5 µs)
3 to 6 V
1/3 (15 µs)
3 to 6 V
1/4 (20 µs)
3 to 6 V
1/1 (4 µs)
3 to 6 V
1/3 (12 µs)
3 to 6 V
1/4 (16 µs)
3 to 6 V
1/3 (3 µs)
3 to 6 V
1/4 (4 µs)
3 to 6 V
200 k to 1444 kHz
1/1 (20 to 2.77 µs) 3 to 6 V
600 k to 4330 kHz
1/3 (20 to 2.77 µs) 3 to 6 V
800 k to 4330 kHz
1/4 (20 to 3.70 µs) 3 to 6 V
Notes
Cannot be used with the divide-by-three
and divide-by-four options.
Cannot be used with the no divider circuit
option.
Two-pin RC
Use the no divider circuit option and the 3 to 6 V
recommended circuit constants. If using other circuit
constants is unavoidable, the application must use a
frequency identical to the external clock and observe
the VDD range specification.
External clock used with the ceramic oscillator option
External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.
LC651154F, LC651152F
Circuit type
Frequency
Divider option
(cycle time)
VDD range
Notes
Ceramic oscillator
4 MHz
1/1 (1 µs)
External clock used with the 2-pin RC oscillator circuit
200 k to 4330 kHz
1/1 (20 to 0.92 µs) 2.5 to 6 V
2.5 to 6 V
External clock used with the ceramic oscillator option
External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.
No. 6278-10/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
LC651154L, LC651152L
Circuit type
Divider option
(cycle time)
Frequency
400 kHz
800 kHz
Ceramic oscillator
1 MHz
External clock used with the 2-pin RC oscillator circuit
VDD range
1/1 (10 µs)
2.2 to 6 V
1/1 (5 µs)
2.2 to 6 V
1/3 (15 µs)
2.2 to 6 V
1/4 (20 µs)
2.2 to 6 V
1/1 (4 µs)
2.2 to 6 V
1/3 (12 µs)
2.2 to 6 V
1/4 (16 µs)
2.2 to 6 V
4 MHz
1/4 (4 µs)
2.2 to 6 V
200 k to 1040 kHz
1/1 (20 to 3.84 µs) 2.2 to 6 V
600 k to 3120 kHz
1/3 (20 to 3.84 µs) 2.2 to 6 V
800 k to 4160 kHz
1/4 (20 to 3.84 µs) 2.2 to 6 V
Notes
Cannot be used with the divide-by-three
and divide-by-four options.
Cannot be used with either the no divider
circuit option or the divide-by-three circuit
option.
Two-pin RC
Use the no divider circuit option and the 2.2 to 6 V
recommended circuit constants. If using other circuit
constants is unavoidable, the application must use a
frequency identical to the external clock and observe
the VDD range specification.
External clock used with the ceramic oscillator option
External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.
Port C and D Output Level During Reset Option
The output level during a reset can be selected from the two options below in 4-bit units for the C and D ports.
Option
Conditions and other notes
High-level output during reset
Ports C and D in 4-bit units
Low-level output during reset
Ports C and D in 4-bit units
Port Output Type Option
The following two options may be selected for the I/O ports individually (bit units).
Option
Circuit
Applicable ports
1. Open-drain output
Ports A, C, D, E, F, and G
2. Built-in pull-up resistor
Watchdog Reset Option
This option allows the PE1/WDR pin to be selected either to be used as the normal port PE1 or to be used as the
watchdog reset pin WDR.
No. 6278-11/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
LC651154N, 651152N
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Output voltage
Input voltage
I/O voltage
Peak output current
Symbol
Conditions
Applicable pins and notes
VDD max
Ratings
VDD
Allowed up to the
generated voltage.
OSC2
VO
Unit
–0.3 to +7.0
VI (1)
OSC1 *1
–0.3 to VDD + 0.3
VI (2)
TEST, RES, AV+, AV–
–0.3 to VDD + 0.3
VIO (1)
PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3
Open-drain specification ports
–0.3 to +15
VIO (2)
PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3
Pull-up resistor specification ports
–0.3 to VDD + 0.3
VIO (3)
PC0 to 3, PG0 to 3
–0.3 to VDD + 0.3
IOP
IOA
V
Per single pin, averaged over 100 ms
I/O ports
–2 to +20
I/O ports
–2 to +20
PC0 to 3
∑IOA (1)
Average output current
∑IOA (2)
The total current for PC0 to PC3,
PD0 to PD3, and PE0 to PE1 *2
PD0 to 3
–15 to +100
PE0 to 1
PF0 to 3
The total current for PF0 to PF3,
PG0 to 3
PG0 to PG3, and PA0 to PA3 (See note 2.) *2
PA0 to 3
–15 to +100
Pd max (1) Ta = –40 to +85°C (DIP package)
Allowable power dissipation
mA
310
Pd max (2) Ta = –40 to +85°C (MFP package)
220
Pd max (3) Ta = –40 to +85°C (SSOP package)
160
Operating temperature
Topr
–40 to +85
Storage temperature
Tstg
–55 to +125
mW
°C
Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V (Unless otherwise specified.)
Parameter
Symbol
Conditions
Applicable pins and notes
Ratings
min
typ
max
Operating supply voltage
VDD
VDD
3.0
6.0
Standby supply voltage
VST
RAM and register values retained*3 VDD
1.8
6.0
0.7 VDD
13.5
High-level input voltage
VIH (1)
Output n-channel transistors off
Ports C, D, E, and F with
open-drain specifications
VIH (2)
Output n-channel transistors off
Ports C, D, E, and F with
pull-up resistor specifications
0.7 VDD
VDD
VIH (3)
Output n-channel transistors off
Port A, G
0.7 VDD
VDD
VIH (4)
Output n-channel transistors off
The INT, SCK, and SI
pins with open-drain
specifications
0.8 VDD
13.5
VIH (5)
Output n-channel transistors off
The INT, SCK, and SI
pins with pull-up resistor
specifications
0.8 VDD
VDD
VIH (6)
VDD = 1.8 to 6.0 V
RES
0.8 VDD
VDD
VIH (7)
External clock specifications
OSC1
0.8 VDD
Unit
V
VDD
Continued on next page.
No. 6278-12/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter
Low-level input voltage
Operating frequency
(cycle time)
Symbol
Applicable pins
and notes
Conditions
Ratings
min
typ
Unit
max
VIL (1)
Output n-channel transistors off VDD = 4 to 6 V
Port
VSS
0.3 VDD
VIL (2)
Output n-channel transistors off VDD = 3 to 6 V
Port
VSS
0.25 VDD
VIL (3)
Output n-channel transistors off VDD = 4 to 6 V
INT, SCK, SI
VSS
0.25 VDD
VIL (4)
Output n-channel transistors off VDD = 3 to 6 V
INT, SCK, SI
VSS
0.2 VDD
VIL (5)
External clock specifications VDD = 4 to 6 V
OSC1
VSS
0.25 VDD
VIL (6)
External clock specifications VDD = 3 to 6 V
OSC1
VSS
0.2 VDD
VIL (7)
VDD = 4 to 6 V
TEST
VSS
0.3 VDD
VIL (8)
VDD = 3 to 6 V
TEST
VSS
0.25 VDD
VIL (9)
VDD = 4 to 6 V
RES
VSS
0.25 VDD
VIL (10)
VDD = 3 to 6 V
RES
VSS
0.2 VDD
fop (Tcyc)
External clock conditions
The clock may have a
frequency up to 4.33 MHz
when either the divide-byVDD = 3 to 6 V
three or divide-by-four
internal divider circuit option
is used.
200
(20)
V
1444
kHz (µs)
(2.77)
Figure 1.
Frequency
text
Pulse width
textH, textL
Rise and fall times
textR, textF
Either the divide-bythree or divide-by-four
internal divider circuit
must be used if the
clock frequency
exceeds 1.444 MHz.
VDD = 3 to 6 V
OSC1
200
VDD = 3 to 6 V
OSC1
69
VDD = 3 to 6 V
OSC1
VDD = 3 to 6 V
OSC1, OSC2
VDD = 3 to 6 V
OSC1, OSC2
4330
kHz
ns
50
Recommended oscillator
circuit constants
Cext
Figure 2
Rext
270 ±5%
pF
12 ±1%
kΩ
Two-pin RC oscillator
Cext
Figure 2
Rext
Ceramic oscillator *4
Figure 3
270 ±5%
pF
5.6 ±1%
kΩ
See table 1.
No. 6278-13/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V (Unless otherwise specified.)
Parameter
Conditions
Applicable pins and notes
IIH (1)
• Output n-channel transistors off
(Including the n-channel transistor
off leakage current.)
• VIN = 13.5 V
Ports C, D, E and F with
the open-drain
specifications
5.0
IIH (2)
• Output n-channel transistors off
(Including the n-channel transistor Ports A and G with the
off leakage current.)
open-drain specifications
• VIN = VDD
1.0
IIH (3)
When an external clock is used,
VIN = VDD
OSC1
1.0
IIL (1)
• Output n-channel transistors off
• VIN = VSS
Ports with the open-drain
specifications
–1.0
IIL (2)
• Output n-channel transistors off
• VIN = VSS
Ports with the pull-up
resistor specifications
–1.3
–0.35
IIL (3)
VIN = VSS
RES
–45
–10
IIL (4)
When an external clock is used,
VIN = VSS
OSC1
–1.0
VOH (1)
• IOH = –50 µA
• VDD = 4.0 to 6.0 V
Ports with the pull-up
resistor specifications
VDD – 1.2
VOH (2)
IOH = –10 µA
Ports with the pull-up
resistor specifications
VDD – 0.5
VOL (1)
• IOL = 10 mA
• VDD = 4.0 to 6.0 V
Port
1.5
VOL (2)
When IOL = 1 mA and the IOL for
each port is 1 mA or less.
Port
0.5
High-level input current
Low-level input current
High-level output voltage
Schmitt characteristics
Low-level output voltage
Hysteresis voltage
VtH
Low-level threshold
voltage
VtL
Two-pin RC oscillator
Ceramic oscillator
External clock
Standby mode
min
typ
Unit
max
RES, INT, SCK, SI, and
OSC1 with Schmitt
specifications*5
• Operating, with the output
n-channel transistors off
IDDOP (1)
• With the ports at VDD
• Figure 2, fosc = 800 kHz (typical)
mA
µA
0.4 VDD
0.8 VDD
0.2 VDD
0.6 VDD
VDD
1.5
4
5
IDDOP (2) • Figure 3, 4 MHz, divide-by-three circuit used VDD
1.5
IDDOP (3) • Figure 3, 4 MHz, divide-by-four circuit used VDD
1.5
4
IDDOP (4) • Figure 3, 400 kHz
VDD
1.0
2.5
IDDOP (5) • Figure 3, 800 kHz
VDD
1.5
4
• 200 kHz to 1444 kHz, no divider
circuit
• 600 kHz to 4330 kHz, divide-byIDDOP (6) three circuit used
• 800 kHz to 4330 kHz, divide-byfour circuit used
VDD
1.5
5
Output n-channel transistors off,
VDD = 6 V
VDD
0.05
10
Ports at VDD, VDD = 3 V
VDD
0.025
5
IDDst
µA
V
0.1 VDD
VHIS
High-level threshold
voltage
Current drain *6
Ratings
Symbol
mA
µA
Continued on next page.
No. 6278-14/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter
Symbol
Oscillator characteristics
Ceramic oscillator
Oscillator frequency
Oscillator stabilization time
(note 8)
Two-pin RC oscillator
Oscillator frequency
Pull-up resistor
I/O ports
RES
External reset characteristics
Reset time
Pin capacitances
fCFOSC*7
tCFS
fMOSC
RPP
Ru
Conditions
• Figure 3, fo = 400 kHz
• Figure 3, fo = 800 kHz
• Figure 3, fo = 1 MHz
• Figure 3, fo = 4 MHz, with the
divide-by-three or divide-by-four
circuit used.
Applicable pins and notes
OSC1, OSC2
OSC1, OSC2
OSC1, OSC2
OSC1, OSC2
Ratings
min
typ
392
784
980
3920
400
800
1000
4000
• Figure 4, fo = 400 kHz
• Figure 4, fo = 800 kHz, 1 MHz, or
4 MHz, with the divide-by-three or
divide-by-four circuit used.
408
816
1020
4080
10
10
• Figure 2, Cext = 270 pF ±5%
• Figure 2, Rext = 5.6 kΩ ±1%
OSC1, OSC2
587
800
1298
• Figure 2, Cext = 270 pF ±5%
• Figure 2, Rext = 12 kΩ ±1%
OSC1, OSC2
290
400
818
• Output n-channel transistors off
• VIN = VSS, VDD = 5 V
Pull-up resistor
specification ports
8
14
30
VIN = VSS, VDD = 5 V
RES
200
500
800
kHz
ms
kHz
tRST
Cp
Unit
max
kΩ
See figure 5.
• f = 1 MHz
• With all pins other than the pin
being tested at VIN = VSS.
10
pF
Serial clock
tCKCY (1)
Figure 6
SCK
tCKCY (2)
Figure 6
SCK
Input clock low-level pulse
width
tCKL (1)
Figure 6
SCK
Output clock low-level pulse
width
tCKL (2)
Figure 6
SCK
Input clock high-level pulse
width
tCKH (1)
Figure 6
SCK
Output clock high-level
pulse width
tCKH (2)
Figure 6
SCK
Input clock cycle time
Output clock cycle time
64 × TCYC*9
1.0
32 × TCYC
1.0
32 × TCYC
µs
Serial input
Data setup time
tICK
Data hold time
tCKI
Serial output
Output delay time
2.0
tCKO
• Stipulated with respect to the
rising edge of SCK.
• Figure 6
SI
0.4
SI
0.4
• Stipulated with respect to the
falling edge of SCK.
• With an external resistor of 1 kΩ
and an external capacitor of 50 pF SO
on only the n-channel open-drain
pins.
• Figure 6
0.6
Continued on next page.
No. 6278-15/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter
Symbol
Pulse output function
Period
tPCY
High-level pulse width
tPH
Low-level pulse width
tPL
Applicable pins
and notes
Conditions
• Figure 7
• TCYC = 4 × system clock
period
• With an external resistor of
1 kΩ and an external
capacitor of 50 pF on only
the n-channel open-drain
pins.
Ratings
min
typ
PE0
64 × TCYC
PE0
32 × TCYC
±10%
PE0
32 × TCYC
±10%
Resolution
A/D converter characteristics
Input reference voltage
TCAD
±1
Analog input voltage
range
VAIN
312
(TCYC =
12 µs)
When the A/D converter
speed is one half (1:2),
namely 51 × TCYC
141
(TCYC =
2.77 µs)
612
(TCYC =
12 µs)
AV+
AV–
VDD
AV–
VSS
AV+
AV+, AV–
200
AD0 to AD7
AV–
VDD = 3 to 6 V
AV+ = VDD, AV– = VSS
Including the output off
leakage current.
VAIN = VDD
AD0 to AD7
(The I/O
shared
function ports
have opendrain
specifications.)
IAIN
VAIN = VSS
Recommended
constants*10
Cw
When PE1 has the
open-drain specifications.
Rw
When PE1 has the
open-drain specifications.
Watchdog timer
RI
±2
72
(TCYC =
2.77 µs)
AV–
IRIF
bit
When the A/D converter
speed is normal (1:1),
namely 26 × TCYC
AV+
Input reference current
range
Analog port input current
µs
8
AV+ = VDD
AV– = VSS
Absolute precision
Conversion time
Unit
max
When PE1 has the
open-drain specifications.
500
LSB
µs
V
800
µA
AV+
V
1
µA
–1
WDR
0.1 ±5%
µF
WDR
680 ±1%
kΩ
WDR
100 ±1%
Ω
VDD = 3 to 6 V
Clear time (discharge)
tWCT
Figure 8
WDR
100
µs
Clear period (charge)
tWCCY
Figure 8
WDR
36
ms
Cw
When PE1 has the
open-drain specifications.
WDR
0.047 ±5%
µF
Rw
When PE1 has the
open-drain specifications.
WDR
680 ±1%
kΩ
WDR
100 ±1%
Ω
Recommended
constants*10
RI
When PE1 has the
open-drain specifications.
VDD = 3 to 6 V
Clear time (discharge)
tWCT
Figure 8
WDR
40
µs
Clear period (charge)
tWCCY
Figure 8
WDR
18
ms
Notes:1. Allowed up to the amplitude generated when the oscillator shown in figure 3 is used with the recommended circuit constants and driven by the IC.
2. The average over a 100 ms period.
3. The operating VDD supply voltage must be maintained from the point the HALT instruction is executed until the IC has fully entered the standby
state. Applications must also assure that no chattering occurs on the PA3 pin during the HALT instruction execution cycle.
4. Recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer using the Sanyostipulated oscillator characteristics evaluation board.
5. The OSC1 pin will have Schmitt characteristics when external clock oscillator is selected with the two-pin RC oscillator option.
6. These are the results of testing using our (Sanyo’s) characteristics evaluation board with the recommended circuit constants used as external
components. The current flowing in the IC’s output transistors and transistors that have pull-up resistors is not included.
7. fCFOSC is the frequency when the recommended circuit constants from table 1 are used as external components.
8. Indicates the time required to achieve stable oscillation from the point VDD rises above the lower limit of the operating voltage range.
9. TCYC = 4 × the system clock period
10. If the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between PE1 and
adjacent pins and leakage associated with external resistors and capacitor is required during design.
No. 6278-16/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
External clock
open
Figure 1 External Clock Input Waveform
Ceramic oscillator
element
Figure 2 Two-Pin RC Oscillator Circuit
Figure 3 Ceramic Oscillator Circuit
No. 6278-17/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Lower limit for the operating supply voltage
Stable oscillation
Oscillation
stabilization
time tCFS
Figure 4 Oscillation Stabilization Time
Table 1 Recommended Ceramic Oscillator Circuit Constants
4 MHz (Murata Mfg. Co., Ltd.)
C1
33 pF ±10%
CSA4.00MG
C2
33 pF ±10%
CST4.00MGW (Internal capacitor)
R
0Ω
4 MHz (Kyocera Corporation)
C1
33 pF ±10%
KBR4.0MSA
C2
33 pF ±10%
KBR4.0MKS (Internal capacitor)
R
0Ω
1 MHz (Murata Mfg. Co., Ltd.)
C1
100 pF ±10%
CSB1000J
C2
100 pF ±10%
R
3.3 kΩ
800 kHz (Murata Mfg. Co., Ltd.)
C1
100 pF ±10%
CSB800J
C2
100 pF ±10%
R
3.3 kΩ
400 kHz (Murata Mfg. Co., Ltd.)
C1
220 pF ±10%
CSB400P
C2
220 pF ±10%
R
3.3 kΩ
Figure 5 Reset Circuit
Note: If the power supply rise time is zero, the reset time when CRES = 0.1 µF
will be between 10 and 100 ms.
If the power supply rise time is long, increase the value of CRES so that
the reset time is at least 10 ms.
No. 6278-18/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Input data
Load circuit
Output data
Figure 6 Serial I/O Timing
The load conditions are the same
as those in figure 5.
Figure 7 Port PE0 Pulse Output Timing
tWCCY:
tWCT:
The charge time due to the time constant of the circuit consisting of
the external components Cw, Rw, and Rl.
The discharge time due to software processing.
Figure 8 Watchdog Timer Waveform
No. 6278-19/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
RC Oscillator Characteristics for the LC651154N and LC651152N
Figure 9 shows the RC oscillator characteristics for the LC651154N and LC651152N.
However, the sample-to-sample variation in the LC651154N and LC651152N RC oscillator frequency described below
does occur.
1) When:
VDD = 3.0 to 6.0 V, Ta = –40 to +85°C
External constants: Cext = 270 pF
Rext = 12.0 kΩ
fMOSC will be:
290 kHz ≤ fMOSC ≤ 818 kHz
2) When:
VDD = 3.0 to 6.0 V, Ta = –40 to +85°C
External constants: Cext = 270 pF
Rext = 5.6 kΩ
fMOSC will be:
587 kHz ≤ fMOSC ≤ 1298 kHz
Therefore, only the above circuit constants are recommended.
If use of circuit constants other than the above is unavoidable, they must be in the following ranges.
Cext = 150 to 390 pF
Rext = 3 to 20 kΩ
(See figure 9.)
Notes • The oscillator frequency must be in the range 350 to 850 kHz when VDD = 5.0 V and Ta = 25°C.
• Applications must be designed to have adequate margins so that the oscillator frequency falls in the operating
clock frequency range (see the oscillator divider option table) for the voltage range VDD = 3.0 to 6.0 V and for
the temperature range Ta = –40 to +85°C.
These characteristics curves are for
reference purposes only and are not
guaranteed.
Figure 9 RC Oscillator Frequency Data (Representative Values)
No. 6278-20/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
LC651154F, 651152F
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Output voltage
Input voltage
I/O voltage
Peak output current
Symbol
Conditions
Applicable pins and notes
VDD max
Ratings
VDD
Allowed up to the
generated voltage.
OSC2
VO
Unit
–0.3 to +7.0
VI (1)
OSC1 *1
–0.3 to VDD + 0.3
VI (2)
TEST, RES, AV+, AV–
–0.3 to VDD + 0.3
VIO (1)
PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Open-drain specification ports
–0.3 to +15
VIO (2)
PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Pull-up resistor specification ports
–0.3 to VDD + 0.3
VIO (3)
PA0 to PA3, PG0 to PG3
–0.3 to VDD + 0.3
IOP
IOA
Per single pin, averaged over 100 ms
I/O ports
–2 to +20
I/O ports
–2 to +20
V
PC0 to PC3
∑IOA (1)
Average output current
∑IOA (2)
The total current for PC0 to PC3,
PD0 to PD3, and PE0 and PE1 *2
PD0 to PD3
–15 to +100
PE0 and PE1
PF0 to PF3
The total current for PF0 to PF3, PG0 to PG3,
PG0 to PG3
and PA0 to PA3 (See note 2.) *2
PA0 to PA3
–15 to +100
Pd max (1) Ta = –40 to +85°C (DIP package)
Allowable power dissipation
mA
310
Pd max (2) Ta = –40 to +85°C (MFP package)
220
Pd max (3) Ta = –40 to +85°C (SSOP package)
160
Operating temperature
Topr
–40 to +85
Storage temperature
Tstg
–55 to +125
mW
°C
Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V, VDD = 2.5 to 6.0 V (Unless otherwise specified.)
Parameter
Symbol
Conditions
Applicable pins and notes
Ratings
min
typ
max
Operating supply voltage
VDD
VDD
2.5
6.0
Standby supply voltage
VST
RAM and register values retained*3 VDD
1.8
6.0
0.7 VDD
13.5
High-level input voltage
VIH (1)
Output n-channel transistors off
Ports C, D, E, and F with
open-drain specifications
VIH (2)
Output n-channel transistors off
Ports C, D, E, and F with
pull-up resistor specifications
0.7 VDD
VDD
VIH (3)
Output n-channel transistors off
Port A, G
0.7 VDD
VDD
VIH (4)
Output n-channel transistors off
The INT, SCK, and SI
pins with open-drain
specifications
0.8 VDD
13.5
VIH (5)
Output n-channel transistors off
The INT, SCK, and SI
pins with pull-up resistor
specifications
0.8 VDD
VDD
VIH (6)
VDD = 1.8 to 6.0 V
RES
0.8 VDD
VDD
VIH (7)
External clock specifications
OSC1
0.8 VDD
VDD
Unit
V
Continued on next page.
No. 6278-21/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter
Low-level input voltage
Operating frequency
(cycle time)
Symbol
Applicable pins
and notes
Conditions
Ratings
min
typ
Unit
max
VIL (1)
Output n-channel transistors off VDD = 4 to 6 V
Port
VSS
VIL (2)
Output n-channel transistors off VDD = 2.5 to 6 V Port
VSS
0.2 VDD
VIL (3)
Output n-channel transistors off VDD = 4 to 6 V
VSS
0.25 VDD
INT, SCK, SI
0.3 VDD
VIL (4)
Output n-channel transistors off VDD = 2.5 to 6 V INT, SCK, SI
VSS
0.15 VDD
VIL (5)
External clock specifications VDD = 4 to 6 V
OSC1
VSS
0.25 VDD
VIL (6)
External clock specifications VDD = 2.5 to 6 V OSC1
VSS
0.15 VDD
0.3 VDD
VIL (7)
VDD = 4 to 6 V
TEST
VSS
VIL (8)
VDD = 2.5 to 6 V TEST
VSS
0.2 VDD
VIL (9)
VDD = 4 to 6 V
RES
VSS
0.25 VDD
VIL (10)
VDD = 2.5 to 6 V RES
VSS
0.15 VDD
200
(20)
fop (Tcyc)
V
4330
kHz (µs)
(0.92)
External clock conditions
Frequency
OSC1
200
Pulse width
textH, textL Figure 1.
text
OSC1
69
Rise and fall times
textR, textF
OSC1
Recommended oscillator
circuit constants
4330
kHz
ns
50
ns
See table 1.
Figure 2
Ceramic oscillator *4
Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 2.5 to 6.0 V (Unless otherwise specified.)
Parameter
Symbol
typ
max
5.0
IIH (2)
• Output n-channel transistors off
(Including the n-channel transistor Ports A and G with the
off leakage current.)
open-drain specifications
• VIN = VDD
1.0
When an external clock is used,
VIN = VDD
OSC1
1.0
IIL (1)
• Output n-channel transistors off
• VIN = VSS
Ports with the open-drain
specifications
–1.0
IIL (2)
• Output n-channel transistors off
• VIN = VSS
Ports with the pull-up
resistor specifications
–1.3
–0.35
IIL (3)
VIN = VSS
RES
–45
–10
IIL (4)
When an external clock is used,
VIN = VSS
OSC1
–1.0
VOH (1)
• IOH = –50 µA
• VDD = 4.0 to 6.0 V
Ports with the pull-up
resistor specifications
VDD – 1.2
VOH (2)
IOH = –10 µA
Ports with the pull-up
resistor specifications
VDD – 0.5
VOL (1)
• IOL = 10 mA
• VDD = 4.0 to 6.0 V
Port
1.5
VOL (2)
When IOL = 1 mA and the IOL for
each port is 1 mA or less.
Port
0.5
High-level output voltage
Low-level output voltage
Schmitt characteristics
Ratings
min
IIH (1)
IIH (3)
Hysteresis voltage
Applicable pins and notes
• Output n-channel transistors off
Ports C, D, E and F with
(Including the n-channel transistor
the open-drain
off leakage current.)
specifications
• VIN = 13.5 V
High-level input current
Low-level input current
Conditions
VtH
Low-level threshold
voltage
VtL
µA
mA
µA
V
0.1 VDD
VHIS
High-level threshold
voltage
Unit
RES, INT, SCK, SI, and
OSC1 with Schmitt
specifications*5
0.4 VDD
0.8 VDD
0.25 VDD
0.6 VDD
Continued on next page.
No. 6278-22/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter
Symbol
Conditions
Applicable pins and notes
Ratings
min
typ
Unit
max
Current drain*6
IDDOP (1) • Figure 2, 4 MHz
• 200 kHz to 4330 kHz
Ceramic oscillator
Standby mode
• Operating, with the output
IDDOP (2)
n-channel transistors off and the
ports at VDD.
IDDst
VDD
VDD
VDD
0.05
10
0.025
5
OSC1, OSC2
Oscillator frequency*8
tCFS
• Figure 3, fo = 4 MHz
RPP
• Output n-channel transistors off
• VIN = VSS, VDD = 5 V
Pull-up resistor
specification ports
VIN = VSS, VDD = 5 V
RES
External reset characteristics
Reset time
Pin capacitances
Serial clock
4080
kHz
10
ms
8
14
30
200
500
800
• f = 1 MHz
• With all pins other than the pin
being tested at VIN = VSS.
10
Figure 5
SCK
tCKCY (2)
Figure 5
SCK
Input clock low-level pulse
width
tCKL (1)
Figure 5
SCK
Output clock low-level pulse
width
tCKL (2)
Figure 5
SCK
Input clock high-level pulse
width
tCKH (1)
Figure 5
SCK
Output clock high-level
pulse width
tCKH (2)
Figure 5
SCK
• Stipulated with respect to the
rising edge of SCK.
• Figure 5
SI
Output clock cycle time
4000
µA
kΩ
See figure 4.
tCKCY (1)
Input clock cycle time
3920
tRST
Cp
6
VDD
• Figure 2, fo = 4 MHz
Ru
2
• Output n-channel transistors off
VDD = 6 V
• Ports at VDD, VDD = 2.5 V
fCFOSC*7
RES
6
mA
Oscillator characteristics
Ceramic oscillator
Pull-up resistor
I/O ports
2
pF
2.0
64 × TCYC*9
0.6
32 × TCYC
0.6
32 × TCYC
Serial input
Data setup time
Data hold time
tICK
tCKI
Serial output
Output delay time
tCKO
Pulse output function
Period
tPCY
High-level pulse width
tPH
Low-level pulse width
tPL
0.2
µs
SI
0.2
• Stipulated with respect to the
falling edge of SCK.
• With an external resistor of 1 kΩ
SO
and an external capacitor of 50 pF
on only the n-channel open-drain
pins.
• Figure 5
• Figure 6
• TCYC = 4 × system clock
period
• With an external resistor of
1 kΩ and an external
capacitor of 50 pF on only
the n-channel open-drain
pins.
0.4
PE0
64 × TCYC
PE0
32 × TCYC
±10%
PE0
32 × TCYC
±10%
Continued on next page.
No. 6278-23/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter
Symbol
Resolution
A/D converter characteristics
Input reference voltage
TCAD
8
bit
VDD = 3.5 to 6 V
±1
±2
AV– = VSS A/D converter speed 1/2 VDD = 3.5 to 6 V
±1
±2
When the A/D converter
speed is normal (1/1),
namely 26 × TCYC
VDD = 3.5 to 6 V
24
(TCYC =
0.92 µs)
312
(TCYC =
12 µs)
When the A/D converter
speed is one half (1/2),
namely 51 × TCYC
VDD = 3 to 6 V
47
(TCYC =
0.92 µs)
612
(TCYC =
12 µs)
AV+
AV–
VDD
AV–
VSS
AV+
AV+, AV–
200
AD0 to AD7
AV–
Analog input voltage
range
VAIN
AV+ = VDD, AV– = VSS
Including the output off
leakage current.
VAIN = VDD
IAIN
VAIN = VSS
Watchdog timer
Unit
max
AV–
IRIF
Recommended
constants*10
typ
AV+
Input reference current
range
Analog port input current
Ratings
min
VDD = 3 to 6 V
AV+ = VDD A/D converter speed 1/1
Absolute precision
Conversion time
Applicable pins
and notes
Conditions
VDD = 3 to 6 V
AD0 to AD7
(The I/O
shared
function ports
have opendrain
specifications.)
500
LSB
µs
V
800
µA
AV+
V
1
µA
–1
Cw
When PE1 has the
open drain specifications.
WDR
0.01 ±5%
µF
Rw
When PE1 has the
open drain specifications.
WDR
680 ±1%
kΩ
RI
When PE1 has the
open drain specifications.
WDR
100 ±1%
Ω
Clear time (discharge)
tWCT
Figure 7
WDR
10
µs
Clear period (charge)
tWCCY
Figure 7
WDR
4.2
ms
Notes:1. Allowed up to the amplitude generated when the oscillator shown in figure 2 is used with the recommended circuit constants and driven by the IC.
2. The average over a 100 ms period.
3. The operating VDD supply voltage must be maintained from the point the HALT instruction is executed until the IC has fully entered the standby
state. Applications must also assure that no chattering occurs on the PA3 pin during the HALT instruction execution cycle.
4. Recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer using the Sanyostipulated oscillator characteristics evaluation board.
5. The OSC1 pin will have Schmitt characteristics when external clock oscillator is selected with the two-pin RC oscillator option.
6. These are the results of testing using our (Sanyo’s) characteristics evaluation board with the recommended circuit constants used as external
components. The current flowing in the IC’s output transistors and transistors that have pull-up resistors is not included.
7. fCFOSC is the frequency when the recommended circuit constants from table 1 are used as external components.
8. Indicates the time required to achieve stable oscillation from the point VDD rises above the lower limit of the operating voltage range (See figure 3).
9. TCYC = 4 × the system clock period
10. If the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between PE1 and
adjacent pins and leakage associated with external resistors and capacitor is required during design.
No. 6278-24/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
External clock
open
Figure 1 External Clock Input Waveform
Ceramic oscillator
element
Figure 2 Ceramic Oscillator Circuit
No. 6278-25/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Lower limit for the operating supply voltage
Stable oscillation
Oscillation
stabilization
time tCFS
Figure 4 Oscillation Stabilization Time
Table 1 Recommended Ceramic Oscillator Circuit Constants
4 MHz (Murata Mfg. Co., Ltd.)
C1
33 pF ±10%
CSA4.00MG
C2
33 pF ±10%
CST4.00MGW (Internal capacitor)
R
0Ω
4 MHz (Kyocera Corporation)
C1
33 pF ±10%
KBR4.0MSA
C2
33 pF ±10%
KBR4.0MKS (Internal capacitor)
R
0Ω
Figure 5 Reset Circuit
Note: If the power supply rise time is zero, the reset time when CRES = 0.1 µF
will be between 10 and 100 ms.
If the power supply rise time is long, increase the value of CRES so that
the reset time is at least 10 ms.
No. 6278-26/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Input data
Load circuit
Output data
Figure 5 Serial I/O Timing
The load conditions are the same
as those in figure 4.
Figure 6 Port PE0 Pulse Output Timing
tWCCY:
tWCT:
The charge time due to the time constant of the circuit consisting of
the external components Cw, Rw, and Rl.
The discharge time due to software processing.
Figure 7 Watchdog Timer Waveform
No. 6278-27/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
LC651154L, 651152L
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Output voltage
Input voltage
I/O voltage
Peak output current
Symbol
Conditions
Applicable pins and notes
VDD max
Ratings
VDD
Allowed up to the
generated voltage.
OSC2
VO
Unit
–0.3 to +7.0
VI (1)
OSC1 *1
–0.3 to VDD + 0.3
VI (2)
TEST, RES, AV+, AV–
–0.3 to VDD + 0.3
VIO (1)
PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Open-drain specification ports
–0.3 to +15
VIO (2)
PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Pull-up resistor specification ports
–0.3 to VDD + 0.3
VIO (3)
PA0 to PA3, PG0 to PG3
–0.3 VDD + 0.3
IOP
IOA
V
Per single pin, averaged over 100 ms
I/O ports
–2 to +20
I/O ports
–2 to +20
PC0 to PC3
∑IOA (1)
Average output current
∑IOA (2)
The total current for PC0 to PC3,
PD0 to PD3, and PE0 to PE1 *2
PD0 to PD3
–15 to +100
PE0 to PE1
PF0 to PF3
The total current for PF0 to PF3, PG0 to PG3,
PG0 to PG3
and PA0 to PA3 (See note 2.) *2
PA0 to PA3
–15 to +100
Pd max (1) Ta = –40 to +85°C (DIP package)
Allowable power dissipation
mA
310
Pd max (2) Ta = –40 to +85°C (MFP package)
220
Pd max (3) Ta = –40 to +85°C (SSOP package)
160
Operating temperature
Topr
–40 to +85
Storage temperature
Tstg
–55 to +125
mW
°C
Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V, VDD = 2.2 to 6.0 V (Unless otherwise specified.)
Parameter
Symbol
Conditions
Applicable pins and notes
Ratings
min
typ
max
Operating supply voltage
VDD
VDD
2.2
6.0
Standby supply voltage
VST
RAM and register values retained*3 VDD
1.8
6.0
0.7 VDD
13.5
High-level input voltage
Low-level input voltage
VIH (1)
Output n-channel transistors off
Ports C, D, E, and F with
open-drain specifications
VIH (2)
Output n-channel transistors off
Ports C, D, E, and F with
pull-up resistor specifications
0.7 VDD
VDD
VIH (3)
Output n-channel transistors off
Port A, G
0.7 VDD
VDD
VIH (4)
Output n-channel transistors off
The INT, SCK, and SI
pins with open-drain
specifications
0.8 VDD
13.5
VIH (5)
Output n-channel transistors off
The INT, SCK, and SI
pins with pull-up resistor
specifications
0.8 VDD
VDD
VDD
Unit
V
VIH (6)
VDD = 1.8 to 6.0 V
RES
0.8 VDD
VIH (7)
External clock specifications
OSC1
0.8 VDD
VDD
VIL (1)
Output n-channel transistors off
Port
VSS
0.2 VDD
VIL (2)
Output n-channel transistors off
INT, SCK, SI
VSS
0.15 VDD
VIL (3)
Output n-channel transistors off
OSC1
VSS
0.15 VDD
VIL (4)
TEST
VSS
0.2 VDD
VIL (5)
RES
VSS
0.15 VDD
Continued on next page.
No. 6278-28/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter
Operating frequency
(cycle time)
Symbol
fop (Tcyc)
External clock conditions
Conditions
Applicable pins
and notes
The clock may have a frequency up to
4.16 MHz when the divide-by-four internal
divider circuit option is used.
Ratings
min
typ
200
(20)
max
Unit
1040
kHz (µs)
(3.84)
Figure 1.
Frequency
text
Pulse width
textH, textL
Rise and fall times
textR, textF
OSC1
Either the divide-by-three or divide-byfour internal divider circuit must be used if OSC1
the clock frequency exceeds 1.040 MHz.
OSC1
200
4160
100
kHz
ns
100
ns
Recommended oscillator
circuit constants
Two-pin RC oscillator
Cext
Figure 2
Rext
Ceramic oscillator *4
Figure 3
OSC1, OSC2
270 ±5%
pF
12 ±1%
kΩ
See table 1.
No. 6278-29/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 2.2 to 6.0 V (Unless otherwise specified.)
Parameter
Symbol
Schmitt characteristics
Unit
max
IIH (2)
• Output n-channel transistors off
(Including the n-channel transistor Ports A and G with the
off leakage current.)
open-drain specifications
• VIN = VDD
1.0
When an external clock is used,
VIN = VDD
OSC1
1.0
IIL (1)
• Output n-channel transistors off
• VIN = VSS
Ports with the open-drain
specifications
–1.0
IIL (2)
• Output n-channel transistors off
• VIN = VSS
Ports with the pull-up
resistor specifications
–1.3
–0.35
mA
IIL (3)
VIN = VSS
RES
–45
–10
µA
IIL (4)
When an external clock is used,
VIN = VSS
OSC1
–1.0
VOH
• IOH = –10 µA
Ports with the pull-up
resistor specifications
VOL (1)
• IOL = 3 mA
Port
1.5
VOL (2)
When IOL = 1 mA and the IOL for
each port is 1 mA or less.
Port
0.4
VtH
Low-level threshold
voltage
VtL
*6
• Operating, with the output
n-channel transistors off
• With the ports at VDD
• Figure 2, fosc = 800 kHz (typical)
0.4 VDD
0.8 VDD
0.2 VDD
0.6 VDD
IDDOP (1)
VDD
1.0
4
Ceramic oscillator
IDDOP (2) • Figure 3, 4 MHz, divide-by-four circuit used VDD
1.5
4
• Figure 3, 4 MHz, divide-by-four circuit used
VDD
IDDOP (3)
VDD = 2.2 V
0.5
1
Standby mode
IDDOP (4) • Figure 3, 400 kHz
VDD
1.0
2.5
IDDOP (5) • Figure 3, 800 kHz
VDD
1.5
4
• 200 kHz to 1024 kHz, no divider
circuit
• 600 kHz to 3120 kHz, divide-byIDDOP (6) three circuit used
• 800 kHz to 4160 kHz, divide-byfour circuit used
VDD
1.5
4
Output n-channel transistors off,
VDD = 6 V
VDD
0.05
10
Ports at VDD, VDD = 2.2 V
VDD
0.020
4
IDDst
V
0.1 VDD
RES, INT, SCK, SI, and
OSC1 with Schmitt
specifications*5
Two-pin RC oscillator
External clock
µA
VDD – 0.5
VHIS
High-level threshold
voltage
Current drain
typ
5.0
Low-level output voltage
Hysteresis voltage
Ratings
min
IIH (1)
IIH (3)
High-level output voltage
Applicable pins and notes
• Output n-channel transistors off
Ports C, D, E and F with
(Including the n-channel transistor
the open-drain
off leakage current.)
specifications
• VIN = 13.5 V
High-level input current
Low-level input current
Conditions
mA
µA
Continued on next page.
No. 6278-30/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter
Symbol
Oscillator characteristics
Ceramic oscillator
Oscillator frequency
Oscillator stabilization time *8
Two-pin RC oscillator
Oscillator frequency
Pull-up resistor
I/O ports
RES
External reset characteristics
Reset time
Pin capacitances
Serial clock
Input clock cycle time
fCFOSC*7
tCFS
fMOSC
RPP
Ru
Conditions
• Figure 3, fo = 400 kHz
• Figure 3, fo = 800 kHz
• Figure 3, fo = 1 MHz
• Figure 3, fo = 4 MHz, with the
divide-by-four
circuit used.
Applicable pins and notes
OSC1, OSC2
OSC1, OSC2
OSC1, OSC2
OSC1, OSC2
Ratings
min
typ
392
784
980
3920
408
816
1020
4080
10
10
• Figure 2, Cext = 270 pF ±5%
• Figure 2, Rext = 5.6 kΩ ±1%
OSC1, OSC2
• Output n-channel transistors off
• VIN = VSS, VDD = 5 V
Pull-up resistor
specification ports
VIN = VSS, VDD = 5 V
RES
290
400
841
8
14
30
200
500
800
kHz
ms
kHz
kΩ
See figure 5.
• f = 1 MHz
• With all pins other than the pin
being tested at VIN = VSS.
10
tCKCY (1)
Figure 6
SCK
tCKCY (2)
Figure 6
SCK
Input clock low-level pulse
width
tCKL (1)
Figure 6
SCK
Output clock low-level pulse
width
tCKL (2)
Figure 6
SCK
Input clock high-level pulse
width
tCKH (1)
Figure 6
SCK
Output clock high-level
pulse width
tCKH (2)
Figure 6
SCK
• Stipulated with respect to the
rising edge of SCK.
• Figure 6
SI
0.5
SI
0.5
Output clock cycle time
400
800
1000
4000
• Figure 4, fo = 400 kHz
• Figure 4, fo = 800 kHz, 1 MHz, or
4 MHz, with the divide-by-four
circuit used.
tRST
Cp
Unit
max
pF
2.0
64 × TCYC*9
2.0
32 × TCYC
2.0
32 × TCYC
Serial input
Data setup time
Data hold time
tICK
tCKI
Serial output
Output delay time
tCKO
Pulse output function
Period
tPCY
High-level pulse width
tPH
Low-level pulse width
tPL
µs
• Stipulated with respect to the
falling edge of SCK.
• With an external resistor of 1 kΩ
SO
and an external capacitor of 50 pF
on only the n-channel open-drain
pins.
• Figure 6
• Figure 7
• TCYC = 4 × system clock
period
• With an external resistor of
1 kΩ and an external
capacitor of 50 pF on only
the n-channel open-drain
pins.
1.0
PE0
64 × TCYC
PE0
32 × TCYC
±10%
PE0
32 × TCYC
±10%
Continued on next page.
No. 6278-31/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter
Symbol
Applicable pins
and notes
Conditions
Ratings
min
typ
Resolution
8
AV+ = VDD
AV– = VSS
A/D converter characteristics
Absolute precision
Conversion time
Input reference voltage
TCAD
±1
99
(TCYC =
3.84 µs)
312
(TCYC =
12 µs)
When the A/D converter
speed is one half (1/2),
namely 51 × TCYC
195
(TCYC =
3.84 µs)
612
(TCYC =
12 µs)
AV+
AV–
VDD
AV–
VSS
AV+
AV+, AV–
200
AD0 to AD7
AV–
AV–
IRIF
Analog input voltage
range
VAIN
VDD = 3 to 6 V
AV+ = VDD
AV– = VSS
Including the output off
leakage current.
VAIN = VDD
AD0 to AD7
(The I/O
shared
function ports
have opendrain
specifications.)
IAIN
VAIN = VSS
Recommended
constants*10
Cw
When PE1 has the
open-drain specifications.
Rw
When PE1 has the
open-drain specifications.
Watchdog timer
RI
bit
±2
When the A/D converter
speed is normal (1/1),
namely 26 × TCYC
AV+
Input reference current
range
Analog port input current
Unit
max
When PE1 has the
open-drain specifications.
500
LSB
µs
V
800
µA
AV+
V
1
µA
–1
WDR
0.1 ±5%
µF
WDR
680 ±1%
kΩ
WDR
100 ±1%
Ω
VDD = 2.2 to 6 V
Clear time (discharge)
tWCT
Figure 8
WDR
100
µs
Clear period (charge)
tWCCY
Figure 8
WDR
31
ms
Cw
When PE1 has the
open-drain specifications.
WDR
0.047 ±5%
µF
Rw
When PE1 has the
open-drain specifications.
WDR
680 ±1%
kΩ
WDR
100 ±1%
Ω
Recommended
constants*10
RI
When PE1 has the
open-drain specifications.
VDD = 2.2 to 6 V
Clear time (discharge)
tWCT
Figure 8
WDR
40
µs
Clear period (charge)
tWCCY
Figure 8
WDR
14
ms
Notes:1. Allowed up to the amplitude generated when the oscillator shown in figure 3 is used with the recommended circuit constants and driven by the IC.
2. The average over a 100 ms period.
3. The operating VDD supply voltage must be maintained from the point the HALT instruction is executed until the IC has fully entered the standby
state. Applications must also assure that no chattering occurs on the PA3 pin during the HALT instruction execution cycle.
4. Recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer using the Sanyostipulated oscillator characteristics evaluation board.
5. The OSC1 pin will have Schmitt characteristics when external clock oscillator is selected with the two-pin RC oscillator option.
6. These are the results of testing using our (Sanyo’s) characteristics evaluation board with the recommended circuit constants used as external
components. The current flowing in the IC’s output transistors and transistors that have pull-up resistors is not included.
7. fCFOSC is the frequency when the recommended circuit constants from table 1 are used as external components.
8. Indicates the time required to achieve stable oscillation from the point VDD rises above the lower limit of the operating voltage range (See figure 4).
9. TCYC = 4 × the system clock period
10. If the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between PE1 and
adjacent pins and leakage associated with external resistors and capacitor is required during design.
No. 6278-32/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
External clock
open
0.15 VDD
Figure 1 External Clock Input Waveform
Ceramic oscillator
element
Figure 2 Two-Pin RC Oscillator Circuit
Figure 3 Ceramic Oscillator Circuit
No. 6278-33/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Lower limit for the operating supply voltage
Stable oscillation
Oscillation
stabilization
time tCFS
Figure 4 Oscillation Stabilization Time
Table 1 Recommended Ceramic Oscillator Circuit Constants
4 MHz (Murata Mfg. Co., Ltd.)
C1
33 pF ±10%
CSA4.00MG
C2
33 pF ±10%
CST4.00MGW (Internal capacitor)
R
0Ω
4 MHz (Kyocera Corporation)
C1
33 pF ±10%
KBR4.0MSA
C2
33 pF ±10%
KBR4.0MKS (Internal capacitor)
R
0Ω
1 MHz (Murata Mfg. Co., Ltd.)
C1
100 pF ±10%
CSB1000J
C2
100 pF ±10%
R
3.3 kΩ
800 kHz (Murata Mfg. Co., Ltd.)
C1
100 pF ±10%
CSB800J
C2
100 pF ±10%
R
3.3 kΩ
400 kHz (Murata Mfg. Co., Ltd.)
C1
220 pF ±10%
CSB400P
C2
220 pF ±10%
R
3.3 kΩ
Figure 5 Reset Circuit
Note: If the power supply rise time is zero, the reset time when CRES = 0.1 µF
will be between 10 and 100 ms.
If the power supply rise time is long, increase the value of CRES so that
the reset time is at least 10 ms.
No. 6278-34/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Input data
Load circuit
Output data
Figure 6 Serial I/O Timing
The load conditions are the same
as those in figure 5.
Figure 7 Port PE0 Pulse Output Timing
tWCCY:
tWCT:
The charge time due to the time constant of the circuit consisting of
the external components Cw, Rw, and Rl.
The discharge time due to software processing.
Figure 8 Watchdog Timer Waveform
No. 6278-35/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
RC Oscillator Characteristics for the LC651154L and LC651152L
Figure 9 shows the RC oscillator characteristics for the LC651154L and LC651152L.
However, the sample-to-sample variation in the LC651154L and LC651152L RC oscillator frequency described below
does occur.
1) When:
VDD = 2.2 to 6.0 V, Ta = –40 to +85°C
External constants: Cext = 270 pF
Rext = 12.0 kΩ
fMOSC will be:
290 kHz ≤ fMOSC ≤ 841 kHz
Therefore, only the above circuit constants are recommended.
If use of circuit constants other than the above is unavoidable, they must be in the following ranges.
Cext = 150 to 390 pF
Rext = 3 to 20 kΩ
(See figure 9.)
Note 8. The oscillator frequency must be in the range 350 to 850 kHz when VDD = 5.0 V and Ta = 25°C.
Note 9. Applications must be designed to have adequate margins so that the oscillator frequency falls in the operating
clock frequency range (see the oscillator divider option table) for the voltage range VDD = 2.2 to 6.0 V and for
the temperature range Ta = –40 to 85°C.
These characteristics curves are for
reference purposes only and are not
guaranteed.
Figure 9 RC Oscillator Frequency Data (Representative Values)
No. 6278-36/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Notes on Printed Circuit Board Design
This section describes points that require care concerning noise from the point of view of the microcontroller and
presents means of preventing associated problems when designing a printed circuit board to use with these products in a
mass produced end product. The ideas presented in this section are effective design techniques for preventing and
avoiding problems (such as incorrect microcontroller operation and program failures) due to noise.
1. The VDD and VSS power supply pins
Insert capacitors that meet the following conditions between the VDD and VSS power supply pins.
• The lengths of the lines between the VDD and VSS pins and the capacitors C1 and C2 should be as close to exactly
equal as possible (L1 = L1’, L2 = L2’). Furthermore, these distances should be as short as possible.
• Insert two capacitors, C1 and C2 in parallel, with C1 having a large capacitance and C2 having a small capacitance.
• The VDD and VSS lines in the printed circuit board pattern should be wider than any other lines in the pattern.
2. The OSC1 and OSC2 clock I/O pins
— If the ceramic oscillator option is selected (See figure 2-1.)
• Keep the lines between the clock I/O pins (input: OSC1, output:
OSC2) and the external components as short as possible (the
distance Losc in the figure).
• Make the length of the lines (Lvss + L1 and Lvss + L2) from
the microcontroller VSS pin to the VSS side of the capacitors
connected to the oscillator element as short as possible.
• VSS line for the oscillator circuit and other VSS line should
branch from a point nearest to the VSS pin.
• Due to the capacitances of the wiring on the printed circuit
board, it may be necessary to modify the values of the oscillator
circuit constants (including the values of the capacitors C1 and Figure 2-1 Sample Oscillator Circuit 1
C2 and the limiting resistor Rd) from the values presented in
(Ceramic oscillator)
this catalog. We recommend consulting the manufacturer of the
oscillator element with regard to these circuit constants.
— If the 2-pin RC oscillator option is selected (Figure 2-2)
• Keep the lines between the clock I/O pins (input: OSC1, output:
OSC2) and the external components (the capacitor Cext and the
resistor Rext) as short as possible (the distance Losc in the figure).
• Make the length of the lines (Lvss + Lc) from the
microcontroller V SS pin to the V SS side of the capacitor
functioning as the oscillator element as short as possible.
• Take the VSS used by the oscillator circuit (as well as other VSS
usages) from a point as close as possible to the VSS pin.
Figure 2-2 Sample Oscillator Circuit 2
— If the external oscillator option is selected (Figure 2-3)
• Keep the line between the clock input pin (OSC1) and the external
(2-pin RC oscillator)
oscillator circuit as short as possible (the distance Losc in the figure).
• Leave the clock output pin (OSC2) open.
• Make the length (Losc) of the lines to the VDD and VSS pins
used by the external oscillator as short as possible.
— Other points that apply to all oscillator circuits:
External
• Keep all lines that carry signals that change rapidly, signals that
oscillator
have large amplitudes due to being connected to the mediumvoltage handling capacity ports, or signals that carry large
currents as far away from the oscillator circuit as possible. Also,
do not allow such signal lines to cross any clock-signal related
lines.
Figure 2-3 Sample Oscillator Circuit 3
(External oscillator)
No. 6278-37/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
3. RES: Reset pin
• Keep the length of lines (Lres in the figure) from the RES pin to external circuits as short as possible.
• Keep the length of the lines (L1 and L2) to the capacitor (Cres) inserted between RES and VSS as short as possible.
External
circuit
Figure 3 RES Pin Wiring
4. TEST: Test pin
• Keep the length of the line (L) from the TEST pin to the VSS pin as short as possible.
• Run the line from the TEST pin to the VSS pin as close to the VSS pin as possible.
Figure 4 TEST Pin Wiring
5. AD0 to AD7: Analog input pins
Analog input pin lines, such as those used to connect to an A/D converter input pin or a comparator input pin should
be connected so as to meet the following conditions.
• Keep the line (L1) between the limiting resistor (Rl) and the analog input pin as short as possible.
• Locate the capacitor inserted between the analog input pins and the AV- pin (the A/D converter reference voltage
input pin) as close as possible to the AV- input pin. That is, make the line length L1 + L2 as short as possible.
Analog
input pin
External circuit
(sensor block)
Figure 5 Analog Input Pin Wiring
6. I/O pins
All of the pins on these products function as both input and output pins.
• When used as an input pin, insert a limiting resistor, and keep the length of the line to that pin as short as possible.
Supplement: This is not only useful in printed circuit board design, but is also useful in preventing and avoiding
problems (such as incorrect microcontroller operation and program failures) by taking the program specifications
and microcontroller option selections described below into consideration.
• If signals are input from external sources when the microcontroller power supply is unstable, select the mediumvoltage handling capacity (n-channel open drain) output as the output type option for that input pin, and also insert
a limiting resistor in the input circuit.
• Always implement key chattering exclusion measures for external signals applied to microcontroller input pins.
• The pin output data should be re-output periodically with an output instruction (OP or SPB).
No. 6278-38/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
• When reading data input to a pin that can function as either input or output, set the output value for that pin to 1
every time the input is read using an output instruction (OP or SPB).
7. Unused pins
• See the users manual for the product or refer to the pin functions as described in the semiconductor report for the
device.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of September, 1999. Specifications and information herein are
subject to change without notice.
PS No. 6278-39/39