Sanyo LC72347 Ultralow-voltage etr controller with on-chip lcd driver Datasheet

Ordering number : ENN*6651
CMOS IC
LC72346W, 72347W
Ultralow-Voltage ETR Controller
with On-Chip LCD Driver
Preliminary
Continued on next page.
Package Dimensions
unit: mm
3190-SQFP64
[LC72346W, 72347W]
1.25
0.5
1.25
0.15
33
32
1.25
48
49
12.0
10.0
0.18
10.0
1
1.7max
17
64
16
0.1
• Program memory (ROM):
— 4096 × 16 bits (8K bytes) : LC72346
— 6144 × 16 bits (12K bytes): LC72347
• Data memory (RAM):
— 256 × 4 bits: LC72346
— 512 × 4 bits: LC72347
• Cycle time:
40 µs (all 1-word instructions) at 75kHz crystal oscillation
• Stack: 8 levels
• LCD driver: 48 to 80 segments (1/4 duty, 1/2 bias drive)
• Interrupts: Two external interrupts
Timer interrupts (1, 5, 10, and 50 ms)
• A/D converter:
Four input channels (6-bit successive approximation
conversion)
• Input ports: 7 ports (of which three can be switched for
use as A/D converter inputs)
• Output ports: 6 ports (of which 1 can be switched for use
as the beep tone output and 2 are open-drain ports)
• I/O ports: 20 ports (of which 8 can be switched for use
as LCD ports and as mask options, of which 3 can be
switched for use as serial I/O ports)
• Serial I/O: One system (LC72347)
0.5
Function
1.25
The LC72346W and LC72347W are ultralow-voltage
electronic tuning microcontrollers that include a PLL that
operates up to 250 MHz and a 1/4 duty 1/2 bias LCD
driver on chip. This IC includes an on-chip DC-DC
converter that can easily create the power supply voltages
needed for electronic tuning and contribute to reducing
end product costs. This IC is optimal for portable audio
equipment that must operate from a single battery.
• PLL: Reference frequencies:
1, 3, 3.125, 5, 6.25, 12.5, and 25 kHz
• Input frequencies: FM band: 10 to 250 MHz
AM band (high): 2 to 20 MHz
AM band (low): 0.5 to 10 MHz
• Input sensitivity:
FM band: 35 mVrms (50 mVrms at 130 MHz or higher
frequency)
AM band (high, low): 35 mVrms
• External reset input: During CPU and PLL operations,
instruction execution is started from location 0.
• Built-in power-on reset circuit:
The CPU starts execution from location 0 when power is
first applied.
• Halt mode: The controller-operating clock is stopped.
12.0
Overview
0.5
0.5
SANYO: SQFP64
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N1501TN (OT) No. 6651-1/12
LC72346W, 72347W
Continued from preceding page.
• Built-in remaining battery life verification function:
Converts the VDD pin level to digital.
• Memory retention voltage: 0.5 V or higher
• Dedicated memory power supply: The RAM retention
time has been increased by the provision of a dedicated
memory power supply.
• Package: SQFP-64 (0.5-mm pitch)
• VDD power supply: 0.9 to 1.8 V
• Backup mode: The crystal oscillator is stopped.
• Static power-on function:
Backup state is cleared with the PF port
• Beep tone: 1.5 and 3.1 kHz
• Built-in DC-DC converter:
For LCD and A/D converter use (3 V)
Can also be used for TU + B creation by using a
secondary coil.
XIN
TEST1
EO
VSS
AMIN
FMIN
VDD
BRES
COM1
COM2
COM3
COM4
S1
S2
S3
S4
Pin Assignment
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
4
45
5
44
6
43
7
LC72346W
LC72347W
8
9
42
41
40
10
39
11
38
12
37
13
36
14
35
15
34
S5
S6
S7
S8
S9
S10
S11
S12
S13/PH0
S14/PH1
S15/PH2
S16/PH3
S17/PG0
S18/PG1
S19/PG2
S20/PG3
SO1/PK2
SCK1/PK1
PK0
VSS
VDDRAM
VDC3
VDC1
VADJ
INT1/PD1
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
INT0/PD0
PE1
BEEP/PE0
ADI3/PF2
ADI1/PF1
ADI0/PF0
SI1/PK3
XOUT
TEST2
PA3
PA2
PA1
PA0
PB3
PB2
PB1
PB0
PC3
PC2
PC1
PC0
PD3
PD2
No. 6651-2/12
LC72346W, 72347W
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Symbol
Output current
Allowable power dissipation
Unit
–0.3 to +3.0
V
VDD3 max
VDDRAM
–0.3 to +4.0
V
VDD4 max
VDC3
VIN2
Output voltage
Ratings
VDD
VIN1
Input voltage
Conditions
VDD1 max
–0.3 to +4.0
V
FMIN, AMIN
–0.3 to VDD1 +0.3
V
PA, PC, PD, PF, PK, PG, PH, BRES
–0.3 to VDD1 +0.3
V
–0.3 to +7
V
VOUT1
PE
VOUT2
PB, PC, PD, PG, PH
–0.3 to VDD1 +0.3
V
VOUT3
VDC1, EO
–0.3 to VDD4 +0.3
V
VOUT4
COM1 to COM4, S1 to S20
–0.3 to VDD4 +0.3
IOUT1
PC, PD, PG, PH, EO
0 to 3
mA
V
IOUT2
PB
0 to 1
mA
IOUT3
PE
0 to 2
mA
IOUT4
S1 to S20
IOUT5
COM1 to COM4
Pdmax
Ta = –10 to +60°C
300
µA
3
mA
100
mW
Operating temperature
Topr
–10 to +60
°C
Storage temperature
Tstg
–45 to +125
°C
Allowable Operating Ranges at Ta = –10 to +60°C, VDD = 0.9 to 1.8 V
Parameter
Supply voltage
Input high-level voltage
Input low-level voltage
Input amplitude
Input voltage range
Input frequency
Symbol
Conditions
Ratings
min
typ
max
VDD1
Voltage applied to the VDD pin
0.9
1.3
1.8
VDD3
Voltage applied to the VDDRAM pin
2.7
3.0
3.3
VDD4
Voltage applied to the VDC3 pin
2.7
3.0
3.3
Unit
V
VDD5
Memory retention voltage
VIH1
Ports PC, PD, PG, PH, and PK
0.7 VDD1
VDD1
V
VIH2
Port PA
0.8 VDD1
VDD1
V
VIH3
Port PF
0.8 VDD1
VDD1
V
VIH4
Port BRES
0.6 VDD1
VDD1
V
VIL1
Ports PC, PD, PG, PH, and PK
0
0.3 VDD1
V
VIL2
Port PA
0
0.2 VDD1
V
VIL3
Port PF
0
0.2 VDD1
V
VIL4
Port BRES
0
0.2 VDD1
VIN1
XIN
0.5
0.6
Vrms
VIN2
FMIN, AMIN: VDD1 = 0.9 to 1.8 V
0.035
0.35
Vrms
VIN3
FMIN: VDD1 = 0.9 to 1.8 V
0.05
0.35
Vrms
VIN4
ADI0, ADI1, ADI3, VDD1
0
VDD4
FIN1
XIN: CI ≤ 35 kΩ
0.5
70
75
V
V
80
kHz
MHz
FIN2
FMIN: VIN2, VDD1 = 0.9 to 1.8 V
10
130
FIN3
FMIN: VIN3, VDD1 = 0.9 to 1.8 V
130
250
MHz
FIN4
AMIN(L): VIN2, VDD1 = 0.9 to 1.8 V
0.5
10
MHz
FIN5
AMIN(H): VIN2, VDD1 = 0.9 to 1.8 V
2.0
20
MHz
No. 6651-3/12
LC72346W, 72347W
Electrical Characteristics under allowable operating conditions
Parameter
Input high-level current
Input low-level current
Symbol
IIH1
XIN: VDD1 = 1.3 V
IIH2
FMIN, AMIN: VDD1 = 1.3 V
Pull-down resistor values
Hysteresis
Output off leakage current
3
Unit
max
8
3
µA
20
µA
Port PF: VDD1 = 1.3 V
4
µA
IIH4
3
µA
IIL1
XIN: VDD1 = VSS
–3
µA
IIL2
FMIN, AMIN: VDD1 = VSS
IIL3
VIF
–20
µA
Port PF: VDD1 = VSS
–4
µA
PA (without pull-down resistors), the PC,
PD, PG, and PH ports, and BRES,
PK: VDD1 = VSS
–3
µA
PA/PF (with pull-down resistors), VDD1 = 1.3 V
RPD2
TEST1, TEST2 (with pull-down resistors),
VDD1 = 1.3 V
VH
–3
–8
PA (with pull-down resistors)
RPD1
BRES
0.05 VDD1
75
100
200
10
0.1 VDD1
V
kΩ
kΩ
0.2 VDD1
V
VDD1 –
0.3 VDD
V
VOH1
PB: IO = 1 mA
VOH2
PC, PD, PG, PH and PK: IO = 1 mA
VDD1 –
0.3 VDD1
V
VOH3
EO: IO = 500 µA
VDD4 –
0.3 VDD4
V
VOH4
XOUT: IO = 1 µA
VDD1 –
0.3 VDD1
V
VOH5
S1 to S20: IO = 20 µA
VDD4 –1
V
VOH6
COM1, COM2, COM3, COM4:
IO = 100 µA
VDD4 –1
V
VOH7
VDC1: IO = 1 mA
VDD4 –1
VOL1
PB: IO = –50 µA
VOL2
VOL3
V
0.3 VDD1
V
PC, PD, PG, PH and PK: IO = –1 mA
0.3 VDD1
V
EO: IO = –500 µA
0.3 VDD4
V
VOL4
XOUT: IO = –1 µA
0.3 VDD1
V
VOL5
S1 to S20: IO = –20 µA
VDD4 –2
V
VOL6
COM1, COM2, COM3, COM4:
IO = –100 µA
VDD4 –2
V
VOL7
PE: IO = 2 mA
IOFF1
Ports PB, PC, PD, PG, PK, and EO
IOFF2
A/D converter error
Current drain
typ
PA (without pull-down resistors), the PC,
PD, PG, and PH ports, and BRES,
PK: VDD1 = 1.3 V
Output high-level voltage
Output low-level voltage
Ratings
min
IIH3
IIL4
Input floating voltage
Conditions
0.6 VDD1
V
–3
+3
µA
Port PE
–100
+100
nA
ADI0, ADI1, ADI3 VDD1
–1/2
+1/2
LSB
30
mA
IDD1
VDD1 = 1.3 V: FIN2 130 MHz, Ta = 25°C
IDD2
VDD1 = 1.3 V: In PLL stop mode, Ta = 25°C
0.15
mA
IDD3
VDD1 = 1.3 V: In HALT mode, Ta = 25°C *1
0.1
mA
IDD4
VDD1 = 1.8 V, with the oscillator stopped,
Ta = 25°C *2
1
µA
10
Note*: The halt mode current drain is due to 20 instructions being executed every 125 ms.
No. 6651-4/12
LC72346W, 72347W
*1. Halt and PLL STOP mode current test circuit
7 pF
*2. Backup mode current test circuit
7 pF
A
75 kHz
75 kHz
XOUT
VDD RES
XOUT
XIN
7 pF
VDD RES
XIN
7 pF
PA, PF, PK
VDC3
VSS
FMIN
AMIN
A
VDC3
3V
VADJ
TEST1, 2
With all ports other than those specified above left open.
With output mode selected for PC and PD.
With segments S13 to S20 selected.
VSS
FMIN
AMIN
3V
VADJ
TEST1, 2
With all ports other than those specified above left open.
With output mode selected for PC and PD.
With segments S13 to S20 selected.
DC-DC Converter Application
VADJ
VDC3
VDDRAM
VDC1
VSS
VDD
No. 6651-5/12
LC72346W, 72347W
Block Diagram
DIVIDER
XIN
REFERENCE DIVIDER
PHASE
DETECTOR
SYSTEM CLOCK
GENERATOR
XOUT
1/2
FMIN
1/16,1/17
EO
PROGRAMMBLE DIVIDER
AMIN
1/2
1/8
PLL DATA LATCH
PLL CONTROL
1/2
VSS
S1
LCDA/B
1/2
LCD
80 PORT
DRIVER
SEG
4 LA 7
VDC1
Clock Control
LCPA/B
VDC3
VADJ
RES
S12
*
P-ON
RESET
TEST1
TEST2
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
PC0
PC1
PC2
PC3
INT0/PD0
INT1/PD1
PD2
PD3
BUS
DRIVER
*
RAM
256×4bits
(LC72346)
512×4bits
(LC72347)
BUS
DRIVER
ROM
4k×16bits
(LC72346)
6K×16bits
(LC72347)
DATA
LATCH
ADDRESS DECODER
BUS
DRIVER
14
DATA
LATCH
/
/
DATA
LATCH
14
STACK
DATA
LATCH
BANK
BUS
DRIVER
PK0
SCK1/PK1
SO1/PK2
SI1/PK3
DATA
LATCH
/
BUS
DRIVER
S17/PG0
S18/PG1
S19/PG2
S20/PG3
DATA
LATCH
/
BUS
DRIVER
INSTRUCTION
DECODER
SKIP
JMP
CAL
RETURN
INTERRUPT
RESET
BANK CF
JUDGE
LATCH
A
SIO
S13/PH0
S14/PH1
S15/PH2
S16/PH3
/
BUS
CONTROL
ADDRESS COUNTER
/
BUS
DRIVER
ADDRESS
DECODER
COMMON
DRIVER
COM4
COM3
COM2
COM1
BEEP TONE
DATA
LATCH
/
BUS
DRIVER
ALU
PE0/BEEP
MPX
PE1
VDDRAM
LATCH
B
VDD
MPX
TIMER 0
MPX
(6bits)
DATA
LATCH
/
BUS
DRIVER
PF0/ADI0
PF1/ADI1
PF2/ADI3
DATA BUS
No. 6651-6/12
LC72346W, 72347W
Pin Functions
Pin No.
Pin
I/O
64
XIN
I
1
XOUT
O
63
TEST1
I
2
TEST2
I
6
PA0
5
PA1
4
PA2
3
PA3
Function
I/O circuit
75 kHz oscillator connections
IC testing.
These pins must be connected to ground.
I
Special-purpose ports for key return signal input designed with a low threshold
voltage. When a key matrix is formed in combination with port PB, simultaneous
multiple key presses with up to 3 keys can be detected. The pull-down resistors are
set up for all four pins at the same time with the IOS instruction (PWn = 2.b1). This
setting cannot be specified for individual pins. In backup mode, these pins go to the
input disabled state, and the pull-down resistors are disabled after a reset.
O
Unbalanced CMOS outputs. These outputs are switched with the IOS 0 instruction.
Since these outputs are unbalanced, no diodes are required to prevent short circuits
due to simultaneous multiple key presses. These outputs go to the high-impedance
output state in backup mode. After a reset, they go to the high-impedance output
state and remain in that state until an output instruction (OUT, SPB, or RPB) is
executed.
—
Input with built-in
pull-down resistor
Unbalanced CMOS push-pull
10
PB0
9
PB1
8
PB2
7
PB3
14
PC0
13
PC1
12
PC2
11
PC3
18
INT1/PD0
17
INT0/PD1
In backup mode they go to the input disabled high-impedance state.
16
PD2
After a reset, they switch to the general-purpose input port function.
15
PD3
CMOS push-pull
General-purpose I/O ports.
I/O
PD0, PD1 can be used as an external interrupt port. The IOS instruction (Pwn = 4, 5)
is used for switching the general-purpose I/O port function, and these ports can be set
to input or output in 1-bit units. (0: input, 1: output)
*2
General-purpose output and beep tone output shared function ports (PE0 only). The
BEEP instruction is used to switch PE0 between the general-purpose output port and
beep tone output functions. To use PE0 as a general-purpose output port, execute a
BEEP instruction with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output
port. The b0 and b1 bits are used to select the beep tone frequency. There are two
beep tone frequencies supported.
20
BEEP/PE0
19
PE1
O
N-channel open-drain
*: When PE0 is set up as the beep tone output, executing an output instruction to PE0
only changes the state of the internal output latch, it does not affect the beep tone
output in any way. Only the PE0 pin can be switched between the general-purpose
output function and the beep tone output function; the PE1 pin only functions as a
general-purpose output. These pins go to the high-impedance state in backup
mode and remain in that state until an output instruction or a BEEP instruction is
executed. Since these ports are open-drain ports, resistors must be inserted
between these pins and VDD. These ports are set to general-purpose output port
function after a reset.
CMOS push-pull
27
PK0
26
SCK1/PK1
25
SO1/PK2
24
SI1/PK3
I/O
Shared function pins used as either general-purpose I/O ports or a serial I/O port.
When used as general-purpose I/O ports, the I/O direction can be switched in single
pin units with the IOS instruction (with Pwn = C). The IOS instruction (with Pwn = 1,
b2) is used to switch the function between the general-purpose I/O port and the serial
I/O port function. (0: general-purpose I/O port, 1: serial I/O)
In backup mode (low power mode) these pins go to the input disabled highimpedance state. After a reset, the general-purpose input port function is selected.
Continued on next page.
No. 6651-7/12
LC72346W, 72347W
Continued from preceding page.
Pin No.
Pin
23
PF0/ADI0
22
PF1/ADI1
21
PF2/ADI3
I/O
I
Function
I/O circuit
General-purpose input and A/D converter input shared function ports. The IOS
instruction (Pwn = FH) is used to switch between the general-purpose input and A/D
converter port functions. The general-purpose input and A/D converter port functions
can be switched in a units, with 0 specifying general-purpose input, and 1 specifying
the A/D converter input function. To select the A/D converter function, set up the A/D
converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started
with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion
completes. The INR instruction is used to read in the data.
CMOS input/analog input
*: If an input instruction is executed for one of these pins which is set up for analog
input, the read in data will be at the low level since CMOS input is disabled. In
backup mode these pins go to the input disabled high-impedance state. These
ports are set to their general-purpose input port function after a reset. The A/D
converter is a 6-bit successive approximation type converter, and features a
conversion time of 1.28 ms. Note that the full-scale A/D converter voltage (3FH) is
(63/96) VDD.
LCD driver segment output and general-purpose I/O shared function ports.
CMOS push-pull
The IOS instruction is used for switching between the segment output and generalpurpose I/O functions and between input and output for the general-purpose I/O port
function.
33
PG3/S20
34
PG2/S19
35
PG1/S18
36
PG0/S17
37
PH3/S16
38
PH2/S15
39
PH1/S14
40
PH0/S13
O
• When used as segment output ports
The general-purpose I/O port function is selected with the IOS instruction (Pwn = 8).
b0 = S17 to 20/PG0 to 3 (0: Segment output, 1: PG0 to 3)
The general-purpose I/O port function is selected with the IOS instruction (Pwn = 9).
b0 = S13 to 16/PH0 to 3 (0: Segment output, 1: PH0 to 3)
• When used as general-purpose I/O ports
The IOS instruction (Pwn = 6,7) is used to select input or output. Note that the
mode can be set in a bit units.
b0 = PG0
b1 = PG1
b2 = PG2
b3 = PG3
*2
0: Input
1: Output
b0 = PH0
b1 = PH1
b2 = PH2
b3 = PH3
0: Input
1: Output
In backup mode, these pins go to the input disabled high-impedance state if set up as
general-purpose outputs, and are fixed at the low level if set up as segment outputs.
These ports are set up as segment outputs after a reset.
Although the general-purpose port/LCD port setting is a mask option, the IOS
instruction must be used as described above to set up the port function.
CMOS push-pull
LCD driver segment output pins.
41 to
52
A 1/4-duty 1/2-bias drive technique is used.
S12 to S1
O
The frame frequency is 75 Hz.
In backup mode, these outputs are fixed at the low level.
After a reset, these outputs are fixed at the low level.
53
COM4
54
COM3
55
COM2
56
COM1
LCD driver common output pins.
A 1/4-duty 1/2-bias drive technique is used.
O
The frame frequency is 75 Hz.
In backup mode, these outputs are fixed at the low level.
After a reset, these outputs are fixed at the low level.
Continued on next page.
No. 6651-8/12
LC72346W, 72347W
Continued from preceding page.
Pin No.
Pin
I/O
Function
I/O circuit
System reset input.
In CPU operating mode or halt mode, applications must apply a low level for at least
one full machine cycle to reset the system and restart execution with the PC set to
location 0. This pin is connected in parallel with the internal power on reset circuit.
57
RES
I
31
VDC1
O
30
VDC3
I
29
VDDRAM
I
RAM backup power supply. Connected to the VDC3 voltage through a diode.
32
VADJ
O
VDC3 voltage adjustment pin. Insert a 10 kΩ trimmer between this pin and ground to
adjust the VDC3 voltage.
Output for the 3 V step-up circuit clock. Outputs 1/2 the AM local oscillator frequency
in AM reception mode, and 1/256 the FM local oscillator or 75 kHz in FM reception
mode.
Voltage stepped up by the DC-DC converter (3 V)
May also be used to input an equivalent voltage.
CMOS amplifier input
FM VCO (local oscillator) input.
59
FMIN
I
This pin is selected with the PLL instruction CW1.
The input must be capacitor coupled.
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
CMOS amplifier input
AM VCO (local oscillator) input.
This pin and the bandwidth are selected with the PLL instruction CW1.
CW1 b1, b0
60
AMIN
I
Input pins
Bandwidth
1
0
AMIN (H)
2 to 20 MHz (SW)
1
1
FMIN (L)
0.5 to 10 MHz (MW, LW)
The input must be capacitor coupled.
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
CMOS push-pull
62
EO
O
Main charge pump output. When the local oscillator frequency divided by N is higher
than the reference frequency a high level is output, when lower, a low level is
output,and the pin is set to the high-impedance state when the frequencies match.
This output goes to the high-impedance state in backup mode, in halt mode, after a
reset, and in PLL stop mode.
61
VSS
28
VSS
58
VDD
Power supply pin.
—
This pin must be connected to ground.
This pin must be connected to ground.
—
This pin must be connected to VDD. Supports A/D converter.
Note*: When a pin in an I/O switching port is used as an output, applications must first set up the data with an OUT, SPB, or RPB instruction and then set up
output mode with an IOS instruction.
No. 6651-9/12
LC72346W, 72347W
LC72346/347 Series Instruction Set
Terminology
Instruction
group
ADDR
b
C
DH
DL
I
M
N
Rn
Pn
PW
r
( ), [ ]
M (DH, DL)
Mnemonic
Subtraction instructions
Addition instructions
AD
Operand
1st
2nd
r
M
Function
Add M to r
Operations function
R ← (r) + (M)
Instruction format
f
e
d
c
b
a
0
1
0
0
0
0
9
8
DH
7
6
5
DL
4
3
2
1
0
r
ADS
r
M
Add M to r, then skip if carry
R ← (r) + (M), skip if carry 0
1
0
0
0
1
DH
DL
r
AC
r
M
Add M to r with carry
R ← (r) + (M) + C
0
1
0
0
1
0
DH
DL
r
ACS
r
M
Add M to r with carry,
then skip if carry
R ← (r) + (M) + C
skip if carry
0
1
0
0
1
1
DH
DL
r
AI
M
I
Add I to M
M ← (M) + I
0
1
0
1
0
0
DH
DL
I
AIS
M
I
Add I to M, then skip if carry
M ← (M) + I, skip if carry
0
1
0
1
0
1
DH
DL
I
AIC
M
I
Add I to M with carry
M ← (M) + I + C
0
1
0
1
1
0
DH
DL
I
M ← (M) + I + C,
skip if carry
0
1
0
1
1
1
DH
DL
I
AICS
M
I
Add I to M with carry,
then skip if carry
SU
r
M
Subtract M from r
R ← (r) – (M)
0
1
1
0
0
0
DH
DL
r
R ← (r) – (M),
skip if borrow
0
1
1
0
0
1
DH
DL
r
SUS
r
M
Subtract M from r,
then skip if borrow
SB
r
M
Subtract M from r with borrow
R ← (r) – (M) – b
0
1
1
0
1
0
DH
DL
r
R ← (r) – (M) – b,
skip if borrow
SBS
r
M
Subtract M from r with borrow,
then skip if borrow
0
1
1
0
1
1
DH
DL
r
SI
M
I
Subtract I from M
M ← (M) – I
0
1
1
1
0
0
DH
DL
I
Subtract I from M,
then skip if borrow
M ← (M) – I,
skip if borrow
0
1
1
1
0
1
DH
DL
I
SIS
M
I
SIB
M
I
Subtract I from M with borrow
M ← (M) – I – b
0
1
1
1
1
0
DH
DL
I
M
I
Subtract I from M with borrow,
then skip if borrow
M ← (M) – I – b,
skip if borrow
0
1
1
1
1
1
DH
DL
I
SIBS
Comparison instructions
: Program memory address
: Borrow
: Carry
: Data memory address High (Row address) [2 bits]
: Data memory address Low (Column address) [4 bits]
: Immediate data [4 bits]
: Data memory address
: Bit position [4 bits]
: Resister number [4 bits]
: Port number [4 bits]
: Port control word number [4 bits]
: General register (One of the addresses from 00H to 0FH of BANK0)
: Contents of register or memory
: Data memory specified by DH, DL
SEQ
r
M
Skip if r equal to M
(r) – (M), skip if zero
0
0
0
1
0
0
DH
DL
r
SEQI
M
I
Skip if M equal to I
(M) – I, skip if zero
0
0
0
1
1
0
DH
DL
I
SNEI
M
I
Skip if M not equal to I
(M) – I, skip if not zero
0
0
0
0
0
1
DH
DL
I
(r) – (M),
skip if not borrow
0
0
0
1
1
0
DH
DL
r
SGE
r
M
Skip if r is greater than or
equal to M
SGEI
M
I
Skip if M is greater than
equal to I
(M) – I, skip if not borrow
0
0
0
1
1
1
DH
DL
I
SLEI
M
I
Skip if M is less than I
(M) – I, skip if borrow
0
0
0
0
1
1
DH
DL
I
Continued on next page.
No. 6651-10/12
LC72346W, 72347W
Bank switching
instructions
I/O instructions
Hardware control instructions
Status register
instructions
Jump and subroutine
call instructions
Bit test
instructions
Transfer instructions
Logic operation instructions
Instruction
group
Continued from preceding page.
Mnemonic
Operand
1st
2nd
AND
r
M
ANDI
M
I
OR
r
M
Function
Operations function
Instruction format
f
e
d
c
b
a
R ← (r) AND (M)
0
0
1
0
0
0
DH
DL
AND I with M
M ← (M) AND I
0
0
1
0
0
1
DH
DL
I
OR M with r
R ← (r) OR (M)
0
0
1
0
1
0
DH
DL
r
AND M with r
9
8
7
6
5
4
3
2
1
ORI
M
I
OR I with M
M ← (M) OR I
0
0
1
0
1
1
DH
DL
I
EXL
r
M
Exclusive OR M with r
R ← (r) XOR (M)
0
0
1
1
0
0
DH
DL
r
EXLI
M
I
Exclusive OR M with M
M ← (M) XOR I
0
0
1
1
1
0
DH
DL
I
0
0
0
0
0
0
SHR
r
carry
(r)
Shift r right with carry
0
0
1
1
1
0
r
LD
r
M
Load M to r
R ← (M)
1
1
0
1
0
0
DH
DL
r
ST
M
r
Store r to M
M ← (r)
1
1
0
1
0
1
DH
DL
r
MVRD
r
M
Move M to destination M
referring to r in the same row
[DH, Rn] ← (M)
1
1
0
1
1
0
DH
DL
r
MVRS
M
r
Move source M referring to r
to M in the same row
M ← [DH, Rn]
1
1
0
1
1
1
DH
DL
r
MVSR
M1
M2
Move M to M in the same row
[DH, DL1] ← [DH, DL2]
1
1
1
0
0
0
DH
DL1
DL2
MVI
M
I
Move I to M
M←I
1
1
1
0
0
1
DH
DL
I
if M (N) = all 1, then skip
1
1
1
1
0
0
DH
DL
N
if M (N) = all 0, then skip
1
1
1
1
0
1
DH
DL
N
Jump to the address
PC ← ADDR
1
0
0
ADDR (13 bits)
Call subroutine
PC ← ADDR
Stack ← (PC) + 1
1
0
1
ADDR (13 bits)
Return from subroutine
PC ← Stack
0
0
0
0
0
0
0
0
1
0
0
0
Return from interrupt
PC ← Stack,
BANK ← Stack,
CARRY ← Stack
0
0
0
0
0
0
0
0
1
0
0
1
TMT
M
N
Test M bits, then skip if all bits
specified are true
TMF
M
N
Test M bits, then skip if all bits
specified are false
JMP
CAL
ADDR
ADDR
RT
RTI
SS
SWR
N
Set status register
(Status W-reg) N ← 1
1
1
1
1
1
1
1
1
0
0
0 SWR
N
RS
SWR
N
Reset status register
(Status W-reg) N ← 0
1
1
1
1
1
1
1
1
0
0
1 SWR
N
1
1
1
1
1
1
1
0
1
SRR
N
TST
SRR
N
Test status register true
If (Status R-reg) N = all 1,
1
then skip
TSF
SRR
N
Test status register false
If (Status R-reg) N = all 0,
1
then skip
1
1
1
1
1
1
1
1
0
SRR
N
TUL
N
Test Unlock F/F
If Unlock F/F (N) = All 0,
then skip
0
0
0
0
0
0
0
1
1
0
N
Load M to PLL register
PLL reg ← PLL data
1
1
1
1
1
0
Serial I/O control
SIO reg ← I1, I2
0
0
0
0
0
0
0
1
PLL
SIO
M
I1
I2
0
DH
1
DL
r
I1
I2
UCS
I
Set I to UCCW1
UCCW1 ← I
0
0
0
0
0
0
0
0
0
0
0
1
I
UCC
I
Set I to UCCW2
UCCW2 ← I
0
0
0
0
0
0
0
0
0
0
1
0
I
BEEP
I
Beep control
BEEP reg ← I
0
0
0
0
0
0
0
0
0
1
1
0
I
DZC
I
Dead zone control
DZC reg ← I
0
0
0
0
0
0
0
0
1
0
1
1
I
TMS
I
Set timer register
Timer reg ← I
0
0
0
0
0
0
0
0
1
1
0
0
Set port control word
IOS reg PWn ← N
1
1
1
1
1
1
1
0
IOS
PWn
N
I
PWn
N
IN
M
Pn
Input port data to M
M ← (Pn)
1
1
1
0
1
0
DH
DL
Pn
OUT
M
Pn
Output contents of M to port
Pn ← M
1
1
1
0
1
1
DH
DL
Pn
INR
M
Rn
Input register/port data to M
M ← (Pn reg)
0
0
1
1
1
0
DH
DL
Pn
Rn
Output contents of M to
register/port
Rn reg ← (M)
0
0
1
1
1
1
DH
DL
Rn
SPB
N
Set port1 bits
(Pn)N ← 1
0
0
0
0
0
0
1
0
Pn
N
RPB
N
Reset port1 bits
(Pn)N ← 0
0
0
0
0
0
0
1
1
Pn
N
TPT
N
Test port1 bits, then skip if all bits
If (Pn)N = all 1, then skip
specified are true
1
1
1
1
1
1
0
0
Pn
N
TPF
N
Test port1 bits, then skip if all bits
If (Pn)N = all 0, then skip
specified are false
1
1
1
1
1
1
0
1
Pn
N
0
0
0
0
0
0
0
0
OUTR
BANK
M
I
Select Bank
BANK ← I
0
1
0
r
1
1
I
Continued on next page.
No. 6651-11/12
LC72346W, 72347W
Other
instructions
LCD
instructions
Instruction
group
Continued from preceding page.
Mnemonic
Operand
1st
2nd
LCDA
M
I
LCDB
M
I
LCPA
M
I
LCPB
M
I
HALT
I
CKSTP
NOP
Function
Output segment pattern to LCD
digit direct
Operations function
LCD (DIGIT) ← M
Instruction format
f
e
d
c
b
a
1
1
0
0
0
0
9
DH
8
7
6
DL
5
4
DIGIT
1
1
0
0
0
1
DH
DL
DIGIT
1
1
0
0
1
0
DH
DL
DIGIT
1
1
0
0
1
1
DH
DL
DIGIT
Output segment pattern to LCD
digit through LA
LCD (DIGIT) ← LA ← M
Halt mode control
HALT reg ← I,
then CPU clock stop
0
0
0
0
0
0
0
0
0
1
0
0
Clock stop
Stop x’tal OSC
0
0
0
0
0
0
0
0
0
1
0
1
No operation
No operation
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
0
I
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of November, 2001. Specifications and information herein are
subject to change without notice.
PS No. 6651-12/12
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