Ordering number : ENN6235 CMOS IC LC75844M 1/4 Duty General-Purpose LCD Driver Overview Package Dimensions The LC75844M is a 1/4 duty general-purpose LCD driver that can be used for frequency display in electronic tuners under the control of a microcontroller. The LC75844M can drive an LCD with up to 88 segments directly. The LC75844M can also control up to 4 general-purpose output ports. Since the LC75844M uses separate power supply systems for the LCD drive block and the logic block, the LCD driver block power-supply voltage can be set to any voltage in the range 2.7 to 6.0 volts, regardless of the logic block power-supply voltage. unit: mm 3204-MFP36S [LC75844M] 9.2 10.5 19 7.9 36 1 18 0.15 2.15 2.5max 15.3 0.35 0.8 0.85 0.1 • Support for 1/4 duty 1/2 bias or 1/4 duty 1/3 bias drive of up to 88 segments under serial data control. • Serial data input supports CCB format communication with the system controller. • Serial data control of the power-saving mode based backup function and all the segments forced off function • Serial data control of switching between the segment output port and the general-purpose output port functions • High generality, since display data is displayed directly without decoder intervention. • Independent VLCD for the LCD driver block (VLCD can be set to any voltage in the range 2.7 to 6.0 volts, regardless of the logic block power-supply voltage.) • The INH pin can force the display to the off state. • RC oscillator circuit 0.65 Features SANYO: MFP36S • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is a SANYO’s original bus format and all the bus addresses are controlled by SANYO. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 92299TH (OT) No. 6235-1/14 LC75844M Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Maximum supply voltage Conditions Ratings Unit VDD max VDD –0.3 to +7.0 V VLCD max VLCD –0.3 to +7.0 V VIN 1 CE, CL, DI, INH –0.3 to +7.0 V VIN 2 OSC –0.3 to VDD + 0.3 V VIN 3 VLCD 1, VLCD 2 –0.3 to VLCD + 0.3 V –0.3 to VDD + 0.3 V Input voltage Output voltage Output current Allowable power dissipation VOUT 1 OSC VOUT 2 S1 to S22, COM1 to COM4, P1 to P4 IOUT 1 S1 to S22 IOUT 2 COM1 to COM4 3 mA IOUT 3 P1 to P4 5 mA 100 mW Pd max –0.3 to VLCD + 0.3 V 300 µA Ta = 85°C Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V Ratings Parameter Supply voltage Input voltage Input high level voltage Input low level voltage Symbol Conditions min typ Unit max VDD VDD 2.7 6.0 V VLCD VLCD 2.7 6.0 V VLCD1 VLCD1 2/3 VLCD VLCD V VLCD2 VLCD2 1/3 VLCD VLCD V 6.0 V VIH CE, CL, DI, INH 0.8 VDD VIL CE, CL, DI, INH 0 Recommended external resistance ROSC OSC Recommended external capacitance COSC OSC Guaranteed oscillation range fOSC OSC 0.2 VDD 43 680 25 50 V kΩ pF 100 kHz Data setup time tds CL, DI: Figure 2 160 Data hold time tdh CL, DI: Figure 2 160 ns ns CE wait time tcp CE, CL: Figure 2 160 ns CE setup time tcs CE, CL: Figure 2 160 ns CE hold time tch CE, CL: Figure 2 160 ns High level clock pulse width tøH CL: Figure 2 160 ns Low level clock pulse width tøL CL: Figure 2 160 ns Rise time tr CE, CL, DI: Figure 2 160 Fall time tf CE, CL, DI: Figure 2 160 INH switching time tc INH, CE: Figure 3 10 ns ns µs DI CL CE INH OSC VSS VLCD2 VLCD1 VLCD VDD COM4 COM3 COM2 COM1 S22 S21 S20 S19 Pin Assignment P1/S1 P2/S2 P3/S3 P4/S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 LC75844M Top view A12595 No. 6235-2/14 LC75844M Electrical Characteristics for the Allowable Operating Ranges Ratings Parameter Symbol Conditions Hysteresis VH CE, CL, DI, INH Input high level current IIH CE, CL, DI, INH; VI = 6.0 V IIL CE, CL, DI, INH; VI = 0 V Input low level current Output high level voltage Output low level voltage Output middle level voltage*1 Oscillator frequency Current drain min typ Unit max 0.1 VDD V 5.0 µA –5.0 µA VOH 1 S1 to S22; IO = –20 µA VLCD – 0.9 V VOH 2 COM1 to COM4; IO = –100 µA VLCD – 0.9 V VOH 3 P1 to P4; IO = –1 mA VLCD – 0.9 VOL 1 S1 to S22; IO = 20 µA 0.9 V VOL 2 COM1 to COM4; IO = 100 µA 0.9 V VOL 3 P1 to P4; IO = 1 mA 0.9 V VMID 1 COM1 to COM4; 1/2 bias, IO = ±100 µA 1/2 VLCD – 0.9 1/2 VLCD + 0.9 V VMID 2 S1 to S22; 1/3 bias, IO = ±20 µA 2/3 VLCD – 0.9 2/3 VLCD + 0.9 V VMID 3 S1 to S22; 1/3 bias, IO = ±20 µA 1/3 VLCD – 0.9 1/3 VLCD + 0.9 V VMID 4 COM1 to COM4; 1/3 bias, IO = ±100 µA 2/3 VLCD – 0.9 2/3 VLCD + 0.9 V VMID 5 COM1 to COM4; 1/3 bias, IO = ±100 µA 1/3 VLCD – 0.9 1/3 VLCD + 0.9 V fOSC OSC; ROSC = 43 kΩ, COSC = 680 pF IDD 1 VDD; power saving mode IDD 2 VDD; VDD = 6.0 V, output open, fosc = 50 k Hz 40 V 50 230 60 kHz 5 µA 460 µA 5 µA ILCD 1 VLCD; power saving mode ILCD 2 VLCD; VLCD = 6.0 V, output open 1/2 bias, fosc = 50 k Hz 100 200 µA ILCD 3 VLCD; VLCD = 6.0 V, output open 1/3 bias, fosc = 50 k Hz 60 120 µA Note: *1 Excluding the bias voltage generation divider resistors built in the VLCD1 and VLCD2. (See Figure 1.) VLCD VLCD1 To the common segments drivers VLCD2 Except these resistors VSS A06588 Figure 1 No. 6235-3/14 LC75844M 1. When CL is stopped at the low level VIH CE VIL tøH CL tøL VIH 50% VIL tr DI tf tcp tcs tch VIH VIL tds tdh A12597 2. When CL is stopped at the high level VIH CE VIL tøL tøH VIH 50% VIL CL tf tr tcp tcs tch VIH VIL DI tds tdh A12598 Figure 2 S5 S4/P4 S3/P3 S2/P2 S1/P1 S22 S21 COM1 COM2 COM3 COM4 Block Diagram COMMON DRIVER SEGMENT DRIVER & LATCH INH OSC CLOCK GENERATOR SHIFT REGISTER VDD VLCD VLCD1 ADDRESS DETECTOR VLCD2 CE CL DI VSS A12599 No. 6235-4/14 LC75844M Pin Functions Active I/O Handling when unused Segment outputs for displaying the display data transferred by serial data input. The pins S1/P1 to S4/P4 can be used as general-purpose output ports when so set up by the control data. — O Open 23 24 25 26 Common driver outputs. The frame frequency fO is given by: fO = (fOSC/512) Hz. — O Open OSC 32 Oscillator connection An oscillator circuit is formed by connecting an external resistor and capacitor to this pin. — I/O VDD CE CL DI 34 35 36 Serial data transfer inputs. These pins are connected to the control microprocessor. I GND INH 33 Display off control input •INH = low (VSS): Off S1/P1 to S4/P4 = Low (These pins are forcibly set to the segment output port function and fixed at the VSS level.) S5 to S22 = Low (VSS), COM1 to COM4 = Low (VSS) •INH = high (VDD): On Note that serial data transfers can be performed when the display is forced off by this pin. L I GND VLCD1 29 Used to apply the LCD drive 2/3 bias voltage externally. This pin must be connected to VLCD2 when 1/2 bias drive is used. — I Open VLCD2 30 Used to apply the LCD drive 1/3 bias voltage externally. This pin must be connected to VLCD1 when 1/2 bias drive is used. — I Open Pin Pin No. S1/P1 to S4/P4 S5 to S22 1 to 4 5 to 22 COM1 COM2 COM3 COM4 Function H CE: Chip enable CL: Synchronization clock DI: Transfer data — VDD 27 Logic block power supply. Provide a voltage in the range 2.7 to 6.0 V. — — — VLCD 28 LCD driver block power supply. Provide a voltage in the range 2.7 to 6.0 V. — — — VSS 31 Ground pin. Connect to ground. — — — Serial Data Transfer Format 1. When CL is stopped at the low level CE CL DI 0 0 1 0 0 0 1 0 D1 D2 D3 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits 0 0 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits D37 D38 D39 D40 D41 D42 D43 D44 0 0 0 0 Display data 44 bits D45 D46 D47 D81 D82 D83 D84 D85 D86 D87 D88 0 Display data 44 bits 0 P0 P1 P2 DR SC BU Control data 11 bits 0 0 0 0 0 0 Fixed data 11 bits 0 DD 1 bit 0 0 0 0 1 DD 1 bit A12600 Note: DD ... Direction data No. 6235-5/14 LC75844M 2. When CL is stopped at the high level CE CL 0 DI 1 0 B0 B1 B2 B3 A0 A1 A2 CCB address 8 bits 0 A3 0 1 0 0 1 0 0 0 0 0 D1 D2 D3 D37 D38 D39 D40 D41 D42 D43 D44 0 0 0 0 Display data 44 bits 1 0 B0 B1 B2 B3 A0 A1 A2 CCB address 8 bits A3 D45 D46 D47 0 P0 P1 P2 DR SC BU 0 Control data 11 bits D81 D82 D83 D84 D85 D86 D87 D88 0 0 0 0 0 Display data 44 bits 0 DD 1 bit 0 0 0 0 0 1 Fixed data 11 bits DD 1 bit Note: DD ... Direction data A12601 • • • • • • CCB address...............44H D1 to D88...................Display data P0 to P2 ......................Segment output port/general-purpose output port switching control data DR ..............................1/2 bias drive or 1/3 bias drive switching control data SC...............................Segments on/off control data BU ..............................Normal mode/power-saving mode control data Serial Data Transfer Examples • When 45 or more segments are used, all 112 bits of the serial data must be sent. 56 bits 8 bits 0 0 1 0 0 0 1 0 D1 D2 D3 D37 D38 D39 D40 D41 D42 D43 D44 0 0 0 0 0 P0 P1 P2 DR SC BU 0 D45 D46 D47 D81 D82 D83 D84 D85 D86 D87 D88 0 0 0 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 0 0 1 0 0 0 1 0 0 0 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 A12602 • When fewer than 45 segments are used, only 56 bits of serial data need to be sent. However, the display data D1 to D44 and the control data must be sent. 56 bits 8 bits 0 0 1 0 0 0 1 0 D1 D2 D3 D37 D38 D39 D40 D41 D42 D43 D44 0 0 0 0 0 P0 P1 P2 DR SC BU 0 B0 B1 B2 B3 A0 A1 A2 A3 A12603 Note: When fewer than 45 segments are used, transfers such as that shown in the figure below cannot be used. 56 bits 8 bits 0 0 1 0 0 0 1 0 D45 D46 D47 D81 D82 D83 D84 D85 D86 D87 D88 0 0 0 0 0 0 0 0 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 A12604 No. 6235-6/14 LC75844M Control Data Functions 1. P0 to P2: Segment output port/general-purpose output port switching control data. These control data bits switch the S1/P1 to S4/P4 output pins between their segment output port and general-purpose output port functions. Control data Output pin states P0 P1 P2 S1/P1 S2/P2 S3/P3 S4/P4 0 0 0 S1 S2 S3 S4 0 0 1 P1 S2 S3 S4 0 1 0 P1 P2 S3 S4 0 1 1 P1 P2 P3 S4 1 0 0 P1 P2 P3 P4 Note: Sn (n = 1 to 4): Segment output ports Pn (n = 1 to 4): General-purpose output ports Also note that when the general-purpose output port function is selected, the output pins and the display data will have the correspondences listed in the tables below. Output pin Corresponding display data S1/P1 D1 S2/P2 D5 S3/P3 D9 S4/P4 D13 For example, if the output pin S4/P4 has the general-purpose output port function selected, it will output a high level (VLCD) when the display data D13 is 1, and will output a low level (VSS) when D13 is 0. 2. DR: 1/2 bias drive or 1/3 bias drive switching control data This control data bit selects either 1/2 bias drive or 1/3 bias drive. DR Drive type 0 1/3 bias drive 1 1/2 bias drive 3. SC: Segments on/off control data This control data bit controls the on/off state of the segments. SC Display state 0 On 1 Off However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 4. BU: Normal mode/power-saving mode control data This control data bit selects either normal mode or power-saving mode. BU Mode 0 Normal mode 1 Power saving mode (The OSC pin oscillator is stopped, and the common and segment output pins go to the VSS level. However, the S1/P1 to S4/P4 output pins that are set to be general-purpose output ports by the control data P0 to P2 can be used as generalpurpose output ports.) No. 6235-7/14 LC75844M Display Data to Segment Output Pin Correspondence Segment output pin COM1 COM2 COM3 COM4 S1/P1 D1 D2 D3 D4 S2/P2 D5 D6 D7 D8 S3/P3 D9 D10 D11 D12 S4/P4 D13 D14 D15 D16 S5 D17 D18 D19 D20 S6 D21 D22 D23 D24 S7 D25 D26 D27 D28 S8 D29 D30 D31 D32 S9 D33 D34 D35 D36 S10 D37 D38 D39 D40 S11 D41 D42 D43 D44 S12 D45 D46 D47 D48 S13 D49 D50 D51 D52 S14 D53 D54 D55 D56 S15 D57 D58 D59 D60 S16 D61 D62 D63 D64 S17 D65 D66 D67 D68 S18 D69 D70 D71 D72 S19 D73 D74 D75 D76 S20 D77 D78 D79 D80 S21 D81 D82 D83 D84 S22 D85 D86 D87 D88 Note: This applies to the case where the S1/P1 to S4/P4 output pins are set to be segment output ports. For example, the table below lists the segment output states for the S11 output pin. Display data Segment output pin (S11) state D41 D42 D43 D44 0 0 0 0 The LCD segments corresponding to COM1 to COM4 are off. 0 0 0 1 The LCD segment corresponding to COM4 is on. 0 0 1 0 The LCD segment corresponding to COM3 is on. 0 0 1 1 The LCD segments corresponding to COM3 and COM4 are on. 0 1 0 0 The LCD segment corresponding to COM2 is on. 0 1 0 1 The LCD segments corresponding to COM2 and COM4 are on. 0 1 1 0 The LCD segments corresponding to COM2 and COM3 are on. 0 1 1 1 The LCD segments corresponding to COM2, COM3 and COM4 are on. 1 0 0 0 The LCD segment corresponding to COM1 is on. 1 0 0 1 The LCD segments corresponding to COM1 and COM4 are on. 1 0 1 0 The LCD segments corresponding to COM1 and COM3 are on. 1 0 1 1 The LCD segments corresponding to COM1, COM3 and COM4 are on. 1 1 0 0 The LCD segments corresponding to COM1 and COM2 are on. 1 1 0 1 The LCD segments corresponding to COM1, COM2 and COM4 are on. 1 1 1 0 The LCD segments corresponding to COM1 to COM3 are on. 1 1 1 1 The LCD segments corresponding to COM1 to COM4 are on. No. 6235-8/14 LC75844M 1/4 Duty, 1/2 Bias Drive Technique fosc [Hz] 512 COM1 VLCD VLCD1, VLCD2 0V COM2 VLCD VLCD1, VLCD2 0V COM3 VLCD VLCD1, VLCD2 0V COM4 VLCD VLCD1, VLCD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are turned off. VLCD VLCD1, VLCD2 0V LCD driver output when only LCD segments corresponding to COM1 are on. VLCD VLCD1, VLCD2 0V LCD driver output when only LCD segments corresponding to COM2 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM1 and COM2 are on. VLCD VLCD1, VLCD2 0V LCD driver output when only LCD segments corresponding to COM3 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM1 and COM3 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM2 and COM3 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM1, COM2, and COM3 are on. VLCD VLCD1, VLCD2 0V LCD driver output when only LCD segments corresponding to COM4 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM2 and COM4 are on. VLCD VLCD1, VLCD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2,COM3, and COM4 are on. VLCD VLCD1, VLCD2 0V A12605 1/4 Duty, 1/2 Bias Waveforms No. 6235-9/14 LC75844M 1/4 Duty, 1/3 Bias Drive Technique fosc [Hz] 512 COM1 COM2 COM3 COM4 LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are turned off. LCD driver output when only LCD segments corresponding to COM1 are on. LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM1 and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM1 and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when LCD segments corresponding to COM1, COM2, and COM3 are on. LCD driver output when only LCD segments corresponding to COM4 are on. LCD driver output when LCD segments corresponding to COM2 and COM4 are on. LCD driver output when all LCD segments corresponding to COM1, COM2,COM3, and COM4 are on. VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V A12606 1/4 Duty, 1/3 Bias Waveforms No. 6235-10/14 LC75844M The INH pin and Display Control Since the IC internal data (the display data and the control data) is undefined when power is first applied, applications should set the INH pin low at the same time as power is applied to turn off the display (This sets the S1/P1 to S4/P4, S5 to S22, and COM1 to COM4 to the VSS level.) and during this period send serial data from the controller. The controller should then set the INH pin high after the data transfer has completed. This procedure prevents meaningless displays at power on. (See Figure 3.) Notes on the Power On/Off Sequences Applications should observe the following sequence when turning the LC75844M power on and off. • At power on: Logic block power supply (VDD) on → LCD driver block power supply (VLCD) on • At power off: LCD driver block power supply (VLCD) off → Logic block power supply (VDD) off However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time. Display and control data transfer D1 to D44 P0 to P2 DR, SC, BU Undefined Internal data (D45 to D88) Undefined Internal data Defined Defined Undefined Undefined Note: t1 ≥ 0 t2 > 0 t3 ≥ 0 (t2 > t3) tc ... 10 µs min Figure 3 Notes on Controller Transfer of Display Data Since the LC75844M accept display data (D1 to D88) divided into two separate transfer operations, we recommend that applications transfer all of the display data within a period of less than 30 ms to prevent observable degradation of display quality. No. 6235-11/14 LC75844M Sample Application Circuit 1 1/2 Bias (for use with normal panels) General-purpose output ports C ≥ 0.047 µF LCD panel (up to 88 segments) Used for functions such as backlight control From the microcontroller Note: *2 When a capacitor except the recommended external capacitance (COSC = 680 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. Sample Application Circuit 2 1/2 Bias (for use with large panels) General-purpose output ports 10 kΩ ≥ R ≥ 1 kΩ C ≥ 0.047 µF LCD panel (up to 88 segments) Used for functions such as backlight control From the microcontroller Note: *2 When a capacitor except the recommended external capacitance (COSC = 680 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. No. 6235-12/14 LC75844M Sample Application Circuit 3 1/3 Bias (for use with normal panels) General-purpose output ports C ≥ 0.047 µF LCD panel (up to 88 segments) Used for functions such as backlight control From the microcontroller Note: *2 When a capacitor except the recommended external capacitance (COSC = 680 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. Sample Application Circuit 4 1/3 Bias (for use with large panels) General-purpose output ports 10 kΩ ≥ R ≥ 1 kΩ C ≥ 0.047 µF LCD panel (up to 88 segments) Used for functions such as backlight control From the microcontroller Note: *2 When a capacitor except the recommended external capacitance (COSC = 680 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. No. 6235-13/14 LC75844M Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1999. Specifications and information herein are subject to change without notice. PS No. 6235-14/14