ON LC75863W Duty lcd display driver with key input function Datasheet

Ordering number : ENN7135A
LC75863W
CMOS IC
1/3 Duty LCD Display Driver
with Key Input Function
http://onsemi.com
Overview
The LC75863W is the 1/3 duty LCD display driver that can directly drive up to 75 segments and can control up to
four general-purpose output ports. This product also incorporates a key scan circuit that accepts input from up to 30
keys to reduce printed circuit board wiring.
Features
 Key input function for up to 30 keys (A key scan is performed only when a key is pressed.)
 1/3duty - 1/2bias and 1/3duty - 1/3bias drive schemes can be controlled from serial data (up to 75 segments).
 Sleep mode and all segments off functions that are controlled from serial data.
 Segment output port/general-purpose output port function switching that is controlled from serial data.
 Serial data I/O supports CCB format communication with the system controller.
 Direct display of display data without the use of a decoder provides high generality.
 Independent VLCD for the LCD driver block (VLCD can be set to in the range VDD-0.5 to 6.0 volts.)
 Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays.
 RC oscillator circuit.

CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
36
0.5
9.0
7.0
25
24
48
13
7.0
9.0
37
1
12
0.5
0.18
0.15
(0.75)
0.1
(1.5)
1.7max
SQFP48(7X7)
SQFP48(7X7)

CCB is a registered trademark of Semiconductor Components Industries, LLC.
ORDERING INFORMATION
See detailed ordering and shipping information on page 25 of this data sheet.
Semiconductor Components Industries, LLC, 2013
October, 2013
O2313HKPC B8-8715/D2001TN(OT) No.7135-1/25
LC75863W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0V
Parameter
Maximum supply voltage
Input voltage
Symbol
Conditions
Ratings
Unit
VDD max
VDD
-0.3 to +7.0
VLCD max
VLCD
-0.3 to +7.0
VIN1
CE, CL, DI
VIN2
OSC, TEST
V
-0.3 to +7.0
V
-0.3 to VDD+0.3
VIN3
VLCD1, VLCD2, KI1 to KI5
VOUT1
DO
VOUT2
OSC
VOUT3
S1 to S25, COM1 to COM3, KS1 to KS6, P1 to P4
IOUT1
S1 to S25
IOUT2
COM1 to COM3
3
IOUT3
KS1 to KS6
1
IOUT4
P1 to P4
5
Allowable power dissipation
Pd max
Ta = 85C
Operating temperature
Topr
-40 to +85
C
Storage temperature
Tstg
-55 to +125
C
Output voltage
Output current
-0.3 to VLCD+0.3
-0.3 to +7.0
-0.3 to VDD+0.3
V
-0.3 to VLCD+0.3
A
300
mA
150
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0V
Ratings
Parameter
Symbol
Conditions
unit
min
Supply voltage
Input voltage
Input high level voltage
VDD
VDD
VLCD
VLCD
typ
max
4.5
6.0
VDD-0.5
6.0
V
VLCD1
VLCD1
2/3VLCD
VLCD
VLCD2
VLCD2
1/3VLCD
VLCD
VIH1
CE, CL, DI
0.8VDD
6.0
VIH2
KI1 to KI5
0.6VDD
VDD
0
0.2VDD
V
Input low level voltage
VIL
CE, CL, DI, KI1 to KI5
Recommended external resistance
Rosc
OSC
39
Recommended external capacitance
Cosc
OSC
1000
Guaranteed oscillation range
fosc
OSC
Data setup time
tds
CL, DI
19
V
38
V
k
pF
76
kHz
[Figure 2]
160
ns
Data hold time
tdh
CL, DI
[Figure 2]
160
ns
CE wait time
tcp
CE, CL
[Figure 2]
160
ns
CE setup time
tcs
CE, CL
[Figure 2]
160
ns
CE hold time
tch
CE, CL
[Figure 2]
160
ns
High level clock pulse width
tH
CL
[Figure 2]
160
ns
Low level clock pulse width
tL
CL
[Figure 2]
160
ns
Rise time
tr
CE, CL, DI
[Figure 2]
160
Fall time
tf
CE, CL, DI
[Figure 2]
160
DO output delay time
tdc
DO RPU = 4.7k, CL = 10pF *1
[Figure 2]
1.5
s
DO rise time
tdr
DO RPU = 4.7k, CL = 10pF *1
[Figure 2]
1.5
s
ns
ns
Note: *1. Since DO is an open-drain output, these times depend on the values of the pull-up resistor RPU and the load
capacitance CL.
No.7135-2/25
LC75863W
Electrical Characteristics for the Allowable Operating Ranges
Ratings
Parameter
Symbol
Pin
Conditions
unit
min
Hysteresis
VH
typ
CE, CL, DI,
0.1VDD
KI1 to KI5
Power-down detection voltage
VDET
Input high level current
IIH
CE, CL, DI
VI = 6.0V
Input low level current
IIL
CE, CL, DI
VI = 0V
Input floating voltage
VIF
KI1 to KI5
Pull-down resistance
RPD
KI1 to KI5
VDD = 5.0V
Output off leakage current
IOFFH
DO
VO = 6.0V
VOH1
KS1 to KS6
IO = -500A
VLCD-1.0
VOH2
P1 to P4
IO = -1mA
VLCD-1.0
VOH3
S1 to S25
IO = -20A
VLCD-1.0
VLCD-1.0
Output high level voltage
Output low level voltage
Output middle level voltage *2
max
2.5
3.0
V
5.0
A
A
-5.0
0.05VDD
50
100
VLCD-0.5
k
6.0
A
VLCD-0.2
VOH4
COM1 to COM3
IO = -100A
KS1 to KS6
IO = 25A
VOL2
P1 to P4
IO = 1mA
1.0
VOL3
S1 to S25
IO = 20A
1.0
VOL4
COM1 to COM3
IO = 100A
1.0
0.2
0.5
1.5
VOL5
DO
IO = 1mA
VMID1
COM1 to COM3
1/2bias, IO = 100A
1/2VLCD
-1.0
+1.0
VMID2
S1 to S25
1/3bias, IO = 20A
2/3VLCD
2/3VLCD
-1.0
+1.0
VMID3
S1 to S25
1/3bias, IO = 20A
1/3VLCD
1/3VLCD
-1.0
+1.0
2/3VLCD
2/3VLCD
COM1 to COM3
1/3bias, IO = 100A
0.1
V
0.5
1/2VLCD
-1.0
+1.0
1/3VLCD
1/3VLCD
VMID5
COM1 to COM3
1/3bias, IO = 100A
fosc
OSC
Rosc = 39k, Cosc = 1000pF
IDD1
VDD
Sleep mode
IDD2
VDD
VDD = 6.0V, output open,
fosc = 38kHz
ILCD1
VLCD
Sleep mode
ILCD2
VLCD
VLCD = 6.0V, output open,
1/2bias, fosc = 38kHz
100
200
ILCD3
VLCD
VLCD = 6.0V, output open,
1/3bias, fosc = 38kHz
60
120
30.4
V
250
V
-1.0
Current drain
3.5
VOL1
VMID4
Oscillator frequency
V
V
+1.0
38
45.6
kHz
100
270
540
5
A
Note: *2 Excluding the bias voltage generation divider resistor built into VLCD1 and VLCD2. (See Figure 1.)
VLCD
VLCD1
To the common segment driver
VLCD2
Excluding these resistors.
Figure 1
No.7135-3/25
LC75863W
1. When CL is stopped at the low level

VIH1
tH
tL
VIH1
50%
VIL
tf
tr
   
DI
VIH1
VIL
tdh
tds
DO
tcp
    
CL
VIL
 
CE
tcs
tdc
D0
tch
tdr
D1
2. When CL is stopped at the high level

VIH1
tH
50%
tds
tdh
tcp
tcs
D0
D1
tdc
   
VIH1
VIL
    
tr
DI
DO
VIH1
VIL
tf

tL
CL
VIL

CE
tch
tdr
Figure 2
No.7135-4/25
KI5
36
37
COM2
KS1/S24
COM3
KS3
KS4
KS5
KS6
KI1
KI2
KI3
KI4
Pin Assignment
KS2/S25
LC75863W
25
24
VDD
COM1
S23
S22
S21
VLCD
VLCD1
VLCD2
LC75863W
(SQFP48)
VSS
S20
S19
TEST
S18
OSC
DO
S17
S16
CE
S15
S14
S12
S11
S10
S9
S8
S7
S6
S5
P4/S4
P3/S3
13
12
P2/S2
48
1
P1/S1
CL
DI
S13
Top view
Package Dimensions
unit:mm
SPQFP48 7x7 / SQFP48
CASE 131AJ
ISSUE O
No.7135-5/25
LC75863W
S1/P1
S2/P2
S3/P3
S4/P4
S5
S23
COM1
COM2
COM3
Block Diagram
VLCD
SEGMENT DRIVER & LATCH
VLCD1
COMMON
DRIVER
VLCD2
SHIFT REGISTER
VSS
TEST
CLOCK
GENERATOR
OSC
CONTROL
REGISTER
DO
CCB
INTERFACE
DI
KEY BUFFER
CL
CE
VDD
VDET
S24/KS1
S25/KS2
KS3
KS4
KS5
KS6
KI1
KI2
KI3
KI4
KI5
KEY SCAN
No.7135-6/25
LC75863W
Pin Functions
Symbol
Pin No.
Function
S1/P1
1
S2/P2
2
Segment outputs for displaying the display data transferred by serial data input.
S3/P3
3
The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial
S4/P4
4
data control.
S5 to S23
5 to 23
COM1
24
COM2
25
COM3
26
Common driver outputs
The frame frequency fo is given by : fo = (fosc/384)Hz.
Handling
Active
I/O
-
O
OPEN
-
O
OPEN
-
O
OPEN
H
I
GND
-
I/O
VDD
H
I
when unused
Key scan outputs
KS1/S24
27
KS2/S25
28
KS3 to KS6
29 to 32
Although normal key scan timing lines require diodes to be inserted in the timing
lines to prevent shorts, since these outputs are unbalanced CMOS transistor
outputs, these outputs will not be damaged by shorting when these outputs are
used to form a key matrix. The KS1/S24 and KS2/S25 pins can be used as
segment outputs when so specified by the control data.
KI1 to KI5
33 to 37
OSC
44
Key scan inputs
These pins have built-in pull-down resistors.
Oscillator connection
An oscillator circuit is formed by connecting an external resistor and capacitor at
this pin.
CE
46
Serial data interface connections to the controller. Note that DO, being an opendrain output, requires a pull-up resistor.
CL
47
CE : Chip enable
DI
48
CL : Synchronization clock
I
-
I
GND
DI : Transfer data
DO
45
DO : Output data
-
O
OPEN
TEST
43
This pin must be connected to ground.
-
I
-
VLCD1
40
-
I
OPEN
VLCD2
41
VDD
Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to
VLCD2 when a 1/2 bias drive scheme is used.
Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to
-
I
OPEN
38
VLCD1 when a 1/2 bias drive scheme is used.
Logic block power supply connection. Provide a voltage of between 4.5 and 6.0V.
-
-
-
VLCD
39
LCD driver block power supply connection. Provide a voltage of between VDD-0.5
-
-
-
VSS
42
Power supply connection. Connect to ground.
-
-
-
and 6.0V.
No.7135-7/25
LC75863W
Serial Data Input
(1) When CL is stopped at the low level
CE
CL
DI
0
1
0
0
0
0
1
0
D1 D2
D34 D35 D36 D37 D38 D39 0
0
0
0
0
0
Display Data
B0 B1 B2 B3 A0 A1 A2 A3
0 S0 S1 K0 K1 P0 P1 P2 SC DR 0
Control Data
DD
DO
0
1
0
0
0
0
1
0
D40 D41
D73 D74 D75 0
0
0
0
0
0
0
0
Display Data
B0 B1 B2 B3 A0 A1 A2 A3
0
0
0
0
0
0
0
0
0
0
0
Fixed Data
1
DD
Note: B0 to B3, A0 to A3 ···· CCB address
DD ························ Direction data
(2) When CL is stopped at the high level
CE
CL
DI
0
1
0
0
0
0
1
0
D1 D2
D34 D35 D36 D37 D38 D39 0
0
0
0
0
0
Display Data
B0 B1 B2 B3 A0 A1 A2 A3
0 S0 S1 K0 K1 P0 P1 P2 SC DR 0
Control Data
DD
DO
0
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Note: B0 to B3, A0 to A3 ····
DD ························
• CCB address ·················
• D1 to D75 ·····················
• S0, S1 ·························
• K0, K1 ························
• P0 to P2 ·······················
• SC ·····························
• DR ·····························
D40 D41
D73 D74 D75 0
Display Data
0
0
0
0
0
0
0
0
0
0
0
0
0
Fixed Data
0
0
0
0
0
1
DD
CCB address
Direction data
42H
Display data
Sleep control data
Key scan output/segment output selection data
Segment output port/general-purpose output port selection data
Segment on/off control data
1/2 bias or 1/3 bias drive selection data
No.7135-8/25
LC75863W
Control Data Functions
(1) S0, S1      Sleep control data
These control data bits switch between normal mode and sleep mode and set the states of the KS1 to KS6 key scan
output during key scan standby.
Control data
Mode
S0
OSC oscillator
S1
Output pin states during key scan standby
Segment outputs
Common outputs
KS1
KS2
KS3
KS4
KS5
KS6
0
0
Normal
Operating
Operating
H
H
H
H
H
H
0
1
Sleep
Stopped
L
L
L
L
L
L
H
1
0
Sleep
Stopped
L
L
L
L
L
H
H
1
1
Sleep
Stopped
L
H
H
H
H
H
H
Note: This assumes that the KS1/S24 and KS2/S25 output pins are selected for key scan output.
(2) K0, K1      Key scan output/segment output selection data
These control data bits switch the functions of the KS1/S24 and KS2/S25 output pins between key scan output and
segment output.
Control data
Output pin state
Maximum number of
K0
K1
KS1/S24
KS2/S25
input keys
0
0
KS1
KS2
30
0
1
S24
KS2
25
1
X
S24
S25
20
Note: KSn (n=1 or 2): Key scan output
Sn (n=24 or 25): Segment output
X : don't care
(3) P0 to P2      Segment output port/general-purpose output port selection data
These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and
the general-purpose output port.
Control data
Output pin state
P0
P1
P2
S1/P1
S2/P2
S3/P3
S4/P4
0
0
0
S1
S2
S3
S4
0
0
1
P1
S2
S3
S4
0
1
0
P1
P2
S3
S4
0
1
1
P1
P2
P3
S4
1
0
0
P1
P2
P3
P4
Note: Sn (n=1 to 4): Segment output port
Pn (n=1 to 4): General-purpose output port
The table below lists the correspondence between the display data and the output pins when these pins are selected
to be general-purpose output ports.
Output pin
Corresponding display data
S1/P1
D1
S2/P2
D4
S3/P3
D7
S4/P4
D10
For example, if the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output
a high level (VLCD) when the display data D10 is 1, and will output a low level (VSS) when D10 is 0.
(4) SC      Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
on
1
off
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting
segment off waveforms from the segment output pins.
(5) DR      1/2 bias or 1/3 bias drive selection data
This control data bit switches between LCD 1/2 bias or 1/3 bias drive.
DR
Drive scheme
0
1/3 bias drive
1
1/2 bias drive
No.7135-9/25
LC75863W
Display Data and Output Pin Correspondence
Output pin
COM1
COM2
COM3
Output pin
COM1
COM2
COM3
S1/P1
D1
D2
D3
S14
D40
D41
D42
S2/P2
D4
D5
D6
S15
D43
D44
D45
S3/P3
D7
D8
D9
S16
D46
D47
D48
S4/P4
D10
D11
D12
S17
D49
D50
D51
S5
D13
D14
D15
S18
D52
D53
D54
S6
D16
D17
D18
S19
D55
D56
D57
S7
D19
D20
D21
S20
D58
D59
D60
S8
D22
D23
D24
S21
D61
D62
D63
S9
D25
D26
D27
S22
D64
D65
D66
S10
D28
D29
D30
S23
D67
D68
D69
S11
D31
D32
D33
KS1/S24
D70
D71
D72
S12
D34
D35
D36
KS2/S25
D73
D74
D75
S13
D37
D38
D39
Note: This is for the case where the output pins S1/P1 to S4/P4, KS1/S24 and KS2/S25 are selected for use as segment
outputs.
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D31
D32
D33
0
0
0
The LCD segments for COM1, COM2 and COM3 are off.
0
0
1
The LCD segment for COM3 is on.
0
1
0
The LCD segment for COM2 is on.
0
1
1
The LCD segments for COM2 and COM3 are on.
1
0
0
The LCD segment for COM1 is on.
1
0
1
The LCD segments for COM1 and COM3 are on.
1
1
0
The LCD segments for COM1 and COM2 are on.
1
1
1
The LCD segments for COM1, COM2 and COM3 are on.
No.7135-10/25
LC75863W
Serial Data Output
(1) When CL is stopped at the low level
CE
CL
DI
1
B0
1
0
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
X
DO
KD1 KD2
KD27 KD28 KD29 KD30 SA
Output data
X don’t care
Note: B0 to B3, A0 to A3 ··· CCB sddress
(2) When CL is stopped at the high level
CE
CL
DI
1
B0
1
0
0
0
0
1
0
B1
B2
B3
A0
A1
A2
A3
X KD1 KD2 KD3
DO
KD28 KD29 KD30 SA
Output data
Note: B0 to B3, A0 to A3 ··· CCB sddress
X
X don’t care
• CCB address ····· 43H
• KD1 to KD30 ···· Key data
• SA ················· Sleep acknowledge data
Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep
acknowledge data (SA) will be invalid.
Output Data
(1) KD1 to KD30      Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and
one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the
relationship between those pins and the key data bits.
KI1
KI2
KI3
KI4
KI5
KS1/S24
KD1
KD2
KD3
KD4
KD5
KS2/S25
KD6
KD7
KD8
KD9
KD10
KS3
KD11
KD12
KD13
KD14
KD15
KS4
KD16
KD17
KD18
KD19
KD20
KS5
KD21
KD22
KD23
KD24
KD25
KS6
KD26
KD27
KD28
KD29
KD30
When the KS1/S24 and KS2/S25 output pins are selected to be segment outputs by control data bits K0 and K1 and
a key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to
KD10 key data bits will be set to 0.
(2) SA      Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial
data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in
sleep mode and 0 in normal mode.
No.7135-11/25
LC75863W
Sleep Mode Functions
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common
outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces
power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the
S1/P1 to S4/P4 outputs can be used as general-purpose output ports according to the state of the P0 to P2 control data
bits, even in sleep mode. (See the control data description for details.)
Key Scan Operation Functions
(1) Key scan timing
The key scan period is 288T(s). To reliably determine the on/off state of the keys, the LC75863W scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 615T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75863W cannot detect a key press shorter than 615T(s).
KS1
*3
KS2
*3
KS3
*3
1
*3
1
2
*3
2
3
*3
3
T=
1
fosc
KS4
*3
KS5
*3
4
5
Key on
*3
5
6
KS6
*3
4
6
576T[s]
Note: *3. In sleep mode the high/low state of these pins is determined by the S0 and S1 bits in the control data. Key
scan output signals are not output from pins that are set low.
(2) In normal mode
1) The pins KS1 to KS6 are set high.
2) When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key
presses are recognized by determining whether multiple key data bits are set.
1
3) If a key is pressed for longer than 615T(s) (Where T=
) the LC75863W outputs a key data read request (a
fosc
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
4) After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75863W
performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1
and 10k).
No.7135-12/25
LC75863W
Key input 1
Key input 2
Key scan
615T[s]
615T[s]
615T[s]
CE
Serial data
transfer
Serial data Key address
transfer
(43H)
Serial data
transfer Key address
Key address
DI
DO
Key data read
Key data read request
Key data read
Key data read request
Key data read
Key data read request
T=
1
fosc
(3) In sleep mode
1) The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the control data. (See the control data
description for details.)
2) If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the
OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses
are recognized by determining whether multiple key data bits are set.
1
3) If a key is pressed for longer than 615T(s)(Where T=
) the LC75863W outputs a key data read request (a
fosc
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
4) After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75863W
performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain
output, requires a pull-up resistor (between 1 and 10k).
5) Sleep mode key scan example
Example: S0 = 0, S1 = 1 (sleep with only KS6 high)
L KS1
L KS2
L KS3
When any one of these keys is pressed,
the oscillatior on the OSC pin is started
and the keys are scanned.
L KS4
L KS5
H KS6
*4
KI1
KI2
KI3
KI4
KI5
Note: *4. These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state
with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak
currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time.
No.7135-13/25
LC75863W
Key input
(KS6 line)
Key scan
615T[s]
615T[s]
CE
Serial data
transfer
Serial data Key address
transfer
(43H)
Serial data
transfer Key address
DI
T=
1
fosc
DO
Key data read
Key data read request
Key data read
Key data read request
Multiple Key Presses
Although the LC75863W is capable of key scanning without inserting diodes for dual key presses, triple key presses
on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other
than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must
be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys
should check the key data for three or more 1 bits and ignore such data.
No.7135-14/25
LC75863W
1/3 Duty, 1/2 Bias Drive Technique
fosc
384
[Hz]
VLCD
VLCD1,VLCD2
COM1
0V
VLCD
VLCD1,VLCD2
COM2
0V
VLCD
VLCD1,VLCD2
COM3
0V
LCD driver output when all LCD
segments corresponding to COM1,
COM2 and COM3 are turned off.
VLCD
VLCD1,VLCD2
LCD driver output when only LCD
segments corresponding to COM1
are on.
VLCD
VLCD1,VLCD2
LCD driver output when only LCD
segments corresponding to COM2
are on.
VLCD
VLCD1,VLCD2
LCD driver output when LCD
segments corresponding to COM1
and COM2 are on.
VLCD
VLCD1,VLCD2
LCD driver output when only LCD
segments corresponding to COM3
are on.
VLCD
VLCD1,VLCD2
LCD driver output when LCD
segments corresponding to COM1
and COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD
segments corresponding to COM2
and COM3 are on.
VLCD
VLCD1,VLCD2
LCD driver output when all LCD
segments corresponding to COM1,
COM2 and COM3 are on.
VLCD
VLCD1,VLCD2
0V
0V
0V
0V
0V
0V
0V
1/3 Duty, 1/2 Bias Waveforms
No.7135-15/25
LC75863W
1/3 Duty, 1/3 Bias Drive Technique
fosc
384
[Hz]
VLCD
VLCD1
COM1
VLCD2
0V
VLCD
VLCD1
COM2
VLCD2
0V
VLCD
VLCD1
COM3
VLCD2
0V
VLCD
LCD driver output when all LCD
segments corresponding to COM1,
COM2 and COM3 are turned off.
VLCD1
VLCD2
0V
VLCD
VLCD1
LCD driver output when only LCD
segments corresponding to COM1
are on.
VLCD2
0V
VLCD
LCD driver output when only LCD
segments corresponding to COM2
VLCD1
VLCD2
are on.
0V
VLCD
LCD driver output when LCD
segments corresponding to COM1
VLCD1
VLCD2
0V
and COM2 are on.
VLCD
LCD driver output when only LCD
segments corresponding to COM3
VLCD1
VLCD2
are on.
0V
VLCD
VLCD1
LCD driver output when LCD
segments corresponding to COM1
VLCD2
and COM3 are on.
0V
VLCD
LCD driver output when LCD
segments corresponding to COM2
VLCD1
VLCD2
0V
and COM3 are on.
VLCD
VLCD1
LCD driver output when all LCD
segments corresponding to COM1,
VLCD2
COM2 and COM3 are on.
0V
1/3 Duty, 1/3 Bias Waveforms
No.7135-16/25
LC75863W
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when logic block power is first applied and when the
voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection
voltage VDET, which is 3.0V, typical. To assure that this function operates reliably, a capacitor must be added to the
logic block power supply line so that the logic block power supply voltage VDD rise time when the logic block
power is first applied and the logic block power supply voltage VDD fall time when the voltage drops are both at
least 1 ms. (See Figure 3.)
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 3.)
 Power on: Logic block power supply (VDD) on  LCD driver block power supply (VLCD) on
 Power off: LCD driver block power supply (VLCD) off  Logic block power supply (VDD) off
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and
off at the same time.
System Reset
The LC75863W supports the reset methods described below. When a system reset is applied, display is turned off,
key scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key
scanning become possible.
(1) Reset methods
Reset at power-on and power-down
If at least 1 ms is assured as the logic block supply voltage VDD rise time when logic block power is applied, a
system reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least
1 ms is assured as the logic block supply voltage VDD fall time when logic block power drops, a system reset will
be applied in the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is
cleared at the point when all the serial data (the display data D1 to D75 and the control data) has been transferred,
i.e., on the fall of the CE signal on the transfer of the last direction data, after all the direction data has been
transferred (see Figure 3).
t1
t2
t3
t4
VDD
VDET
VDET
VLCD
VIL
CE
Display and control data transfer
D1 to D39
Internal data S0, S1, K0, K1
P0 to P2, SC, DR
Undefined
Defined
Undefined
Internal data (D40 to D75)
Undefined
Defined
Undefined
System reset period
Note: t1  1 [ms] (Logic block power supply voltage VDD rise time)
t2  0
t3  0
t4  1 [ms] (Logic block power supply voltage VDD fall time)
Figure 3
No.7135-17/25
LC75863W
S1/P1
S2/P2
S3/P3
S4/P4
S5
S23
COM1
COM2
COM3
(2) LC75863W internal block states during the reset period
1) CLOCK GENERATOR
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined
after the S0 and S1 control data bits are transferred.
2) COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
3) KEY SCAN
Reset is applied, the circuits is set to the initial state, and at the same time the key scan operation is disabled.
4) KEY BUFFER
Reset is applied and all the key data is set to low.
5) CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
Since serial data transfer is possible, these circuits are not reset.
VLCD
SEGMENT DRIVER & LATCH
VLCD1
COMMON
DRIVER
VLCD2
SHIFT REGISTER
VSS
TEST
CLOCK
GENERATOR
OSC
CONTROL
REGISTER
DO
CCB
INTERFACE
DI
KEY BUFFER
CL
CE
VDD
VDET
S24/KS1
S25/KS2
KS3
KS4
KS5
KS6
KI1
KI2
KI3
KI4
KI5
KEY SCAN
Blocks that are reset
No.7135-18/25
LC75863W
(3) Output pin states during the reset period
Output pin
State during reset
S1/P1 to S4/P4
L *5
S5 to S23
L
COM1 to COM3
L
KS1/S24, KS2/S25
L *5
KS3 to KS5
X *6
KS6
H
DO
H *7
X : don't care
Note: *5. These output pins are forcibly set to the segment output function and held low.
*6. When power is first applied, these output pins are undefined until the S0 and S1 control data bits have
been transferred.
*7. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10k is required. This
pin remains high during the reset period even if a key data read operation is performed.
Sample Application Circuit 1
1/2 bias (for use with normal panels)
(P1)
(P2)
(P3)
(P4)
VDD
OSC
COM1
COM2
*8
VSS
COM3
TEST
P1/S1
P2/S2
+5.5V
C  0.047F
VLCD
P3/S3
VLCD1
P4/S4
S5
VLCD2
C
S23
CE
From the
controller
To the controller
To the controller
power supply
Used with the
backlight controller
or other circuit.
LCD panel (up to 75 segments)
+5V
(general-purpose
output ports)
CL
DI
DO
KK K KK
I I I I I
5 4 3 2 1
S
2
5
/
K K KK K
S S SS S
6 5 4 3 2
S
2
4
/
K
S
1
(S24)
(S25)
*9
Key matrix
(up to 30 keys)
Note: *8. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD
rise time when power is applied and the logic block power supply voltage VDD fall time when power
drops are both at least 1 ms, as the LC75863W is reset by the VDET.
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to
10k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
No.7135-19/25
LC75863W
Sample Application Circuit 2
1/2 bias (for use with large panels)
(P1)
(P2)
(P3)
(P4)
VDD
OSC
COM1
*8
COM2
VSS
10k  R  1k
C  0.047F
+5.5V
R
C
R
TEST
COM3
P1/S1
P2/S2
VLCD
P3/S3
P4/S4
VLCD1
S5
VLCD2
S23
CE
From the
controller
CL
DI
To the controller
To the controller
power supply
Used with the
backlight controller
or other circuit.
LCD panel (up to 75 segments)
+5V
(general-purpose
output ports)
DO
KK K KK
I I I I I
5 4 3 2 1
S
2
5
/
K K KK K
S S SS S
6 5 4 3 2
S
2
4
/
K
S
1
(S24)
(S25)
*9
Key matrix
(up to 30 keys)
Note: *8. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD
rise time when power is applied and the logic block power supply voltage VDD fall time when power
drops are both at least 1 ms, as the LC75863W is reset by the VDET.
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to
10k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
No.7135-20/25
LC75863W
Sample Application Circuit 3
1/3 bias (for use with normal panels)
(P1)
(P2)
(P3)
(P4)
VDD
OSC
COM1
*8
COM2
VSS
+5.5V
TEST
COM3
P1/S1
P2/S2
VLCD
P3/S3
P4/S4
VLCD1
C  0.047F
S5
VLCD2
C
C
S23
CE
From the
controller
CL
To the controller
DO
To the controller
power supply
Used with the
backlight controller
or other circuit.
LCD panel (up to 75 segments)
+5V
(general-purpose
output ports)
DI
KK K KK
I I I I I
5 4 3 2 1
S
2
5
/
K K KK K
S S SS S
6 5 4 3 2
S
2
4
/
K
S
1
(S24)
(S25)
*9
Key matrix
(up to 30 keys)
Note: *8. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD
rise time when power is applied and the logic block power supply voltage VDD fall time when power
drops are both at least 1 ms, as the LC75863W is reset by the VDET.
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to
10k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
No.7135-21/25
LC75863W
Sample Application Circuit 4
1/3 bias (for use with large panels)
(P1)
(P2)
(P3)
(P4)
OSC
COM1
COM2
*8
10k  R  1k
C  0.047F
VSS
COM3
TEST
P1/S1
P2/S2
VLCD
+5.5V
P3/S3
R
P4/S4
VLCD1
S5
R
VLCD2
C
C
R
S23
CE
From the
controller
CL
To the controller
DO
To the controller
power supply
DI
KK K KK
I I I I I
5 4 3 2 1
Used with the
backlight controller
or other circuit.
LCD panel (up to 75 segments)
VDD
+5V
(general-purpose
output ports)
S
2
5
/
K K KK K
S S SS S
6 5 4 3 2
S
2
4
/
K
S
1
(S24)
(S25)
*9
Key matrix
(up to 30 keys)
Note: *8. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD
rise time when power is applied and the logic block power supply voltage VDD fall time when power
drops are both at least 1 ms, as the LC75863W is reset by the VDET.
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to
10k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
Notes on transferring display data from the controller
The display data (D1 to 75) is transferred to the LC75863W in two operations. All of the display data should be
transferred within 30ms to maintain the quality of the displayed image.
No.7135-22/25
LC75863W
Notes on the Controller Key Data Read Techniques
(1) Timer based key data acquisition
1) Flowchart
CE = L
NO
DO = L
YES
Key data read
processing
2) Timing chart
Key on
Key on
Key input
Key scan
t5
t6
t5
t5
CE
t8
Key
address
DI
t7
t8
Key data read
t8
t7
t7
DO
Key data read request
t9
Controller
datermination
(Key on)
t9
Controller
datermination
(Key on)
t9
Controller
datermination
(Key off)
t9
Controller
datermination
(Key on)
Controller
datermination
(Key off)
t5 ···· Key scan execution time when the key data agreed for two key scans. (615T(s))
t6 ···· Key scan execution time when the key data did not agree for two key scans and the key scan was
executed again. (1230T(s))
1
t7 ···· Key address (43H) transfer time
T = fosc
t8 ···· Key data read time
3) Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller
must check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a
key has been pressed and executes the key data read operation.
The period t9 in this technique must satisfy the following condition.
t9 > t6 + t7 + t8
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
No.7135-23/25
LC75863W
(2) Interrupt based key data acquisition
1) Flowchart
CE = L
NO
DO = L
YES
Key data read
processing
Wait for at
least t10
CE = L
NO
DO = H
YES
Key OFF
2) Timing chart
Key on
Key on
Key input
Key scan
t5
t5
t6
t5
CE
t8
Key
address
DI
t7
t8
Key data read
t8
t7
t7
t8
t7
DO
Key data read request
t10
Controller
datermination
(Key on)
Controller
datermination
(Key off)
t10
Controller
datermination
(Key on)
Controller
datermination
(Key on)
t10
Controller
datermination
(Key on)
t10
Controller
datermination
(Key off)
t5 ···· Key scan execution time when the key data agreed for two key scans. (615T(s))
t6 ···· Key scan execution time when the key data did not agree for two key scans and the key scan was
executed again. (1230T(s))
1
t7 ···· Key address (43H) transfer time
T = fosc
t8 ···· Key data read time
No.7135-24/25
LC75863W
3) Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller
must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and
executes the key data read operation. After that the next key on/off determination is performed after the time t10
has elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique
must satisfy the following condition.
t10 > t6
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
ORDERING INFORMATION
Device
LC75863W-E
Package
SQFP48(7X7)
(Pb-Free)
LC75863WS-E
SQFP48(7X7)
(Pb-Free)
Shipping (Qty / Packing)
50 / Tray Foam
50 / Tray Foam
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PS No.7135-25/25
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