Sanyo LC868012A 8-bit single chip microcontroller with 16/12/08k-byte rom and 640-byte ram on chip Datasheet

Ordering number : ENN*6723
CMOS IC
LC868016/12/08A
8-Bit Single Chip Microcontroller with
16/12/08K-Byte ROM and 640-Byte RAM On Chip
Preliminary
Overview
The LC868016A/12A/08A microcontrollers are 8-bit single chip microcontrollers with the following on-chip functional
blocks :
- CPU : Operable at a minimum bus cycle time of 0.5µs (microseconds)
- On-chip ROM maximum capacity : 16K bytes
- On-chip RAM capacity : 640 bytes
- Dot-matrix liquid crystal display (LCD) automatic display controller / driver
- External memory
- 16-bit timer / counter (or two 8-bit timers)
- 16-bit timer / PWM (or two 8-bit timers)
- Two 8-bit synchronous serial-interface circuits
- 13-source 9-vectored interrupt system
All of the above functions are fabricated on a single chip.
Ver.1.12
61298
91400 RM (IM) HO No.6723-1/28
LC868016/12/08A
Features
16384 × 8 bits
12288 × 8 bits
8192 × 8 bits
(1) Read Only Memory (ROM)
: LC868016A
: LC868012A
: LC868008A
(2) Random Access Memory (RAM)
: 512 × 8 bits (calculation area)
128 × 8 bits (display area)
(3) Bus Cycle Time / Instruction Cycle Time
Bus cycle time
Instruction cycle time
System clock oscillation
Oscillation frequency
Voltage
Note
0.5µs
1µs
Ceramic (CF)
4.5-6.0V
2.0µs
4µs
Ceramic (CF)
7.5µs
3.8µs
183µs
91.5
15µs
7.5µs
366µs
183µs
Internal RC
12MHz
6MHz
3MHz
1.5MHz
800kHz
Crystal (XTAL)
32.768kHz
2.5-6.0V
OCR7=0
OCR7=1
OCR7=0
OCR7=1
OCR7=0
OCR7=1
OCR7=0
OCR7=1
2.5-6.0V
2.5-6.0V
* Bus cycle time means ROM-read period.
OCR7 : Bit-7 of the oscillation control register.
(4) Ports
- Input / output ports
: 6 ports (47 terminals)
Input/output port programmable in a nibble
: 1 port (8 terminals)
Input/output port programmable every function unit : 1 port (7 terminals)
Input/output port programmable in a bit
: 4 ports (32 terminals)
- Input port
: 1 port (4 terminals)
- Ports at external memory mode
1. External Latch
Port 0 : Address output of lower 8-bit, input/output of data
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output
2. No External Latch
Port 0 : Input/output of data
Port 3 : Address output of lower 8-bit
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output
(Set whether the external latch is used or not by program.)
- LCD segment driver output ports
: 48 terminals
(Function change available : segment/common)
- LCD common driver output ports
: 16 terminals
(1/64 duty maximum : at using segment output ports as common output by mask option)
(5) External memory access
- External program memory access function
External program memory capacity : 64K bytes
Programable switch internal program/external program
(At initial : Internal program)
Enable/disable control of external program --> internal program memory switch
No.6723-2/28
LC868016/12/08A
Ports
Port 2 : Address output of upper 8-bit
Uses EROE terminal ( OE signal of the external ROM)
1. Using the external latch
Port 0 : Address output of lower 8-bit, data input port
Uses the ADLC terminal (latch clock of the lower 8-bit address signal)
2. Not use the external latch
Port 0 : Input port of data
Port 3 : Address output of lower 8-bit
- External data memory access function
Using the LDC instruction
External memory capacity : 16M bytes
1. Internal program memory
Switch the reference of internal ROM data/external ROM data by program.
2. External program memory
Reference external ROM data only.
Ports
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output
Uses EROE terminal ( OE signal of the external ROM)
1. Using external latch
Port 0 : Address output of lower 8-bit, input port of data
Uses the ADLC terminal (latch clock of the lower 8-bit address signal)
2. Not use external latch
Port 0 : Input port of data
Port 3 : Address output of lower 8-bit
- External RAM memory access function
Using the LDX, STX instruction
External memory capacity : 16M bytes
Ports
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output
Uses the P46 terminal ( OE signal of external RAM) : the LDX instruction execution
Uses the P47 terminal ( WE signal of external RAM) : the STX instruction execution
1. Using the external latch circuit
Port 0 : Address output of lower 8-bit, input/output port of data
Uses the ADLC terminal (latch clock of the lower 8-bit address signal)
2. Not use the external latch circuit
Port 0 : Input/output port of data
Port 3 : Address output of lower 8-bit
(6) LCD automatic display controller
- Display duty
: 1/1 - 1/64 duty
- Display bias
: 1/4, 1/5, 1/7, 1/9 bias
- Programmable character display / graphic display
- Character display
1. On-chip character generator ROM
ROM capacity
: 8960 bits
Character font
: 5 × 7 dots
Number of Characters
: 256
2. LCD instruction
Display
: ON/OFF
Cursor
: ON/OFF/BLINK
Character blink
: ON/OFF
Character scroll
: Control by specified starting address
No.6723-3/28
LC868016/12/08A
- Graphic display
LC868000 series
: 1024 dots Maximum
External segment driver : Enable to extend of LCD drive
- LCD contrast
LCD display contrast programmable
- LCD display power supply
Doubler/Tripler circuit programmable
Doubler voltage in the tripler mode must not be used for LCD display power supply
If doubler voltage is used for LCD display power supply, the doubler mode must be selected by user program.
- LCD driver
Following three kinds of combination can be selected by mask option
No.
Segment output port
Common output port
1
2
3
48
32
0
16
32
64
(7) Serial-interface
- Two 8-bit serial-interface circuits
LSB first / MSB first function available
- Internal 8-bit baud-rate generator in common with two serial-interface circuits
(8) Timers
- Timer0 (T0L, T0H)
16-bit timer / counter
2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
- Timer1 (T1L, T1H)
16-bit timer / PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9-16 bits)
- Base timer
Every 500ms overflow system for a clock application (using 32.768kHz crystal oscillation for Base timer clock)
The Base timer clock selectable ; 32.768kHz crystal oscillation, System clock, and programmable prescaler output of
Timer 0
(9) Buzzer output
- The Buzzer sound frequency selectable ; 4KHz, 2KHz
(10) Remote control receiver circuit (using P73/INT3/T0IN terminal)
- Noise rejection available
- The interrupt polarity selectable
(11) Watchdog timer
- The watchdog timer is taken on RC outside. (using P70/INT0 terminal)
- Watchdog timer operation selectable : interrupt system, system reset
No.6723-4/28
LC868016/12/08A
(12) Interrupts system
- 13-source 9-vectored interrupts :
1. External interrupt INT0 (includes watchdog timer)
2. External interrupt INT1
3. External interrupt INT2, timer / counter T0L (timer 0 lower 8 bits)
4. External interrupt INT3, base timer
5. Timer / counter T0H (timer 0 upper 8-bit)
6. Timer T1L (timer 1 lower 8-bit), Timer T1H (timer 1 upper 8-bit)
7. Serial interface SIO0
8. Serial interface SIO1
9. Port 0 or Port 3
- Interrupt priority control available
Microcomputer allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. It can
specify a low level or a high level interrupt priority from INT2/T0L through port 0 or port 3 (the above interrupt
number from three through nine). It can also specify a low level or the highest level interrupt priority to INT0 and
INT1.
(13) Sub-routine stack levels
- 128 levels (Max.) : stack area included in RAM area
(14) Multiplication and division
- 16 bits × 8-bit (7 instruction cycle times)
- 16 bits / 8-bit (7 instruction cycle times)
(15) Three oscillation circuits
- On-chip RC oscillation circuit using for the system clock, for the LCD display and for the step-up circuit.
- On-chip CF oscillation circuit using for the system clock and for the LCD display.
- On-chip crystal oscillation circuit using for the system clock, for time-base clock and for the LCD display.
(16) Standby function
- HALT mode function
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This operation mode can be released by the interrupt request signals or setting to low level for the reset terminal
( RES ).
- HOLD mode function
The HOLD mode is used to freeze all the oscillations ;
RC (internal), CF and Crystal oscillations. This mode can be released by the following operations:
• Reset terminal ( RES ) set to low level.
• Set to assigned level to INT0/1 terminals.
• Set to assigned level to Port 0/3.
(17) Factory shipment
- Chip
QIC160 package shipping available for sample evaluation.
(18) Development support tools
- Evaluation (EVA) chip
- Emulator
: LC868099
: EVA86000 + ECB868000 (Evaluation chip board)
No.6723-5/28
LC868016/12/08A
VDD
P30
P31
P32
P33
P34
P35
P36
P37
P00
P01
P02
P03
P04
P05
P06
P07
P20
P21
P22
P23
P24
P25
P26
P27
ADLC
EROE
RES
XT1
XT2
VSS
CF1
CF2
Pin Assignment
106
VDD
P50
1
S1
P51
S2
P52
S3
P53
S4
P54
S5
P55
S6
P56
S7
P57
S8
P17/PWM
S9
P16/BUZ
S10
P15/SCK1
S11
P14/SI1/SB1
S12
P13/SO1
S13
P12/SCK0
S14
P11/SI0/SB0
S15
P10/SO0
S16
P73/INT3/T0IN
P72/INT2/T0IN
S17
S18
P71/INT1
(X, Y) = (0, 0)
S19
P70/INT0
S20
P47/WR
S21
P46/RD
S22
P44/FRM
S23
P43/M
S24
P42/DO
S25
P41/CL2
S26
P40/CL1
S27
VSS
S28
CUP1
S29
CUP2
S30
VOUT2
S31
VOUT3
S32
TEST
TEST
S33
S34
66
VLCD
V5
V4
V3
V2
V1
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
36
No.6723-6/28
LC868016/12/08A
Pad Name and coordinates table
Pad
No.
Name
1
2
Coordinates
Xµm
Yµm
Pad
No.
Name
VDD
-2960
2695
47
S1
-2960
2505
48
Coordinates
Pad
No.
Name
Coordinates
Xµm
Yµm
Xµm
Yµm
S46
-1075
-3630
93
P13
2845
500
S47
-915
-3630
94
P14
2845
675
3
S2
-2960
2345
49
S48
-750
-3630
95
P15
2845
855
4
S3
-2960
2180
50
C16
-590
-3630
96
P16
2845
1035
5
S4
-2960
2020
51
C15
-425
-3630
97
P17
2845
1215
6
S5
-2960
1855
52
C14
-265
-3630
98
P57
2845
1400
7
S6
-2960
1695
53
C13
-100
-3630
99
P56
2845
1580
8
S7
-2960
1530
54
C12
60
-3630
100
P55
2845
1760
9
S8
-2960
1370
55
C11
225
-3630
101
P54
2845
1935
10
S9
-2960
1205
56
C10
385
-3630
102
P53
2845
2115
11
S10
-2960
1045
57
C9
550
-3630
103
P52
2845
2295
12
S11
-2960
880
58
C8
710
-3630
104
P51
2845
2475
13
S12
-2960
720
59
C7
875
-3630
105
P50
2845
2650
14
S13
-2960
555
60
C6
1035
-3630
106
VDD
2965
3530
15
S14
-2960
395
61
C5
1200
-3630
107
P30
2800
3530
16
S15
-2960
230
62
C4
1360
-3630
108
P31
2620
3530
17
S16
-2960
70
63
C3
1525
-3630
109
P32
2445
3530
18
S17
-2960
-95
64
C2
1685
-3630
110
P33
2265
3530
19
S18
-2960
-255
65
C1
1850
-3630
111
P34
2085
3530
20
S19
-2960
-420
66
V1
2055
-3445
112
P35
1905
3530
21
S20
-2960
-580
67
V2
2220
-3445
113
P36
1730
3530
22
S21
-2960
-745
68
V3
2380
-3445
114
P37
1550
3530
23
S22
-2960
-905
69
V4
2545
-3445
115
P00
1370
3530
24
S23
-2960
-1070
70
V5
2705
-3445
116
P01
1190
3530
25
S24
-2960
-1230
71
VLCD
2870
-3445
117
P02
1015
3530
26
S25
-2960
-1395
72
TEST
2915
-3180
118
P03
835
3530
27
S26
-2960
-1555
73
TEST
2915
-2995
119
P04
655
3530
28
S27
-2960
-1720
74
VOUT3
2820
-2810
120
P05
475
3530
29
S28
-2960
-1880
75
VOUT2
2820
-2650
121
P06
300
3530
30
S29
-2960
-2045
76
CUP2
2820
-2485
122
P07
120
3530
31
S30
-2960
-2205
77
CUP1
2820
-2325
123
P20
-60
3530
32
S31
-2960
-2370
78
VSS
2845
-2120
124
P21
-240
3530
33
S32
-2960
-2530
79
P40
2845
-1945
125
P22
-415
3530
34
S33
-2960
-2695
80
P41
2845
-1765
126
P23
-595
3530
35
S34
-2960
-2855
81
P42
2845
-1585
127
P24
-775
3530
36
S35
-2865
-3630
82
P43
2845
-1410
128
P25
-955
3530
37
S36
-2700
-3630
83
P44
2845
-1230
129
P26
-1130
3530
38
S37
-2540
-3630
84
P46
2845
-1050
130
P27
-1310
3530
39
S38
-2375
-3630
85
P47
2845
-870
131
ADLC
-1490
3530
40
S39
-2215
-3630
86
P70
2845
-690
132
EROE
-1670
3530
41
S40
-2050
-3630
87
P71
2845
-525
133
RES
-1845
3530
42
S41
-1890
-3630
88
P72
2845
-365
134
XT1
-2025
3530
43
S42
-1725
-3630
89
P73
2845
-200
135
XT2
-2205
3530
44
S43
-1565
-3630
90
P10
2845
-40
136
VSS
-2385
3530
45
S44
-1400
-3630
91
P11
2845
140
137
CF1
-2560
3530
46
S45
-1240
-3630
92
P12
2845
320
138
CF2
-2740
3530
Note ; Connect the substrate of chip to VDD (or open).
No.6723-7/28
LC868016/12/08A
System Block Diagram
Interrupt Control
IR
CF
RC
ROM
Clock
Generator
Standby Control
PLA
PC
X'tal
Base Timer
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 7
C Register
Timer 0
ALU
Timer 1
Port 2
Port 3
PSW
INT0-3
Noise Rejection Filter
Port 4
RAR
XRAM
128 Bytes
Port 5
RAM
Stack Pointer
CGROM
Port 0
LCD Display
Controller
EXT Register
Watchdog Timer
LCD Driver
No.6723-8/28
LC868016/12/08A
Pin Description
No.
I/O
VSS
VDD
VLCD
V1 to 5
VOUT2,3
CUP1,2
Port0
Name
78,136
1,106
71
66-70
75,74
77,76
I/O
P00 to P07
115-122
Port1
P10 to P17
90-97
Port2
P20 to P27
123-130
Port3
P30 to P37
107-114
I/O
I/O
I/O
Function description
Option
Power terminal (-)
Power terminal (+)
Power terminal (-) for LCD driver
Voltage supply terminals to LCD drivers
Output terminals for doubler, tripler
Capacitor connecting terminals for doubler, tripler
•8-bit input/output port
•Input/output can be specified in 4-bit
•External memory mode
1. EXT resistor bit 2=0
Address output of lower 8-bit, input/output
of data
2. EXT resistor bit 2=1
•Input/output of data
•Input for key interrupt (P30INT=0)*
•8-bit input/output port
•Input/output can be specified in a bit
•Another functions
P10 SIO0 data output
P11 SIO0 data input, bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input, bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer 1 output (PWM output)
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/N-ch open drain
•8-bit input/output port
•Input/output can be specified in a bit
•External memory mode
Address output of upper 8-bit
•8-bit input/output port
•Input/output in a bit
•External memory mode
1. EXT resistor bit 2=0 : input/output port
2. EXT resistor bit 2=1 : address output of lower
8-bit for external memory
•Input for key interrupt (P30INT=L)*
•Output form :
CMOS/N-ch open drain
•Output form :
CMOS/N-ch open drain
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/N-ch open drain
*P30INT : Bit 0 of Port 3 interrupt control register.
No.6723-9/28
LC868016/12/08A
Name
No.
Port4
P40 to P44
P46, P47
79-83
84,85
Port5
P50 to P57
105-98
I/O
I/O
Port7
P70 to P73
I/O
I
86-89
Function description
•7-bit input/output port
•Input/output can be specified each upper
2 bits and lower 5 bits
•Another functions
P40 CL1
Latch clock
P41 CL2
Shift clock
P42 DO
Output data
P43 M
Alternate signal
P44 FRM Frame signal
RD
Read signal
P46
WR
Write signal
P47
(P40-P44 : LCD display extend signal,
P46, P47 : External RAM access signal)
•8-bit input/output port
•Input/output in bit unit
•External memory mode
1. EXT resistor bit 3=0 : input/output
2. EXT resistor bit 3=1 : bank address output for
external memory
•4-bit input port
•Another functions
P70 INT0 input/HOLD release/N-ch Tr.
output for watchdog timer
P71 INT1 input/HOLD release
P72 INT2 input/timer 0 event input
P73 INT3 input with noise filter/timer 0
event input
•Interrupt received form, vector address
leading trailing leading
high
low
&
level
level
trailing
INT0
enable enable disable enable enable
INT1
enable enable disable enable enable
INT2
enable enable enable disable disable
INT3
enable enable enable disable disable
Option
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/N-ch open drain
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/N-ch open drain
•Pull-up resistor :
Provided/Not provided
vector
03H
0BH
13H
1BH
No.6723-10/28
LC868016/12/08A
Name
No.
I/O
65-50
2-49
O
O
LCD output terminals for common
LCD output terminals for segment
RES
ADLC
EROE
XT1
133
131
132
134
I
O
O
I
XT2
135
O
CF1
137
I
CF2
138
O
Reset
Address control signal for external memory
Enable signal of external ROM output
Input for 32.768kHz crystal oscillation
In case of non use, connect to VDD
Output for 32.768kHz crystal oscillation
In case of non use, should be left unconnected
Input for ceramic resonator oscillation
In case of non use, connect to VDD
Output for ceramic resonator oscillation
In case of non use, should be left unconnected
C1 to C16
S1 to S48
Function description
Option
LCD output terminals :
segment/common
-
* Port options can be specified in a bit.
* A state of port at initial
Pin name
Input/output mode
Port 0, 7
Ports 1, 2
Ports 3, 5
Port 4
Input
Input
Fixed pull-up resistor exist
Programmable pull-up resistor OFF
Input
Programmable pull-up resistor ON
Name
Output level
C1 to C16
S1 to S48
VDD (Display OFF)
VDD (Display OFF)
A state of pull-up resistor specified at pull-up option
No.6723-11/28
LC868016/12/08A
1. Absolute Maximum Ratings at VSS=0V and Ta=25°C
Parameter
Supply voltage
Input voltage
Output voltage
Input/output
voltage
High
Peak
level
output
output current
current Total
output
current
Low
level
output
current
Peak
output
current
Total
output
current
Operating
temperature
range
Storage
temperature
range
Symbol
Pins
Conditions
Ratings
VDD[V]
min.
VDDMAX VDD
VI(1)
•Ports 71,72,73
• RES
VI(2)
VLCD
VO(1)
•C1 to C16
•S1 to S48
VO(2)
•VOUT2,VOUT3
•CUP1,CUP2
VO(3)
ADLC, EROE
VIO(1)
•Ports 0,1,2,3,4,5
•Port 70
IOPH(1)
•Ports 0,1,2,3,4,5
•ADLC, EROE
•CMOS output
•At each pin
-4
ΣIOAH(1)
Total all pins
-25
Total all pins
At each pin
-25
ΣIOAH(2)
IOPL(1)
IOPL(2)
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
ΣIOAL(5)
ΣIOAL(6)
ΣIOAL(7)
Topr
Tstg
•Ports 0,2,3
•C1-C16,S1-S48
•ADLC, EROE
Ports 1, 4, 5
•Ports 0,1,2,3,4,5
•ADLC, EROE
Port 70
Port 0
•Port 2
•ADLC, EROE
Port 3
Ports 1, 5
Port 4
Port 70
C1-C16,S1-S48
typ.
max.
-0.3
-0.3
+7.0
VDD+0.3
VDD-21
VLCD-0.3
VDD+0.3
VDD+0.3
VDD-21
VDD+0.3
-0.3
-0.3
VDD+0.3
VDD+0.3
unit
V
mA
20
At each pin
Total all pins
Total all pins
15
40
40
Total all pins
Total all pins
Total all pins
Total all pins
Total all pins
-30
40
40
40
15
30
+70
-55
+125
°C
Notes :
The specifications above are for a die mounted in a QIC160 type package.
However, we ship this product as a die only, not a package chip.
Therefore, the operational characteristics may vary depending on the user’s packaging techniques.
No.6723-12/28
LC868016/12/08A
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V
Parameter
Operating
supply voltage
range
Symbol
VDD(1)
Pins
VDD(3)
Hold voltage
VHD
VDD
LCD display
voltage
Input high
voltage
VLCD
VLCD
VIH(1)
Port 0
VIH(2)
•Ports 1,2,4,5
•Ports 72,73
(Schmitt)
•Port 70 for
Port input/interrupt
•Port 71
• RES (Schmitt)
Port 70 for watchdog
timer
Port 3
Port 0 (Schmitt)
•Ports 1,2,4,5
•Ports 72,73 (Schmitt)
•Port 70
Port input/interrupt
•Port 71
• RES
Port 70 for watchdog
timer
Port 3
VIH(4)
Input low
voltage
VIH(5)
VIL(1)
VIL(2)
VIL(3)
VIL(4)
Operation
cycle time
Oscillation
frequency
range
(Note 1)
VIL(5)
tCYC
(Schmitt)
FmCF(1)
CF1, CF2
FmCF(2)
CF1, CF2
FmCF(3)
CF1, CF2
FmRC
FsXtal
VDD[V]
0.98µs ≤ tCYC ≤
400µs
1.9µs ≤ tCYC ≤
400µs
3.9µs ≤ tCYC ≤
400µs
RAMs and the
registers hold
voltage at HOLD
mode.
VDD
VDD(2)
VIH(3)
Conditions
XT1, XT2
min.
4.5
Ratings
typ.
max.
6.0
4.5
6.0
2.5
6.0
2.0
6.0
-2VDD
-VDD
0.4VDD
+0.9
2.5-6.0 0.75VDD
VDD-4.5
VDD-4.5
VDD
Output N-channel
Tr. OFF
2.5-6.0 0.75VDD
VDD
Output N-channel
Tr. OFF
Output disable
Output disable
Output disable
2.5-6.0
VDD
Output disable
Output disable
4.5-6.0
2.5-4.5
2.5-6.0
unit
V
VDD
0.9VDD
2.5-6.0 0.75VDD
2.5-6.0
VSS
2.5-6.0
VSS
VDD
0.2VDD
0.25VDD
Output N-channel
Tr. OFF
2.5-6.0
VSS
0.25VDD
Output N-channel
Tr. OFF
Output disable
2.5-6.0
VSS
2.5-6.0
4.5-6.0
2.5-6.0
4.5-6.0
VSS
0.98
3.9
11.76
12
0.8VDD
-1.0
0.25VDD
400
µs
400
12.24 MHz
4.5-6.0
5.88
6
6.12
2.5-6.0
2.94
3
3.06
2.5-4.5
4.5-6.0
1.0
0.8
1.4
1.3
2.0
1.8
2.5-4.5
4.5-6.0
0.5
0.4
0.9
0.75
1.2
1.0
•12MHz
(ceramic resonator
oscillation)
•Refer to figure 1
•6MHz
(ceramic resonator
oscillation)
•Refer to figure 1
•3MHz
(ceramic resonator
oscillation)
•Refer to figure 1
•Internal RC
oscillation Mask
option is ‘High’
•Internal RC
oscillation Mask
option is ‘Low’
•32.768kHz
(crystal oscillation)
•Refer to figure 2
2.5-6.0
32.768
kHz
Continue.
No.6723-13/28
LC868016/12/08A
Parameter
Symbol
Pins
Oscillation
stabilizing
time period
(Note 1)
tmsCF(1)
CF1, CF2
tmsCF(2)
CF1, CF2
tmsCF(3)
CF1, CF2
tssXtal
XT1, XT2
Conditions
•12MHz
(ceramic resonator
oscillation)
•Refer to figure 3
•6MHz
(ceramic resonator
oscillation)
•Refer to figure 3
•3MHz
(ceramic resonator
oscillation)
•Refer to figure 3
•32.768kHz
(crystal oscillation)
•Refer to figure 3
Ratings
VDD[V]
min.
typ.
max.
4.5-6.0
0.02
0.3
4.5-6.0
0.02
0.3
4.5-6.0
2.5-6.0
0.1
0.1
1
3
4.5-6.0
2.5-6.0
1
1
1.5
3
unit
ms
s
(Note 1) The oscillation constant is shown on table 1 and table 2.
No.6723-14/28
LC868016/12/08A
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter
Input high
current
Input low
current
Output high
voltage
Output low
voltage
Symbol
Pins
IIH(1)
•Ports 1,2,3,4,5
•Port 0 without
pull-up MOS Tr.
IIH(2)
Port 7 without
pull-up MOS Tr.
IIH(3)
IIL(1)
RES
•Ports 1,2,3,4,5
•Port 0 without
pull-up MOS Tr.
IIL(2)
Port 7 without
pull-up MOS Tr.
IIL(3)
VOH(1)
VOH(2)
VOH(3)
VOH(4)
RES
Port 0 of
CMOS output
VOL(1)
VOL(2)
VOL(3)
•Ports 1,2,3,4,5 of
CMOS output
•ADLC, EROE
•Ports 0,1,2,3,4,5
•ADLC, EROE
VOL(4)
VOL(5)
Rpu
Port 70
Hysteresis
voltage
VHIS
Pin
capacitance
CP
•Ports 0,1,2,3,4,5
•Port 7
• RES
All pins
Pull-up MOS
Tr. resistor
•Ports 0,1,2,3,4,5
•Port 7
Conditions
•Output disable
•Pull-up MOS Tr. OFF
•VIN=VDD
(including the offleak current of the
output Tr.)
•Output Nch Tr. OFF
•VIN=VDD
(including the offleak current of the
output Tr.)
VIN=VDD
•Output disable
•Pull-up MOS Tr. OFF
•VIN=VSS
(including the offleak current of the
output Tr.)
•Output Nch Tr. OFF
•VIN=VSS
(including the offleak current of the
output Tr.)
VIN=VSS
IOH=-10mA
IOH=-1mA
IOH=-1.0mA
IOH=-0.1mA
IOL=10mA
IOL=1.6mA
•IOL=1.0mA
•The current of any
measurement pin is
not over 1mA.
IOL=1mA
IOL=0.5mA
VOH=0.9VDD
Output disable
•f=1MHz
•Unmeasurement
terminals for the
input are set to
VSS level.
•Ta=25°C
Ratings
VDD[V]
min.
typ.
max.
2.5-6.0
1
2.5-6.0
1
2.5-6.0
2.5-6.0
-1
2.5-6.0
-1
µA
1
2.5-6.0
-1
4.5-6.0 VDD-1.5
2.5-6.0 VDD-0.4
4.5-6.0 VDD-1
2.5-6.0 VDD-0.5
V
4.5-6.0
4.5-6.0
2.5-6.0
1.5
0.4
0.4
4.5-6.0
2.5-6.0
4.5-6.0
2.5-4.5
2.5-6.0
0.4
0.4
70
120
2.5-6.0
unit
15
25
40
60
0.1VDD
10
kΩ
V
pF
No.6723-15/28
LC868016/12/08A
Serial output
Serial input
Symbol
Cycle
Low Level
pulse width
High Level
pulse width
Cycle
Low Level
pulse width
High Level
pulse width
Data set up time
tCKCY(1)
tCKL(1)
Data hold time
tCKI
Output delay time
(Serial clock is
external clock)
tCKO(1)
Input clock
Parameter
Output clock
Serial clock
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=0V
Output delay time
(Serial clock is
internal clock)
Pins
SCK0,
SCK1
Conditions
Refer to figure 5.
Ratings
VDD[V]
min.
2.5-6.0
2
1
tCKH(1)
tCKCY(2)
tCKL(2)
tCKO(2)
max.
unit
tCYC
1
SCK0,
SCK1
•Use pull-up
resistor (1kΩ)
when Nch opendrain output.
•Refer to figure 5.
2.5-6.0
•SI0,SI1
•SB0,SB1
•Data set-up to
SCK0,1
•Data hold from
SCK0,1
•Refer to figure 5.
4.5-6.0
2.5-6.0
4.5-6.0
2.5-6.0
•SO0,SO1
•SB0,SB1
•Data set-up to
SCK0,1
•Use pull-up
resistor (1kΩ)
when Nch opendrain output.
•Refer to figure 5.
•Data hold from
SCK0,1
•Use pull-up
resistor (1kΩ)
when Nch opendrain output.
•Refer to figure 5.
4.5-6.0
7/12
tCYC
2.5-6.0
7/12
tCYC
tCKH(2)
tICK
typ.
•SO0,SO1
•SB0,SB1
2
1/2
tCKCY
1/2
tCKCY
µs
0.1
0.4
0.1
0.4
+0.2
+1
4.5-6.0
1/3
tCYC
+0.2
2.5-6.0
1/3
tCYC
+1
No.6723-16/28
LC868016/12/08A
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=0V
Parameter
Symbol
Pins
High/low level
pulse width
tPIH(1)
tPIL(1)
•INT0, INT1
•INT2/T0IN
•Refer to figure 6
•INT3/T0IN
(The noise rejection
clock is selected to
1/1.)
•Refer to figure 6
•INT3/T0IN
(The noise rejection
clock is selected to
1/16.)
•Refer to figure 6
•INT3/T0IN
(The noise rejection
clock is selected to
1/64.)
•Refer to figure 6
• RES
•Refer to figure 6
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
Conditions
Ratings
VDD[V]
min.
•Interrupt acceptable
•Timer0-countable
2.5-6.0
1
•Interrupt acceptable
•Timer0-countable
2.5-6.0
2
•Interrupt acceptable
•Timer0-countable
2.5-6.0
32
•Interrupt acceptable
•Timer0-countable
2.5-6.0
128
Reset acceptable
2.5-6.0
200
typ.
max.
unit
tCYC
µs
No.6723-17/28
LC868016/12/08A
6. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter
Current
dissipation
during basic
operation
(Note 2)
Symbol
IDDOP(1)
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
IDDOP(8)
IDDOP(9)
IDDOP(10)
IDDOP(11)
IDDOP(12)
IDDOP(13)
IDDOP(14)
IDDOP(15)
IDDOP(16)
IDDOP(17)
Pins
Ratings
Conditions
OCR7 VDD[V] min.
VDD •FmCF=12MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
12MHz
•Internal RC
oscillation stops
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
6MHz
•Internal RC
oscillation stops
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
3MHz
•Internal RC
oscillation stops
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
Mask option
is “High”
Mask option
is “Low”
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
typ.
max.
0
4.5-6.0
10
25
1
4.5-6.0
10
25
0
1
0
4.5-6.0
3
6
1.5
9
15
5
1.2
2.0
0.7
1.4
0.7
1.2
0.4
0.8
38
60
15
25
5.8
7.8
4.8
6.2
3.4
4.5
2.8
3.6
150
300
70
120
0
1
0
1
0
1
0
1
0
1
0
1
2.5-4.5
4.5-6.0
2.5-4.5
4.5-6.0
2.5-4.5
4.5-6.0
2.5-4.5
unit
mA
µA
*OSCR : Bit 7 of the oscillation control register.
Continue.
No.6723-18/28
LC868016/12/08A
Parameter
Symbol
Pins
Conditions
Current
IDDHALT(1) VDD •HALT mode
dissipation
•FmCF=12MHz
in HALT
Ceramic resonator
mode
oscillation
(Note 2)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
12MHz
•Internal RC
oscillation stops
IDDHALT(2)
•HALT mode
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
6MHz
•Internal RC
oscillation stops
IDDHALT(3)
•HALT mode
•FmCF=3MHz
IDDHALT(4)
Ceramic resonator
IDDHALT(5)
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
3MHz
•Internal RC
oscillation stops
•HALT mode
IDDHALT(6)
•FmCF=0Hz
IDDHALT(7)
(when oscillation
IDDHALT(8)
stops)
IDDHALT(9)
•FsXtal=32.768kHz
IDDHALT(10)
crystal oscillation
IDDHALT(11)
•System
clock :
IDDHALT(12)
RC oscillation
IDDHALT(13)
IDDHALT(14)
•HALT mode
•FmCF=0Hz
IDDHALT(15)
(when oscillation
IDDHALT(16)
stops)
IDDHALT(17)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
Current
IDDHOLD(1) VDD HOLD mode
dissipation
IDDHOLD(2)
in HOLD
mode
(Note 2)
Mask option
is “High”
Mask option
is “Low”
Ratings
OCR7 VDD[V] min.
typ.
max.
0
4.5-6.0
5.0
14
1
4.5-6.0
5.0
14
0
1
0
4.5-6.0
2.3
4.5
0.8
7
15
4
650
1000
340
600
400
600
200
350
25
36
8
12
2700
4200
2200
2500
1600
2400
1300
1500
100
140
55
85
4.5-6.0
0.05
30
2.5-4.5
0.02
20
0
1
0
1
0
1
0
1
0
1
0
1
2.5-4.5
4.5-6.0
2.5-4.5
4.5-6.0
2.5-4.5
4.5-6.0
2.5-4.5
unit
mA
µA
(Note 2) The currents of the output transistors, pull-up transistors and the LCD bleeder resistors are ignored.
Refer to figure 7.
No.6723-19/28
LC868016/12/08A
7. LCD Voltage and LCD Driver Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter
Symbol
VDD-Ci drop
voltage (i : 1 to 16)
VX-Ci drop
voltage (X : 1 to 4)
(i : 1 to 16)
VX-Ci drop
voltage (X : 1 to 5)
(i : 1 to 16)
|VD1|
VDD-Si drop
voltage (i : 1 to 48)
VX-Si drop
voltage (X : 1 to 4)
(i : 1 to 48)
VX-Si drop
voltage (i : 1 to 5)
(i : 1 to 48)
|VD4|
V1 output voltage
VV1
V2 output voltage
VV2
V3 output voltage
VV3
V4 output voltage
VV4
LCD display
current
ILCD1
|VD2|
|VD3|
|VD5|
|VD6|
ILCD2
Step up voltage
VOUT2
VOUT3
Contrast current
(VLCD terminal)
ILC1
ILC2
ILC3
ILC4
ILC5
Pins, Conditions
•Only a Ci terminal for –15µA
•LCD display ON
•1/5 bias
•V5=0V
•Only a Ci terminal for +15µA
•LCD display ON
•1/5 bias
•V5=0V
•Only a Si terminal for -15µA
•LCD display ON
•1/5 bias
•V5=0V
min.
2.9
5.0
-120
-200
Ratings
typ.
2.9
5.0
2.9
5.0
•Only a Ci terminal for +15µA
•LCD display ON
•1/5 bias
•V5=0V
•LCD clock frequency=0Hz
•LCD display ON
•1/5 bias
•V5=0V
•Refer to figure 9
•LCD display ON
•1/5 bias
•VLCD=0V
•V1-V5 are opened
•Refer to figure 8
•V1-V5 resistor=20kΩ
•LCD display ON
•LVCR0=1 (doubler)
•VOUT2
•C5=C6=0.1µF
•Internal RC oscillation
start
•Refer to figure 10
•V1-V5 resistor=20kΩ
•LCD display ON
•LVCR0=0 (tripler)
•VOUT3
•C5=C6=0.1µF
•Internal RC oscillation
start
•Refer to figure 11
•LCD display ON
•V5=0V
•VLCD=-3V
•Refer to figure 12
VDD[V]
2.9
5.0
2.9
5.0
2.9
5.0
2.9
5.0
2.9
5.0
2.9
5.0
2.9
5.0
5
2.9
5
2.9
max.
120
200
120
200
unit
mV
120
200
120
200
-120
-200
0.75VDD 0.80VDD 0.85VDD
V
0.55VDD 0.60VDD 0.65VDD
0.35VDD 0.40VDD 0.45VDD
0.15VDD 0.20VDD 0.25VDD
25
15
125
75
50
29
250
150
100
60
500
300
µA
2.7
3
5
2.7
3
5
-2.7
-3
-5
-2.7
-3
-5
-1.9
-2.8
-4.8
-1.8
-2.6
-4.6
-1.7
-2.6
-4.5
-1.5
-2.2
4.2
V
IL=100µA
5
-10
-9.4
-9.0
IL=500µA
5
-10
-8.5
-7.5
VCCR=1
VCCR=2
VCCR=4
VCCR=8
VCCR=10H
5
5
5
5
5
5
2.5
1.25
0.6
0.3
10
5
2.5
1.25
0.6
20
10
5
2.5
1.25
20kΩ
mode
4kΩ
mode
IL=100µA
IL=500µA
mA
µA
VCCR : The LCD contrast control register
LVCR0 : Bit 0 of the LCD bias control register
No.6723-20/28
LC868016/12/08A
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type
Maker
Oscillator
12MHz ceramic resonator
oscillation
Murata
CSA12.0MT
CST12.00MTW
KBR-12.0M
CSA6.00MG
CST6.00MGW
KBR-6.0MSA
KBR-6.0MKS
CSA3.0MG
CST3.0MGW
KBR-3.0MS
6MHz ceramic resonator
oscillation
Kyocera
Murata
Kyocera
3MHz ceramic resonator
oscillation
Murata
Kyocera
C1
C2
33pF
33pF
on chip
33pF
33pF
33pF
33pF
on chip
33pF
33pF
on chip
33pF
33pF
on chip
47pF
47pF
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type
Maker
Oscillator
C3
C4
32.768kHz crystal oscillation
CITIZEN
SII
CFS-308
DT-VT-200
18pF
18pF
18pF
18pF
* Both C3 and C4 must use J rank (±5%) and CH characteristics.
(It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.)
(Notes)
•Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation
pins as possible with the shortest possible pattern length.
•For other oscillators, please request an evaluation of microcomputer and oscillator matching to the oscillator
manufacturer.
CF1
CF2
XT1
XT2
X’tal
CF
C1
Figure 1
C2
Ceramic oscillation circuit
C3
Figure 2
C4
Crystal oscillation circuit
No.6723-21/28
LC868016/12/08A
VDD
VDD limit
0V
Power supply
Reset time
RES
Internal RC oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
Unstable
Reset
Execution of instructions
Reset time and oscillation stable time
HOLD release signal
Valid
Internal RC oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
HOLD
Execution of instructions
HOLD release signal and oscillation stable time
Figure 3
Oscillation stable time
No.6723-22/28
LC868016/12/08A
VDD
RRES
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has been over inferior limit of
supply voltage.
RES
CRES
Figure 4
Reset circuit
0.5VDD
<AC Timing Point>
VDD
tCKCY
tCKL
tCKH
SCK0
SCK1
1kΩ
tICK
tCKI
SI0
SI1
tCKO
50pF
SO0, SO1
SB0, SB1
<Timing>
Figure 5
tPIL
Figure 6
<Test Load>
Serial input / output test condition
tPIH
Pulse input timing condition
No.6723-23/28
LC868016/12/08A
VDD
VDD
A
VDD
VDD
CUP1
Open
V1
V1
CUP2
CUP1
Open
CUP2
Open
VOUT2
V5
VOUT2
V5
VOUT3
VLCD
VOUT3
VLCD
CF1
CF2
VSS
XT1
XT2
CF1
CF2
VSS
XT1
XT2
A
VSS
Figure 7
VSS
Current dissipation measurement
Figure 8
LCD display current measurement
VDD
VDD
VDD
VDD
V1
CUP1
V1
CUP1
CUP2
VOUT2
Open
CUP2
IL
V4
VOUT3
V5
VLCD
CF1
CF2
VSS
XT1
XT2
V5
VOUT3
VLCD
CF1
V
CF2
Figure 10
Step up output voltage measurement (1)
VDD
VDD
C7
XT2
*VOUT3 FOpen
VDD
C6
XT1
VSS
Output voltage of V1-V4 measurement
C5
VSS
V
VSS
Figure 9
Open
VOUT2
VDD
V1
V1
CUP1
CUP1
CUP2
Open
Open
CUP2
V4
VOUT2
V5
VOUT2
VOUT3
VLCD
VOUT3
V5
VLCD
IL
CF1
CF2
VSS
XT1
XT2
CF1
CF2
VSS
XT1
XT2
V
A
VSS
Figure 11
Step up output voltage measurement (2)
VSS
Figure 8
-3V
Contrast current measurement
No.6723-24/28
LC868016/12/08A
8. AC Characteristics at Ta=-30°C to +70°C, VSS=0V
Load capacity : 100pF
(Port 0, ADLC, EROE )
Load capacity : 80pF
(Output terminals except above)
*tCLCL=1/12 tCYC
External program memory timing
Parameter
Symbol
Pads and Conditions
ADLC pulse width
tLHLL
Address settling time
tAVLL
For ADLC
Address hold time
tLLAX
For ADLC
ADLC ! control signal
tLLEL
For EROE
EROE pulse width
tELEH
Data delay time
tELIV
From EROE
Data hold time
tEHIX
For EROE
EROE ! address in
tEHAV
Ratings
VDD[V]
min.
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
2tCLCL-40
2tCLCL-160
tCLCL-40
tCLCL-160
tCLCL-35
tCLCL-140
tCLCL-25
tCLCL-100
3tCLCL-35
3tCLCL-140
max.
unit
ns
3tCLCL-125
3tCLCL-400
0
0
tCLCL-8
tCLCL-32
Refer to figure 13.
1 tCYC
tCLCL
SCLK
tLHLL
ADLC
tLLEL
tELEH
EROE
tELIV
tEHAV
tLLAX
tAVLL
Port 0
tEHIX
IR
A7-A0
A7-A0
Port 2
A15-A8
A15-A8
Port 3
A7-A0
A7-A0
EROE
Port 0
A7-A0
DATA
Port 2
A15-A8
Port 3
A7-A0
Port 5
Bank
Figure 13
Timing of the external Program Memory/Data Memory
No.6723-25/28
LC868016/12/08A
External data memory timing
Parameter
Symbol
RD pulse width
tRLRH
WR pulse width
tWLWH
Data address hold time
tLLAX
Pads and Conditions
For ADLC (at LDX)
For ADLC (at STX)
Data delay time
tRLDV
From RD
Data hold time
tRHDX
From RD
Data floating time
tRHDZ
From RD
Data address setting
time
ADLC ! control signal
tAVLL
For ADLC
tLLRL
For RD
tLLWL
For WR
Data settling time
tQVWL
For WR
Data in WR =1
tQVWH
Data hold time
tWHQX
From WR
Control signal ! ADLC
tRHLH
For RD
tWHLH
For WR
Ratings
min.
max.
6tCLCL-80
6tCLCL-320
6tCLCL-80
6tCLCL-320
2tCLCL-35
2tCLCL-140
2tCLCL-35
2tCLCL-140
5tCLCL-125
5tCLCL-400
0
0
2tCLCL-70
2tCLCL+70
2tCLCL-280
2tCLCL+280
tCLCL-40
tCLCL-160
3tCLCL-50
3tCLCL+50
3tCLCL-200
3tCLCL+200
3tCLCL-50
3tCLCL+50
3tCLCL-200
3tCLCL+200
tCLCL-60
tCLCL-240
7tCLCL-140
7tCLCL-560
tCLCL-50
tCLCL-200
tCLCL-50
tCLCL+50
tCLCL-200
tCLCL+200
tCLCL-50
tCLCL+50
tCLCL-200
tCLCL+200
VDD[V]
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
unit
ns
Refer to figure 14.
tCLCL
1 tCYC
SCLK
ADLC
tLLRL
EROE
tRLRH
tRHLH
tRLDV
RD
tRHDZ
tAVLL
tLLAX
tRHDX
(at reading)
A7-A0
Port 0
DATA
tLLWL
tWLWH
Z
tWHLH
WR
tLLAX
(at writing)
Port 0
A7-A0
tQVWL
tWHQX
DATA
tQVWH
Port 2
A15-A8
Bank
Port 5
A7-A0
Port 3
Figure 14
Timing of the external RAM
No.6723-26/28
LC868016/12/08A
• Evaluation Sample (ES)
The factory shipment of this microcomputer is chip.
But there are two types of shipment of evaluation sample.
One type is chip and the other is package (QIC160).
If you selected package type, please refer to the following pin assignment and layout, and make the user target board.
85
90
P10
P73
P72
P71
P70
P47
P46
P44
P43
P42
P41
P40
VSS
CUP1
CUP2
VOUT2
VOUT3
P11
100
P15
P14
P13
P12
P16
110
P55
P56
P57
P17
P52
P53
P54
115
P51
P50
• Pin Assignment of evaluation sample (Package type)
VLCD
VSS
V5
V4
V3
V2
V1
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
CF1
CF2
S35
VDD
P30
125
75
P31
P32
P33
P34
P35
P36
P37
P00
P01
P02
P03
P04
P05
P06
P07
P20
P21
P22
P23
P24
P25
P26
P27
130
70
140
LC868016-QIC160
60
150
ADLC
EROM
RES
XT1
XT2
50
155
35
30
20
10
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
1
VDD
45
No.6723-27/28
LC868016/12/08A
• Layout of evaluation sample (Package type) : QIC160
PS No.6723-28/28
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