Semtech LCDA05TB Low capacitance tvs diode array for high-speed data interfacesã Datasheet

LCDA05 THRU LCDA24
Low Capacitance TVS Diode Array
For High-Speed Data Interfaces
PROTECTION PRODUCTS
Description
Features
The LCDA series of TVS arrays are designed to protect
sensitive electronics from damage or latch-up due to
ESD and other voltage-induced transient events. Each
device will protect two high-speed lines. They are
available with operating voltages of 5V, 12V, 15V and
24V. They are bidirectional devices and may be used on
lines where the signal polarities are above and below
ground.
TVS diodes are solid-state devices designed specifically
for transient suppression. They offer desirable characteristics for board level protection including fast response time, low operating and clamping voltage and
no device degradation. The LCDA series devices
feature low capacitance compensation diodes in series
with standard TVS diodes to provide an integrated, low
capacitance solution for use on high-speed interfaces.
The LCDA series devices may be used to meet the
immunity requirements of IEC 61000-4-2, level 4.
u Transient protection for high-speed data lines to
u
u
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IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact)
IEC 61000-4-4 (EFT) 40A (tp = 5/50ns)
IEC 61000-4-5 (Lightning) 24A (tp = 8/20µs)
Protects two I/O lines
Low capacitance for high-speed data lines
Working voltages: 5V, 12V, 15V and 24V
Low leakage current
Low operating and clamping voltages
Solid-state silicon avalanche technology
Mechanical Characteristics
u
u
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JEDEC SO-8 (MS-012AA) small outline package
Molding compound flammability rating: UL 94V-0
Marking : Part Number, Logo, Date Code
Packaging : Tape and Reel per EIA 481
Applications
u
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Circuit Diagram (Each Line Pair)
High-Speed Data Lines
Microprocessor Based Equipment
Universal Serial Bus (USB) Port Protection
Notebooks, Desktops, & Servers
Instrumentation
LAN/WAN Equipment
Peripherals
Schematic & PIN Configuration
1
8
2
7
3
6
4
5
SO-8 (Top View)
Revision 9/2000
1
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LCDA05 THRU LCDA24
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Symbo l
Value
Units
Peak Pulse Pow er (tp = 8/20µs)
Pp k
300
Watts
Lead Soldering Temp erature
TL
260 (10 sec.)
°C
Op erating Temp erature
TJ
-55 to +125
°C
TSTG
-55 to +150
°C
Storage Temp erature
Electrical Characteristics
LCDA05
Par ame te r
Reverse Stand -Off Voltage
Reverse Breakd ow n Voltage
Symbo l
Co nd itio ns
Minimum
Typ ical
V RWM
Maximum
Units
5
V
V BR
It = 1mA
Reverse Leakage Current
IR
V RWM = 5V, T=25°C
20
µA
Clamp ing Voltage
VC
IPP = 1A , tp = 8/20µ s
9.8
V
Clamp ing Voltage
VC
IPP = 5A , tp = 8/20µ s
11
V
Junction Cap acitance
Cj
Betw een I/O Pins and
Gnd
V R = 0V, f = 1MHz
5
pF
Symbo l
Co nd itio ns
Maximum
Units
12
V
6
V
LCDA12
Par ame te r
Reverse Stand -Off Voltage
Reverse Breakd ow n Voltage
Minimum
V RWM
Typ ical
V BR
It = 1mA
Reverse Leakage Current
IR
V RWM = 12V, T=25°C
1
µA
Clamp ing Voltage
VC
IPP = 1A , tp = 8/20µ s
19
V
Clamp ing Voltage
VC
IPP = 5A , tp = 8/20µ s
24
V
Junction Cap acitance
Cj
Betw een I/O Pins and
Gnd
V R = 0V, f = 1MHz
5
pF
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LCDA05 THRU LCDA24
PROTECTION PRODUCTS
Electrical Characteristics (continued)
LCDA15
Par ame te r
Symbo l
Co nd itio ns
Minimum
Typ ical
Maximum
Units
15
V
Reverse Stand-Off Voltage
VRWM
Reverse Breakdow n Voltage
V BR
It = 1mA
Reverse Leakage Current
IR
VRWM = 15V, T=25°C
1
µA
Clamp ing Voltage
VC
IPP = 1A, tp = 8/20µs
24
V
Clamp ing Voltage
VC
IPP = 5A, tp = 8/20µs
30
V
Junction Cap acitance
Cj
Betw een I/O Pins and
Gnd
V R = 0V, f = 1MHz
5
pF
Symbo l
Co nd itio ns
Maximum
Units
24
V
16.7
V
LCDA24
Par ame te r
Minimum
Typ ical
Reverse Stand-Off Voltage
VRWM
Reverse Breakdow n Voltage
V BR
It = 1mA
Reverse Leakage Current
IR
VRWM = 24V, T=25°C
1
µA
Clamp ing Voltage
VC
IPP = 1A, tp = 8/20µs
43
V
Clamp ing Voltage
VC
IPP = 5A, tp = 8/20µs
55
V
Junction Cap acitance
Cj
Betw een I/O Pins and
Gnd
V R = 0V, f = 1MHz
5
pF
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LCDA05 THRU LCDA24
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
Power Derating Curve
10
110
90
% of Rated Power or IPP
Peak Pulse Power - P PP (kW)
100
1
0.1
80
70
60
50
40
30
20
10
0
0.01
0.1
1
10
100
0
1000
25
50
75
100
125
150
Ambient Temperature - TA (oC)
Pulse Duration - tp (µs)
Pulse Waveform
110
Waveform
Parameters:
tr = 8µs
td = 20µs
100
90
Percent of IPP
80
70
e
60
-t
50
40
td = IPP/2
30
20
10
0
0
5
10
15
20
25
30
Time (µs)
ESD Discharge Parameters Per IEC 61000-4-2
ESD Pulse Waveform (Per IEC 61000-4-2)
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Level
First
Peak
Current
(A)
Peak
Current
at 30ns
(A)
Peak
Current
at 60ns
(A)
Test
Test
Voltage
Voltage
(Contact
( A ir
Discharge) Discharge)
(kV)
(kV)
1
7.5
4
8
2
2
2
15
8
4
4
4
3
22.5
12
6
6
8
4
30
16
8
8
15
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LCDA05 THRU LCDA24
PROTECTION PRODUCTS
Applications Information
LCDA Connection Diagram
Device Connection for Protection of Two High-Speed
Data Lines
The LCDAxx is designed to protect up to two high-speed
data lines. The LCDAxx utilizes a low capacitance
compensation diode in series with, but in opposite
polarity to a TVS diode in each line. The resulting
capacitance is less than 5pF per line. Each line will
only suppress transient events in one polarity. Therefore, to achieve protection in both positive and negative polarity, a second TVS/rectifier pair is connected in
anti-parallel to the first. Pins 1, 2, 7, and 8 are used to
protect one data line. Pins 3, 4, 5, and 6 are used to
protect the second data line.
The device is connected as follows:
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l
l
l
l
2
7
3
6
4
5
I/O 2
I/O 2
I/O Line Protection
Pins 1 & 2 are tied together and pins 7 & 8 are tied
together providing the protection circuit for one I/O
line. Pins 3 & 4 are tied together and pins 5 & 6
are tied together providing the protection circuit for
the second I/O line. Since the device is electrically
symmetrical, either side of the connected pairs
may be used to protect the lines. The other side of
the pair is used to make the ground connection.
The ground connections should be made directly to
the ground plane for best results. The path length
is kept as short as possible to reduce the effects
of parasitic inductance in the board traces.
Connection Options
To Protected
Device
Line 1
In/Out
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
l
8
I/O 1
Circuit Board Layout Recommendations for Suppression of ESD.
l
1
I/O 1
Line 2
Ground
Place the TVS near the input terminals or connectors to restrict transient coupling.
Minimize the path length between the TVS and the
protected line.
Minimize all conductive loops including power and
ground loops.
The ESD transient return path to ground should be
kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible.
1
8
2
7
3
6
4
5
Line 1
Ground
Line 2
In/Out
From Connector
To Protected
Device
Line 1
In/Out
1
8
2
7
3
6
Ground
4
Line 2
In/Out
5
From Connector
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LCDA05 THRU LCDA24
PROTECTION PRODUCTS
Outline Drawing - SO-8
Land Pattern - SO-8
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LCDA05 THRU LCDA24
PROTECTION PRODUCTS
Ordering Information
P ar t
Numbe r
Wo r king
Vo ltage
Qty p e r
Reel
R e e l Size
LCDA 05.TB
5V
500
7 Inch
LCDA 05.TE
5V
2,500
13 Inch
LCDA 12.TB
12V
500
7 Inch
LCDA 12.TE
12V
2,500
13 Inch
LCDA 15TB
15V
500
7 Inch
LCDA 15.TE
15V
2,500
13 Inch
LCDA 24.TB
24V
500
7 Inch
LCDA 24.TE
24V
2,500
13 Inch
Note:
(1) No suffix indicates tube pack.
Contact Information
Semtech Corporation
Protection Products Division
652 Mitchell Rd., Newbury Park, CA 91320
Phone: (805)498-2111 FAX (805)498-3804
ã 2000 Semtech Corp.
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