Intersil LCL8068ACJD Precision 4 1/2 digit, a/d converter Datasheet

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May 2001
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3081.2
Precision 4 1/2 Digit, A/D Converter
Features
The ICL8052A or ICL8068A/lCL71C03 chip pairs with their
multiplexed BCD output and digit drivers are ideally suited
for the visual display DVM/DPM market. The outstanding
41/2 digit accuracy, 200.00mV to 2.0000V full scale
capability, auto-zero and auto-polarity combine with true
ratiometric operation, almost ideal differential linearity and
time-proven dual slope conversion. Use of these chip pairs
eliminates clock feedthrough problems, and avoids the
critical board layout usually required to minimize charge
injection.
• Typically Less Than 2µVP-P Noise (200.00mV Full Scale,
lCL8068A
• Guaranteed Zero Reading for 0V Input
When only 2000 counts of resolution are required, the 71C03
can be wired for 31/2 digits and give up to 30 readings/sec.,
making it ideally suited for a wide variety of applications.
• All Outputs TTL Compatible
The ICL71C03 is an improved CMOS plug-in replacement for
the lCL7103 and should be used in all new designs.
Part Number Information
PART NUMBER
TEMP.
RANGE ( oC)
PACKAGE
PKG.
NO.
lCL8052ACPD
0 to 70
14 Ld PDIP
E14.3
ICL8068ACDD
0 to 70
14 Ld CERDIP
F14.3
lCL8068ACJD
0 to 70
14 Ld CERDIP
F14.3
lCL71C03ACPl
0 to 70
28 Ld PDIP
E28.6
• Accuracy Guaranteed to ±1 Count Over Entire ±20,000
Counts (2.0000V Full Scale)
• True Polarity at Zero Count for Precise Null Detection
• Single Reference Voltage Required
• Over-Range and Under-Range Signals Available for AutoRanging Capability
• Medium Quality Reference, 40ppm (Typ) on Board
• Blinking Display Gives Visual Indication of Over Range
• Six Auxiliary Inputs/Outputs are Available for Interfacing to
UARTs, Microprocessors or Other Complex Circuitry
• 5pA Input Current (Typ) (8052A)
Pinouts
ICL71C03 (PDIP)
TOP VIEW
ICL8052A/ICL8068A
(CERDIP, PDIP)
TOP VIEW
V+ 1
gital
nver
,
D,
crop
esso
File Number
41/2 / 31/2 2
V- 1
14 INT OUT
-1.2V
COMP OUT 2
13 +BUFF IN
12 +INT IN
REF BYPASS 4
GND 5
VREF
REF OUT 6
REF SUPPLY 7
26 D2
RUN/HOLD 4
25 D3
COMP IN
24 D4
5
23 B8 (MSB)
REFERENCE 7
22 B4
11 -INT IN
REF. CAP. 1 8
21 B2
10 -BUFF IN
REF. CAP. 2 9
20 B1 (LSB)
ANALOG IN 10
19 D5 (MSD)
ANALOG GND 11
18 STROBE
9 BUFF OUT
ICL8052A/ 8 V+
ICL8068A
CLOCK IN 12
UNDER-RANGE 13
OVER-RANGE 14
1
27 D1 (LSD)
POL 3
V- 6
REF CAP 3
28 BUSY
17 A-Z IN
16 A-Z OUT
15 DIGITAL GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001
ICL8052A/ICL71C03, ICL8068A/ICL71C03
Functional Block Diagram
10kΩ
90kΩ
100kΩ
0.22µF
-BUF IN
BUF OUT
-INT IN
10
BUFFER
9
+15V -15V
6
8 7
INT.
3 REF.
300pF
10kΩ
11
INTEG.
-
A1
+
ICL8052A/8068A
A2
+
REF
CAP 1
10kΩ
A3
+
D5
D4
D3
D2
D1
19
24
25
26
27
AZ OUT
AZ IN
16
9
20 B1
LSD
COMP IN
17
SW3
21 B2
22 B3
MULTIPLEXER
23 B4
5
LATCH
LATCH
ZERO
CROSSING
DETECTOR
2
5
MSD
COMP
OUT
1µF (TYP)
REF
CAP 2
8
4
3
2
7
LATCH
LATCH
LATCH
COUNTERS
10
1
0.1µF
ANALOG
GND
-
+INT IN 12
10µF (TYP)
ANALOG
INPUT
COMP.
-
+BUF IN 13
10µF
REF
14
-1.2V
5
1kΩ
1
POLARITY
REF
OUT
SEVENSEGMENT
DECODER
INT OUT
6
CONTROL LOGIC
ICL71C03
11
1
+5V
15
6
-15V
4
RUN/
HOLD
FIGURE 1.
2
12
2
14
13
18
28
CLOCK 4 1/2 DIGIT/ OVER UNDER STROBE BUSY
IN
3 1/2 DIGIT RANGE RANGE
ICL8052A/ICL71C03, ICL8068A/ICL71C03
Absolute Maximum Ratings
Thermal Information
ICL8052A, ICL8068A
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
Differential Input Voltage
(8068A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30V
(8052A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6V
Input Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
Output Short Circuit Duration All Outputs (Note 2) . . . . . . Indefinite
ICL71C03
Power Supply Voltage (GND to V+). . . . . . . . . . . . . . . . . . . . . . 6.5V
Negative Supply Voltage (GND to V-) . . . . . . . . . . . . . . . . . . . . -17V
Analog Input Voltage (Note 3) . . . . . . . . . . . . . . . . . . . . . . . V+ to VDigital Input Voltage (Note 4) . . . . . . . . .(GND - 0.3V) to (V+ + 0.3V)
Thermal Resistance (Typical, Note 5) θJA ( oC/W)
θJC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . .
75
20
14 Ld PDIP Package . . . . . . . . . . . . . .
100
N/A
28 Ld PDIP Package . . . . . . . . . . . . . .
65
N/A
Maximum Storage Temperature. . . . . . . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
3. Short circuit may be to ground or either supply. Rating applies to 70oC ambient temperature.
4. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.
5. Connecting any digital inputs or outputs to voltages greater then V+ or less than GND may cause destructive device latchup. For this reason it
is recommended that the power supply to the ICL71C03 be established before any inputs from sources not on that supply are applied.
6. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
Clock In, Run/Hold, 4 1/2 / 3 1/2
Comp. In Current
Threshold Voltage
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNITS
IINL
VIN = 0
-
0.2
0.6
mA
IINH
VIN = +5V
-
0.1
10
µA
IINL
VIN = 0
-
0.1
10
µA
IINH
VIN = +5V
-
0.1
10
µA
-
2.5
-
V
VINTH
All Outputs
VOL
IOL = 1.6mA
-
0.25
0.40
V
B 1 , B2 , B4 , B8 , D1 , D2 , D3 , D4 , D5
VOH
IOH = -1mA
2.4
4.2
-
V
Busy, Strobe, Over-Range, Under-Range Polarity
V OH
IOH = -10µA
4.9
4.99
-
V
Switches 1, 3, 4, 5, 6
rDS(ON)
-
400
-
Ω
Switch 2
rDS(ON)
-
1200
-
Ω
Switch Leakage (All)
ID(OFF)
-
2
-
pA
+5V Supply Range
V+
4
5
6
V
-15V Supply Range
V-
-5
-15
-18
V
+5V Supply Current
I+
fCLK = 0
-
1.1
3
mA
-15V Supply Current
I-
fCLK = 0
-
0.8
3
mA
vs Clock Frequency
-
40
-
pF
DC
2000
1200
kHz
Power Dissipation Capacitance
CPD
Clock Frequency (Note 6)
NOTE:
7. This specification relates to the clock frequency range over which the ICL71C03A will correctly perform its various functions. See the “Max Clock
Frequency” section under Component Value Selection for limitations on the clock frequency range in a system.
3
ICL8052A/ICL71C03, ICL8068A/ICL71C03
ICL8068A Electrical Specifications VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNITS
EACH OPERATIONAL AMPLIFIER
Input Offset Voltage
Input Current (Either Input) (Note 7)
Common-Mode Rejection Ratio
VOS
VCM = 0V
-
20
65
mV
IIN
VCM = 0V
-
80
150
pA
VCM = ±10V
70
90
-
dB
VCM = ±2V
-
110
-
dB
R L = 50kΩ
20,000
-
-
V/V
CMRR
Non-Linear Component of Common-Mode Rejection
Ratio (Note 8)
Large Signal Voltage Gain
AV
Slew Rate
SR
-
6
-
V/µs
GBW
-
2
-
MHz
ISC
-
5
-
mA
-
-
-
V/V
Unity Gain Bandwidth
Output Short-Circuit Current
COMPARATOR AMPLIFIER
R L = 30kΩ
Small-Signal Voltage Gain
AVOL
Positive Output Voltage Swing
+VO
12
13
-
V
Negative Output Voltage Swing
-VO
-2.0
-2.6
-
V
Output Voltage
VO
1.60
1.75
1.90
V
Output Resistance
RO
-
5
-
Ω
Temperature Coefficient
TC
-
40
-
ppm/oC
Supply Voltage (V++ -V-)
VSUPPLY
±10
-
±16
V
Supply Current Total
ISUPPLY
-
8
14
mA
MIN
TYP
MAX
UNITS
VOLTAGE REFERENCE
ICL8052A Electrical Specifications VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST
CONDITIONS
EACH OPERATIONAL AMPLIFIER
Input Offset Voltage
Input Current (Either Input) (Note 7)
Common-Mode Rejection Ratio
VOS
VCM = 0V
-
20
75
mV
IIN
VCM = 0V
-
2
10
pA
VCM = ±10V
70
90
-
dB
VCM = ±2V
-
110
-
dB
R L = 50kΩ
20,000
-
-
V/V
CMRR
Non-Linear Component of Common-Mode Rejection
Ratio (Note 8)
Large Signal Voltage Gain
AV
Slew Rate
SR
-
6
-
V/µs
GBW
-
1
-
MHz
ISC
-
20
-
mA
-
-
-
V/V
Unity Gain Bandwidth
Output Short-Circuit Current
COMPARATOR AMPLIFIER
R L = 30kΩ
Small-Signal Voltage Gain
AVOL
Positive Output Voltage Swing
+VO
12
13
-
V
Negative Output Voltage Swing
-VO
-2.0
-2.6
-
V
Output Voltage
VO
1.60
1.75
1.90
V
Output Resistance
RO
-
5
-
Ω
VOLTAGE REFERENCE
4
ICL8052A/ICL71C03, ICL8068A/ICL71C03
ICL8052A Electrical Specifications VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER
TEST
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Temperature Coefficient
TC
-
40
-
ppm/oC
Supply Voltage (V++ -V-)
VSUPPLY
±10
-
±16
V
Supply Current Total
ISUPPLY
-
6
14
mA
NOTES:
8. The input bias currents are junction leakage currents which approximately double for every 10oC increase in the junction temperature, TJ . Due
to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal operation the junction
temperature rises above the ambient temperature as a result of internal power dissipation, PD. TJ = TA + RθJAPD, where RθJA is the thermal
resistance from junction to ambient. A heat sink can be used to reduce temperature rise.
9. This is the only component that causes error in dual-slope converter.
System Electrical Specifications: ICL8068A/ICL71C03
V++ = +15V, V+ = +5V, V- = -15V, TA = 25oC, fCLK Set for 3 Readings/Sec.
TEST
CONDITIONS
PARAMETER
ICL8068A/ICL71C03
(NOTE 9)
ICL8068A/ICL71C03
(NOTE 10)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Zero Input Reading
VIN = 0V,
Full Scale = 200mV
-000.0
±000.0
+000.0
-000.0
±000.0
000.0
Digital
Reading
Ratiometric Error (Note 11)
VIN = VREF
Full Scale = 2V
0.999
1.000
1.001
0.9999
1.0000
1.0001
Digital
Reading
Linearity Over ± Full Scale (Error of
Reading from Best Straight Line)
-2V ≤ VIN ≤ +2V
-
0.2
1
-
0.5
1
Counts
Differential Linearity (Difference between -2V ≤ VIN ≤ +2V
Worst Case Step of Adjacent Counts and
Ideal Step)
-
0.01
-
-
0.01
-
Counts
Rollover Error (Difference in Reading for
Equal Positive & Negative Voltage Near
Full Scale)
-VIN ≅ +VIN ≈ 2V
-
0.2
1
-
0.5
1
Counts
Noise (P-P Value Not Exceeded 95% of
Time)
VIN = 0V,
Full Scale = 200mV
-
3
-
-
2
-
µV
Leakage Current at Input
VIN = 0V
-
200
300
-
100
200
pA
Zero Reading Drift (Note 12)
VIN = 0V,
0oC ≤ TA ≤ 50oC
-
1
5
-
0.5
2
µV/oC
Scale Factor Temperature Coefficient
(Note 12)
VIN = 2V,
0oC ≤ TA ≤ 50oC
Ext. Ref. 0ppm/oC
-
3
15
-
2
5
ppm/oC
System Electrical Specifications: ICL8052A/ICL71C03
V++ = +15V, V+ = +5V, V- = -15V, TA = 25oC, fCLK Set for 3 Reading/Sec.
TEST
CONDITIONS
PARAMETER
ICL8052A/ICL71C03
(NOTE 9)
ICL8052A/A/ICL71C03
(NOTE 10)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Zero Input Reading
VIN = 0V,
Full Scale = 2V
-0.000
±0.000
+0.000
-0.000
±0.000
0.000
Digital
Reading
Ratiometric Error (Note 11)
VIN = VREF
Full Scale = 2V
0.999
1.000
1.001
0.9999
1.0000
1.0001
Digital
Reading
Linearity Over ± Full Scale (Error of
Reading from Best Straight Line)
-2V ≤ VIN ≤ +2V
-
0.2
1
-
0.5
1
Counts
5
ICL8052A/ICL71C03, ICL8068A/ICL71C03
System Electrical Specifications: ICL8052A/ICL71C03
V++ = +15V, V+ = +5V, V- = -15V, TA = 25oC, fCLK Set for 3 Reading/Sec. (Continued)
TEST
CONDITIONS
PARAMETER
Differential Linearity (Difference between -2V ≤ VIN ≤ +2V
Worst Case Step of Adjacent Counts and
Ideal Step)
ICL8052A/ICL71C03
(NOTE 9)
ICL8052A/A/ICL71C03
(NOTE 10)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
-
0.01
-
-
0.01
-
Counts
Rollover Error (Difference in Reading for
Equal Positive & Negative Voltage Near
Full Scale)
-VIN ≅ +VIN ≈ 2V
-
0.2
1
-
0.5
1
Counts
Noise (Peak-To-Peak Value Not
Exceeded 95% of Time)
VIN = 0V,
Full Scale = 200mV,
Full Scale = 2V
-
20
50
-
-
-
µV
30
Leakage Current at Input
VIN = 0V
-
5
30
-
3
10
pA
Zero Reading Drift
VIN = 0V,
0oC To 70oC
-
1
5
-
0.5
2
µV/oC
Scale Factor Temperature Coefficient
VIN = 2V,
0oC To 70oC,
Ext. Ref. 0ppm/ oC
-
3
15
-
2
5
ppm/oC
NOTES:
10. Tested in 31/2 digit (2,000 count) circuit shown in Figure 5, clock frequency 12kHz. Pin 2 71C03 connected to GND.
11. Tested in 41/2 digit (20,000 count) circuit shown in Figure 5, clock frequency 120kHz. Pin 2 71C03A open.
12. Tested with a low dielectric absorption integrating capacitor. See Component Selection Section.
13. The temperature range can be extended to 70oC and beyond if the Auto-Zero and Reference capacitors are increased to absorb the high
temperature leakage of the 8068A.
Detailed Description
Zero phase, and the integrator will generate a ramp whose
slope is proportional to VIN . At the end of this phase, the
sign of the ramp is latched into the polarity F/F.
Analog Section
Figure 2 shows the equivalent Circuit of the Analog Section
of both the ICL71C03/8052A and the ICL71C03/8068A in
the 3 different phases of operation. IF the RUN/HOLD pin is
left open or tied to V+, the system will perform conversions
at a rate determined by the clock frequency: 40,0002 at 41/2
digit and 4002 at 31/2 digit clock periods per cycle (see
Figure 3 for details of conversion timing).
Auto-Zero Phase I (Figure 2A)
During the Auto-Zero, the input of the buffer is connected to
VREF through switch 2, and switch 3 closes a loop around
the integrator and comparator, the purpose of which is to
charge the auto-zero capacitor until the integrator output
does not change with time. Also, switches 1 and 2 recharge
the reference capacitor to VREF.
Input Integrate Phase II (Figure 2B)
During Input Integrate the auto-zero loop is opened and the
ANALOG INPUT is connected to the BUFFER INPUT
through switch 4 and CREF. If the input signal is zero, the
buffer, integrator and comparator will see the same voltage
that existed in the previous state (Auto-Zero). Thus, the
integrator output will not change but will remain stationary
during the entire Input Integrate cycle. If VIN is not equal to
zero, and unbalanced condition exists compared to the Auto
6
Deintegrate Phase II (Figures 2C and 2D)
During the Deintegrate phase, the switch drive logic uses the
output of the polarity F/F in determining whether to close
switch 6 or 5. If the input signal is positive, switch 6 is closed
and a voltage which is VREF more negative than during
Auto-Zero is impressed on the BUFFER INPUT. Negative
Inputs will cause +2(VREF) to be applied to the BUFFER
INPUT via switch 5. Thus, the reference capacitor generates
the equivalent of a (+) or (-) reference from the single
reference voltage with negligible error. The reference voltage
returns the output of the integrator to the zero-crossing point
established in Phase I. The time, or number of counts,
required to do this is proportional to the input voltage. Since
the Deintegrate phase can be twice as long as the Input
Integrate Phase, the input voltage required to give a full
scale reading is 2VREF.
ICL8052A/ICL71C03, ICL8068A/ICL71C03
CINT
RINT
VREF (+1.000V)
BUFFER
4
5
VIN
1
2
1µF
INTEGRATOR
COMPARATOR
-
-
A1
+
A2
+
A3
+
CREF
6
CSTRAY
ZERO
CROSSING
DETECTOR
CAZ
3
FIGURE 2A. PHASE I AUTO-ZERO
CINT
RINT
VREF (+1.000V)
BUFFER
4
5
VIN
1
2
1µF
INTEGRATOR
COMPARATOR
-
-
A1
+
A2
+
A3
+
CREF
6
CSTRAY
ZERO
CROSSING
DETECTOR
CAZ
POLARITY
FF
3
FIGURE 2B. PHASE II INTEGRATE INPUT
RINT
CINT
VREF (+1.000V)
BUFFER
4
5
2
1µF
INTEGRATOR
COMPARATOR
-
-
A1
+
A2
+
A3
+
CREF
VIN
1
6
CSTRAY
ZERO
CROSSING
DETECTOR
CAZ
POLARITY
FF
3
FIGURE 2C. PHASE III + DEINTEGRATE
RINT
CINT
VREF (+1.000V)
BUFFER
4
5
VIN
1
2
1µF
INTEGRATOR
COMPARATOR
-
-
A1
+
A2
+
A3
+
CREF
6
CSTRAY
ZERO
CROSSING
DETECTOR
CAZ
3
POLARITY
FF
FIGURE 2D. PHASE III - DEINTEGRATE
FIGURE 2. ANALOG SECTION OF EITHER ICL8052A OR ICL8068A WITH ICL71C03
7
ICL8052A/ICL71C03, ICL8068A/ICL71C03
COUNTS
41/2 DIGIT
31/2 DIGIT
PHASE I
PHASE II
PHASE III
10,001
10,000
20,001
1,001
1,000
2,001
POLARITY
DETECTED
ZERO CROSSING
OCCURS
INTEGRATOR
OUTPUT
ZERO CROSSING
DETECTED
AZ PHASE I
INT PHASE II
DEINT PHASE III
AZ
CLOCK
INTERNAL LATCH
BUSY OUTPUT
AFTER ZERO CROSSING,
ANALOG SECTION WILL
BE IN AUTOZERO
CONFIGURATION
NUMBER OF COUNTS TO ZERO CROSSING
PROPORTIONAL TO VIN
FIGURE 3. CONVERSION TIMING
Zero-Crossing Flip-Flop
Figure 4 shows the problem that the zero-crossing F/F is
designated to solve.
The integrator output is approaching the zero-crossing point
where the count will be latched and the reading displayed.
For a 20,000 count instrument, the ramp is changing
approximately 0.50mV per clock pulse (10V Max integrator
output divided by 20,000 counts). The clock pulse
feedthrough superimposed upon this ramp would have to be
less than 100mV peak to avoid causing significant errors.
The flip-flop interrogates the data once every clock pulse
after the transients of the previous clock pulse and half-clock
pulse have died down. False zero-crossings caused by clock
pulses are not recognized. Of course, the flip-flop delays the
true zero-crossing by one count in every instance, and if a
correction were not made, the display would always be one
count too high. Therefore, the counter is disabled for one
clock pulse at the beginning of phase 3. This one count
delay compensates for the delay of the zero crossing flipflop, and allows the correct number to be latched into the
display. Similarly, a one count delay at the beginning of
phase 1 gives an overload display of 0000 instead of 0001.
No delay occurs during phase 2, so that true ratiometric
readings result.
8
CLOCK
PULSE
FEEDTHROUGH
TRUE ZERO
CROSSING
FALSE ZERO
CROSSING
FIGURE 4. INTEGRATOR OUTPUT NEAR ZERO-CROSSING
Detailed Description
Digital Section
The 71C03 includes several pins which allow it to operate
conveniently in more sophisticated systems. These include:
4-1/2 / 3-1/2 (PIN 2)
When high (or open) the internal counter operates as a full
41/2 decade counter, with a complete measurement cycle
requiring 40,002 counts. When held low, the least significant
decade is cleared and the clock is fed directly into the next
decade. A measurement cycle now requires only 4,0002
clock pulses. All 5 digit drivers are active in either case, with
each digit lasting 200 counts with Pin 2 high (41/2 digit) and
20 counts for Pin 2 low (31/2 digit).
ICL8052A/ICL71C03, ICL8068A/ICL71C03
RUN/HOLD (PIN 4)
BUSY (PIN 28)
When high (or open) the A/D will free-run with equally
spaced measurement cycles every 40,0002/4,002 clock
pulses. If taken low, the converter will continue the full
measurement cycle that it is doing and then hold this reading
as long as Pin 4 is held low. A short positive pulse (greater
then 300ns) will now initiate a new measurement cycle
beginning with up to 10,001/1,001 counts of auto zero. Of
course if the pulse occurs before the full measurement cycle
(40,002/4,002 counts) is completed, it will not be recognized
and the converter will simply complete the measurement it is
doing. An external indication that full measurement cycle
has been completed is that the first STROBE pulse (see
below) will occur 101/ 11 counts after the end of this cycle.
Thus, if RUN/HOLD is low and has been low for at least
101/ 11 counts, converter is holding and ready to start a new
measurement when pulsed high.
BUSY goes high at the beginning of signal integrate and
stays high until the first clock pulse after zero-crossing (or
after end of measurement in the case of an OVER-RANGE).
The internal latches are enabled (i.e., loaded) during the first
clock pulse after BUSY and are latched at the end of this
clock pulse. The circuit automatically reverts to auto-zero
when not BUSY so it may also be considered an A-Z signal.
A very simple means for transmitting the data down a single
wire pair from a remote location would be to AND BUSY with
clock and subtract 10,001/1,001 counts from the number of
pulses received - as mentioned previously there is one “NOcount” pulse in each Reference Integrate cycle.
STROBE (PIN 18)
This is a negative-going output pulse that aids in transferring
the BCD data to external latches, UARTs or
microprocessors. There are 5 negative-going STROBE
pulses that occur once and only once for each measurement
cycle starting 101/11 pulses after the end of the full
measurement cycle. Digit 5 (MSD) goes high at the end of
the measurement cycle and stays on for 201/ 21 counts. In
the center of this digit pulse (to avoid race conditions
between changing BCD and digit drives) the first STROBE
pulse goes negative for 1/2 clock pulse width. Similarly, after
Digit 5, Digit 4 goes high (for 200/ 20 clock pulses) and
100/ 10 pulses later the STROBE goes negative for the
second time. This continues through Digit 1 (LSD) when the
fifth and last STROBE pulse is sent. The digit drive will
continue to scan (unless the previous signal was over-range)
but no additional STROBE pulses will be sent until a new
measurement is available.
OVER-RANGE (PIN 4)
This pin goes positive when the input signal exceeds the
range (20,000/2,000) of the converter. The output F-F is set
at the end of BUSY and is reset to zero at the beginning of
Reference Integrate in the next measurement cycle.
UNDER-RANGE (PIN 13)
This pin goes positive when the reading is 9% of range or
less. The output F-F is set at the end of BUSY (if the new
reading is 1800/180 or less) and is reset a the beginning of
Signal Integrate of the next reading.
POLARITY (PIN 3)
This pin is positive for a positive input signal. It is valid even for a
zero reading. In other words, +0000 means the signal is
positive but less than the least significant bit. The converter can
be used as null detector by forcing equal (+) and (-) readings.
The null at this point should be less than 0.1 LSB. This output
becomes valid at the beginning of Reference Integrate and
remains correct until it is revalidated for the next measurement.
DIGIT DRIVES (PINS 19, 24, 25, 26, AND 27)
Each digit drive is a positive-going signal which lasts for
200/ 20 clock pulses. The scan sequence is D 5 (MSD), D4 ,
D3 , D 2 , and D1 (LSD). All five digits are scanned even when
operating in the 31/2 digit mode, and this scan is continuous
unless and OVER-RANGE occurs. Then all Digit drives are
blanked from the end of the STROBE sequence until the
beginning of Reference Integrate, at which time D5 will start
the scan again. This gives a blinking display as a visual
indication of OVER-RANGE.
BCD (PINS 20, 21, 22 AND 23)
The Binary coded decimal bit B8 , B4 , B2 , and B1 are positive
logic signals that go on simultaneously with the Digit driver.
9
ICL8052A/ICL71C03, ICL8068A/ICL71C03
INTEGRATOR
OUTPUT
AUTO
SIGNAL
ZERO
REFERENCE
INTEG.
INTEGRATE
10,001
10,000
20,001 / 2,001
/ 1,001
/ 1,000
COUNTS MAX
COUNTS
COUNTS
FULL MEASUREMENT CYCLE
40,002/4,002 COUNTS
BUSY
OVER-RANGE
WHEN APPLICABLE
UNDER-RANGE
WHEN APPLICABLE
EXPANDED SCALE BELOW
DIGIT SCAN
FOR OVER-RANGE
D5
D4
D3
D2
D1
1000† /100 COUNTS
STROBE
DIGIT SCAN
FOR OVER-RANGE
D5
AUTO ZERO
† FIRST D5 OF AZ AND REF INT
ONE COUNT LONGER
SIGNAL
INTEGRATE
REFERENCE
INTEGRATE
D4
D3
D2
D1
FIGURE 5. TIMING DIAGRAM FOR OUTPUTS
Component Value Selection
For optimum performance of the analog section, care must
be taken in the selection of values for the integrator capacitor
and resistor, auto-zero capacitor, reference voltage, and
conversion rate. These values must be chosen to suit the
particular application.
Integrating Resistor
The integrating resistor is determined by the full scale input
voltage and the output current of the buffer used to charge
the integrator capacitor. This current should be small
compared to the output short circuit current such that
thermal effects are kept to a minimum and linearity is not
affected. Values of 5µA to 40µA give good results with a
nominal of 20µA. The exact value may be chosen by:
Full Scale Voltage (See Note)
R I NT = ------------------------------------------------------------------------------20µA
NOTE: If gain is used in the buffer amplifier, then:
( Bu fferGa in ) (Full Scale Voltage)
R IN T = -------------------------------------------------------------------------------------------20µA
Integrating Capacitor
The product of integrating resistor and capacitor is selected
to give 9V swing for full scale inputs. This is a compromise
between possibly saturating the integrator (at +14V) due to
tolerance buildup between the resistor, capacitor and clock
and the errors a lower voltage swing could induce due to
offsets referred to the output of the comparator. In general,
the value of CINT is given by:
10
10,000(4-1/2 Digit)
× Clock Period × ( 20µA )
1000(3-1/2 Digit)
C I NT = ------------------------------------------------------------------------------------------------------------------------Integrator Output Voltage Swing
A very important characteristic of the integrating capacitor is
that it has low dielectric absorption to prevent roll-over or
ratiometric errors. A good test for dielectric absorption is to
use the capacitor with the input tied to the reference.
This ratiometric condition should be read half scale 1.0000,
and any deviation is probably due to dielectric absorption.
Polypropylene capacitors give undetectable errors at
reasonable cost. Polystyrene and polycarbonate capacitors
may be used in less critical applications.
Auto-Zero and Reference Capacitor
The size of the auto-zero capacitor has some influence on
the noise of the system, with a larger value capacitor giving
less noise. The reference capacitor should be large enough
such that stray capacitance to ground from its nodes is
negligible.
When gain is used in the buffer amplifier the reference
capacitor should be substantially larger than the auto-zero
capacitor. As a rule of thumb, the reference capacitor should
be approximately the gain times the value of the auto-zero
capacitor. The dielectric absorption of the reference cap and
auto-zero cap are only important at power-on or when the
circuit is recovering from an overload. Thus, smaller or
cheaper caps can be used here if accurate readings are not
required for the first few seconds of recovery.
ICL8052A/ICL71C03, ICL8068A/ICL71C03
10-50K
+15V -15V
REF
OUT
300pF
6
10kΩ
1kΩ
8
7
INT.
3 REF.
5
1
100kΩ
-BUF IN
BUF OUT
10
BUFFER
9
-INT IN
11
INTEG.
-
-
A1
+
A2
+
ICL8068A
INT OUT
14
COMP.
COMP
OUT
A3
+
2
-1.2V
+BUF IN 13
+INT IN 12
-15V
TO ICL7104
FIGURE 6. ADDING BUFFER GAIN TO ICL8068A
Reference Voltage
The analog input required to generate a full scale output is:
VIN = 2VREF.
The stability of the reference voltage is a major factor in the
overall absolute accuracy of the converter. For this reason, it
is recommended that an external high quality reference be
used where ambient temperature is not controlled or where
high-accuracy absolute measurements are being made.
Buffer Gain
At the end of the auto-zero interval, the instantaneous noise
voltage on the auto-zero capacitor is stored and subtracted
from the input voltage while adding to the reference voltage
during the next cycle. The result of this is that the noise
voltage is effectively somewhat greater than the input noise
voltage of the buffer itself during integration. By introducing
some voltage gain into the buffer, the effect of the auto-zero
noise (referred to the input) can be reduced to the level of
the inherent buffer noise. This generally occurs with a buffer
gain of between 3 and 10. Further increase in buffer gain
merely increases the total offset to be handled by the autozero loop, and reduces the available buffer and integrator
swings, without improving the noise performance of the
system. The circuit recommended for doing this with the
ICL8068A/ICL71C03 is shown in Figure 6.
ICL8052A vs ICL8068A
The ICL8052A offers significantly lower input leakage
currents than the ICL8068A, and may be found preferable in
systems with high input impedances. However, the
ICL8068A has substantially lower noise voltage, and is the
device of choice for systems where noise is a limiting factor,
particularly in low signal level conditions.
Max Clock Frequency
The maximum conversion rate of most dual-slope A/D
converters is limited by frequency response of the
comparator. The comparator in this circuit is no exception,
even though it is entirely NPN with an open-loop, gain11
bandwidth product of 300MHz. The comparator output
follows the integrator ramp with a 3µs delay, and at a clock
frequency of 160kHz (6µs period) half of the first reference
integrate clock period is lost in delay. This means that the
meter reading will change from 0 to 1 with 50µV input, 1 to 2
with 150µV, 2 to 3 at 250µV, etc. This transition at midpoint is
considered desirable by most users. However, if the clock
frequency is increased appreciably above 160kHz, the
instrument will flash “1” on noise peaks even when the input
is shorted.
For many dedicated applications where the input signal is
always on one polarity, the dealy of the comparator need not
be limitation. Since the non-linearity and noise do not
increase substantially with frequency, clock rates of up to
approximately 1MHz may be used. For a fixed clock
frequency, the extra count or counts caused by comparator
delay will be a constant and can be subtracted out digitally.
The minimum clock frequency is established by leakage on
the auto-zero and reference caps. With most devices,
measurement cycles as long as 10 seconds give no
measurable leakage error.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz,
40kHz, 331/3kHz, etc, should be selected. For 50Hz
rejection, oscillator frequencies of 250kHz, 1662/3kHz,
125kHz, 100kHz, etc. would be suitable. Note that 100kHz
(2.5 readings/second) will reject both 50Hz and 60Hz.
The clock used should be free from significant phase or
frequency jitter. A simple two-gate oscillator and one based
on CMOS 7555 timer are shown in the Applications section.
The multiplexed output means that if the display takes
significant current from the logic supply, the clock should
have good PSRR.
ICL8052A/ICL71C03, ICL8068A/ICL71C03
Applications
Specific Circuits Using the 8068A/71C03
8052A/A71C03
Figure 7 shows the complete circuit for a ±41/2 digit
(±200mV full scale) A/D converter with LED readout using
the internal reference of the 8068A/52A. If an external
reference is used, the reference supply (pin 7) should be
connected to ground and the 300pF reference cap deleted.
The circuit also shows a typical RC input filter. Depending on
the application, the time-constant of this filter can be made
faster, slower, or the filter deleted completely. The 1/2 digit
LED is driven from the 7-segment decoder, with a zero
reading blanked by connecting a D 5 signal to RBI input of
the decoder.
A voltage translation network is connected between the
comparator output of the 8068A/52A and the auto-zero input
of the 71C03. The purpose of this network is to assure that,
during auto-zero, the output of the comparator is at or near the
threshold of the 71C03 logic (+2.5V) while the auto-zero
capacitor is being charged to VREF (+100mV for a 200mV
instrument). Otherwise, even with 0V in, some reference
integrate period would be required to drive the comparator
output to the threshold level. This would show up as an
equivalent offset error. Once the divider network has been
selected, the unit-to-unit variation should contribute less than
a tenth of a count error. A second feature is the back-to-back
diodes, used to lower the noise. In the normal operating mode
they offer a high impedance and long integrating time
constant to any noise pulses charging the auto-zero cap. At
startup or recovery from an overload, their impedance is low
to large signals so that the cap can be charged up in one
auto-zero cycle. The buffer gain does not have to be set
precisely at 10 since the gain is used in both the integrate and
deintegrate phase. For scale factors other then 200mV the
gain of the buffer should be changed to give a ±2V buffer
output. For 2.0000V full scale this means unity gain and for
20,000mV (1µV resolution) a gain of 100 is necessary. Not all
8068As can operate properly at a gain of 100 since their offset
should be less than 10mV in order to accommodate the autozero circuitry. However, for devices selected with less than
10mV offset, the noise performance is reasonable with
approximately 1.5µV near full scale. On all scales less than
200mV, the voltage translation network should be made
adjustable as an offset trim.
12
The auto-zero cap should be 1µF for all scales and the
reference capacitor should be 1µF times the gain of the
buffer amplifier. At this value if the input leakages of the
8052A/ 8068A are equal, the droop effects will cancel giving
zero offset. This is especially important at high temperature.
Some typical component values are shown in Table 1. For
31/2 digit conversion, use 12kHz clock.
V++ = +15V, V+ = 5V, V- = -15V
Clock Freq. = 120kHz (41/2 Digit) or 12kHz (31/2 Digit)
TABLE 1.
SPECIFICATION
VALUE
UNITS
Full Scale VIN
20
200
2000
mV
Buffer Gain
( RB1 + RB2 )
-----------------------------------RB2
100
(See
Note)
10
1
V/V
RINT
100
100
100
kΩ
CINT
0.22
0.22
0.22
µF
CAZ
1.0
1.0
1.0
µF
CREF
10
10
1.0
µF
VREF
10
100
1000
mV
1
10
100
µV
Resolution (41/2 Digit)
NOTE: Comment on offset limitations above. Buffer gain does not
improve ICL8052A noise performance adequately.
ICL8052A/ICL71C03, ICL8068A/ICL71C03
+5V
5
4
3
2
1
150Ω
150Ω
7447
a
b
B1
c
B2
d
B3
e
B4
f
g RBI
4.7kΩ
150Ω
ICL71C03
+5V
1 V+
BUSY 28
2 4 1/2 / 31/2
3 POLARITY
D2 26
4 RUN/HOLD
D3 25
5 COMP IN
-15V
D4 24
6 V-
10kΩ
SIGNAL
INPUT
1.0µF
(MSB) B8 23
7 REFERENCE
10µF
47kΩ
(LSD) D1 27
ICL8068A
0.22µF
B4 22
8 REF. CAP. 1
B2 21
9 REF. CAP. 2
(LSB) B1 20
10 ANALOG IN
(MSD) D5 19
11 ANALOG GND
STROBE 18
0.1µF
12 CLOCK IN
300µF
36
kΩ
10
kΩ
A-Z IN 17
13 UNDER-RANGE
1 V-
-15V
INT OUT 14
2 COMP OUT
+BUFF IN 13
3 REF CAP
+INT IN 12
4 REF BYPASS
-INT IN 11
5 GND
A-Z OUT 16
-BUFF IN 10
300
kΩ
14 OVER-RANGE DIGITAL GND 15
CLOCK
IN
6 REF OUT
1kΩ
BUFF OUT 9
V++ 8
7 REF SUPPLY
-15V
120kHz = 3
READINGS/SEC
+15V
NOTE: For 31/2 digit, tie pin 2 low and change clock to 12kHz.
FIGURE 7. ICL8052A (8068A)/71C03A 41/2 DIGIT A/D CONVERTER
a
a
V+
POL
g
g
RBI BI D
PROG
0V
A
HI VOLTAGE BUFFER DI 505
47kΩ
5kΩ
0.02µF
0.02
µF
2.5kΩ
GATES
ARE
7409
POL D5
8052A/
8068A
0.02
µF 0.02
µF
0.02
µF
D4
D3
D2
71C03A
D1
B8
B4
B2
B1
FIGURE 8. ICL8052A-8068A/71C03A PLASMA DISPLAY CIRCUIT
13
+5V
3kΩ
DM8880
+5V
100
kΩ
10µF
90kΩ
10kΩ
ICL8052A/ICL71C03, ICL8068A/ICL71C03
driver circuit could be ganged to the one shown if required.
This would be useful if additional annunciators were needed.
A suitable circuit for driving a plasma-type display is shown
in Figure 8. The high voltage anode driver buffer is made by
Dionics. The 3 AND gates and caps driving “Bl” are needed
for interdigit blanking of multiple-digit display elements, and
can be omitted if not needed. The 2K and 3K resistors set
the current levels in the display. A similar arrangement can
be used with “Nixie” tubes.
Figure 10 shows the complete circuit for a 41/2 digit
(±2.000V) A/D, again using the internal reference of the
8052A/8068A.
Figure 11 shows a more complicated circuit for driving LCD
displays. Here the data is latched into the ICM7211 by the
STROBE signal and “Overrange” is indicated by blanking the
4 digits. A clock oscillator circuit using the ICM7555 CMOS
timer is shown. Some other suitable clock circuits are
suggested in Figures 12 and 13. The 2-gate circuit should
use CMOS gates to maintain good power supply rejection.
Nixie is a registered trademark of Burroughs Corporation.
Analog and Digital Grounds
Extreme care must be taken to avoid ground loops in the
layout of 8068A or 8052A/71C03A circuits, especially in high
sensitivity circuits. It is most important that return currents
from digital loads are not fed into the analog ground line.
Both of the above circuits have considerable current flowing
in the digital ground returns from drivers, etc. A
recommended connection sequence for the ground lines is
shown in Figure 9.
A problem sometimes encountered with the
8052A/68A/71C03 A/D is that of gross over-voltage applied
in the input. Voltage in excess of ±2.000V may cause the
integrator output to saturate. When this occurs, the integrator
can no longer source (or sink) the current required to hold
the summing junction (Pin 11) at the voltage stored on the
auto zero capacitor. As a result, the voltage across the
integrator capacitor decreases sufficiently to give a false
voltage reading. This problem can also show up as largesignal instability on overrange conditions. A simple solution
to this problem is to use junction FET transistors across the
integrator capacitor to source (or sink) current into the
summing junction and prevent the integrator amplifier from
saturating, as shown in Figure 14.
Other Circuits for Display Applications
Popular LCD displays can be interfaced to the Output of the
ICL71C03 with suitable display drivers, such as the
ICM7211A as shown in Figure 10. A standard CMOS 4000
series LCD driver circuit is used for displaying the 1/2 digit,
the polarity, and the “over-range” flag. A similar circuit can be
used with the ICM7212A LED driver. Of course, another full
BUFF
OUT
+
VIN
-
I/P
FILTER
CAP
PIN 11
ICL71C03
AN GND
CAZ
BUFF
-IN
(IF USED)
REF
VOLTAGE
VREF
EXTERNAL
REFERENCE
(IF USED)
ANALOG SUPPLY
BYPASS CAPACITORS
+15V
-15V
PIN 5
ICL8052A/68A
AN GND
ANALOG
SUPPLY
RETURN
8068A PIN 2
COMPARATOR
BOARD
EDGE
DIGITAL
SUPPLY
RETURN
DIGITAL
LOGIC
DIG GND
ICL7104
PIN 2
DEVICE PIN
+5V SUPPLY BYPASS CAPACITOR(S)
FIGURE 9. GROUNDING SEQUENCE
14
ICL8052A/ICL71C03, ICL8068A/ICL71C03
41/2 DIGIT LCD DISPLAY
28 SEGMENTS
D1 - D4
+5V
1 16 15 14 12 5 3 4
CD4054A
7 8 13 11 10 9 2 6
BACKPLANE
0V
1 V+
-15V
1µF
ICM7211A
ICL71C03
+5V
2 41/2 / 31/2
D1 27
31 D 1
3 POL
D2 26
32 D 2
4 R/H
D3 25
33 D 3
5 COMP IN
D4 24
34 D 4
6 V-
B8 23
30 B 3
7 REF
B4 22
29 B 2
8 REF. CAP. 1
B2 21
9 REF. CAP. 2
B1 20
100kΩ
10 INPUT
INPUT
0.1µF
5 BP
BUSY 28
2, 3, 4
6 - 26
37 - 40
OPTIONAL
CAPACITOR
+5V
28 B 1 OSC 36
22-100pF
27 B 0
D5 19
35 V-
V+ 1
11 ANALOG GND STROBE 18
0V
12 CLOCK
A-Z IN 17
13 UR
A-Z OUT 16
14 OR
DIG GND 15
0V
CLOCK IN (120kHz = 3 READINGS/SEC)
1.0µF
-15V
1
14
2
13
0.22µF
300µF
36kΩ
3
ICL8052A
8068A
12
4
11
5
10
6
9
7
8
300kΩ
-15V
5kΩ
100kΩ
+15V
10kΩ
10µF
ANALOG GND
FIGURE 10. DRIVING LCD DISPLAYS
15
+5V
ICL8052A/ICL71C03, ICL8068A/ICL71C03
+5V
41/2 DIGIT LCD DISPLAY
28 SEGMENTS
D1 - D4
1/ CD4030
2
BACKPLANE
ICM7211A
+5V
ICL71C03(A)
1 V+
-15V
D1 27
3 POL
D2 26
32 D2
4 R/H
D3 25
33 D3
5 COMP IN
D4 24
34 D4
6 V-
B8 23
7 REF
B4 22
8 REF. CAP. 1
B2 21
28 B1
9 REF. CAP. 2
B1 20
27 B0
100kΩ
10 INPUT
0.1µF
1/ CD4030
4
2 41/2 / 31/2
1µF
INPUT
5 BP
BUSY 28
CD4081
31 D1
CD4071
30 B3
29 B2
2, 3, 4
6 - 26
37 - 40
OPTIONAL
CAPACITOR
+5V
OSC 36
22-100pF
CD4071
D5 19
V+ 1
35 V-
11 ANALOG GND STROBE 18
0V
12 CLOCK
13 UR
A-Z OUT 16
14 OR
DIG GND 15
+5V
+5V
1/ CD4030
4
0V
4.7kΩ
0V
1 V2
1.0µF
+5V
-15V
+5V
A-Z IN 17
1
14
2
13
V+ 8
ICM7555
7
3 OUT
6
4 RESET
5
10 TO 15kΩ
ADJUST TO
FCL = 120kHz
0.22µF
300µF
36kΩ
3
ICL8052A
8068A
300pF
12
4
11
5
10
6
9
7
8
0V
300kΩ
-15V
5kΩ
100kΩ
+15V
10kΩ
10µF
ANALOG GND
FIGURE 11. 41/2 DIGIT LCD DPM WITH DIGIT BLANKING ON OVERRANGE
16
ICL8052A/ICL71C03, ICL8068A/ICL71C03
+5V
1kΩ
16kΩ
56kΩ
2
LM311
-
3
fOSC = 0.45/RC
R
37.5kΩ
8
+
0.22µF
7
1
4
30kΩ
16kΩ
390pF
C
100pF
FIGURE 12. CMOS OSCILLATOR
+15V
REF
OUT
300pF
6
FIGURE 13. LM311 OSCILLATOR
8
7
REF
COMP
5
1
S 2N5461
D
S 2N5458
100K
0.22µF
-BUF IN
BUF OUT
-INT IN
10
BUFFER
9
-15V
INT.
3 REF.
D
11
INTEG.
-
-
A1
+
A2
+
+BUF IN 13
8052A/
8068A
INT OUT
14
COMP.
COMP
OUT
A3
+
2
-1.2V
+INT IN 12
TO ICL71C03
FIGURE 14. GROSS OVERVOLTAGE PROTECTION CIRCUIT
Interfacing with UARTs and
Microprocessors
Figure 15 shows a very simple interface between a freerunning 8068A/8052A/71C03A and a UART. The five
STROBE pulses start the transmission of the five data words.
The digit 5 word is 0000XXXX, digit 4 is 1000XXXX, digit 3 is
0100XXXX, etc. Also, the polarity is transmitted indirectly by
using it to drive the Even Parity Enable Pin (EPE). If EPE of
the receiver is held low, a parity flag at the receiver can be
decoded as a positive signal, no flag as negative. A complex
arrangement is shown in Figure 14. Here the UART can
instruct the A/D to begin a measurement sequence by a word
on RRI. The Busy signal resets the Data Ready Reset (DRR).
Again STROBE starts the transmit sequence. A quad 2 input
multiplexer is used to superimpose polarity, over-range, and
under-range onto the D5 word since in this instance it is
known that B2 = B4 = B8 = 0.
For correct operation it is important that the UART clock be
fast enough that each word is transmitted before the next
STROBE pulse arrives. Parity is locked into the UART at
load time but does not change in this connection during an
output stream.
17
Circuits to interface the 71C03(A) directly with three popular
microprocessors are shown in Figures 17, 18 and 19. The
main differences in the circuits are that the IM6100 with its
12-bit word capability can accept polarity, over-range, underrange, 4 bits of BCD and 5 digits simultaneously where the
8080/8048 and the MC6800 groups with 8-bit words need to
have polarity, over-range and under-range multiplexed onto
the Digit 5 word - as in the UART circuits. In each case the
microprocessor can instruct the A/D when to begin a
measurement and when to hold this measurement.
Application Notes
NOTE #
DESCRIPTION
AN016
“Selecting A/D Converters”
AN017
“The Integrating A/D Converter”
AN018
“Do’s and Don’ts of Applying A/D Converters”
AN023
“Low Cost Digital Panel Meter Designs”
AN028
“Build an Auto-Ranging DMM Using the 8052A / 7103A
A/D Converter Pair,” by Larry Goff
ICL8052A/ICL71C03, ICL8068A/ICL71C03
SERIAL OUTPUT
TO RECEIVING UART
TRO
UART
IM6402/3
TBRL
EPE
TBR
NC
1
2
3
4
5
6
7
8
D4
D3
D2
D1
B1
B2
B4
B8
D5
STROBE
71C03/A
POL
RUN/HOLD
+5V
FIGURE 15. SIMPLE ICL71C03/71C03A TO UART INTERFACE
TRO
RRI
DRR
UART
IM6402/3
DR
EPE
TBRL
TBR
1
2
3
4
5
6
7
8
1Y
2Y
3Y
ENABLE
74C157
D4
D3
D2
D1
B1
1A
2A
3A SELECT 1B
B2
B4
B8
2B
3B
POL OVER UNDER
D5
71C03/A
STROBE
RUN/HOLD
BUSY
+5V
100pF
FIGURE 16. COMPLEX ICL71C03/7103A TO UART INTERFACE
18
10kΩ
ICL8052A/ICL71C03, ICL8068A/ICL71C03
12
12
1
12
1
80C95
80C95
15
15
READ 1
IM6101
IM6100
B1 B2 B4 B8 POL OVER
D1 D2 D3 D4 D5
71C03/A
STROBE
SENSE 1
RUN/HOLD
WRITE 1
7
FIGURE 17. IM6100 TO ICL71C03A/71C03A INTERFACE
EN
74C157
PA0
2Y
PA1
OVER
RUN/
HOLD
UNDER
POL
PA3
D5 B8 B4 B2 B1
71C03
STROBE
D1
D2
D3
D4
2Y
PA1
PA2
MC6820
MC680X
OR
MCS650X
PA4
PA5
PA6
PA7
OVER
1B 2B 3B SEL 1A 2A 3A 3Y
PA0
1B 2B 3B SEL 1A 2A 3A 3Y
RUN/
HOLD
UNDER
74C157
1Y
POL
EN
1Y
D5 B 8 B4 B2 B1
71C03
STROBE
D1
D2
D3
D4
PA2
PA3
8255
(MODE 1)
8080,
8085,
ETC.
PA4
PA5
PA6
PA7
STBA PB0
CA1 CA2
FIGURE 18. ICL71C03 TO MC6800, MCS650X INTERFACE
19
FIGURE 19. ICL71C03 TO MCS-48, -80, -85 INTERFACE
ICL8052A/ICL71C03, ICL8068A/ICL71C03
ICL71C03 with ICL8052A/8068A Integrating A/D Converter Equations
The ICL71C03 does not have an internal crystal or RC
oscillator. It has a clock input only.
Integration Period
10, 000
tI NT = --------------------- ( 4-1/2 Digit )
fCLOCK
Integrator Output Voltage
( t INT ) ( I IN T )
VI NT = -------------------------------C INT
VINT (Typ) = 9V
Output Count
1, 000
tI NT = --------------------- ( 3-1/2 Digit )
fCLOCK
VI N
Count = 10, 000 × --------------- (4-1/2 Digit)
V REF
Integration Clock Period
V IN
Count = 1, 000 × --------------- (3-1/2 Digit)
VREF
tCLOCK = 1/fCLOCK
NOTE: The 41/2 digit mode’s LSD will be output as a zero in the 31/2
digit mode.
60/50Hz Rejection Criterion
tINT/t60Hz or tINT/t50Hz = Integer
Output Type:
Optimum Integration Current
4 Nibbles BCD with Polarity and Over-range.
IINT = 20µA
Power Supply: ±15V, +5V
Full Scale Analog Input Voltage
V++ = +15V
V- = -15V
V+ = +5V
VREF ≅ 1.75V
If VREF not used, float output pin.
VINFS (Typ) = 200mV to 2.0V = 2VREF
Integrate Resistor
( BufferG ain ) × VIN FS
R I NT = ------------------------------------------------------------II NT
Auto Zero Capacitor Values
Integrate Capacitor
0.01µF < C AZ < 1µF
( tI NT ) ( I INT )
C I NT = -------------------------------V INT
Reference Capacitor Value
CREF = (Buffer Gain) x CAZ
AUTO ZERO
(COUNTS)
30,001 - 10,001
3,001 - 1,001
INTEGRATE
(FIXED COUNT)
10,000
1,000
DEINTEGRATE
(COUNTS)
1 - 20,001
1 - 2,001
TOTAL CONVERSION TIME (tCONV)
(IN CONTINUOUS MODE)
tCONV = 40,002 * tCLOCK (41/2 DIGIT MODE)
tCONV = 4,002 * tCLOCK (31/2 DIGIT MODE)
FIGURE 20. INTEGRATOR OUTPUT
20
(41/2 DIGIT)
(31/2 DIGIT)
ICL8052A/ICL71C03, ICL8068A/ICL71C03
Dual-In-Line Plastic Packages (PDIP)
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AE
D
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8
eA
C
0.008
0.014
C
D
0.735
0.775
18.66
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
0.005
-
0.13
-
5
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
eB
-
L
0.115
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
N
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
21
5
E
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
0.355
19.68
D1
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
0.204
14
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
10.92
3.81
14
6
7
4
9
Rev. 0 12/93
ICL8052A/ICL71C03, ICL8068A/ICL71C03
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-011-AB ISSUE B)
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N
E1
INDEX
AREA
1 2 3
INCHES
N/2
SYMBOL
-B-AE
D
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M C A B S
MILLIMETERS
MIN
MAX
MIN
MAX
NOTES
A
-
A1
0.015
0.250
-
6.35
4
-
0.39
-
4
A2
0.125
0.195
3.18
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.030
0.070
0.77
1.77
8
eA
C
0.008
0.015
0.204
0.381
-
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
D
1.380
1.565
D1
0.005
-
35.1
0.13
E
0.600
0.625
15.24
15.87
6
E1
0.485
0.580
12.32
14.73
5
0.100 BSC
2.54 BSC
-
0.600 BSC
15.24 BSC
6
17.78
7
5.08
4
-
0.700
-
L
0.115
0.200
2.93
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
N
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
22
5
e
eB
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
5
-
eA
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
39.7
28
28
9
Rev. 1 12/00
ICL8052A/ICL71C03, ICL8068A/ICL71C03
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
eA
e
ccc M C A - B S
eA/2
c
aaa M C A - B S D S
D S
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MAX
A
Q
SEATING
PLANE
MILLIMETERS
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.785
-
19.94
5
E
0.220
0.310
5.59
7.87
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
14
14
8
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
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