TI1 LM139AFKB Low-power low-offset voltage quad comparator Datasheet

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LM139-N, LM239-N, LM2901-N, LM3302-N, LM339-N
SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
LMx39-N, LM2901-N, LM3302-N Low-Power Low-Offset Voltage Quad Comparators
1 Features
3 Description
•
•
•
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The LMx39-N series consists of four independent
precision voltage comparators with an offset voltage
specification as low as 2 mV maximum for all four
comparators. These comparators were designed
specifically to operate from a single power supply
over a wide range of voltages. Operation from split
power supplies is also possible and the low power
supply current drain is independent of the magnitude
of the power supply voltage. These comparators also
have a unique characteristic in that the input
common-mode voltage range includes ground, even
though they are operated from a single power supply
voltage.
1
•
•
•
•
•
•
•
•
Wide Supply Voltage Range
LM139/139A Series 2 to 36 VDC or ±1 to ±18 VDC
LM2901-N: 2 to 36 VDC or ±1 to ±18 VDC
LM3302-N: 2 to 28 VDC or ±1 to ±14 VDC
Very Low Supply Current Drain (0.8 mA) —
Independent of Supply Voltage
Low Input Biasing Current: 25 nA
Low Input Offset Current: ±5 nA
Offset Voltage: ±3 mV
Input Common-Mode Voltage Range Includes
GND
Differential Input Voltage Range Equal to the
Power Supply Voltage
Low Output Saturation Voltage: 250 mV at 4 mA
Output Voltage Compatible With TTL, DTL, ECL,
MOS, and CMOS Logic Systems
Advantages:
– High-Precision Comparators
– Reduced VOS Drift Overtemperature
– Eliminates Need for Dual Supplies
– Allows Sensing Near GND
– Compatible With All Forms of Logic
– Power Drain Suitable for Battery Operation
The LMx39-N series was designed to directly
interface with TTL and CMOS. When operated from
both plus and minus power supplies, the devices
directly interface with MOS logic— where the low
power drain of the LM339 is a distinct advantage over
standard comparators.
Device Information(1)
PART NUMBER
LM139-N
LM239-N
LM2901-N
LM339-N
2 Applications
•
•
•
•
•
Limit Comparators
Simple Analog-to-Digital Converters (ADCs)
Pulse, Squarewave, and Time Delay Generators
Wide Range VCO; MOS Clock Timers
Multivibrators and High-Voltage Digital Logic
Gates
PACKAGE
BODY SIZE (NOM)
CDIP (14)
19.56 mm × 6.67 mm
SOIC (14)
8.65 mm × 3.91 mm
PDIP (14)
19.177 mm × 6.35 mm
CDIP (14)
19.56 mm × 6.67 mm
SOIC (14)
8.65 mm × 3.91 mm
PDIP (14)
19.177 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
One-Shot Multivibrator With Input Lock Out
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM139-N, LM239-N, LM2901-N, LM3302-N, LM339-N
SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
5
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: LM139A, LM239A,
LM339A, LM139.........................................................
6.6 Electrical Characteristics: LM239, LM339, LM2901,
LM3302 .....................................................................
6.7 Typical Characteristics ..............................................
7
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Applications ................................................ 12
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
6
7
8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
11.1
11.2
11.3
11.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Revision D (March 2013) to Revision E
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision C (March 2013) to Revision D
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 10
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SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
J, D and NFF Package
14-Pin CDIP, SOIC, PDIP
Top View
14-Pin CLGA Package
Top View
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
OUTPUT2
O
Output, Channel 2
2
OUTPUT1
O
Output, Channel 1
3
V+
P
Positive Supply
4
INPUT1-
I
Inverting Input, Channel 1
5
INPUT1+
I
Noninverting Input, Channel 1
6
INPUT2-
I
Inverting Input, Channel 2
7
INPUT2+
I
Noninverting Input, Channel 2
8
INPUT3-
I
Inverting Input, Channel 3
9
INPUT3+
I
Noninverting Input, Channel 3
10
INPUT4-
I
Inverting Input, Channel 4
11
INPUT4+
I
Noninverting Input, Channel 4
12
GND
P
Ground
13
OUTPUT4
O
Output, Channel 4
14
OUTPUT3
O
Output, Channel 3
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SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
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6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
Supply Voltage, V+
Differential Input Voltage
Input Voltage
28
LM139N, LM239N, LM339N, LM2901N
LM3302N
(2)
36
(2)
LM139N, LM239N, LM339N, LM2901N
−0.3
36
LM3302
–0.3
28
(3)
50
PDIP
1050
Cavity DIP
1190
SOIC Package
260
SOIC Package
260
Vapor Phase (60 seconds)
215
Infrared (15 seconds)
220
−65
Storage temperature, Tstg
(4)
(5)
mW
760
PDIP Package (10 seconds)
(3)
mA
Continuous
Lead Temperature (Soldering, 10 seconds)
(1)
(2)
VDC
28
Output Short-Circuit to GND (5)
Soldering Information
UNIT
36
LM3302N
Input Current (VIN<−0.3 VDC)
Power Dissipation (4)
MAX
LM139N, LM239N, LM339N, LM2901N
°C
150
Refer to RETS139AX for LM139A military specifications and to RETS139X for LM139 military specifications.
Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3 VDC (or 0.3 VDC below
the magnitude of the negative power supply, if used) (at 25°C).
This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of
the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is
also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go
to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive
and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than −0.3 VDC (at
25°C).
For operating at high temperatures, the LM339/LM339A, LM2901, LM3302 must be derated based on a 125°C maximum junction
temperature and a thermal resistance of 95°C/W which applies for the device soldered in a printed circuit board, operating in a still air
ambient. The LM239-N and LM139-N must be derated based on a 150°C maximum junction temperature. The low bias dissipation and
the “ON-OFF” characteristic of the outputs keeps the chip dissipation very small (PD≤100 mW), provided the output transistors are
allowed to saturate.
Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 20 mA independent of the magnitude of V+.
6.2 ESD Ratings
V(ESD)
(1)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±600
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
LM139N, LM239N, LM339N, LM2901N
2
36
LM3302N
2
28
LM139N, LM239N, LM339N, LM2901N
±1
±18
LM3302N
±1
±14
LM139/LM139A
−55
125
LM2901/LM3302
−40
85
LM239/LM239A
−25
85
LM339/LM339A
0
70
Single Supply
Supply Voltage
Dual Supply
Operating Temperature
UNIT
V
°C
6.4 Thermal Information
THERMAL METRIC (1)
LM139-N,
LM239-N,
LM339-N
LM2901-N,
LM339-N
LM2901-N,
LM339-N
J
D
NFF
UNIT
14 PINS
RθJA
(1)
Junction-to-ambient thermal resistance
95
95
95
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 1999–2014, Texas Instruments Incorporated
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SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
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6.5 Electrical Characteristics: LM139A, LM239A, LM339A, LM139
(V+=5 VDC, TA = 25°C (1) unless otherwise stated)
PARAMETER
TEST CONDITIONS
LM139A
MIN
TYP
LM239A, LM339A
MAX
MIN
TYP
MAX
LM139
MIN
TYP
MAX
UNIT
Input Offset Voltage
See (2)
1.0
2.0
1.0
2.0
2.0
5.0
mVDC
Input Bias Current
IIN(+) or IIN(−) with Output in
Linear Range (3), VCM=0 V
25
100
25
250
25
100
nADC
Input Offset Current
IIN(+) − IIN(−), VCM= 0 V
3.0
25
5.0
50
3.0
25
nADC
Input Common-Mode
Voltage Range
V+=30 VDC (LM3302,
V+−1.5
VDC
Supply Current
(LM3302, V+ = 28 VDC), RL = ∞
on all Comparators
V+ = 28 VDC) (4)
V+−1.5
0
0.8
V+−1.5
0
2.0
0
0.8
2.0
0.8
2.0
mADC
1.0
2.5
1.0
2.5
mADC
+
(LM3302, V = 28 VDC), RL =
∞, V+ = 36 V
Voltage Gain
RL≥15 kΩ, V+ = 15 VDC
VO = 1 VDC to 11 VDC
Large Signal
Response Time
50
200
50
200
50
200
V/mV
VIN = TTL Logic Swing, VREF =
1.4 VDC, VRL = 5 VDC,
300
300
300
ns
1.3
1.3
1.3
μs
16
mADC
RL = 5.1 kΩ
Response Time
VRL = 5 VDC, RL = 5.1 kΩ (5)
Output Sink Current
VIN(−) = 1 VDC, VIN(+) = 0,
VO ≤ 1.5 VDC
Saturation Voltage
6.0
VIN(−) = 1 VDC, VIN(+) = 0,
16
250
ISINK ≤ 4 mA
6.0
400
16
250
6.0
400
250
400
mVDC
Output Leakage
Current
VIN(+) = 1 VDC, VIN(−) = 0,
Input Offset Voltage
See (2)
4.0
4.0
9.0
mVDC
Input Offset Current
IIN(+)−IIN(−), VCM = 0 V
100
150
100
nADC
Input Bias Current
IIN(+) or IIN(−) with Output in
300
400
300
nADC
0.1
VO = 5 VDC
0.1
0.1
nADC
Linear Range, VCM = 0 V (3)
Input Common-Mode
V+=30 VDC (LM3302),
+
0
V+−2.0
0
V+−2.0
0
V+−2.0
(4)
VDC
Voltage Range
V = 28 VDC)
Saturation Voltage
VIN(−)=1 VDC, VIN(+) = 0,
ISINK ≤ 4 mA
700
700
700
mVDC
Output Leakage
Current
VIN(+) = 1 VDC, VIN(−) = 0,
VO = 30 VDC, (LM3302,
VO = 28 VDC)
1.0
1.0
1.0
μADC
Differential Input
Voltage
Keep all VIN's ≥ 0 VDC (or V−, if
used) (6)
36
36
36
VDC
(1)
(2)
(3)
(4)
(5)
(6)
6
These specifications are limited to −55°C ≤ TA ≤ 125°C, for the LM139/LM139A. With the LM239/LM239A, all temperature specifications
are limited to −25°C ≤ TA ≤ 85°C, the LM339/LM339A temperature specifications are limited to 0°C ≤ TA ≤ 70°C, and the LM2901,
LM3302 temperature range is −40°C ≤ TA ≤ 85°C.
At output switch point, VO≃1.4 VDC, RS = 0 Ω with V+ from 5 VDC to 30 VDC; and over the full input common-mode range (0 VDC to V+
−1.5 VDC), at 25°C. For LM3302, V+ from 5 VDC to 28 VDC.
The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the reference or input lines.
The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end
of the common-mode voltage range is V+ −1.5V at 25°C, but either or both inputs can go to 30 VDC without damage (25V for LM3302),
independent of the magnitude of V+.
The response time specified is a 100-mV input step with 5-mV overdrive. For larger overdrive signals 300 ns can be obtained, see
typical performance characteristics section.
Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3 VDC (or 0.3 VDCbelow
the magnitude of the negative power supply, if used) (at 25°C).
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6.6 Electrical Characteristics: LM239, LM339, LM2901, LM3302
(V+ = 5 VDC, TA = 25°C (1) unless otherwise stated)
LM239, LM339
PARAMETER
TEST CONDITIONS
MI
N
TYP
MAX
LM2901
MIN
LM3302
TYP
MAX
MIN
TYP
MAX
UNIT
Input Offset Voltage
See (2)
2.0
5.0
2.0
7.0
3
20
mVDC
Input Bias Current
IIN(+) or IIN(−) with Output in Linear
Range (3), VCM=0 V
25
250
25
250
25
500
nADC
Input Offset Current
IIN(+)−IIN(−), VCM = 0 V
5.0
50
5
50
3
100
nADC
V+−1.5
VDC
Input Common-Mode V+ = 30 VDC (LM3302,
Voltage Range
V+ = 28 VDC) (4)
Supply Current
Voltage Gain
V+−1.5
0
0
(LM3302, V+ = 28 VDC) RL = ∞ on
all Comparators
0.8
2.0
0.8
2.0
0.8
2.0
mADC
(LM3302, V+ = 28 VDC) RL = ∞, V+
= 36 V
1.0
2.5
1.0
2.5
1.0
2.5
mADC
RL ≥ 15 kΩ, V+ = 15 VDC
VO = 1 VDC to 11 VDC
Large Signal
Response Time
V+−1.5
0
50
200
25
100
2
V/mV
30
VIN = TTL Logic Swing, VREF =
ns
1.4 VDC, VRL = 5 VDC,
300
300
300
1.3
1.3
1.3
RL = 5.1 kΩ,
Response Time
VRL = 5 VDC, RL = 5.1 kΩ (5)
Output Sink Current
VIN(−)= 1 VDC, VIN(+) = 0,
VO ≤ 1.5 VDC
Saturation Voltage
VIN(−) = 1 VDC, VIN(+) = 0,
ISINK ≤ 4 mA
6.0
16
250
6.0
400
Output Leakage
Current
VIN(+) = 1 VDC,VIN(−) = 0,
Input Offset Voltage
See (2)
9.0
Input Offset Current
IIN(+)− IIN(−), VCM = 0 V
Input Bias Current
IIN(+) or IIN(−) with Output in
VO = 5 VDC
16
250
0.1
6.0
400
mADC
16
250
0.1
μs
500
nADC
0.1
9
15
150
50
400
200
mVDC
40
mVDC
200
300
nADC
500
1000
nADC
V+−2.0
VDC
700
700
mVDC
Linear Range, VCM = 0V (3)
Input Common-Mode V+ = 30 VDC (LM3302, V+ = 28
VDC)
V+−2.0
V+−2.0
0
0
Voltage Range
See (4)
Saturation Voltage
VIN(−) = 1 VDC, VIN(+) = 0,
ISINK ≤ 4 mA
700
Output Leakage
Current
VIN(+) = 1 VDC, VIN(−) = 0, VO = 30
VDC, (LM3302, V O = 28 VDC)
1.0
1.0
1.0
μADC
Differential Input
Voltage
Keep all VIN's ≥ 0 VDC (or V−, if
used) (6)
36
36
28
VDC
(1)
(2)
(3)
(4)
(5)
(6)
400
These specifications are limited to −55°C ≤ TA ≤ 125°C, for the LM139/LM139A. With the LM239/LM239A, all temperature specifications
are limited to −25°C ≤ TA ≤ 85°C, the LM339/LM339A temperature specifications are limited to 0°C ≤ TA ≤ 70°C, and the LM2901,
LM3302 temperature range is −40°C ≤ TA ≤ 85°C.
At output switch point, VO≃1.4 VDC, RS = 0 Ω with V+ from 5 VDC to 30 VDC; and over the full input common-mode range (0 VDC to V+
−1.5 VDC), at 25°C. For LM3302, V+ from 5 VDC to 28 VDC.
The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the reference or input lines.
The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end
of the common-mode voltage range is V+ −1.5V at 25°C, but either or both inputs can go to 30 VDC without damage (25V for LM3302),
independent of the magnitude of V+.
The response time specified is a 100-mV input step with 5-mV overdrive. For larger overdrive signals 300 ns can be obtained, see
typical performance characteristics section.
Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3 VDC (or 0.3 VDCbelow
the magnitude of the negative power supply, if used) (at 25°C).
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6.7 Typical Characteristics
6.7.1 LM139/LM239/LM339, LM139A/LM239A/LM339A, LM3302
Figure 1. Supply Current
Figure 2. Input Current
Figure 3. Output Saturation Voltage
Figure 4. Response Time for Various Input Overdrives –
Negative Transition
Figure 5. Response Time for Various Input Overdrives –
Positive Transition
8
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6.7.2 LM2901
Figure 6. Supply Current
Figure 7. Input Current
Figure 8. Output Saturation Voltage
Figure 9. Response Time for Various Input Overdrives –
Negative Transition
Figure 10. Response Time for Various Input Overdrives –
Positive Transition
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7 Detailed Description
7.1 Overview
The LM139/LM239/LM339 family of devices is a monolithic quad of independently functioning comparators
designed to meet the needs for a medium-speed, TTL compatible comparator for industrial applications. Since no
antisaturation clamps are used on the output such as a Baker clamp or other active circuitry, the output leakage
current in the OFF state is typically 0.1 nA. This makes the device ideal for system applications where it is
desired to switch a node to ground while leaving it totally unaffected in the OFF state. Other features include
single supply, low voltage operation with an input common mode range from ground up to approximately one volt
below VCC . The output is an uncommitted collector so it may be used with a pullup resistor and a separate
output supply to give switching levels from any voltage up to 36V down to a V CE SAT above ground
(approximately 100 mV), sinking currents up to 16 mA. The open collector output configuration allows the device
to be used in wired-OR configurations, such as a window comparators.
In addition it may be used as a single pole switch to ground, leaving the switched node unaffected while in the
OFF state. Power dissipation with all four comparators in the OFF state is typically 4 mW from a single 5-V
supply (1 mW/comparator).
7.2 Functional Block Diagram
7.3 Feature Description
The LMx39-N series are high-gain, wide bandwidth devices which, like most comparators, can easily oscillate if
the output lead is inadvertently allowed to capacitively couple to the inputs through stray capacitance. This shows
up only during the output voltage transition intervals as the comparator changes states. Reducing the input
resistors to < 10 kΩ reduces the feedback signal levels and finally, adding even a small amount (1 to 10 mV) of
positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are not
possible. Simply socketing the IC and attaching resistors to the pins will cause input-output oscillations during the
small transition intervals unless hysteresis is used. If the input signal is a pulse waveform, with relatively fast rise
and fall times, hysteresis is not required.
The differential input voltage may be larger than V+ without damaging the device. Protection should be provided
to prevent the input voltages from going negative more than −0.3 VDC (at 25°C). An input clamp diode can be
used as shown in the applications section.
The output of the LMx39-N series is the uncommitted collector of a grounded-emitter NPN output transistor.
Many collectors can be tied together to provide an output OR'ing function. An output pullup resistor can be
connected to any available power supply voltage within the permitted supply voltage range and there is no
restriction on this voltage due to the magnitude of the voltage which is applied to the V+ terminal of the LM139A
package. The output can also be used as a simple SPST switch to ground (when a pullup resistor is not used).
10
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LM139-N, LM239-N, LM2901-N, LM3302-N, LM339-N
www.ti.com
SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
Feature Description (continued)
The amount of current which the output device can sink is limited by the drive available (which is independent of
V+) and the β of this device. When the maximum current limit is reached (approximately 16 mA), the output
transistor will come out of saturation and the output voltage will rise very rapidly. The output saturation voltage is
limited by the approximately 60-Ω RSAT of the output transistor. The low offset voltage of the output transistor (4
mV) allows the output to clamp essentially to ground level for small load currents.
7.4 Device Functional Modes
A basic comparator circuit is used for converting analog signals to a digital output. The output is HIGH when the
voltage on the non-inverting (+IN) input is greater than the inverting (-IN) input. The output is LOW when the
voltage on the noninverting (+IN) input is less than the inverting (-IN) input. The inverting input (-IN) is also
commonly referred to as the "reference" or "VREF" input.
All pins of any unused comparators should be tied to the negative supply.
The bias network of the LMx39-N series establishes a drain current which is independent of the magnitude of the
power supply voltage over the range of from 2 VDC to 30 VDC.
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SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM139-N is specified for operation from 2.0 V to 36 V (±1V to ±18V) over the temperature range of –55°C to
125°C. While it may seem like a comparator has a well-defined and somewhat limited functionality as a '1-bit
ADC', a comparator is a versatile component which can be used for many functions.
Refer to AN-74 LM139/LM239/LM339 A Quad of Independently Functioning Comparators (SNOA654) for
additional application information on use of the LM139-N.
8.2 Typical Applications
8.2.1 Basic Comparator
Figure 11. Basic Comparator Schematic
8.2.1.1 Design Requirements
The basic usage of a comparator is to indicate when a specific analog signal has exceeded some predefined
threshold. In this application, the negative input is tied to a reference voltage, and the positive input is connected
to the input signal. The output is pulled up with a resistor to the logic supply voltage, V+.
For an example application, the supply voltage is 5 V. The input signal varies between 1 V and 3 V, and we want
to know when the input exceeds 2.5 V. For this example, we would set the VREF to 2.5 V.
8.2.1.2 Application Curve
Figure 12. Basic Comparator Response
12
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SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
Typical Applications (continued)
8.2.2 System Examples
Figure 13. Driving CMOS
(V+ = 5.0 VDC)
Figure 14. Driving TTL
(V+ = 5.0 VDC)
Figure 15. AND Gate
(V+ = 5.0 VDC)
Figure 16. OR Gate
(V+ = 5.0 VDC)
Figure 17. One-Shot Multivibrator
(V+= 15 VDC)
Figure 18. Bi-Stable Multivibrator
(V+= 15 VDC)
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SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
www.ti.com
Typical Applications (continued)
Figure 19. One-Shot Multivibrator with Input Lock
Out
(V+= 15 VDC)
Figure 20. Pulse Generator
(V+= 15 VDC)
Figure 21. Large Fan-In AND Gate
(V+= 15 VDC)
Figure 22. ORing the Outputs
(V+= 15 VDC)
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www.ti.com
SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
Typical Applications (continued)
Figure 23. Time Delay Generator
(V+= 15 VDC)
Figure 24. Non-Inverting Comparator with
Hysteresis
(V+= 15 VDC)
Figure 25. Inverting Comparator With Hysteresis
(V+= 15 VDC)
Figure 26. Squarewave Oscillator
(V+= 15 VDC)
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SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
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Typical Applications (continued)
Figure 27. Basic Comparator
(V+= 15 VDC)
Figure 28. Limit Comparator
(V+= 15 VDC)
* Or open-collector logic gate without pullup resistor
Figure 29. Comparing Input Voltages of Opposite
Polarity
(V+= 15 VDC)
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Figure 30. Output Strobing
(V+= 15 VDC)
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www.ti.com
SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
Typical Applications (continued)
250 mVDC ≤ VC ≤ +50 VDC
700 Hz ≤ fO ≤ 100 kHz
Figure 31. Crystal Controlled Oscillator
(V+= 15 VDC)
Figure 32. Two-Decade High-Frequency VCO
V+ = +30 VDC
Figure 33. Transducer Amplifier
(V+= 15 VDC)
Figure 34. Zero Crossing Detector (Single Power
Supply)
(V+= 15 VDC)
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SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
www.ti.com
Typical Applications (continued)
8.2.2.1 Split-Supply Applications
Figure 35. MOS Clock Driver
(V+ = +15 VDC and V− = −15 VDC)
Figure 36. Zero Crossing Detector
(V+ = +15 VDC and V− = −15 VDC)
Figure 37. Comparator With a Negative Reference
(V+ = +15 VDC and V− = −15 VDC)
18
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www.ti.com
SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
9 Power Supply Recommendations
Even in low-frequency applications, the LM139-N can have internal transients which are extremely quick. For this
reason, bypassing the power supply with 1.0 µF to ground will provide improved performance; the supply bypass
capacitor should be placed as close as possible to the supply pin and have a solid connection to ground. The
bypass capacitors should have a low ESR.
10 Layout
10.1 Layout Guidelines
Try to minimize parasitic impedances on the inputs to avoid oscillation. Any positive feedback used as hysteresis
should place the feedback components as close as possible to the input pins. Take care to ensure that the
output pins do not couple to the inputs. This can occur through capacitive coupling if the traces are too close and
lead to oscillations on the output.
The optimum bypass capacitor placement is closest to the V+ and ground pins. Take care to minimize the loop
area formed by the bypass capacitor connection between V+ and ground. The ground pin should be connected
to the PCB ground plane at the pin of the device. The feedback components should be placed as close to the
device as possible minimizing strays.
10.2 Layout Example
Figure 38. Layout Example
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SNOSBJ3E – NOVEMBER 1999 – REVISED DECEMBER 2014
www.ti.com
11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LM139-N
Click here
Click here
Click here
Click here
Click here
LM239-N
Click here
Click here
Click here
Click here
Click here
LM2901-N
Click here
Click here
Click here
Click here
Click here
LM3302-N
Click here
Click here
Click here
Click here
Click here
LM339-N
Click here
Click here
Click here
Click here
Click here
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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Product Folder Links: LM139-N LM239-N LM2901-N LM3302-N LM339-N
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM139AJ/PB
ACTIVE
CDIP
J
14
25
TBD
Call TI
Call TI
-55 to 125
LM139AJ
LM139J/PB
ACTIVE
CDIP
J
14
25
TBD
Call TI
Call TI
-55 to 125
LM139J
LM239J
ACTIVE
CDIP
J
14
25
TBD
Call TI
Call TI
-25 to 85
LM239J
LM2901M
ACTIVE
SOIC
D
14
55
TBD
Call TI
Call TI
-40 to 85
LM2901M
LM2901M/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM2901M
LM2901MX
NRND
SOIC
D
14
2500
TBD
Call TI
Call TI
-40 to 85
LM2901M
LM2901MX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM2901M
LM2901N/NOPB
ACTIVE
PDIP
NFF
14
25
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 85
LM2901N
LM339AM
NRND
SOIC
D
14
55
TBD
Call TI
Call TI
-25 to 85
LM339AM
LM339AM/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-25 to 85
LM339AM
LM339AMX
NRND
SOIC
D
14
2500
TBD
Call TI
Call TI
-25 to 85
LM339AM
LM339AMX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-25 to 85
LM339AM
LM339AN/NOPB
ACTIVE
PDIP
NFF
14
25
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-25 to 85
LM339AN
LM339J
ACTIVE
CDIP
J
14
25
TBD
Call TI
Call TI
-25 to 85
LM339J
LM339M
NRND
SOIC
D
14
55
TBD
Call TI
Call TI
-25 to 85
LM339M
LM339M/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-25 to 85
LM339M
LM339MX
NRND
SOIC
D
14
2500
TBD
Call TI
Call TI
-25 to 85
LM339M
LM339MX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-25 to 85
LM339M
LM339N/NOPB
ACTIVE
PDIP
NFF
14
25
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-25 to 85
LM339N
MLM339P
OBSOLETE
PDIP
NFF
14
TBD
Call TI
Call TI
Addendum-Page 1
LM339N
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jan-2016
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Oct-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM2901MX
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LM2901MX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LM339AMX
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LM339AMX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LM339MX
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LM339MX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Oct-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM2901MX
SOIC
D
14
2500
367.0
367.0
35.0
LM2901MX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LM339AMX
SOIC
D
14
2500
367.0
367.0
35.0
LM339AMX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LM339MX
SOIC
D
14
2500
367.0
367.0
35.0
LM339MX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NFF0014A
N0014A
N14A (Rev G)
www.ti.com
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