LM3673 2MHz, 350mA Step-Down DC-DC Converter General Description Features The LM3673 step-down DC-DC converter is optimized for powering low voltage circuits from a single Li-Ion cell battery and input voltage rails from 2.7V to 5.5V. It provides up to 350mA load current, over the entire input voltage range. There are several different fixed voltage output options available as well as an adjustable output voltage version ranging from 1.1V to 3.3V. The device offers superior features and performance for mobile phones and similar portable systems. The LM3673 uses intelligent automatic switching between PWM and PFM for better efficiency. During PWM mode, the device operates at a fixed-frequency of 2 MHz (typ). Hysteretic PFM mode extends the battery life by reducing the quiescent current to 16 µA (typ) during light load and standby operation. Internal synchronous rectification provides high efficiency during PWM mode operation. In shutdown mode, the device turns off and reduces battery consumption to 0.01 µA (typ). The LM3673 is available in a tiny 5-bump MicroSMD package in leaded (PB) and lead-free (NO PB) versions. A high switching frequency of 2 MHz (typ) allows the use of three tiny surface-mount components, an inductor and two ceramic capacitors. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 16 µA typical quiescent current 350 mA maximum load capability 2 MHz PWM fixed switching frequency (typ) Automatic PFM/PWM mode switching Available in fixed and adjustable output voltages 5-bump MicroSMD package Internal synchronous rectification for high efficiency Internal soft start 0.01 µA typical shutdown current Operates from a single Li-Ion cell battery Only three tiny surface-mount external components required (one inductor, two ceramic capacitors) ■ Current overload and Thermal shutdown protection Applications ■ ■ ■ ■ ■ ■ ■ Mobile phones PDAs MP3 players W-LAN Portable instruments Digital still cameras Portable Hard disk drives Typical Application Circuits 20183301 FIGURE 1. Typical Application Circuit © 2006 National Semiconductor Corporation 201833 www.national.com LM3673 2MHz, 350mA Step-Down DC-DC Converter November 2006 LM3673 20183331 FIGURE 2. Typical Application Circuit for ADJ version Connection Diagram and Package Mark Information 20183344 FIGURE 3. 5-Bump MicroSMD Package NS Package Number TLA05CBA Pin Descriptions (5-Bump MicroSMD) Pin # Name A1 VIN A3 GND C1 EN Enable pin. The device is in shutdown mode when voltage to this pin is <0.4V and enabled when >1.0V. Do not leave this pin floating. C3 FB Feedback analog input. Connect directly to the output filter capacitor for fixed voltage versions. For adjustable version external resistor dividers are required (Figure 2). The internal resistor dividers are disabled for the adjustable version. B2 SW Switching node connection to the internal PFET switch and NFET synchronous rectifier. www.national.com Description Power supply input. Connect to the input filter capacitor (Figure 1). Ground pin. 2 LM3673 Ordering Information (5-Bump MicroSMD) Voltage Option ADJ 1.2 1.5 Order Number NOPB LM3673TLX-ADJ NOPB Supplied As 250 units, Tape-and-Reel R 3000 units, Tape-and-Reel PB LM3673TLX-ADJ PB 3000 units, Tape-and-Reel LM3673TL-1.2 NOPB 250 units, Tape-and-Reel LM3673TLX-1.2 NOPB 1 250 units, Tape-and-Reell 3000 units, Tape-and-Reel LM3673TL-1.2 PB LM3673TLX-1.2 PB 3000 units, Tape-and-Reel LM3673TL-1.5 NOPB 250 units, Tape-and-Reel LM3673TLX-1.5 NOPB LM3673TLX-1.5 1.875 Package Marking LM3673TL-ADJ LM3673TL-1.5 1.8 Spec LM3673TL-ADJ H PB 250 units, Tape-and-Reel 3000 units, Tape-and-Reel 250 units, Tape-and-Reel PB 3000 units, Tape-and-Reel LM3673TL-1.8 NOPB 250 units, Tape-and-Reel LM3673TLX-1.8 NOPB F 3000 units, Tape-and-Reel LM3673TL-1.8 PB LM3673TLX-1.8 PB 3000 units, Tape-and-Reel LM3673TL-1.875 NOPB 250 units, Tape-and-Reel LM3673TLX-1.875 NOPB LM3673TL-1.875 PB LM3673TLX-1.875 PB 2 250 units, Tape-and-Reel 3000 units, Tape-and-Reel 250 units, Tape-and-Reel 3000 units, Tape-and-Reel 3 www.national.com LM3673 Human Body Model Machine Model Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN Pin: Voltage to GND FB, SW, EN Pin: Continuous Power Dissipation (Note 3) Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Lead Temperature (Soldering, 10 sec.) ESD Rating (Note 4) 2 KV 200V Operating Ratings (Notes 1, 2) −0.2V to 6.0V (GND−0.2V) to (VIN + 0.2V) Internally Limited Input Voltage Range (Note 10) 2.7V to 5.5V Recommended Load Current 0mA to 350 mA Junction Temperature (TJ) Range −30°C to +125°C Ambient Temperature (TA) Range (Note −30°C to +85°C 5) +125°C −65°C to +150°C 260°C Thermal Properties Junction-to-Ambient Thermal Resistance (θJA) (MicroSMD) for 4 layer board (Note 6) 85°C/W Electrical Characteristics (Notes 2, 8, 9) Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature range (−30°C ≤ TA ≤ +85°C). Unless otherwise noted, specifications apply to the LM3673TL with VIN = EN = 3.6V Symbol Parameter Condition Min VIN Input Voltage (Note 10) 2.7 VFB Feedback Voltage (Fixed / ADJ) TL PWM mode (Note 11) -2.5 Line Regulation Load Regulation Typ Max Units 5.5 V +2.5 % 2.7V ≤ VIN ≤ 5.5V IO = 20 mA 0.025 %/V 150 mA ≤ IO ≤ 350 mA VIN= 3.6V 0.0015 %/mA 0.5 V VREF Internal Reference Voltage ISHDN Shutdown Supply Current EN = 0V 0.01 1 µA IQ DC Bias Current into VIN No load, device is not switching (FB forced higher than programmed output voltage) 16 35 µA RDSON (P) Pin-Pin Resistance for PFET VIN= VGS= 3.6V 350 450 mΩ RDSON (N) Pin-Pin Resistance for NFET VIN= VGS= 3.6V 150 250 mΩ ILIM Switch Peak Current Limit Open Loop (Note 7) 750 855 mA VIH Logic High Input VIL Logic Low Input IEN Enable (EN) Input Current FOSC Internal Oscillator Frequency 590 V 1.0 V 0.4 PWM Mode (Note 11) 1.6 0.01 1 µA 2 2.6 MHz Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 150°C (typ.) and disengages at TJ= 130°C (typ.). Note 4: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7 Note 5: In Applications where high power dissipation and/or poor package resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX), the maximum power dissipation of the device in the application (PD-MAX) and the junction to ambient thermal resistance of the package (θJA) in the application, as given by the following equation:TA-MAX= TJ-MAX − (θJAx PD-MAX). Refer to Dissipation rating table for PD-MAX values at different ambient temperatures. Note 6: Junction to ambient thermal resistance is highly application and board layout dependent. In applications where high power dissipation exists, special care must be given to thermal dissipation issues in board design. Specified value of 85 °C/W for µSMD is based on a 4 layer, 4" x 3", 2/1/1/2 oz. Cu board as per JEDEC standards is used. Note 7: Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Electrical Characteristic table reflects open loop data (FB=0V and current drawn from SW pin ramped up until cycle by cycle current limit is activated). Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops by 10%. Note 8: Min and Max limits are guaranteed by design, test or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 9: The parameters in the electrical characteristic table are tested at VIN= 3.6V unless otherwise specified. For performance over the input voltage range refer to datasheet curves. www.national.com 4 LM3673 Note 10: The input voltage range recommended for ideal applications performance for the specified output voltages are given below: VIN = 2.7V to 4.5V for 1.1V ≤ VOUT < 1.5V VIN = 2.7V to 5.5V for 1.5V ≤ VOUT < 1.8V VIN = (VOUT+ VDROPOUT) to 5.5V for 1.8V ≤ VOUT ≤ 3.3V where VDROPOUT = ILOAD *( RDSON, PFET + RINDUCTOR) Note 11: Test condition: for VOUT less than 2.5V, VIN = 3.6V; for VOUT greater than or equal to 2.5V, VIN = VOUT + 1V. Dissipation Rating Table θJA TA≤ 25°C Power Rating TA= 60°C Power Rating TA= 85°C Power Rating 85°C/W (4 layer board) 5Bump MicroSMD 1179mW 765mW 470mW 5 www.national.com LM3673 Block Diagram 20183318 FIGURE 4. Simplified Functional Diagram www.national.com 6 LM3673 Typical Performance Characteristics LM3673TL, Circuit of Figure 1, VIN= 3.6V, VOUT= 1.5V, TA= 25°C, unless otherwise noted. Quiescent Supply Current vs. Supply Voltage Shutdown Current vs. Temp 20183305 20183304 Feedback Bias Current vs. Temp Switching Frequency vs. Temperature 20183340 20183347 RDS(ON) vs. Temperature Open/Closed Loop Current Limit vs. Temperature 20183333 20183348 7 www.national.com LM3673 Output Voltage vs. Supply Voltage (VOUT = 1.5V) Output Voltage vs. Temperature (VOUT = 1.5V) 20183329 20183306 Output Voltage vs. Output Current (VOUT = 1.5V) Efficiency vs. Output Current (VOUT = 1.2V, L = 2.2 µH, dcr = 200mΩ) 20183308 20183359 Efficiency vs. Output Current (VOUT = 1.5V, L = 2.2 µH, dcr = 200mΩ) Efficiency vs. Output Current (VOUT = 1.8V, L = 2.2 µH, dcr = 200mΩ) 20183309 20183399 www.national.com 8 Efficiency vs. Output Current (VOUT-ADJ = 3.3V, L = 2.2 µH, dcr = 200mΩ) 20183341 20183342 Line Transient Response VOUT = 1.5V (PWM Mode) Load Transient Response VOUT = 1.5V (PWM Mode) 20183319 20183312 Load Transient Response (VOUT = 1.5V) (PFM Mode 0.5mA to 50mA) Load Transient Response (VOUT = 1.5V) (PFM Mode 50mA to 0.5mA) 20183314 20183315 9 www.national.com LM3673 Efficiency vs. Output Current (VOUT-ADJ = 1.1V, L= 2.2 µH, dcr = 200mΩ) LM3673 Mode Change by Load Transients VOUT = 1.5V (PFM to PWM) Mode Change by Load Transients VOUT = 1.5V (PWM to PFM) 20183354 20183355 Start Up into PWM Mode VOUT = 1.5V (Output Current= 150mA) Start Up into PFM Mode VOUT = 1.5V (Output Current= 5mA) 20183356 20183324 www.national.com 10 DEVICE INFORMATION The LM3673, a high efficiency step down DC-DC switching buck converter, delivers a constant voltage from a single LiIon battery and input voltage ranging from 2.7V to 5.5V to portable devices such as cell phones and PDAs. Using a voltage mode architecture with synchronous rectification, the LM3673 has the ability to deliver up to 350 mA depending on the input voltage, output voltage, ambient temperature and the inductor chosen. There are three modes of operation depending on the current required - PWM (Pulse Width Modulation), PFM (Pulse Frequency Modulation), and shutdown. The device operates in PWM mode at load current of approximately 80 mA or higher. Lighter load current cause the device to automatically switch into PFM for reduced current consumption (IQ = 16 µA typ) and a longer battery life. Shutdown mode turns off the device, offering the lowest current consumption. (ISHUTDOWN = 0.01 µA typ) Additional features include soft-start, under voltage protection, current overload protection, and thermal shutdown protection. As shown in Figure 1, only three external power components are required for implementation. The part uses an internal reference voltage of 0.5V. It is recommended to keep the part in shutdown until the input voltage is 2.7V or higher. 20183323 FIGURE 5. Typical PWM Operation Internal Synchronous Rectification While in PWM mode, the LM3673 uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. CIRCUIT OPERATION During the first portion of each switching cycle, the control block in the LM3673 turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VIN–VOUT)/L, by storing energy in a magnetic field. During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of - VOUT/L. The output filter stores charge when the inductor current is high, and releases it when inductor current is low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. Current Limiting A current limit feature allows the LM3673 to protect itself and external components during overload conditions. PWM mode implements current limiting using an internal comparator that trips at 750mA (typ). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold. This allows the inductor current more time to decay, thereby preventing runaway. PFM OPERATION At very light load, the converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency. The part automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: A. The NFET current reaches zero. B. The peak PMOS switch current drops below the IMODE level, (Typically IMODE < 30mA + VIN/42 Ω ). PWM OPERATION During PWM operation the converter operates as a voltagemode controller with input voltage feed forward. This allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is introduced. While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator 11 www.national.com LM3673 can also turn off the switch in case the current limit of the PFET is exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off the NFET and turning on the PFET. Operation Description LM3673 is turned on. It remains on until the output voltage reaches the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The typical peak current in PFM mode is: IPFM = 112mA + VIN/27Ω . Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 7), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this ‘sleep’ mode is 16µA (typ), which allows the part to achieve high efficiency under extremely light load conditions. If the load current should increase during PFM mode (see Figure 7) causing the output voltage to fall below the "Low 2" PFM threshold, the part will automatically transition into fixedfrequency PWM mode. When VIN = 2.7V the part transitions from PWM to PFM mode at ~35mA output current and from PFM to PWM mode at ~85mA , when VIN= 3.6V, PWM to PFM transition happens at ~50mA and PFM to PWM transition happens at ~100mA, when VIN = 4.5V, PWM to PFM transition happens at ~65mA and PFM to PWM transition happens at ~115mA. 20183322 FIGURE 6. Typical PFM Operation During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between ~0.6% and ~1.7% above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch 20183303 FIGURE 7. Operation in PFM Mode and Transfer to PWM Mode www.national.com 12 SOFT START The LM3673 has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after Vin reaches 2.7V. Soft start is implemented by increasing switch current limit in steps of 70mA, 140mA, 280mA and 750mA (typical switch current limit). The start-up time thereby depends on the output capacitor and load current. Typical start-up times with a 10µF output capacitor and 150mA load is 280µs and with 5mA load is 240µs. • VOUT: output voltage (volts) • VFB : feedback voltage = 0.5V • R1: feedback resistor from VOUT to FB • R2: feedback resistor from FB to GND For any output voltage greater than or equal to 1.1V, a zero must be added around 45 kHz for stability. The formula for calculation of C1 is: LDO - LOW DROP OUT OPERATION The LM3673-ADJ can operate at 100% duty cycle (no switching; PMOS switch completely on) for low drop out support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25mV. The minimum input voltage needed to support the output voltage is VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT • ILOAD • RDSON, PFET • RINDUCTOR For output voltages higher than 2.5V, a pole must be placed at 45 kHz as well. If the pole and zero are at the same frequency the formula for calculation of C2 is: Load current The formula for location of zero and pole frequency created by adding C1 and C2 is given below. By adding C1, a zero as well as a higher frequency pole is introduced. Drain to source resistance of PFET switch in the triode region Inductor resistance Application Information OUTPUT VOLTAGE SELECTION FOR LM3673-ADJ The output voltage of the adjustable parts can be programmed through the resistor network connected from VOUT to FB, then to GND. VOUT is adjusted to make the voltage at FB equal to 0.5V. The resistor from FB to GND (R2) should be 200 kΩ to keep the current drawn through this network well See the "LM3673-ADJ configurations for various VOUT" table. 13 www.national.com LM3673 below the 16 µA quiescent current level (PFM mode) but large enough that it is not susceptible to noise. If R2 is 200 kΩ, and VFB is 0.5V, the current through the resistor feedback network will be 2.5 µA. The output voltage of the adjustable parts ranges from 1.1V to 3.3V. The formula for output voltage selection is: SHUTDOWN MODE Setting the EN input pin low (<0.4V) places the LM3673 in shutdown mode. During shutdown the PFET switch, NFET switch, reference, control and bias circuitry of the LM3673 are turned off. Setting EN high (>1.0V) enables normal operation. It is recommended to set EN pin low to turn off the LM3673 during system power up and undervoltage conditions when the supply is less than 2.7V. Do not leave the EN pin floating. LM3673 LM3673-ADJ Configurations For Various VOUT (Circuit of Figure 2) VOUT(V) R1(kΩ) R2 (kΩ) C1 (pF) C2 (pF) L (µH) CIN (µF) COUT(µF) 1.1 240 200 15 None 2.2 4.7 10 1.2 280 200 12 None 2.2 4.7 10 1.3 320 200 12 None 2.2 4.7 10 1.5 357 178 10 None 2.2 4.7 10 1.6 442 200 8.2 None 2.2 4.7 10 1.7 432 178 8.2 None 2.2 4.7 10 1.8 464 178 8.2 None 2.2 4.7 10 1.875 523 191 6.8 None 2.2 4.7 10 2.5 402 100 8.2 None 2.2 4.7 10 2.8 464 100 8.2 33 2.2 4.7 10 3.3 562 100 6.8 33 2.2 4.7 10 A 2.2 µH inductor with a saturation current rating of at least 855mA is recommended for most applications.The inductor’s resistance should be less than 0.3Ω for good efficiency. Table 1 lists suggested inductors and suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical applications, a toroidal or shielded-bobbin inductor should be used. A good practice is to lay out the board with overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor, in the event that noise from low-cost bobbin models is unacceptable. INDUCTOR SELECTION There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current rating specifications are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of application should be requested from the manufacturer. The minimum value of inductance to guarantee good performance is 1.76µH at ILIM (typ) dc current over the ambient temperature range. Shielded inductors radiate less noise and should be preferred. There are two methods to choose the inductor saturation current rating. INPUT CAPACITOR SELECTION A ceramic input capacitor of 4.7 µF, 6.3V is sufficient for most applications. Place the input capacitor as close as possible to the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The minimum input capacitance to guarantee good performance is 2.2µF at 3V dc bias; 1.5µF at 5V dc bias including tolerances and over ambient temperature range. The input filter capacitor supplies current to the PFET switch of the LM3673 in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple current rating. The input current ripple can be calculated as: Method 1: The saturation current should be greater than the sum of the maximum load current and the worst case average to peak inductor current. This can be written as • • • • IRIPPLE: average to peak inductor current IOUTMAX: maximum load current (350mA) VIN: maximum input voltage in application L : min inductor value including worst case tolerances (30% drop can be considered for method 1) • f : minimum switching frequency (1.6MHz) • VOUT: output voltage Method 2: A more conservative and recommended approach is to choose an inductor that has a saturation current rating greater than the maximum current limit of 855mA. www.national.com 14 Model Vendor BRL2518T2R2M (* mass production in Feb. 2007; Contact vendor for further information) Dimensions LxWxH(mm) D.C.R (max) Taiyo Yuden 2.5 x 1.8 x 1.2 135 mΩ DO3314-222MX Coilcraft 3.3 x 3.3 x 1.4 200 mΩ LPO3310-222MX Coilcraft 3.3 x 3.3 x 1.0 150 mΩ CDRH2D14-2R2 Sumida 3.2 x 3.2 x 1.55 94 mΩ Coil Chip KSLI-2520101AG2R2 * Hitachi Metals 2.5 x 2.0 x 1.0 115 mΩ LQM31PN2R2M00 Murata 3.2 x 1.6 x 0.95 220 mΩ LQM2HPN2R2MJ0 Murata 2.5 x 2.0 x 1.2 160 mΩ Voltage peak-to-peak ripple due to ESR can be expressed as follow: VPP-ESR = (2 * IRIPPLE) * RESR Because these two components are out of phase the rms (root mean squared) value can be used to get an approximate value of peak-to-peak ripple. The peak-to-peak ripple voltage, rms value can be expressed as follow: OUTPUT CAPACITOR SELECTION A ceramic output capacitor of 10 µF, 6.3V is sufficient for most applications. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be requested from them as part of the capacitor selection process. The minimum output capacitance to guarantee good performance is 5.75µF at 1.8V dc bias including tolerances and over ambient temperature range. The output filter capacitor smoothes out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions. The output voltage ripple is caused by the charging and discharging of the output capacitor and by the RESR and can be calculated as: Voltage peak-to-peak ripple due to capacitance can be expressed as follow: Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (RESR). The RESR is frequency dependent (as well as temperature dependent); make sure the value used for calculations is at the switching frequency of the part. TABLE 2. Suggested Capacitors and Their Suppliers Model Type Vendor Voltage Rating Case Size Inch (mm) 4.7 µF for CIN C2012X5R0J475K Ceramic, X5R TDK 6.3V 0805 (2012) JMK212BJ475K Ceramic, X5R Taiyo-Yuden 6.3V 0805 (2012) GRM21BR60J475K Ceramic, X5R Murata 6.3V 0805 (2012) C1608X5R0J475K Ceramic, X5R TDK 6.3V 0603 (1608) 10 µF for COUT GRM21BR60J106K Ceramic, X5R Murata 6.3V 0805 (2012) JMK212BJ106K Ceramic, X5R Taiyo-Yuden 6.3V 0805 (2012) C2012X5R0J106K Ceramic, X5R TDK 6.3V 0805 (2012) C1608X5R0J106K Ceramic, X5R TDK 6.3V 0603 (1608) 15 www.national.com LM3673 TABLE 1. Suggested Inductors and Their Suppliers LM3673 radiated noise. Special care must be given to place the input filter capacitor very close to the VIN and GND pin. 2. Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor through the LM3673 and inductor to the output filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground through the LM3673 by the inductor to the output filter capacitor and then back through ground forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise. 3. Connect the ground pins of the LM3673 and filter capacitors together using generous component-side copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several vias. This reduces ground-plane noise by preventing the switching currents from circulating through the ground plane. It also reduces ground bounce at the LM3673 by giving it a lowimpedance ground connection. 4. Use wide traces between the power components and for power connections to the DC-DC converter circuit. This reduces voltage errors caused by resistive losses across the traces. 5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power components. The voltage feedback trace must remain close to the LM3673 circuit and should be direct but should be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC converter’s own voltage feedback trace. A good approach is to route the feedback trace on another layer and to have a ground plane between the top layer and layer on which the feedback trace is routed. In the same manner for the adjustable part it is desired to have the feedback dividers on the bottom layer. 6. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks and other noisy circuitry. Interference with noisesensitive circuitry in the system can be reduced through distance. In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board, arrange the CMOS digital circuitry around it (since this also generates noise), and then place sensitive preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a metal pan and power to it is postregulated to reduce conducted noise, using low-dropout linear regulators. MicroSMD PACKAGE ASSEMBLY AND USE Use of the microSMD package requires specialized board layout, precision mounting and careful re-flow techniques, as detailed in National Semiconductor Application Note 1112. Refer to the section "Surface Mount Technology (SMD) Assembly Considerations". For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style used with microSMD package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the soldermask and pad overlap, from holding the device off the surface of the board and interfering with mounting. See Application Note 1112 for specific instructions how to do this. The 5-Bump package used for LM3673 has 300 micron solder balls and requires 10.82 mils pads for mounting on the circuit board. The trace to each pad should enter the pad with a 90° entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad should be 7 mil wide, for a section approximately 7 mil long or longer, as a thermal relief. Then each trace should neck up or down to its optimal width. The important criteria is symmetry. This ensures the solder bumps on the LM3673 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps A1 and A3, because VIN and GND are typically connected to large copper planes, inadequate thermal relief can result in late or inadequate re-flow of these bumps. The MicroSMD package is optimized for the smallest possible size in applications with red or infrared opaque cases. Because the MicroSMD package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, MicroSMD devices are sensitive to light, in the red and infrared range, shining on the package’s exposed die edges. BOARD LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DCDC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or instability. Good layout for the LM3673 can be implemented by following a few simple design rules below. Refer to Figure 9 for top layer board layout. 1. Place the LM3673, inductor and filter capacitors close together and make the traces short. The traces between these components carry relatively high switching currents and act as antennas. Following this rule reduces www.national.com 16 LM3673 20183349 FIGURE 8. Top layer board layout for Micro SMD 17 www.national.com LM3673 Physical Dimensions inches (millimeters) unless otherwise noted 5-Bump (Large) MicroSMD Package, 0.5mm Pitch NS Package Number TLA05CBA The dimensions for X1, X2, and X3 are as given: X1 = 1.057 mm +/- 0.030mm X2 = 1.387 mm +/- 0.030mm X3 = 0.600 mm +/- 0.075mm www.national.com 18 LM3673 Notes 19 www.national.com LM3673 2MHz, 350mA Step-Down DC-DC Converter Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. 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