ETC2 LM3S3748-IQR50-A0T Microcontroller Datasheet

P R E L IMI NA RY
LM3S3748 Microcontroller
D ATA SH E E T
D S -LM3 S 3 748 - 2 8 3 0
Copyr i ght © 2007- 2008 Lum i na r y M i c ro, Inc.
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2
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Table of Contents
About This Document .................................................................................................................... 23
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
23
23
23
23
1
Architectural Overview ...................................................................................................... 26
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Analog Peripherals ....................................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
2
ARM Cortex-M3 Processor Core ...................................................................................... 42
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
3
Memory Map ....................................................................................................................... 48
4
Interrupts ............................................................................................................................ 51
5
JTAG Interface .................................................................................................................... 54
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
6
System Control ................................................................................................................... 66
6.1
6.1.1
6.1.2
Functional Description ............................................................................................................... 66
Device Identification .................................................................................................................. 66
Reset Control ............................................................................................................................ 66
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26
33
34
35
35
36
37
37
39
39
40
41
43
43
44
44
44
44
44
45
55
55
56
57
58
58
61
61
61
63
3
Preliminary
Table of Contents
6.1.3
6.1.4
6.1.5
6.1.6
6.2
6.3
6.4
Non-Maskable Interrupt .............................................................................................................
Power Control ...........................................................................................................................
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
7
Hibernation Module .......................................................................................................... 137
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.4
7.5
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Register Access Timing ...........................................................................................................
Clock Source ..........................................................................................................................
Battery Management ...............................................................................................................
Real-Time Clock ......................................................................................................................
Non-Volatile Memory ...............................................................................................................
Power Control .........................................................................................................................
Interrupts and Status ...............................................................................................................
Initialization and Configuration .................................................................................................
Initialization .............................................................................................................................
RTC Match Functionality (No Hibernation) ................................................................................
RTC Match/Wake-Up from Hibernation .....................................................................................
External Wake-Up from Hibernation ..........................................................................................
RTC/External Wake-Up from Hibernation ..................................................................................
Register Reset ........................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
8
Internal Memory ............................................................................................................... 160
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.2
8.4
8.5
8.6
8.7
Block Diagram ........................................................................................................................ 160
Functional Description ............................................................................................................. 160
SRAM Memory ........................................................................................................................ 160
ROM Memory ......................................................................................................................... 161
Flash Memory ......................................................................................................................... 161
Flash Memory Initialization and Configuration ........................................................................... 162
Flash Programming ................................................................................................................. 162
Nonvolatile Register Programming ........................................................................................... 163
Register Map .......................................................................................................................... 164
ROM Register Descriptions (System Control Offset) .................................................................. 165
Flash Register Descriptions (Flash Control Offset) ..................................................................... 166
Flash Register Descriptions (System Control Offset) .................................................................. 173
9
Micro Direct Memory Access (μDMA) ............................................................................ 189
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
Block Diagram ........................................................................................................................ 190
Functional Description ............................................................................................................. 190
Channel Assigments ................................................................................................................ 191
Priority .................................................................................................................................... 191
Arbitration Size ........................................................................................................................ 191
Request Types ........................................................................................................................ 192
Channel Configuration ............................................................................................................. 192
Transfer Modes ....................................................................................................................... 194
4
69
69
69
73
74
75
76
138
138
138
139
141
142
142
142
143
143
143
144
144
144
144
144
145
146
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Preliminary
LM3S3748 Microcontroller
9.2.7
9.2.8
9.2.9
9.2.10
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.4
9.5
9.6
Transfer Size and Increment ....................................................................................................
Peripheral Interface .................................................................................................................
Software Request ....................................................................................................................
Interrupts and Errors ................................................................................................................
Initialization and Configuration .................................................................................................
Module Initialization .................................................................................................................
Configuring a Memory-to-Memory Transfer ...............................................................................
Configuring a Peripheral for Simple Transmit ............................................................................
Configuring a Peripheral for Ping-Pong Receive ........................................................................
Register Map ..........................................................................................................................
μDMA Channel Control Structure .............................................................................................
μDMA Register Descriptions ....................................................................................................
10
General-Purpose Input/Outputs (GPIOs) ....................................................................... 250
10.1
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
10.1.6
10.2
10.3
10.4
Functional Description ............................................................................................................. 250
Data Control ........................................................................................................................... 252
Interrupt Control ...................................................................................................................... 253
Mode Control .......................................................................................................................... 254
Commit Control ....................................................................................................................... 254
Pad Control ............................................................................................................................. 254
Identification ........................................................................................................................... 255
Initialization and Configuration ................................................................................................. 255
Register Map .......................................................................................................................... 256
Register Descriptions .............................................................................................................. 258
11
General-Purpose Timers ................................................................................................. 297
11.1
11.2
11.2.1
11.2.2
11.2.3
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.4
11.5
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
12
Watchdog Timer ............................................................................................................... 331
12.1
12.2
12.3
12.4
12.5
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
13
Analog-to-Digital Converter (ADC) ................................................................................. 354
13.1
13.2
Block Diagram ........................................................................................................................ 355
Functional Description ............................................................................................................. 355
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202
202
202
203
203
203
203
205
206
209
210
216
297
298
299
299
300
304
304
305
305
306
306
307
307
308
331
331
332
332
333
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Preliminary
Table of Contents
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.3
13.3.1
13.3.2
13.4
13.5
Sample Sequencers ................................................................................................................ 355
Module Control ........................................................................................................................ 356
Hardware Sample Averaging Circuit ......................................................................................... 357
Analog-to-Digital Converter ...................................................................................................... 357
Differential Sampling ............................................................................................................... 357
Internal Temperature Sensor .................................................................................................... 359
Initialization and Configuration ................................................................................................. 359
Module Initialization ................................................................................................................. 360
Sample Sequencer Configuration ............................................................................................. 360
Register Map .......................................................................................................................... 360
Register Descriptions .............................................................................................................. 361
14
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 386
14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.2.6
14.2.7
14.2.8
14.2.9
14.3
14.4
14.5
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Transmit/Receive Logic ...........................................................................................................
Baud-Rate Generation .............................................................................................................
Data Transmission ..................................................................................................................
Serial IR (SIR) .........................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
DMA Operation .......................................................................................................................
IrDA SIR block ........................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
15
Synchronous Serial Interface (SSI) ................................................................................ 429
15.1
15.2
15.2.1
15.2.2
15.2.3
15.2.4
15.2.5
15.3
15.4
15.5
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Bit Rate Generation .................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Frame Formats .......................................................................................................................
DMA Operation .......................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
16
Inter-Integrated Circuit (I2C) Interface ............................................................................ 468
16.1
16.2
16.2.1
16.2.2
16.2.3
16.2.4
16.2.5
16.3
16.4
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
I2C Bus Functional Overview ....................................................................................................
Available Speed Modes ...........................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
Command Sequence Flow Charts ............................................................................................
Initialization and Configuration .................................................................................................
I2C Register Map .....................................................................................................................
6
387
387
387
388
388
389
390
390
391
391
392
392
393
394
429
430
430
430
430
431
438
439
440
441
468
468
469
471
472
473
473
479
480
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Preliminary
LM3S3748 Microcontroller
16.5
16.6
Register Descriptions (I2C Master) ........................................................................................... 481
Register Descriptions (I2C Slave) ............................................................................................. 494
17
Univeral Serial Bus (USB) Controller ............................................................................. 503
17.1
17.2
17.2.1
17.2.2
17.3
17.3.1
17.3.2
17.4
17.5
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Operation as a Device .............................................................................................................
Operation as a Host ................................................................................................................
Initialization and Configuration .................................................................................................
Pin Configuration .....................................................................................................................
Endpoint Configuration ............................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
18
Analog Comparators ....................................................................................................... 591
18.1
18.2
18.2.1
18.3
18.4
18.5
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Internal Reference Programming ..............................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
19
Pulse Width Modulator (PWM) ........................................................................................ 603
19.1
19.2
19.2.1
19.2.2
19.2.3
19.2.4
19.2.5
19.2.6
19.2.7
19.2.8
19.3
19.4
19.5
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
PWM Timer .............................................................................................................................
PWM Comparators ..................................................................................................................
PWM Signal Generator ............................................................................................................
Dead-Band Generator .............................................................................................................
Interrupt/ADC-Trigger Selector .................................................................................................
Synchronization Methods .........................................................................................................
Fault Conditions ......................................................................................................................
Output Control Block ...............................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
20
Quadrature Encoder Interface (QEI) ............................................................................... 657
20.1
20.2
20.3
20.4
20.5
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
21
Pin Diagram ...................................................................................................................... 674
22
Signal Tables .................................................................................................................... 675
23
Operating Characteristics ............................................................................................... 690
24
Electrical Characteristics ................................................................................................ 691
503
504
504
509
513
513
513
514
517
591
592
593
594
594
595
603
604
604
604
605
606
607
607
608
609
609
610
612
657
658
660
660
661
24.1
DC Characteristics .................................................................................................................. 691
24.1.1 Maximum Ratings ................................................................................................................... 691
24.1.2 Recommended DC Operating Conditions .................................................................................. 691
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Preliminary
Table of Contents
24.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 692
24.1.4 Power Specifications ............................................................................................................... 692
24.1.5 Flash Memory Characteristics .................................................................................................. 694
24.1.6 Hibernation ............................................................................................................................. 694
24.1.7 USB ....................................................................................................................................... 694
24.2
AC Characteristics ................................................................................................................... 694
24.2.1 Load Conditions ...................................................................................................................... 694
24.2.2 Clocks .................................................................................................................................... 695
24.2.3 Analog-to-Digital Converter ...................................................................................................... 696
24.2.4 Analog Comparator ................................................................................................................. 696
24.2.5 I2C ......................................................................................................................................... 696
24.2.6 Hibernation Module ................................................................................................................. 697
24.2.7 Synchronous Serial Interface (SSI) ........................................................................................... 698
24.2.8 JTAG and Boundary Scan ........................................................................................................ 699
24.2.9 General-Purpose I/O ............................................................................................................... 701
24.2.10 Reset ..................................................................................................................................... 701
24.2.11 USB ....................................................................................................................................... 702
25
Package Information ........................................................................................................ 703
A
Boot Loader ...................................................................................................................... 705
A.1
A.2
A.2.1
A.2.2
A.2.3
A.3
A.3.1
A.3.2
A.3.3
A.4
A.4.1
A.4.2
A.4.3
A.4.4
A.4.5
A.4.6
Boot Loader ............................................................................................................................
Interfaces ...............................................................................................................................
UART .....................................................................................................................................
SSI .........................................................................................................................................
I2C .........................................................................................................................................
Packet Handling ......................................................................................................................
Packet Format ........................................................................................................................
Sending Packets .....................................................................................................................
Receiving Packets ...................................................................................................................
Commands .............................................................................................................................
COMMAND_PING (0X20) ........................................................................................................
COMMAND_GET_STATUS (0x23) ...........................................................................................
COMMAND_DOWNLOAD (0x21) .............................................................................................
COMMAND_SEND_DATA (0x24) .............................................................................................
COMMAND_RUN (0x22) .........................................................................................................
COMMAND_RESET (0x25) .....................................................................................................
B
ROM DriverLib Functions ................................................................................................ 710
B.1
DriverLib Functions Included in the Integrated ROM .................................................................. 710
C
Register Quick Reference ............................................................................................... 724
D
Ordering and Contact Information ................................................................................. 752
D.1
D.2
D.3
D.4
Ordering Information ................................................................................................................
Kits .........................................................................................................................................
Company Information ..............................................................................................................
Support Information .................................................................................................................
8
705
705
705
705
706
706
706
706
707
707
707
707
707
708
708
709
752
752
752
753
April 08, 2008
Preliminary
LM3S3748 Microcontroller
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 8-1.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 9-5.
Figure 9-6.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 11-4.
Figure 12-1.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 15-1.
Figure 15-2.
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
®
Stellaris Series High-Level Block Diagram ....................................................................... 34
CPU Block Diagram ......................................................................................................... 43
TPIU Block Diagram ........................................................................................................ 44
JTAG Module Block Diagram ............................................................................................ 55
Test Access Port State Machine ....................................................................................... 58
IDCODE Register Format ................................................................................................. 63
BYPASS Register Format ................................................................................................ 64
Boundary Scan Register Format ....................................................................................... 64
External Circuitry to Extend Reset .................................................................................... 67
Main Clock Tree .............................................................................................................. 71
Hibernation Module Block Diagram ................................................................................. 138
Clock Source Using Crystal ............................................................................................ 140
Clock Source Using Dedicated Oscillator ......................................................................... 141
Flash Block Diagram ...................................................................................................... 160
μDMA Block Diagram ..................................................................................................... 190
Example of Ping-Pong DMA Transaction ......................................................................... 195
Memory Scatter-Gather, Setup and Configuration ............................................................ 197
Memory Scatter-Gather, μDMA Copy Sequence .............................................................. 198
Peripheral Scatter-Gather, Setup and Configuration ......................................................... 200
Peripheral Scatter-Gather, μDMA Copy Sequence ........................................................... 201
Digital I/O Pads ............................................................................................................. 251
Analog/Digital I/O Pads .................................................................................................. 252
GPIODATA Write Example ............................................................................................. 253
GPIODATA Read Example ............................................................................................. 253
GPTM Module Block Diagram ........................................................................................ 298
16-Bit Input Edge Count Mode Example .......................................................................... 302
16-Bit Input Edge Time Mode Example ........................................................................... 303
16-Bit PWM Mode Example ............................................................................................ 304
WDT Module Block Diagram .......................................................................................... 331
ADC Module Block Diagram ........................................................................................... 355
Differential Sampling Range, VIN_ODD = 1.5 V .................................................................. 358
Differential Sampling Range, VIN_ODD = 0.75 V ................................................................ 358
Differential Sampling Range, VIN_ODD = 2.25 V ................................................................ 359
Internal Temperature Sensor Characteristic ..................................................................... 359
UART Module Block Diagram ......................................................................................... 387
UART Character Frame ................................................................................................. 388
IrDA Data Modulation ..................................................................................................... 390
SSI Module Block Diagram ............................................................................................. 429
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 432
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 432
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 433
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 433
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 434
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 435
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 435
April 08, 2008
9
Preliminary
Table of Contents
Figure 15-9.
Figure 15-10.
Figure 15-11.
Figure 15-12.
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 16-4.
Figure 16-5.
Figure 16-6.
Figure 16-7.
Figure 16-8.
Figure 16-9.
Figure 16-10.
Figure 16-11.
Figure 16-12.
Figure 16-13.
Figure 17-1.
Figure 18-1.
Figure 18-2.
Figure 18-3.
Figure 19-1.
Figure 19-2.
Figure 19-3.
Figure 19-4.
Figure 19-5.
Figure 19-6.
Figure 20-1.
Figure 20-2.
Figure 21-1.
Figure 24-1.
Figure 24-2.
Figure 24-3.
Figure 24-4.
Figure 24-5.
Figure 24-6.
Figure 24-7.
Figure 24-8.
Figure 24-9.
Figure 24-10.
Figure 24-11.
Figure 24-12.
Figure 24-13.
Figure 25-1.
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 436
MICROWIRE Frame Format (Single Frame) .................................................................... 437
MICROWIRE Frame Format (Continuous Transfer) ......................................................... 438
MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 438
I2C Block Diagram ......................................................................................................... 468
I2C Bus Configuration .................................................................................................... 469
START and STOP Conditions ......................................................................................... 469
Complete Data Transfer with a 7-Bit Address ................................................................... 470
R/S Bit in First Byte ........................................................................................................ 470
Data Validity During Bit Transfer on the I2C Bus ............................................................... 470
Master Single SEND ...................................................................................................... 473
Master Single RECEIVE ................................................................................................. 474
Master Burst SEND ....................................................................................................... 475
Master Burst RECEIVE .................................................................................................. 476
Master Burst RECEIVE after Burst SEND ........................................................................ 477
Master Burst SEND after Burst RECEIVE ........................................................................ 478
Slave Command Sequence ............................................................................................ 479
USB Module Block Diagram ........................................................................................... 503
Analog Comparator Module Block Diagram ..................................................................... 591
Structure of Comparator Unit .......................................................................................... 592
Comparator Internal Reference Structure ........................................................................ 593
PWM Unit Diagram ........................................................................................................ 603
PWM Module Block Diagram .......................................................................................... 604
PWM Count-Down Mode ................................................................................................ 605
PWM Count-Up/Down Mode .......................................................................................... 605
PWM Generation Example In Count-Up/Down Mode ....................................................... 606
PWM Dead-Band Generator ........................................................................................... 606
QEI Block Diagram ........................................................................................................ 657
Quadrature Encoder and Velocity Predivider Operation .................................................... 659
100-Pin LQFP Package Pin Diagram .............................................................................. 674
Load Conditions ............................................................................................................ 694
I2C Timing ..................................................................................................................... 697
Hibernation Module Timing ............................................................................................. 698
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 698
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 699
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 699
JTAG Test Clock Input Timing ......................................................................................... 700
JTAG Test Access Port (TAP) Timing .............................................................................. 700
External Reset Timing (RST) .......................................................................................... 701
Power-On Reset Timing ................................................................................................. 702
Brown-Out Reset Timing ................................................................................................ 702
Software Reset Timing ................................................................................................... 702
Watchdog Reset Timing ................................................................................................. 702
100-Pin LQFP Package .................................................................................................. 703
10
April 08, 2008
Preliminary
LM3S3748 Microcontroller
List of Tables
Table 1.
Table 3-1.
Table 4-1.
Table 4-2.
Table 5-1.
Table 5-2.
Table 6-1.
Table 7-1.
Table 8-1.
Table 8-2.
Table 8-3.
Table 9-1.
Table 9-2.
Table 9-3.
Table 9-4.
Table 9-5.
Table 9-6.
Table 9-7.
Table 9-8.
Table 9-9.
Table 9-10.
Table 9-11.
Table 9-12.
Table 9-13.
Table 10-1.
Table 10-2.
Table 10-3.
Table 11-1.
Table 11-2.
Table 11-3.
Table 12-1.
Table 13-1.
Table 13-2.
Table 13-3.
Table 14-1.
Table 15-1.
Table 16-1.
Table 16-2.
Table 16-3.
Table 17-1.
Table 18-1.
Table 18-2.
Table 18-3.
Table 18-4.
Table 19-1.
Table 20-1.
Documentation Conventions ............................................................................................ 23
Memory Map ................................................................................................................... 48
Exception Types .............................................................................................................. 51
Interrupts ........................................................................................................................ 52
JTAG Port Pins Reset State ............................................................................................. 56
JTAG Instruction Register Commands ............................................................................... 61
System Control Register Map ........................................................................................... 75
Hibernation Module Register Map ................................................................................... 145
Flash Protection Policy Combinations ............................................................................. 162
Flash Resident Registers ............................................................................................... 163
Flash Register Map ........................................................................................................ 164
DMA Channel Assignments ............................................................................................ 191
Request Type Support ................................................................................................... 192
Control Structure Memory Map ....................................................................................... 193
Channel Control Structure .............................................................................................. 193
μDMA Read Example: 8-Bit Peripheral ............................................................................ 202
μDMA Interrupt Assignments .......................................................................................... 203
Channel Control Structure Offsets for Channel 30 ............................................................ 204
Channel Control Word Configuration for Memory Transfer Example .................................. 204
Channel Control Structure Offsets for Channel 7 .............................................................. 205
Channel Control Word Configuration for Peripheral Transmit Example .............................. 206
Primary and Alternate Channel Control Structure Offsets for Channel 8 ............................. 207
Channel Control Word Configuration for Peripheral Ping-Pong Receive Example ............... 208
μDMA Register Map ...................................................................................................... 209
GPIO Pad Configuration Examples ................................................................................. 255
GPIO Interrupt Configuration Example ............................................................................ 256
GPIO Register Map ....................................................................................................... 257
Available CCP Pins ........................................................................................................ 298
16-Bit Timer With Prescaler Configurations ..................................................................... 301
Timers Register Map ...................................................................................................... 307
Watchdog Timer Register Map ........................................................................................ 332
Samples and FIFO Depth of Sequencers ........................................................................ 355
Differential Sampling Pairs ............................................................................................. 357
ADC Register Map ......................................................................................................... 360
UART Register Map ....................................................................................................... 393
SSI Register Map .......................................................................................................... 440
Examples of I2C Master Timer Period versus Speed Mode ............................................... 471
Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 480
Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 485
Univeral Serial Bus (USB) Controller Register Map .......................................................... 514
Comparator 0 Operating Modes ...................................................................................... 592
Comparator 1 Operating Modes ..................................................................................... 593
Internal Reference Voltage and ACREFCTL Field Values ................................................. 593
Analog Comparators Register Map ................................................................................. 595
PWM Register Map ........................................................................................................ 610
QEI Register Map .......................................................................................................... 660
April 08, 2008
11
Preliminary
Table of Contents
Table 22-1.
Table 22-2.
Table 22-3.
Table 22-4.
Table 23-1.
Table 23-2.
Table 24-1.
Table 24-2.
Table 24-3.
Table 24-4.
Table 24-5.
Table 24-6.
Table 24-7.
Table 24-8.
Table 24-9.
Table 24-10.
Table 24-11.
Table 24-12.
Table 24-13.
Table 24-14.
Table 24-15.
Table 24-16.
Table 24-17.
Table 24-18.
Table 24-19.
Table D-1.
Signals by Pin Number ................................................................................................... 675
Signals by Signal Name ................................................................................................. 679
Signals by Function, Except for GPIO ............................................................................. 684
GPIO Pins and Alternate Functions ................................................................................. 687
Temperature Characteristics ........................................................................................... 690
Thermal Characteristics ................................................................................................. 690
Maximum Ratings .......................................................................................................... 691
Recommended DC Operating Conditions ........................................................................ 691
LDO Regulator Characteristics ....................................................................................... 692
Detailed Power Specifications ........................................................................................ 693
Flash Memory Characteristics ........................................................................................ 694
Hibernation Module DC Electricals .................................................................................. 694
USB Controller DC Electricals ........................................................................................ 694
Phase Locked Loop (PLL) Characteristics ....................................................................... 695
Clock Characteristics ..................................................................................................... 695
Crystal Characteristics ................................................................................................... 695
ADC Characteristics ....................................................................................................... 696
Analog Comparator Characteristics ................................................................................. 696
Analog Comparator Voltage Reference Characteristics .................................................... 696
I2C Characteristics ......................................................................................................... 696
Hibernation Module Characteristics ................................................................................. 697
SSI Characteristics ........................................................................................................ 698
JTAG Characteristics ..................................................................................................... 699
GPIO Characteristics ..................................................................................................... 701
Reset Characteristics ..................................................................................................... 701
Part Ordering Information ............................................................................................... 752
12
April 08, 2008
Preliminary
LM3S3748 Microcontroller
List of Registers
System Control .............................................................................................................................. 66
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Device Identification 0 (DID0), offset 0x000 ....................................................................... 77
Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 79
LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 80
Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 81
Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 82
Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 83
Reset Cause (RESC), offset 0x05C .................................................................................. 84
Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 85
XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 90
GPIO High Speed Control (GPIOHSCTL), offset 0x06C ..................................................... 91
Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 93
Main Oscillator Control (MOSCCTL), offset 0x07C ............................................................. 95
Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 96
Device Identification 1 (DID1), offset 0x004 ....................................................................... 97
Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 99
Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 100
Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 102
Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 104
Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 106
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 107
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 109
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 110
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 112
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 114
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 116
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 118
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 121
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 124
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 127
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 129
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 131
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 133
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 134
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 136
Hibernation Module ..................................................................................................................... 137
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Hibernation RTC Counter (HIBRTCC), offset 0x000 .........................................................
Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 .......................................................
Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 .......................................................
Hibernation RTC Load (HIBRTCLD), offset 0x00C ...........................................................
Hibernation Control (HIBCTL), offset 0x010 .....................................................................
Hibernation Interrupt Mask (HIBIM), offset 0x014 .............................................................
Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 ..................................................
Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................
Hibernation Interrupt Clear (HIBIC), offset 0x020 .............................................................
April 08, 2008
147
148
149
150
151
154
155
156
157
13
Preliminary
Table of Contents
Register 10:
Register 11:
Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 158
Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 159
Internal Memory ........................................................................................................................... 160
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
ROM Control (RMCTL), offset 0x0F0 ..............................................................................
Flash Memory Address (FMA), offset 0x000 ....................................................................
Flash Memory Data (FMD), offset 0x004 .........................................................................
Flash Memory Control (FMC), offset 0x008 .....................................................................
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 .....................
USec Reload (USECRL), offset 0x140 ............................................................................
ROM Version Register (RMVER), offset 0x0F4 ................................................................
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ...................
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ...............
User Debug (USER_DBG), offset 0x1D0 .........................................................................
User Register 0 (USER_REG0), offset 0x1E0 ..................................................................
User Register 1 (USER_REG1), offset 0x1E4 ..................................................................
User Register 2 (USER_REG2), offset 0x1E8 ..................................................................
User Register 3 (USER_REG3), offset 0x1EC .................................................................
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 ....................................
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 ....................................
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ...................................
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ...............................
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ...............................
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ...............................
166
167
168
169
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
Micro Direct Memory Access (μDMA) ........................................................................................ 189
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ......................
DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................
DMA Channel Control Word (DMACHCTL), offset 0x008 ..................................................
DMA Status (DMASTAT), offset 0x000 ............................................................................
DMA Configuration (DMACFG), offset 0x004 ...................................................................
DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 ..................................
DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C ....................
DMA Channel Wait on Request Status (DMAWAITSTAT), offset 0x010 .............................
DMA Channel Software Request (DMASWREQ), offset 0x014 .........................................
DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 ....................................
DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C .................................
DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 ..............................
DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ...........................
DMA Channel Enable Set (DMAENASET), offset 0x028 ...................................................
DMA Channel Enable Clear (DMAENACLR), offset 0x02C ...............................................
DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 ....................................
DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 .................................
DMA Channel Priority Set (DMAPRIOSET), offset 0x038 .................................................
DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C ..............................................
DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................
DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 .........................................
DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 .........................................
14
211
212
213
217
219
220
221
222
223
224
226
227
229
230
232
233
235
236
238
239
241
242
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 .........................................
DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................
DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 .........................................
DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ...........................................
DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ...........................................
DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ...........................................
DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ...........................................
243
244
245
246
247
248
249
General-Purpose Input/Outputs (GPIOs) ................................................................................... 250
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
GPIO Data (GPIODATA), offset 0x000 ............................................................................ 259
GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 260
GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 261
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 262
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 263
GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 264
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 265
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 266
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 268
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 269
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 271
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 272
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 273
GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 274
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 275
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 276
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 277
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 278
GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 280
GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 281
GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 283
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 285
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 286
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 287
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 288
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 289
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 290
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 291
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 292
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 293
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 294
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 295
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 296
General-Purpose Timers ............................................................................................................. 297
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
GPTM Configuration (GPTMCFG), offset 0x000 ..............................................................
GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................
GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................
GPTM Control (GPTMCTL), offset 0x00C ........................................................................
GPTM Interrupt Mask (GPTMIMR), offset 0x018 ..............................................................
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C .....................................................
April 08, 2008
309
310
312
314
317
319
15
Preliminary
Table of Contents
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................
GPTM Interrupt Clear (GPTMICR), offset 0x024 ..............................................................
GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 .................................................
GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ...................................................
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 ..................................................
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C .......................................................
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................
GPTM TimerB (GPTMTBR), offset 0x04C .......................................................................
320
321
323
324
325
326
327
328
329
330
Watchdog Timer ........................................................................................................................... 331
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Load (WDTLOAD), offset 0x000 ......................................................................
Watchdog Value (WDTVALUE), offset 0x004 ...................................................................
Watchdog Control (WDTCTL), offset 0x008 .....................................................................
Watchdog Interrupt Clear (WDTICR), offset 0x00C ..........................................................
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ..................................................
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 .............................................
Watchdog Test (WDTTEST), offset 0x418 .......................................................................
Watchdog Lock (WDTLOCK), offset 0xC00 .....................................................................
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 .................................
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 .................................
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 .................................
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 .................................
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 .................................
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 .................................
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 ....................................
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 ....................................
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 ....................................
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ..................................
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
Analog-to-Digital Converter (ADC) ............................................................................................. 354
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 362
ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 363
ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 364
ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 365
ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 366
ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 367
ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 370
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 371
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 372
ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 373
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 374
ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 376
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 379
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 379
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 379
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 379
16
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C .............................
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C .............................
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ...............
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ...............
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ...............
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................
380
380
380
380
381
381
382
382
384
385
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 386
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
UART Data (UARTDR), offset 0x000 ...............................................................................
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ...........................
UART Flag (UARTFR), offset 0x018 ................................................................................
UART IrDA Low-Power Register (UARTILPR), offset 0x020 .............................................
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 .......................................
UART Line Control (UARTLCRH), offset 0x02C ...............................................................
UART Control (UARTCTL), offset 0x030 .........................................................................
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ...........................................
UART Interrupt Mask (UARTIM), offset 0x038 .................................................................
UART Raw Interrupt Status (UARTRIS), offset 0x03C ......................................................
UART Masked Interrupt Status (UARTMIS), offset 0x040 .................................................
UART Interrupt Clear (UARTICR), offset 0x044 ...............................................................
UART DMA Control (UARTDMACTL), offset 0x048 ..........................................................
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 .....................................
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 .....................................
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 .....................................
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC .....................................
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ......................................
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ......................................
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ......................................
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC .....................................
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................
395
397
399
401
402
403
404
406
408
410
412
413
414
416
417
418
419
420
421
422
423
424
425
426
427
428
Synchronous Serial Interface (SSI) ............................................................................................ 429
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
SSI Control 0 (SSICR0), offset 0x000 ..............................................................................
SSI Control 1 (SSICR1), offset 0x004 ..............................................................................
SSI Data (SSIDR), offset 0x008 ......................................................................................
SSI Status (SSISR), offset 0x00C ...................................................................................
SSI Clock Prescale (SSICPSR), offset 0x010 ..................................................................
SSI Interrupt Mask (SSIIM), offset 0x014 .........................................................................
SSI Raw Interrupt Status (SSIRIS), offset 0x018 ..............................................................
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................
SSI Interrupt Clear (SSIICR), offset 0x020 .......................................................................
SSI DMA Control (SSIDMACTL), offset 0x024 .................................................................
April 08, 2008
442
444
446
447
449
450
452
453
454
455
17
Preliminary
Table of Contents
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 .............................................
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 .............................................
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 .............................................
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 .............................................
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 .............................................
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 .............................................
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ...............................................
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ...............................................
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ...............................................
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ...............................................
456
457
458
459
460
461
462
463
464
465
466
467
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 468
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
I2C Master Slave Address (I2CMSA), offset 0x000 ...........................................................
I2C Master Control/Status (I2CMCS), offset 0x004 ...........................................................
I2C Master Data (I2CMDR), offset 0x008 .........................................................................
I2C Master Timer Period (I2CMTPR), offset 0x00C ...........................................................
I2C Master Interrupt Mask (I2CMIMR), offset 0x010 .........................................................
I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 .................................................
I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ...........................................
I2C Master Interrupt Clear (I2CMICR), offset 0x01C .........................................................
I2C Master Configuration (I2CMCR), offset 0x020 ............................................................
I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................
I2C Slave Control/Status (I2CSCSR), offset 0x004 ...........................................................
I2C Slave Data (I2CSDR), offset 0x008 ...........................................................................
I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ...........................................................
I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ...................................................
I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 ..............................................
I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................
482
483
487
488
489
490
491
492
493
495
496
498
499
500
501
502
Univeral Serial Bus (USB) Controller ......................................................................................... 503
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
USB Device Functional Address (USBFADDR), offset 0x000 ............................................
USB Power (USBPOWER), offset 0x001 .........................................................................
USB Transmit Interrupt Status (USBTXIS), offset 0x002 ...................................................
USB Receive Interrupt Status (USBRXIS), offset 0x004 ...................................................
USB Transmit Interrupt Enable (USBTXIE), offset 0x006 ..................................................
USB Receive Interrupt Enable (USBRXIE), offset 0x008 ..................................................
USB General Interrupt Status (USBIS), offset 0x00A ........................................................
USB Interrupt Enable (USBIE), offset 0x00B ....................................................................
USB Frame Value (USBFRAME), offset 0x00C ................................................................
USB Endpoint Index (USBEPIDX), offset 0x0E ................................................................
USB Test Mode (USBTEST), offset 0x00F .......................................................................
USB FIFO Endpoint 0 (USBFIFO0), offset 0x020 .............................................................
USB FIFO Endpoint 1 (USBFIFO1), offset 0x024 .............................................................
USB FIFO Endpoint 2 (USBFIFO2), offset 0x028 .............................................................
USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C ............................................................
USB Device Control (USBDEVCTL), offset 0x060 ............................................................
USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062 .................................
18
518
519
521
522
523
524
525
527
529
530
531
533
533
533
533
534
536
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
Register 65:
USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063 .................................. 536
USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064 ................................. 537
USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066 .................................. 537
USB Connect Timing (USBCONTIM), offset 0x07A .......................................................... 538
USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF), offset 0x07D ...... 539
USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF), offset 0x07E ...... 540
USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0), offset 0x080 ........... 541
USB Transmit Functional Address Endpoint 1 (USBTXFUNCADDR1), offset 0x088 ........... 541
USB Transmit Functional Address Endpoint 2 (USBTXFUNCADDR2), offset 0x090 ........... 541
USB Transmit Functional Address Endpoint 3 (USBTXFUNCADDR3), offset 0x098 ........... 541
USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0), offset 0x082 ...................... 542
USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1), offset 0x08A ...................... 542
USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2), offset 0x092 ...................... 542
USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3), offset 0x09A ...................... 542
USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset 0x083 ............................. 543
USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset 0x08B ............................ 543
USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset 0x093 ............................. 543
USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset 0x09B ............................ 543
USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1), offset 0x08C ........... 544
USB Receive Functional Address Endpoint 2 (USBRXFUNCADDR2), offset 0x094 ........... 544
USB Receive Functional Address Endpoint 3 (USBRXFUNCADDR3), offset 0x09C ........... 544
USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1), offset 0x08E ...................... 545
USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2), offset 0x096 ....................... 545
USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3), offset 0x09E ...................... 545
USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset 0x08F ............................. 546
USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset 0x097 ............................. 546
USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset 0x09F ............................. 546
USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset 0x110 .......................... 547
USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset 0x120 .......................... 547
USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset 0x130 .......................... 547
USB Control and Status Endpoint 0 Low (USBCSRL0), offset 0x102 ................................. 548
USB Control and Status Endpoint 0 High (USBCSRH0), offset 0x103 ............................... 551
USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108 ................................... 553
USB Type Endpoint 0 (USBTYPE0), offset 0x10A ............................................................ 554
USB NAK Limit (USBNAKLMT), offset 0x10B .................................................................. 555
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1), offset 0x112 ............... 556
USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2), offset 0x122 ............... 556
USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3), offset 0x132 ............... 556
USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1), offset 0x113 .............. 559
USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2), offset 0x123 ............. 559
USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3), offset 0x133 ............. 559
USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset 0x114 ........................... 562
USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset 0x124 ........................... 562
USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset 0x134 ........................... 562
USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1), offset 0x116 ............... 563
USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2), offset 0x126 ............... 563
USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3), offset 0x136 ............... 563
USB Receive Control and Status Endpoint 1 High (USBRXCSRH1), offset 0x117 .............. 566
April 08, 2008
19
Preliminary
Table of Contents
Register 66:
Register 67:
Register 68:
Register 69:
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
Register 87:
Register 88:
Register 89:
Register 90:
Register 91:
Register 92:
Register 93:
Register 94:
Register 95:
USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127 .............. 566
USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137 .............. 566
USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 .............................. 571
USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 .............................. 571
USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 .............................. 571
USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1), offset 0x11A ................... 572
USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2), offset 0x12A ................... 572
USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3), offset 0x13A ................... 572
USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1), offset 0x11B ....................... 574
USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2), offset 0x12B ....................... 574
USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3), offset 0x13B ....................... 574
USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C ................... 575
USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C ................... 575
USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3), offset 0x13C ................... 575
USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D ............. 577
USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D ............ 577
USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D ............ 577
USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset
0x304 ........................................................................................................................... 578
USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset
0x308 ........................................................................................................................... 578
USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset
0x30C ........................................................................................................................... 578
USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 ............. 579
USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 ............ 580
USB External Power Control (USBEPC), offset 0x400 ...................................................... 581
USB External Power Control Raw Interrupt Status (USBEPCRIS), offset 0x404 ................. 584
USB External Power Control Interrupt Mask (USBEPCIM), offset 0x408 ............................ 585
USB External Power Control Interrupt Status and Clear (USBEPCISC), offset 0x40C ......... 586
USB Device Resume Raw Interrupt Status (USBDRRIS), offset 0x410 .............................. 587
USB Device Resume Interrupt Mask (USBDRIM), offset 0x414 ......................................... 588
USB Device Resume Interrupt Status and Clear (USBDRISC), offset 0x418 ...................... 589
USB General-Purpose Control and Status (USBGPCS), offset 0x41C ............................... 590
Analog Comparators ................................................................................................................... 591
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 ....................................
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 .........................................
Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ...........................................
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 .........................
Analog Comparator Status 0 (ACSTAT0), offset 0x20 .......................................................
Analog Comparator Status 1 (ACSTAT1), offset 0x40 .......................................................
Analog Comparator Control 0 (ACCTL0), offset 0x24 .......................................................
Analog Comparator Control 1 (ACCTL1), offset 0x44 .......................................................
596
597
598
599
600
600
601
601
Pulse Width Modulator (PWM) .................................................................................................... 603
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
PWM Master Control (PWMCTL), offset 0x000 ................................................................
PWM Time Base Sync (PWMSYNC), offset 0x004 ...........................................................
PWM Output Enable (PWMENABLE), offset 0x008 ..........................................................
PWM Output Inversion (PWMINVERT), offset 0x00C .......................................................
PWM Output Fault (PWMFAULT), offset 0x010 ................................................................
20
613
614
615
617
618
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 620
PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 622
PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 624
PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 626
PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 ............................................ 627
PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 629
PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 629
PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 629
PWM3 Control (PWM3CTL), offset 0x100 ....................................................................... 629
PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 634
PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 634
PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 634
PWM3 Interrupt and Trigger Enable (PWM3INTEN), offset 0x104 ..................................... 634
PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 636
PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 636
PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 636
PWM3 Raw Interrupt Status (PWM3RIS), offset 0x108 ..................................................... 636
PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 637
PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 637
PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 637
PWM3 Interrupt Status and Clear (PWM3ISC), offset 0x10C ............................................ 637
PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 638
PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 638
PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 638
PWM3 Load (PWM3LOAD), offset 0x110 ........................................................................ 638
PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 639
PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 639
PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 639
PWM3 Counter (PWM3COUNT), offset 0x114 ................................................................. 639
PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 640
PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 640
PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 640
PWM3 Compare A (PWM3CMPA), offset 0x118 ............................................................... 640
PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 641
PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 641
PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 641
PWM3 Compare B (PWM3CMPB), offset 0x11C .............................................................. 641
PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 642
PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 642
PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 642
PWM3 Generator A Control (PWM3GENA), offset 0x120 ................................................. 642
PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 645
PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 645
PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 645
PWM3 Generator B Control (PWM3GENB), offset 0x124 ................................................. 645
PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 648
PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 648
PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 648
April 08, 2008
21
Preliminary
Table of Contents
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
Register 65:
Register 66:
Register 67:
Register 68:
Register 69:
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
PWM3 Dead-Band Control (PWM3DBCTL), offset 0x128 .................................................
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C .............................
PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC .............................
PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC .............................
PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset 0x12C ..............................
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 .............................
PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 .............................
PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 .............................
PWM3 Dead-Band Falling-Edge-Delay (PWM3DBFALL), offset 0x130 ..............................
PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074 ....................................................
PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4 ....................................................
PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4 ....................................................
PWM3 Fault Source 0 (PWM3FLTSRC0), offset 0x134 ....................................................
PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C .....................................
PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC .....................................
PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC .....................................
PWM3 Minimum Fault Period (PWM3MINFLTPER), offset 0x13C .....................................
PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800 ............................................
PWM1 Fault Pin Logic Sense (PWM1FLTSEN), offset 0x880 ............................................
PWM2 Fault Pin Logic Sense (PWM2FLTSEN), offset 0x900 ............................................
PWM3 Fault Pin Logic Sense (PWM3FLTSEN), offset 0x980 ............................................
PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804 ....................................................
PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884 ....................................................
PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904 ....................................................
PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984 ....................................................
648
649
649
649
649
650
650
650
650
651
651
651
651
653
653
653
653
654
654
654
654
655
655
655
655
Quadrature Encoder Interface (QEI) .......................................................................................... 657
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
QEI Control (QEICTL), offset 0x000 ................................................................................
QEI Status (QEISTAT), offset 0x004 ................................................................................
QEI Position (QEIPOS), offset 0x008 ..............................................................................
QEI Maximum Position (QEIMAXPOS), offset 0x00C .......................................................
QEI Timer Load (QEILOAD), offset 0x010 .......................................................................
QEI Timer (QEITIME), offset 0x014 .................................................................................
QEI Velocity Counter (QEICOUNT), offset 0x018 .............................................................
QEI Velocity (QEISPEED), offset 0x01C ..........................................................................
QEI Interrupt Enable (QEIINTEN), offset 0x020 ...............................................................
QEI Raw Interrupt Status (QEIRIS), offset 0x024 .............................................................
QEI Interrupt Status and Clear (QEIISC), offset 0x028 .....................................................
22
662
664
665
666
667
668
669
670
671
672
673
April 08, 2008
Preliminary
LM3S3748 Microcontroller
About This Document
This data sheet provides reference information for the LM3S3748 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■ ARM® Cortex™-M3 Technical Reference Manual
■ ARM® CoreSight Technical Reference Manual
■ ARM® v7-M Architecture Application Level Reference Manual
®
■ Stellaris Peripheral Driver Library User's Guide
®
■ Stellaris ROM User’s Guide
The following related documents are also referenced:
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 23.
Table 1. Documentation Conventions
Notation
Meaning
General Register Notation
REGISTER
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
bit
A single bit in a register.
bit field
Two or more consecutive and related bits.
offset 0xnnn
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 48.
April 08, 2008
23
Preliminary
About This Document
Notation
Meaning
Register N
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
reserved
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
yy:xx
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
Register Bit/Field
Types
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
RC
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO
Software can read this field. Always write the chip reset value.
R/W
Software can read or write this field.
R/W1C
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1S
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
W1C
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
WO
Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field
Reset Value
This value in the register bit diagram shows the bit/field value after any reset, unless noted.
0
Bit cleared to 0 on chip reset.
1
Bit set to 1 on chip reset.
-
Nondeterministic.
Pin/Signal Notation
[]
Pin alternate function; a pin defaults to the signal without the brackets.
pin
Refers to the physical connection on the package.
signal
Refers to the electrical signal encoding of a pin.
assert a signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
deassert a signal
Change the value of the signal from the logically True state to the logically False state.
SIGNAL
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
Numbers
X
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
24
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Notation
Meaning
0x
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
April 08, 2008
25
Preliminary
Architectural Overview
1
Architectural Overview
®
The Luminary Micro Stellaris family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
®
The Stellaris family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
®
capabilities. The Stellaris LM3S3000 series provides the industry's first ARM® Cortex™-M3
microcontrollers with USB 2.0 Full-Speed On-The-Go/Host/Device combinations.
The LM3S3748 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S3748 microcontroller features
a Battery-backed Hibernation module to efficiently power down the LM3S3748 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S3748 microcontroller perfectly for
battery applications.
In addition, the LM3S3748 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S3748 microcontroller is code-compatible
®
to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network. See “Ordering and Contact Information” on page 752 for
®
ordering information for Stellaris family devices.
1.1
Product Features
The LM3S3748 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
26
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LM3S3748 Microcontroller
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 37 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 128 KB single-cycle flash
•
User-managed flash block protection on a 2-KB block basis
•
User-managed flash data programming
•
User-defined and managed flash-protection block
– 64 KB single-cycle SRAM
®
– Pre-programmed ROM containing the Stellaris family peripheral driver library (DriverLib)
®
and Stellaris boot loader
■ DMA Controller
– ARM PrimeCell® 32-channel configurable µDMA controller
– Support for multiple transfer modes:
•
Basic, for simple transfer scenarios
•
Ping-pong, for continuous data flow to/from peripherals
•
Scatter-gather, from a programmable list of arbitrary transfers initiated from a single request
– Dedicated channels for supported peripherals
– One channel each for receive and transmit path for bidirectional peripherals
– Dedicated channel for software-initiated transfers
– Independently configured and operated channels
– Per-channel configurable bus arbitration scheme
– Two levels of priority
– Design optimizations for improved bus access performance between µDMA controller and
the processor core:
•
µDMA controller access is subordinate to core access
April 08, 2008
27
Preliminary
Architectural Overview
•
RAM striping
•
Peripheral bus segmentation
– Data sizes of 8, 16, and 32 bits
– Source and destination address increment size of byte, half-word, word, or no increment
– Maskable device requests
– Optional software initiated requests for any channel
– Interrupt on transfer completion, with a separate interrupt per channel
■ General-Purpose Timers
– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
•
As a single 32-bit timer
•
As one 32-bit Real-Time Clock (RTC) to event capture
•
For Pulse Width Modulation (PWM)
•
To trigger analog-to-digital conversions
– 32-bit Timer modes
•
Programmable one-shot timer
•
Programmable periodic timer
•
Real-Time Clock when using an external 32.768-KHz clock as the input
•
User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
•
ADC event trigger
– 16-bit Timer modes
•
General-purpose timer function with an 8-bit prescaler
•
Programmable one-shot timer
•
Programmable periodic timer
•
User-enabled stalling when the controller asserts CPU Halt flag during debug
•
ADC event trigger
– 16-bit Input Capture modes
•
Input edge count capture
•
Input edge time capture
28
April 08, 2008
Preliminary
LM3S3748 Microcontroller
– 16-bit PWM mode
•
Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ Synchronous Serial Interface (SSI)
– Two SSI modules, each with the following features:
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
– Direct memory access (DMA)
■ UART
– Two fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator allowing speeds up to 3.125 Mbps
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
April 08, 2008
29
Preliminary
Architectural Overview
– Direct memory access (DMA)
■ USB
– Standards-based universal serial bus controller
– USB 2.0 full-speed (12 Mbps) operation
– Flexible configuration option
•
USB Device mode
•
USB Host mode
– Integrated PHY
– 4 transfer types: Control, Interrupt, Bulk, and Isochronous
– 1 dedicated bi-directional control endpoint
– 3 Receive and 3 Transmit configurable endpoints
– 4 KB dedicated endpoint memory
•
Direct memory access (DMA)
•
One endpoint may be defined for double-buffered 1023-byte isochronous packet size
■ ADC
– Single- and differential-input configurations
– Eight 10-bit channels (inputs) when used as single-ended inputs
– Sample rate of one million samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Each sequence triggered by software or internal event (timers, analog comparators, PWM
or GPIO)
– On-chip temperature sensor
■ Analog Comparators
– Two independent integrated analog comparators
– Configurable for output to: drive an output pin or generate an interrupt
– Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
– Compare external pin input to external pin input or to internal programmable voltage reference
30
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Preliminary
LM3S3748 Microcontroller
■ I2C
2
– Two I C modules
– Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
– Interrupt generation
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ PWM
– Four PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator,
and a dead-band generator
– Four fault inputs in hardware to condition low-latency shutdown
– One 16-bit counter
•
Runs in Down or Up/Down mode
•
Output frequency controlled by a 16-bit load value
•
Load value updates can be synchronized
•
Produces output signals at zero and load value
– Two PWM comparators
•
Comparator value updates can be synchronized
•
Produces output signals on match
– PWM generator
•
Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
•
Produces two independent PWM signals
– Dead-band generator
•
Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
•
Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
•
PWM output enable of each PWM signal
•
Optional output inversion of each PWM signal (polarity control)
•
Optional fault handling for each PWM signal
April 08, 2008
31
Preliminary
Architectural Overview
•
Synchronization of timers in the PWM generator blocks
•
Synchronization of timer/comparator updates across the PWM generator blocks
•
Interrupt status summary of the PWM generator blocks
– Can initiate an ADC sample sequence
■ QEI
– Hardware position integrator tracks the encoder position
– Velocity capture using built-in timer
– Interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature
error detection
■ GPIOs
– 3-61 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Low interrupt latency; as low as 6 cycles and never more than 12 cycles
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Pins configured as digital inputs are Schmitt-triggered.
– Programmable control for GPIO pad configuration:
•
Weak pull-up or pull-down resistors
•
2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be
configured with an 18-mA pad drive for high-current applications
•
Slew rate control for the 8-mA drive
•
Open drain enables
•
Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
32
April 08, 2008
Preliminary
LM3S3748 Microcontroller
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 100-pin RoHS-compliant LQFP package
1.2
Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
April 08, 2008
33
Preliminary
Architectural Overview
■ Transportation
1.3
High-Level Block Diagram
®
Figure 1-1 on page 34 represents the full set of features in the Stellaris 3000 series of devices;
not all features may be available on the LM3S3748 microcontroller.
®
Figure 1-1. Stellaris Series High-Level Block Diagram
32
JTAG
128 KB Flash
NVIC
ARM ®
Cortex ™-M3
SWD
50 MHz
32
32
Systick Timer
4 Timer/PWM/CC P
2 SSI/SPI
Each 32-bit or 2x16-bit
Watchdog Timer
USB Full Speed
SYSTEM
SERIAL INTERFACES
ROM
Clocks, Reset
System Control
3 UARTs
GPIOs
Host / Device / OTG
32ch DM A
2 I 2C
R
T
C
Quadrature
Encoder Input
Battery-Backed
Hibernate
LDO Voltage
Regulator
8 PWM Outputs
2 Analog
Comparators
Timer
Comparators
PWM
Generator
10-bit ADC
8 channel
1 Msps
PWM
Interrupt
Dead-Band
Generator
ANALOG
MOTION CONTROL
64 KB SRAM
Temp Sensor
34
April 08, 2008
Preliminary
LM3S3748 Microcontroller
1.4
Functional Overview
The following sections provide an overview of the features of the LM3S3748 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 752.
1.4.1
ARM Cortex™-M3
1.4.1.1
Processor Core (see page 42)
®
All members of the Stellaris product family, including the LM3S3748 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 42 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2
System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3
Nested Vectored Interrupt Controller (NVIC)
The LM3S3748 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM® Cortex™-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 37 interrupts.
“Interrupts” on page 51 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.4
Direct Memory Access (see page 189)
The LM3S3748 microcontroller includes a Direct Memory Access (DMA) controller, known as
micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
April 08, 2008
35
Preliminary
Architectural Overview
Cortex-M3 processor, allowing for more effecient use of the processor and the expanded available
bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It
has dedicated channels for each supported peripheral and can be programmed to automatically
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller also supports sophisticated transfer modes such as ping-pong and
scatter-gather, which allows the processor to set up a list of transfer tasks for the controller.
1.4.2
Motor Control Peripherals
To enhance motor control, the LM3S3748 controller features Pulse Width Modulation (PWM) outputs
and the Quadrature Encoder Interface (QEI).
1.4.2.1
PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
On the LM3S3748, PWM motion control functionality can be achieved through:
■ Dedicated, flexible motion control hardware using the PWM pins
■ The motion control features of the general-purpose timers using the CCP pins
PWM Pins (see page 603)
The LM3S3748 PWM module consists of four PWM generator blocks and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.
CCP Pins (see page 303)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
Fault Pins (see “Fault Conditions”)
The LM3S3748 PWM module includes four fault-condition handling inputs to quickly provide
low-latency shutdown and prevent damage to the motor being controlled.
1.4.2.2
QEI (see page 657)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a
quadrature encoder wheel to integrate position over time and determine direction of rotation. In
addition, it can capture a running estimate of the velocity of the encoder wheel.
36
April 08, 2008
Preliminary
LM3S3748 Microcontroller
1.4.3
Analog Peripherals
To handle analog signals, the LM3S3748 microcontroller offers an Analog-to-Digital Converter
(ADC).
For support of analog signals, the LM3S3748 microcontroller offers two analog comparators.
1.4.3.1
ADC (see page 354)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The LM3S3748 ADC module features 10-bit conversion resolution and supports eight input channels,
plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up
to eight analog input sources without controller intervention. Each sample sequence provides flexible
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.
1.4.3.2
Analog Comparators (see page 591)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S3748 microcontroller provides two independent integrated analog comparators that can
be configured to drive an output or generate an interrupt or ADC event.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
1.4.4
Serial Communications Peripherals
The LM3S3748 controller supports both asynchronous and synchronous serial communications
with:
■ Two fully programmable 16C550-type UARTs
■ Two SSI modules
■ Two I2C modules
■ One USB 2.0 full-speed controller
1.4.4.1
UART (see page 386)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
April 08, 2008
37
Preliminary
Architectural Overview
The LM3S3748 controller includes two fully programmable 16C550-type UARTs that support data
transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2
SSI (see page 429)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S3748 controller includes two SSI modules that provide the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
Each SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
Each SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
Each SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3
I2C (see page 468)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking
devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and
diagnostic purposes in product development and manufacture.
The LM3S3748 controller includes two I2C modules that provide the ability to communicate to other
IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write
and read) data.
Devices on the I2C bus can be designated as either a master or a slave. Each I2C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive,
Slave Transmit, and Slave Receive.
®
A Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error). The I2C slave generates
interrupts when data has been sent or requested by a master.
1.4.4.4
USB (see page 503 )
Universal Serial Bus (USB) is a serial bus standard designed to allow peripherals to be connected
and disconnected using a standardized interface without rebooting the system.
38
April 08, 2008
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LM3S3748 Microcontroller
The LM3S3748 controller supports the USB 2.0 full-speed configuration with Device or USB Host
mode. The specified throughput for a USB 2.0 full-speed controller is 12 Mbps.
1.4.5
System Peripherals
1.4.5.1
Programmable GPIOs (see page 250)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
®
The Stellaris GPIO module is comprised of eight physical GPIO blocks, each corresponding to an
individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP
for Real-Time Microcontrollers specification) and supports 3-61 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page
675 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines. Pins configured as digital inputs are
Schmitt-triggered.
1.4.5.2
Four Programmable Timers (see page 297)
Programmable timers can be used to count or time external events that drive the Timer input pins.
®
The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
Timers can also be used to trigger analog-to-digital (ADC) conversions.
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3
Watchdog Timer (see page 331)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
®
The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.6
Memory Peripherals
The LM3S3748 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1
SRAM (see page 160)
The LM3S3748 static random access memory (SRAM) controller supports 64 KB SRAM. The internal
®
SRAM of the Stellaris devices is located at offset 0x0000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
April 08, 2008
39
Preliminary
Architectural Overview
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
1.4.6.2
Flash (see page 161)
The LM3S3748 Flash controller supports 128 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
1.4.6.3
ROM
®
The LM3S3748 microcontroller ships with the Stellaris family Peripheral Driver Library conveniently
®
preprogrammed in read-only memory (ROM). The Stellaris Peripheral Driver Library is a royalty-free
software library for controlling on-chip peripherals, and includes a boot-loader capability. The library
performs both peripheral initialization and peripheral control functions, with a choice of polled or
interrupt-driven peripheral support, and takes full advantage of the stellar interrupt performance of
the ARM® Cortex™-M3 core. No special pragmas or custom assembly code prologue/epilogue
®
functions are required. For applications that require in-field programmability, the royalty-free Stellaris
®
boot loader included in the Stellaris Peripheral Driver Library can act as an application loader and
support in-field firmware updates.
1.4.7
Additional Features
1.4.7.1
Memory Map (see page 48)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S3748 controller can be found in “Memory Map” on page 48. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
1.4.7.2
JTAG TAP Controller (see page 54)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is composed of the standard four pins: TCK, TMS, TDI, and TDO. Data is transmitted
serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is
dependent on the current state of the TAP controller. For detailed information on the operation of
the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
40
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
1.4.7.3
System Control and Clocks (see page 66)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.7.4
Hibernation Module (see page 137)
The Hibernation module provides logic to switch power off to the main processor and peripherals,
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt
signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used
for saving state during hibernation.
1.4.8
Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 674
■ “Signal Tables” on page 675
■ “Operating Characteristics” on page 690
■ “Electrical Characteristics” on page 691
■ “Package Information” on page 703
April 08, 2008
41
Preliminary
ARM Cortex-M3 Processor Core
2
ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that
meets the needs of minimal memory implementation, reduced pin count, and low power consumption,
while delivering outstanding computational performance and exceptional system response to
interrupts. Features include:
■ Compact core.
■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■ Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler
for safety critical applications.
■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.
■ Migration from the ARM7™ processor family for better performance and power efficiency.
■ Full-featured debug solution with a:
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
■ Optimized for single-cycle flash usage
■ Three sleep modes with clock gating for low power
■ Single-cycle multiply instruction and hardware divide
■ Atomic operations
■ ARM Thumb2 mixed 16-/32-bit instruction set
■ 1.25 DMIPS/MHz
42
April 08, 2008
Preliminary
LM3S3748 Microcontroller
®
The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motors.
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
2.1
Block Diagram
Figure 2-1. CPU Block Diagram
Nested
Vectored
Interrupt
Controller
Interrupts
ARM
Cortex-M3
CM3 Core
Sleep
Debug
Instructions
Data
Trace
Port
Interface
Unit
Memory
Protection
Unit
Flash
Patch and
Breakpoint
Instrumentation
Data
Watchpoint Trace Macrocell
and Trace
2.2
Adv. HighPerf. Bus
Access Port
Private
Peripheral
Bus
(external)
ROM
Table
Private Peripheral
Bus
(internal)
Serial Wire JTAG
Debug Port
Serial
Wire
Output
Trace
Port
(SWO)
Adv. Peripheral
Bus
Bus
Matrix
I-code bus
D-code bus
System bus
Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
®
This section describes the Stellaris implementation.
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 43. As
noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are
flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested
Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
April 08, 2008
43
Preliminary
ARM Cortex-M3 Processor Core
2.2.1
Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the
®
ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris devices.
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
2.2.2
Embedded Trace Macrocell (ETM)
®
ETM was not implemented in the Stellaris devices. This means Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
2.2.3
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
®
Port Analyzer. The Stellaris devices have implemented TPIU as shown in Figure 2-2 on page 44.
This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference
Manual, however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
2.2.4
Debug
ATB
Slave
Port
ATB
Interface
APB
Slave
Port
APB
Interface
Asynchronous FIFO
Trace Out
(serializer)
Serial Wire
Trace Port
(SWO)
ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
2.2.5
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S3748 controller and supports the standard
ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for
protection regions, overlapping protection regions, access permissions, and exporting memory
attributes to the system.
44
April 08, 2008
Preliminary
LM3S3748 Microcontroller
2.2.6
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■ Facilitates low-latency exception and interrupt handling
■ Controls power management
■ Implements system control registers
The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of
priority. The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge
of the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode
if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference
Manual). Any other user-mode access causes a bus fault.
All NVIC registers are accessible using byte, halfword, and word unless otherwise stated.
2.2.6.1
Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts
and interrupt priorities. The LM3S3748 microcontroller supports 37 interrupts with eight priority
levels.
In addition to the peripheral interrupts, the system also provides for a non-maskable interrupt. The
NMI is generally used in safety critical applications where the immediate execution of an interrupt
handler is required. The NMI signal is available as an external signal so that it may be generated
by external circuitry The NMI is also used internally as part of the main oscillator verification circuitry.
More information on the non-maskable interrupt is located in “Non-Maskable Interrupt” on page 69.
2.2.6.2
System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
Functional Description
The timer consists of three registers:
April 08, 2008
45
Preliminary
ARM Cortex-M3 Processor Core
■ A control and status counter to configure its clock, enable the counter, enable the SysTick
interrupt, and determine counter status.
■ The reload value for the counter, used to provide the counter's wrap value.
■ The current value of the counter.
®
A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris devices.
When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value
in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks.
Writing a value of zero to the Reload Value register disables the counter on the next wrap. When
the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write
does not trigger the SysTick exception logic. On a read, the current value is the value of the register
at the time the register is accessed.
If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect
to a reference clock. The reference clock can be the core clock or an external clock source.
SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features. The reset is
0x0000.0000.
Bit/Field
Name
31:17
reserved
16
Type Reset Description
RO
0
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
COUNTFLAG R/W
0
Count Flag
Returns 1 if timer counted to 0 since last time this was read. Clears on read by
application. If read by the debugger using the DAP, this bit is cleared on read-only
if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the
COUNTFLAG bit is not changed by the debugger read.
15:3
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
CLKSOURCE R/W
0
Clock Source
Value Description
0
External reference clock. (Not implemented for Stellaris microcontrollers.)
1
Core clock
If no reference clock is provided, it is held at 1 and so gives the same time as the
core clock. The core clock must be at least 2.5 times faster than the reference clock.
If it is not, the count values are unpredictable.
1
TICKINT
R/W
0
Tick Interrupt
Value Description
0
Counting down to 0 does not generate the interrupt request to the NVIC.
Software can use the COUNTFLAG to determine if ever counted to 0.
1
Counting down to 0 pends the SysTick handler.
46
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
0
ENABLE
Type Reset Description
R/W
0
Enable
Value Description
0
Counter disabled.
1
Counter operates in a multi-shot way. That is, counter loads with the Reload
value and then begins counting down. On reaching 0, it sets the
COUNTFLAG to 1 and optionally pends the SysTick handler, based on
TICKINT. It then loads the Reload value again, and begins counting.
SysTick Reload Value Register
Use the SysTick Reload Value Register to specify the start value to load into the current value
register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value
of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated
when counting from 1 to 0.
Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is
any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99
must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single
shot, then the actual count down must be written. For example, if a tick is next required after 400
clock pulses, 400 must be written into the RELOAD.
Bit/Field
Name
Type Reset Description
31:24
reserved
23:0
RELOAD W1C
RO
0
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a read-modify-write
operation.
-
Reload
Value to load into the SysTick Current Value Register when the counter reaches 0.
SysTick Current Value Register
Use the SysTick Current Value Register to find the current value in the register.
Bit/Field
Name
31:24
reserved
23:0
Type Reset Description
RO
CURRENT W1C
0
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
-
Current Value
Current value at the time the register is accessed. No read-modify-write protection is
provided, so change with care.
This register is write-clear. Writing to it with any value clears the register to 0. Clearing
this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
SysTick Calibration Value Register
The SysTick Calibration Value register is not implemented.
April 08, 2008
47
Preliminary
Memory Map
3
Memory Map
The memory map for the LM3S3748 controller is provided in Table 3-1 on page 48.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
a
Table 3-1. Memory Map
Start
End
Description
For details on
registers, see
page ...
0x0000.0000
0x0001.FFFF
On-chip flash
0x0002.0000
0x00FF.FFFF
Reserved
-
0x0100.0000
0x0100.2BFF
On-chip ROM
165
0x0100.2C00
0x1FFF.FFFF
Reserved
Memory
b
166
c
0x2000.0000
0x2000.FFFF
Bit-banded on-chip SRAM
166
0x2001.0000
0x21FF.FFFF
Reserved
-
0x2200.0000
0x221F.FFFF
Bit-band alias of 0x2000.0000 through 0x200F.FFFF
160
0x2220.0000
0x3FFF.FFFF
Reserved
-
0x4000.0000
0x4000.0FFF
Watchdog timer
333
0x4000.1000
0x4000.3FFF
Reserved
-
0x4000.4000
0x4000.4FFF
GPIO Port A
258
0x4000.5000
0x4000.5FFF
GPIO Port B
258
0x4000.6000
0x4000.6FFF
GPIO Port C
258
0x4000.7000
0x4000.7FFF
GPIO Port D
258
0x4000.8000
0x4000.8FFF
SSI0
441
0x4000.9000
0x4000.9FFF
SSI1
441
0x4000.A000
0x4000.BFFF
Reserved
-
0x4000.C000
0x4000.CFFF
UART0
394
0x4000.D000
0x4000.DFFF
UART1
394
0x4000.E000
0x4001.FFFF
Reserved
-
0x4002.0000
0x4002.07FF
I2C Master 0
481
0x4002.0800
0x4002.0FFF
I2C Slave 0
494
0x4002.1000
0x4002.17FF
I2C Master 1
481
0x4002.1800
0x4002.1FFF
I2C Slave 1
494
0x4002.2000
0x4002.3FFF
Reserved
-
0x4002.4000
0x4002.4FFF
GPIO Port E
258
0x4002.5000
0x4002.5FFF
GPIO Port F
258
0x4002.6000
0x4002.6FFF
GPIO Port G
258
0x4002.7000
0x4002.7FFF
GPIO Port H
258
0x4002.8000
0x4002.8FFF
PWM
612
FiRM Peripherals
Peripherals
48
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Start
End
Description
For details on
registers, see
page ...
0x4002.9000
0x4002.BFFF
Reserved
-
0x4002.C000
0x4002.CFFF
QEI0
661
0x4002.D000
0x4002.FFFF
Reserved
-
0x4003.0000
0x4003.0FFF
Timer0
308
0x4003.1000
0x4003.1FFF
Timer1
308
0x4003.2000
0x4003.2FFF
Timer2
308
0x4003.3000
0x4003.3FFF
Timer3
308
0x4003.4000
0x4003.7FFF
Reserved
-
0x4003.8000
0x4003.8FFF
ADC
361
0x4003.9000
0x4003.BFFF
Reserved
-
0x4003.C000
0x4003.CFFF
Analog Comparators
591
0x4003.D000
0x4004.FFFF
Reserved
-
0x4005.0000
0x4005.0FFF
USB
517
0x4005.1000
0x4005.7FFF
Reserved
-
0x4005.8000
0x4005.8FFF
GPIO Port A (AHB aperture)
258
0x4005.9000
0x4005.9FFF
GPIO Port B (AHB aperture)
258
0x4005.A000
0x4005.AFFF
GPIO Port C (AHB aperture)
258
0x4005.B000
0x4005.BFFF
GPIO Port D (AHB aperture)
258
0x4005.C000
0x4005.CFFF
GPIO Port E (AHB aperture)
258
0x4005.D000
0x4005.DFFF
GPIO Port F (AHB aperture)
258
0x4005.E000
0x4005.EFFF
GPIO Port G (AHB aperture)
258
0x4005.F000
0x4005.FFFF
GPIO Port H (AHB aperture)
258
0x4006.0000
0x400F.BFFF
Reserved
-
0x400F.C000
0x400F.CFFF
Hibernation Module
146
0x400F.D000
0x400F.DFFF
Flash control
166
0x400F.E000
0x400F.EFFF
System control
76
0x400F.F000
0x400F.FFFF
uDMA
209
0x4010.0000
0x41FF.FFFF
Reserved
-
0x4200.0000
0x43FF.FFFF
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
-
0x4400.0000
0xDFFF.FFFF
Reserved
-
0xE000.0000
0xE000.0FFF
Instrumentation Trace Macrocell (ITM)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.1000
0xE000.1FFF
Data Watchpoint and Trace (DWT)
ARM®
Cortex™-M3
Technical
Reference
Manual
Private Peripheral Bus
April 08, 2008
49
Preliminary
Memory Map
Start
End
Description
For details on
registers, see
page ...
0xE000.2000
0xE000.2FFF
Flash Patch and Breakpoint (FPB)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.3000
0xE000.DFFF
Reserved
-
0xE000.E000
0xE000.EFFF
Nested Vectored Interrupt Controller (NVIC)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.F000
0xE003.FFFF
Reserved
-
0xE004.0000
0xE004.0FFF
Trace Port Interface Unit (TPIU)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE004.1000
0xFFFF.FFFF
Reserved
-
a. All reserved space returns a bus fault when read or written.
b. The unavailable flash will bus fault throughout this range.
c. The unavailable SRAM will bus fault throughout this range.
50
April 08, 2008
Preliminary
LM3S3748 Microcontroller
4
Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions. All exceptions are handled in Handler Mode. The processor state is
automatically stored to the stack on an exception, and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which
enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back
interrupts to be performed without the overhead of state saving and restoration.
Table 4-1 on page 51 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 37 interrupts (listed in Table 4-2 on page 52).
Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts
are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt
Priority registers. You also can group priorities by splitting priority levels into pre-emption priorities
and subpriorities. All of the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and
a Hard Fault. Note that 0 is the default priority for all the settable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Table 4-1. Exception Types
Exception Type
Vector
Number
a
Priority
-
Description
-
0
Stack top is loaded from first entry of vector table on reset.
Reset
1
Non-Maskable Interrupt
(NMI)
2
-2
Cannot be stopped or preempted by any exception but reset. This is
asynchronous.
Hard Fault
3
-1
All classes of Fault, when the fault cannot activate due to priority or the
configurable fault handler has been disabled. This is synchronous.
Memory Management
4
settable
Bus Fault
5
settable
-3 (highest) Invoked on power up and warm reset. On first instruction, drops to lowest
priority (and then is called the base level of activation). This is
asynchronous.
MPU mismatch, including access violation and no match. This is
synchronous.
The priority of this exception can be changed.
Pre-fetch fault, memory access fault, and other address/memory related
faults. This is synchronous when precise and asynchronous when
imprecise.
You can enable or disable this fault.
Usage Fault
6
settable
7-10
-
SVCall
11
settable
System service call with SVC instruction. This is synchronous.
Debug Monitor
12
settable
Debug monitor (when not halting). This is synchronous, but only active
when enabled. It does not activate if lower priority than the current
activation.
-
Usage fault, such as undefined instruction executed or illegal state
transition attempt. This is synchronous.
Reserved.
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Interrupts
Exception Type
a
Vector
Number
Priority
Description
-
13
-
PendSV
14
settable
Pendable request for system service. This is asynchronous and only
pended by software.
15
settable
System tick timer has fired. This is asynchronous.
16 and
above
settable
Asserted from outside the ARM Cortex-M3 core and fed through the
NVIC (prioritized). These are all asynchronous. Table 4-2 on page 52
lists the interrupts on the LM3S3748 controller.
SysTick
Interrupts
Reserved.
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Vector Number
Interrupt Number (Bit in
Interrupt Registers)
0-15
-
Processor exceptions
16
0
GPIO Port A
17
1
GPIO Port B
18
2
GPIO Port C
19
3
GPIO Port D
20
4
GPIO Port E
21
5
UART0
22
6
UART1
23
7
SSI0
24
8
I2C0
25
9
PWM Fault
26
10
PWM Generator 0
27
11
PWM Generator 1
28
12
PWM Generator 2
29
13
QEI0
30
14
ADC Sequence 0
31
15
ADC Sequence 1
32
16
ADC Sequence 2
33
17
ADC Sequence 3
34
18
Watchdog timer
35
19
Timer0 A
36
20
Timer0 B
37
21
Timer1 A
38
22
Timer1 B
39
23
Timer2 A
40
24
Timer2 B
41
25
Analog Comparator 0
42
26
Analog Comparator 1
43
27
Reserved
44
28
System Control
45
29
Flash Control
46
30
GPIO Port F
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Description
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LM3S3748 Microcontroller
Vector Number
Interrupt Number (Bit in
Interrupt Registers)
Description
47
31
GPIO Port G
48
32
GPIO Port H
49
33
Reserved
50
34
SSI1
51
35
Timer3 A
52
36
Timer3 B
53
37
I2C1
54-58
38-42
59
43
Hibernation Module
60
44
USB
61
45
PWM Generator 3
62
46
uDMA Software
63
47
uDMA Error
April 08, 2008
Reserved
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Preliminary
JTAG Interface
5
JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of four pins: TCK, TMS, TDI, and TDO. Data is transmitted serially into
the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
The JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions:
– BYPASS instruction
– IDCODE instruction
– SAMPLE/PRELOAD instruction
– EXTEST instruction
– INTEST instruction
■ ARM additional instructions:
– APACC instruction
– DPACC instruction
– ABORT instruction
■ Integrated ARM Serial Wire Debug (SWD)
See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG
controller.
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5.1
Block Diagram
Figure 5-1. JTAG Module Block Diagram
TCK
TMS
TDI
TAP Controller
Instruction Register (IR)
BYPASS Data Register
TDO
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
Cortex-M3
Debug
Port
5.2
Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 55. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs.
The current state of the TAP controller depends on the sequence of values captured on TMS at the
rising edge of TCK. The TAP controller determines when the serial shift chains capture new data,
shift data from TDI towards TDO, and update the parallel load registers. The current state of the
TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register
(DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 5-2 on page 61 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 699 for JTAG timing diagrams.
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JTAG Interface
5.2.1
JTAG Interface Pins
The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO. These pins and their
associated reset state are given in Table 5-1 on page 56. Detailed information on each pin follows.
Table 5-1. JTAG Port Pins Reset State
5.2.1.1
Pin Name
Data Direction
Internal Pull-Up
Internal Pull-Down
Drive Strength
Drive Value
TCK
Input
Enabled
Disabled
N/A
N/A
TMS
Input
Enabled
Disabled
N/A
N/A
TDI
Input
Enabled
Disabled
N/A
N/A
TDO
Output
Enabled
Disabled
2-mA driver
High-Z
Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers
that are daisy-chained together can synchronously communicate serial test data between
components. During normal operation, TCK is driven by a free-running clock with a nominal 50%
duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK
is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction
and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
5.2.1.2
Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered.
Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
module and associated registers are reset to their default values. This procedure should be performed
to initialize the JTAG controller. The JTAG Test Access Port state machine can be seen in its entirety
in Figure 5-2 on page 58.
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost.
5.2.1.3
Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling
edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost.
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5.2.1.4
Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states.
5.2.2
JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 5-2 on page 58. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR).
Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions,
shift in data, or idle during extended testing sequences. For detailed information on the function of
the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1.
April 08, 2008
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Preliminary
JTAG Interface
Figure 5-2. Test Access Port State Machine
Test Logic Reset
1
0
Run Test Idle
0
Select DR Scan
1
Select IR Scan
1
0
1
0
Capture DR
1
Capture IR
0
0
Shift DR
Shift IR
0
1
Exit 1 DR
Exit 1 IR
1
Pause IR
0
1
Exit 2 DR
0
1
0
Exit 2 IR
1
1
Update DR
5.2.3
1
0
Pause DR
1
0
1
0
0
1
0
Update IR
1
0
Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 61.
5.2.4
Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.
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5.2.4.1
GPIO Functionality
When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting
GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate
hardware function (setting GPIOAFSEL to 1) for the PC[3:0] JTAG/SWD pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PC[3:0] in
the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or
board-level testing, this provides four more GPIOs for use in the design.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 269), GPIO Pull-Up Select (GPIOPUR) register (see page 275), and GPIO Digital
Enable (GPIODEN) register (see page 278) are not committed to storage unless the GPIO Lock
(GPIOLOCK) register (see page 280) has been unlocked and the appropriate bits of the GPIO
Commit (GPIOCR) register (see page 281) have been set to 1.
Recovering a "Locked" Device
Note:
Performing the below sequence will cause the nonvolatile registers discussed in “Nonvolatile
Register Programming” on page 163 to be restored to their factory default values. The mass
erase of the flash memory caused by the below sequence occurs prior to the nonvolatile
registers being restored.
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the device. Performing
a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset
mass erases the flash memory. The sequence to recover the device is:
1. Assert and hold the RST signal.
2. Perform the JTAG-to-SWD switch sequence.
3. Perform the SWD-to-JTAG switch sequence.
4. Perform the JTAG-to-SWD switch sequence.
5. Perform the SWD-to-JTAG switch sequence.
6. Perform the JTAG-to-SWD switch sequence.
7. Perform the SWD-to-JTAG switch sequence.
8. Perform the JTAG-to-SWD switch sequence.
9. Perform the SWD-to-JTAG switch sequence.
10. Perform the JTAG-to-SWD switch sequence.
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JTAG Interface
11. Perform the SWD-to-JTAG switch sequence.
12. Release the RST signal.
13. Wait 400 ms.
14. Power-cycle the device.
The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug
(SWD)” on page 60. When performing switch sequences for the purpose of recovering the debug
capabilities of the device, only steps 1 and 2 of the switch sequence need to be performed.
5.2.4.2
ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller
in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the
following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test
Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run
Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequences of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occurring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in SWD mode, before sending the switch sequence, the SWD goes into the line reset
state.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to JTAG mode is defined as b1110011110011110, transmitted LSB first. This can also
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be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C.
3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic
Reset state.
5.3
Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. This is done by enabling the four JTAG
pins (PC[3:0]) for their alternate function using the GPIOAFSEL register.
5.4
Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The registers
can be broken down into two main categories: Instruction Registers and Data Registers.
5.4.1
Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register
connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 5-2 on page 61. A detailed explanation of each instruction, along
with its associated Data Register, follows.
Table 5-2. JTAG Instruction Register Commands
IR[3:0]
Instruction
0000
EXTEST
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction onto the pads.
0001
INTEST
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction into the controller.
0010
Description
SAMPLE / PRELOAD Captures the current I/O values and shifts the sampled values out of the Boundary Scan
Chain while new preload data is shifted in.
1000
ABORT
Shifts data into the ARM Debug Port Abort Register.
1010
DPACC
Shifts data into and out of the ARM DP Access Register.
1011
APACC
Shifts data into and out of the ARM AC Access Register.
1110
IDCODE
Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE
chain and shifts it out.
1111
BYPASS
Connects TDI to TDO through a single Shift Register chain.
All Others
Reserved
Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO.
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5.4.1.1
EXTEST Instruction
The EXTEST instruction does not have an associated Data Register chain. The EXTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. This allows
tests to be developed that drive known values out of the controller, which can be used to verify
connectivity.
5.4.1.2
INTEST Instruction
The INTEST instruction does not have an associated Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows tests
to be developed that drive known values into the controller, which can be used for testing.
5.4.1.3
SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data
Register” on page 64 for more information.
5.4.1.4
ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. Please see the “ABORT Data Register” on page 65 for more
information.
5.4.1.5
DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 64 for more information.
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5.4.1.6
APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
Please see “APACC Data Register” on page 64 for more information.
5.4.1.7
IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a power-on-reset (POR) is asserted, or the Test-Logic-Reset
state is entered. Please see “IDCODE Data Register” on page 63 for more information.
5.4.1.8
BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 64 for
more information.
5.4.2
Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan,
APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed
in the following sections.
5.4.2.1
IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-3 on page 63. The standard requires that every JTAG-compliant device implement either
the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x3BA00477. This value indicates an ARM Cortex-M3, Version 1
processor. This allows the debuggers to automatically configure themselves to work correctly with
the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
31
TDI
28 27
Version
12 11
Part Number
April 08, 2008
1 0
Manufacturer ID
1
TDO
63
Preliminary
JTAG Interface
5.4.2.2
BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-4 on page 64. The standard requires that every JTAG-compliant device implement either
the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default instruction.
Figure 5-4. BYPASS Register Format
0
0
TDI
5.4.2.3
TDO
Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 64. Each GPIO
pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because
the reset pin is always an input, only the input signal is included in the Data Register chain.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 5-5. Boundary Scan Register Format
TDI
I
N
O
U
T
O
E
GPIO PB6
...
I
N
O
U
T
O
E
GPIO m
I
N
O
U
T
GPIO m +1
O
E
...
I
N
O
U
T
O
E
TDO
GPIO n
For detailed information on the order of the input, output, and output enable bits for each of the
®
GPIO ports, please refer to the Stellaris Family Boundary Scan Description Language (BSDL) files,
downloadable from www.luminarymicro.com.
5.4.2.4
APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.5
DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
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LM3S3748 Microcontroller
5.4.2.6
ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
April 08, 2008
65
Preliminary
System Control
6
System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.
6.1
Functional Description
The System Control module provides the following capabilities:
■ Device identification, see “Device Identification” on page 66
■ Local control, such as reset (see “Reset Control” on page 66), power (see “Power
Control” on page 69) and clock control (see “Clock Control” on page 69)
■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 73
6.1.1
Device Identification
Seven read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC7 registers.
6.1.2
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
6.1.2.1
Reset Sources
The controller has six sources of reset:
1. External reset input pin (RST) assertion, see “RST Pin Assertion” on page 66.
2. Power-on reset (POR), see “Power-On Reset (POR)” on page 67.
3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 67.
4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 68.
5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 68.
6. MOSC failure
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator.
6.1.2.2
RST Pin Assertion
The external reset pin (RST) resets the controller. This resets the core and all the peripherals except
the JTAG TAP controller (see “JTAG Interface” on page 54). The external reset sequence is as
follows:
1. The external reset pin (RST) is asserted and then de-asserted.
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2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for
synchronization.
The external reset timing is shown in Figure 24-9 on page 701.
6.1.2.3
Power-On Reset (POR)
The Power-On Reset (POR) circuit monitors the power supply voltage (VDD). The POR circuit
generates a reset signal to the internal logic when the power supply ramp reaches a threshold value
(VTH). If the application only uses the POR circuit, the RST input needs to be connected to the power
supply (VDD) through a pull-up resistor (1K to 10K Ω).
The device must be operating within the specified operating parameters at the point when the on-chip
power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within
10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of
an external reset to hold the device in reset longer than the internal POR, the RST input may be
used with the circuit as shown in Figure 6-1 on page 67.
Figure 6-1. External Circuitry to Extend Reset
Stellaris
D1
R1
RST
C1
R2
The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from
the RST input. The diode (D1) discharges C1 rapidly when the power supply is turned off.
The Power-On Reset sequence is as follows:
1. The controller waits for the later of external reset (RST) or internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing
is shown in Figure 24-10 on page 702.
Note:
6.1.2.4
The power-on reset also resets the JTAG controller. An external reset does not.
Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops
below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may
generate a controller interrupt or a system reset.
April 08, 2008
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Preliminary
System Control
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
The brown-out reset is equivelent to an assertion of the external RST input and the reset is held
active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt
handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to
determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 24-11 on page 702.
6.1.2.5
Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 73). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
The software-initiated system reset timing is shown in Figure 24-12 on page 702.
6.1.2.6
Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
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The watchdog reset timing is shown in Figure 24-13 on page 702.
6.1.3
Non-Maskable Interrupt
The controller has two sources of non-maskable interrupt (NMI):
■ The assertion of the NMI signal.
■ A main oscillator verification error.
If both sources of NMI are enabled, software must check that the main oscillator verification is the
cause of the interrupt in order to distinguish between the two sources.
6.1.3.1
NMI Pin
The alternate function to GPIO port pin B7 is an NMI signal. The alternate function must be enabled
in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose Input/Outputs
(GPIOs)” on page 250. Note that enabling the NMI alternate function requires the use of the GPIO
lock and commit function just like the GPIO port pins associated with JTAG/SWD functionality. The
active sense of the NMI signal is High; asserting the enabled NMI signal above VIH initiates the NMI
interrupt sequence.
6.1.3.2
Main Oscillator Verification Failure
The main oscillator verification circuit may generate a reset event and then, during the subsequent
POR, control is transferred to the NMI handler. The detection circuit is enabled using the CVAL bit
in the Main Oscillator Control (MOSCCTL) register. The main oscillator verification error is indicated
in the main oscillator fail status bit (MOSCFAIL bit in the Reset Cause (RESC) register. The main
oscillator verification circuit action is described in more detail in “Clock Control” on page 69.
6.1.4
Power Control
®
The Stellaris microcontroller provides an integrated LDO regulator that may be used to provide
power to the majority of the controller's internal logic. The LDO regulator provides software a
mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V
to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ
field in the LDO Power Control (LDOPCTL) register.
Note:
6.1.5
The use of the LDO is optional. The internal logic may be supplied by the on-chip LDO or
by an external regulator. If the LDO is used, the LDO output pin is connected to the VDD25
pins on the printed circuit board. The LDO requires decoupling capacitors on the printed
circuit board. If an external regulator is used, it is strongly recommended that the external
regulator supply the controller only and not be shared with other devices on the printed
circuit board.
Clock Control
System control determines the control of clocks in this part.
6.1.5.1
Fundamental Clock Sources
There are four clock sources for use in the device:
■ Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
Applications that do not depend on accurate clock sources may use this clock source to reduce
system cost. The internal oscillator is the clock source the device uses during and following POR.
April 08, 2008
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Preliminary
System Control
If the main oscillator is required, software must enable the main oscillator following reset and
allow the main oscillator to stabilize before changing the clock reference.
■ Main Oscillator (MOSC): The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being
used, the crystal value must be one of the supported frequencies between 3.579545 MHz through
16.384 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 16.384 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit field
in the RCC register (see page 85).
■ Internal 30-kHz Oscillator: The internal 30-kHz oscillator is similar to the internal oscillator,
except that it provides an operational frequency of 30 kHz ± 50%. It is intended for use during
Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal
switching and also allows the main oscillator to be powered down.
■ External Real-Time Oscillator: The external real-time oscillator provides a low-frequency,
accurate clock reference. It is intended to provide the system with a real-time clock source. The
real-time oscillator is part of the Hibernation Module (“Hibernation Module” on page 137) and may
also provide an accurate source of Deep-Sleep or Hibernate mode power savings.
The internal system clock (SysClk), is derived from any of the four sources plus two others: the
output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The
frequency of the PLL clock reference must be in the range of 3.579545 MHz to 16.384 MHz
(inclusive).
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options.
Figure 6-2 on page 71 shows the logic for the main clock tree. The peripheral blocks are driven by
the system clock signal and can be programmatically enabled/disabled. The ADC clock signal is
automatically divided down to 16 MHz for proper ADC operation. The PWM clock signal is a
synchronous divide by of the system clock to provide the PWM circuit with more range.
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Figure 6-2. Main Clock Tree
XTALa
USBPWRDN c
PLL
(240 MHz)
USB Clock
÷4
USEPWMDIV a
PWMDW a
PWM Clock
XTALa
PWRDN b
MOSCDIS a
PLL
(400 MHz)
Main OSC
USESYSDIV a,d
IOSCDIS a
System Clock
Internal
OSC
(12 MHz)
SYSDIV b,d
÷4
BYPASS
Internal
OSC
(30 kHz)
b,d
OSCSRC b,d
Hibernation
Module
(32.768 kHz)
PWRDN
ADC Clock
÷ 25
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
6.1.5.2
Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 16.384 MHz, otherwise,
the range of supported crystals is 1 to 16.384 MHz.
The XTAL bit in the RCC register (see page 85) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
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Preliminary
System Control
6.1.5.3
Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency, and enables the
main PLL to drive the output.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 90). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency.
The Crystal Value field (XTAL) on page 85 describes the available crystal choices and default
programming of the PLLCFG register. The crystal number is written into the XTAL field of the
Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings
are translated and the internal PLL settings are updated.
6.1.5.4
USB PLL Frequency Configuration
The USB PLL is disabled by default during power-on reset and is enabled later by software. The
USB PLL must be enabled and running for proper USB function. The main oscillator is the only clock
reference for the USB PLL. The USB PLL is enabled by clearing the USBPWRDN bit of the RCC2
register. The XTAL bit field (Crystal Value) of the RCC register describes the available crystal choices.
The main oscillator must be connected to one of the following crystal values in order to correctly
generate the USB clock: 4, 5, 6, 8, 10, 12, or 16 MHz. Only these crystals provide the necessary
USB PLL VCO frequency to conform with the USB timing specifications.
6.1.5.5
PLL Modes
Both PLLs have two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 85 and page 93).
6.1.5.6
PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
24-8 on page 695) for the main PLL and TUSBREADY for the USB PLL. During the relock time, the
affected PLL is not usable as a clock reference.
Either PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure both the TREADY and TUSBREADY requirements. The counter is
clocked by the main oscillator. The range of the main oscillator has been taken into account and
the down counter is set to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). When
the XTAL value is greater than 0x0f, the down counter is set to 0x2400 to maintain the required lock
time on higher frequency crystal inputs. Hardware is provided to keep the PLL from being used as
a system clock until the TREADY condition is met after one of the two changes above. It is the user's
responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register
is switched to use the PLL.
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If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the controller from the oscillator selected by the RCC/RCC2
register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software
can use many methods to ensure that the system is clocked from the main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.
The USB PLL is not protected during the lock time (TUSBREADY) and software should ensure that
the USB PLL has locked before using the interface. Software can use many methods to ensure the
TUSBREADY period has passed, including periodically polling the the USBPLLLRIS bit in the Raw
Interrupt Status (RIS) register, and enabling the USB PLL Lock interrupt.
6.1.5.7
Main Oscillator Verification Circuit
A circuit is added to ensure that the main oscillator is running at the appropriate frequency. The
circuit monitors the main oscillator frequency and signals if the frequency is outside of the allowable
band of attached crystals.
The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL)
register. If this circuit is enabled and detects an error, the following sequence is performed by the
hardware:
1. The MOSCFAIL bit in the Reset Cause (RESC) register is set.
2. If the internal oscillator (IOSC) is disabled, it is enabled.
3. The system clock is switched from the main oscillator to the IOSC.
4. A system-wide reset is initiated that lasts for 32 IOSC periods.
5. Reset is de-asserted and the processor is directed to the NMI handler during the reset sequence.
6.1.6
System Control
For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
mode, respectively.
In Run mode, the processor executes code. In Sleep mode, the clock frequency of the active
peripherals is unchanged, but the processor is not clocked and therefore no longer executes code.
In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns
the device to Run mode from one of the sleep modes; the sleep modes are entered on request from
the code. Each mode is described in more detail below.
There are four levels of operation for the device defined as:
■ Run Mode. Run mode provides normal operation of the processor and all of the peripherals that
are currently enabled by the RCGCn registers. The system clock can be any of the available
clock sources including the PLL.
■ Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for
Interrupt) instruction. Any properly configured interrupt event in the system will bring the
processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3
Technical Reference Manual for more details.
April 08, 2008
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Preliminary
System Control
In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
■ Deep-Sleep Mode. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in
the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any
properly configured interrupt event in the system will bring the processor back into Run mode.
See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual
for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the
WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active
RCC/RCC2 register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of
Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep
duration.
■ Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device
and only the Hibernation module's circuitry is active. An external wake event or RTC event is
required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside
of the Hibernation module see a normal "power on" sequence and the processor starts running
code. It can determine that it has been restarted from Hibernate mode by inspecting the
Hibernation module registers.
6.2
Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source (using the
main oscillator or internal oscillator) and allows for the new PLL configuration to be validated
before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
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6.3
Register Map
Table 6-1 on page 75 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note:
Spaces in the System Control register space that are not used are reserved for future or
internal use by Luminary Micro, Inc. Software should not modify any reserved memory
address.
Note:
Additional Flash and ROM registers defined in the System Control register space are
described in the “Internal Memory” on page 160.
Table 6-1. System Control Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
DID0
RO
-
Device Identification 0
77
0x004
DID1
RO
-
Device Identification 1
97
0x008
DC0
RO
0x00FF.003F
Device Capabilities 0
99
0x010
DC1
RO
0x0011.33FF
Device Capabilities 1
100
0x014
DC2
RO
0x030F.5133
Device Capabilities 2
102
0x018
DC3
RO
0xBFFF.86FF
Device Capabilities 3
104
0x01C
DC4
RO
0x0000.F0FF
Device Capabilities 4
106
0x020
DC5
RO
0x0F30.00FF
Device Capabilities 5
107
0x024
DC6
RO
0x0000.0002
Device Capabilities 6
109
0x028
DC7
RO
0x03C0.0F3F
Device Capabilities 7
110
0x030
PBORCTL
R/W
0x0000.7FFD
Brown-Out Reset Control
79
0x034
LDOPCTL
R/W
0x0000.0000
LDO Power Control
80
0x040
SRCR0
R/W
0x00000000
Software Reset Control 0
133
0x044
SRCR1
R/W
0x00000000
Software Reset Control 1
134
0x048
SRCR2
R/W
0x00000000
Software Reset Control 2
136
0x050
RIS
RO
0x0000.0000
Raw Interrupt Status
81
0x054
IMC
R/W
0x0000.0000
Interrupt Mask Control
82
0x058
MISC
R/W1C
0x0000.0000
Masked Interrupt Status and Clear
83
0x05C
RESC
R/W
-
Reset Cause
84
0x060
RCC
R/W
0x078E.3AD1
Run-Mode Clock Configuration
85
0x064
PLLCFG
RO
-
XTAL to PLL Translation
90
0x06C
GPIOHSCTL
R/W
0x0000.0000
GPIO High Speed Control
91
0x070
RCC2
R/W
0x0780.6810
Run-Mode Clock Configuration 2
93
0x07C
MOSCCTL
R/W
0x0000.0000
Main Oscillator Control
95
April 08, 2008
75
Preliminary
System Control
See
page
Offset
Name
Type
Reset
0x100
RCGC0
R/W
0x00000040
Run Mode Clock Gating Control Register 0
112
0x104
RCGC1
R/W
0x00000000
Run Mode Clock Gating Control Register 1
118
0x108
RCGC2
R/W
0x00000000
Run Mode Clock Gating Control Register 2
127
0x110
SCGC0
R/W
0x00000040
Sleep Mode Clock Gating Control Register 0
114
0x114
SCGC1
R/W
0x00000000
Sleep Mode Clock Gating Control Register 1
121
0x118
SCGC2
R/W
0x00000000
Sleep Mode Clock Gating Control Register 2
129
0x120
DCGC0
R/W
0x00000040
Deep Sleep Mode Clock Gating Control Register 0
116
0x124
DCGC1
R/W
0x00000000
Deep Sleep Mode Clock Gating Control Register 1
124
0x128
DCGC2
R/W
0x00000000
Deep Sleep Mode Clock Gating Control Register 2
131
0x144
DSLPCLKCFG
R/W
0x0780.0000
Deep Sleep Clock Configuration
96
6.4
Description
Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
76
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the device.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset 31
30
reserved
Type
Reset
29
28
27
26
VER
25
24
23
22
21
20
reserved
18
17
16
CLASS
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
MAJOR
Type
Reset
19
MINOR
Bit/Field
Name
Type
Reset
31
reserved
RO
0
30:28
VER
RO
0x1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows:
Value Description
0x1
Second version of the DID0 register format.
27:24
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:16
CLASS
RO
0x3
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all devices in a particular product line. The CLASS
field value is changed for new product lines, for changes in fab process
(for example, a remap or shrink), or any case where the MAJOR or MINOR
fields require differentiation from prior devices. The value of the CLASS
field is encoded as follows (all other encodings are reserved):
Value Description
0x3
Stellaris® DustDevil-class devices
April 08, 2008
77
Preliminary
System Control
Bit/Field
Name
Type
Reset
15:8
MAJOR
RO
-
Description
Major Revision
This field specifies the major revision number of the device. The major
revision reflects changes to base layers of the design. The major revision
number is indicated in the part number as a letter (A for first revision, B
for second, and so on). This field is encoded as follows:
Value Description
0x0
Revision A (initial device)
0x1
Revision B (first base layer revision)
0x2
Revision C (second base layer revision)
and so on.
7:0
MINOR
RO
-
Minor Revision
This field specifies the minor revision number of the device. The minor
revision reflects changes to the metal layers of the design. The MINOR
field value is reset when the MAJOR field is changed. This field is numeric
and is encoded as follows:
Value Description
0x0
Initial device, or a major revision update.
0x1
First metal layer change.
0x2
Second metal layer change.
and so on.
78
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0
1
BORIOR
R/W
0
BORIOR reserved
R/W
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
79
Preliminary
System Control
Register 3: LDO Power Control (LDOPCTL), offset 0x034
The VADJ field in this register adjusts the on-chip output voltage (VOUT).
LDO Power Control (LDOPCTL)
Base 0x400F.E000
Offset 0x034
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
VADJ
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0
5:0
VADJ
R/W
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
LDO Output Voltage
This field sets the on-chip output voltage. The programming values for
the VADJ field are provided below.
Value
VOUT (V)
0x00
2.50
0x01
2.45
0x02
2.40
0x03
2.35
0x04
2.30
0x05
2.25
0x06-0x3F Reserved
0x1B
2.75
0x1C
2.70
0x1D
2.65
0x1E
2.60
0x1F
2.55
80
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 4: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
MOSCPUPRIS USBPLLLRIS
RO
0
PLLLRIS
RO
0
RO
0
reserved
BORRIS reserved
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
MOSCPUPRIS
RO
0
MOSC Power Up Raw Interrupt Status
This bit is set when the PLL TMOSCPUP Timer asserts.
7
USBPLLLRIS
RO
0
USB PLL Lock Raw Interrupt Status
This bit is set when the USB PLL TUSBREADY Timer asserts.
6
PLLLRIS
RO
0
PLL Lock Raw Interrupt Status
This bit is set when the PLL TREADY Timer asserts.
5:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
BORRIS
RO
0
Brown-Out Reset Raw Interrupt Status
This bit is the raw interrupt status for any brown-out conditions. If set,
a brown-out condition is currently active. This is an unregistered signal
from the brown-out detection circuit. An interrupt is reported if the BORIM
bit in the IMC register is set and the BORIOR bit in the PBORCTL register
is cleared.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
81
Preliminary
System Control
Register 5: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
BORIM
reserved
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
MOSCPUPIM USBPLLLIM
R/W
0
PLLLIM
R/W
0
R/W
0
reserved
Bit/Field
Name
Type
Reset
Description
31:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
MOSCPUPIM
R/W
0
MOSC Power Up Interrupt Mask
This bit specifies whether a current limit detection is promoted to a
controller interrupt. If set, an interrupt is generated if MOSCPUPRIS in
RIS is set; otherwise, an interrupt is not generated.
7
USBPLLLIM
R/W
0
USB PLL Lock Interrupt Mask
This bit specifies whether a current limit detection is promoted to a
controller interrupt. If set, an interrupt is generated if USBPLLLRIS in
RIS is set; otherwise, an interrupt is not generated.
6
PLLLIM
R/W
0
PLL Lock Interrupt Mask
This bit specifies whether a current limit detection is promoted to a
controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS
is set; otherwise, an interrupt is not generated.
5:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
BORIM
R/W
0
Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
82
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
On a read, this register gives the current masked status value of the corresponding interrupt. All of
the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register
(see page 81).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
MOSCPUPMIS USBPLLLMIS
R/W1C
0
PLLLMIS
R/W1C
0
R/W1C
0
reserved
BORMIS reserved
R/W1C
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
MOSCPUPMIS
R/W1C
0
MOSC Power Up Masked Interrupt Status
This bit is set when the TMOSCPUP timer asserts. The interrupt is cleared
by writing a 1 to this bit.
7
USBPLLLMIS
R/W1C
0
USB PLL Lock Masked Interrupt Status
This bit is set when the USB PLL TUSBREADY timer asserts. The interrupt
is cleared by writing a 1 to this bit.
6
PLLLMIS
R/W1C
0
PLL Lock Masked Interrupt Status
This bit is set when the PLL TREADY timer asserts. The interrupt is cleared
by writing a 1 to this bit.
5:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
BORMIS
R/W1C
0
BOR Masked Interrupt Status
The BORMIS is simply the BORRIS ANDed with the mask value, BORIM.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
83
Preliminary
System Control
Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an external reset is the cause, and then
all the other bits in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
SW
WDT
BOR
POR
EXT
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
MOSCFAIL
reserved
Type
Reset
RO
0
16
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
MOSCFAIL
R/W
-
MOSC Failure Reset
When set, indicates the MOSC circuit was enable for clock validation
and failed. This generated a reset event.
15:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
SW
R/W
-
Software Reset
When set, indicates a software reset is the cause of the reset event.
3
WDT
R/W
-
Watchdog Timer Reset
When set, indicates a watchdog reset is the cause of the reset event.
2
BOR
R/W
-
Brown-Out Reset
When set, indicates a brown-out reset is the cause of the reset event.
1
POR
R/W
-
Power-On Reset
When set, indicates a power-on reset is the cause of the reset event.
0
EXT
R/W
-
External Reset
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
84
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x078E.3AD1
31
30
29
28
RO
0
RO
0
RO
0
RO
0
15
14
13
12
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
27
26
25
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
RO
0
R/W
0
R/W
1
R/W
1
R/W
1
RO
0
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
0
ACG
24
SYSDIV
PWRDN reserved BYPASS
R/W
1
RO
1
R/W
1
23
22
USESYSDIV
XTAL
Bit/Field
Name
Type
Reset
31:28
reserved
RO
0x0
27
ACG
R/W
0
R/W
0
21
20
19
reserved USEPWMDIV
OSCSRC
R/W
1
18
17
PWMDIV
reserved
RO
0
RO
0
16
reserved
IOSCDIS MOSCDIS
R/W
0
R/W
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
April 08, 2008
85
Preliminary
System Control
Bit/Field
Name
Type
Reset
26:23
SYSDIV
R/W
0xF
Description
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
Value Divisor (BYPASS=1) Frequency (BYPASS=0)
0x0
reserved
reserved
0x1
/2
reserved
0x2
/3
reserved
0x3
/4
50 MHz
0x4
/5
40 MHz
0x5
/6
33.33 MHz
0x6
/7
28.57 MHz
0x7
/8
25 MHz
0x8
/9
22.22 MHz
0x9
/10
20 MHz
0xA
/11
18.18 MHz
0xB
/12
16.67 MHz
0xC
/13
15.38 MHz
0xD
/14
14.29 MHz
0xE
/15
13.33 MHz
0xF
/16
12.5 MHz (default)
When reading the Run-Mode Clock Configuration (RCC) register (see
page 85), the SYSDIV value is MINSYSDIV if a lower divider was
requested and the PLL is being used. This lower value is allowed to
divide a non-PLL source.
22
USESYSDIV
R/W
0
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
21
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20
USEPWMDIV
R/W
0
Enable PWM Clock Divisor
Use the PWM clock divider as the source for the PWM clock.
86
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
19:17
PWMDIV
R/W
0x7
Description
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. This clock
is only power 2 divide and rising edge is synchronous without phase
shift from the system clock.
Value Divisor
0x0
/2
0x1
/4
0x2
/8
0x3
/16
0x4
/32
0x5
/64
0x6
/64
0x7
/64 (default)
16:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
PWRDN
R/W
1
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
12
reserved
RO
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
BYPASS
R/W
1
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
Note:
April 08, 2008
The ADC must be clocked from the PLL or directly from a
14-MHz to 18-MHz clock source to operate properly. While
the ADC works in a 14-18 MHz range, to maintain a 1 M
sample/second rate, the ADC must be provided a 16-MHz
clock source.
87
Preliminary
System Control
Bit/Field
Name
Type
Reset
10:6
XTAL
R/W
0xB
Description
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below.
Frequencies that may be used with the USB interface are indicated in
the table. To function within the clocking requirements of the USB
specification, a crystal of 4, 5, 6, 8, 10, 12, or 16 MHz must be used.
Value
5:4
OSCSRC
R/W
0x1
Crystal Frequency (MHz)
Not Using the PLL
Crystal Frequency (MHz)
Using the PLL
0x00
1.000
reserved
0x01
1.8432
reserved
0x02
2.000
reserved
0x03
2.4576
reserved
0x04
3.579545 MHz
0x05
3.6864 MHz
0x06
4 MHz (USB)
0x07
4.096 MHz
0x08
4.9152 MHz
0x09
5 MHz (USB)
0x0A
5.12 MHz
0x0B
6 MHz (reset value)(USB)
0x0C
6.144 MHz
0x0D
7.3728 MHz
0x0E
8 MHz (USB)
0x0F
8.192 MHz
0x10
10.0 MHz (USB)
0x11
12.0 MHz (USB)
0x12
12.288 MHz
0x13
13.56 MHz
0x14
14.31818 MHz
0x15
16.0 MHz (USB)
0x16
16.384 MHz
Oscillator Source
Picks among the four input sources for the OSC. The values are:
Value Input Source
3:2
reserved
RO
0x0
0x0
Main oscillator
0x1
Internal oscillator (default)
0x2
Internal oscillator / 4 (this is necessary if used as input to PLL)
0x3
30 KHz internal oscillator
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
1
IOSCDIS
R/W
0
Description
Internal Oscillator Disable
0: Internal oscillator (IOSC) is enabled.
1: Internal oscillator is disabled.
0
MOSCDIS
R/W
1
Main Oscillator Disable
0: Main oscillator is enabled .
1: Main oscillator is disabled (default).
April 08, 2008
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Preliminary
System Control
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 85).
The PLL frequency is calculated using the PLLCFG field values, as follows:
PLLFreq = OSCFreq * F / (R + 1)
XTAL to PLL Translation (PLLCFG)
Base 0x400F.E000
Offset 0x064
Type RO, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
-
RO
-
RO
-
RO
-
RO
-
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
F
R
Bit/Field
Name
Type
Reset
31:14
reserved
RO
0x0
13:5
F
RO
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL F Value
This field specifies the value supplied to the PLL’s F input.
4:0
R
RO
-
PLL R Value
This field specifies the value supplied to the PLL’s R input.
90
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 10: GPIO High Speed Control (GPIOHSCTL), offset 0x06C
This register provides the user the ability to change the GPIO ports to run on a single-cycle bus
equivalent to the processor clock instead of the legacy bus with two-cycle access. The address
aperture in the memory map will change for the ports that are enabled for high-speed access (see
Table 10-3 on page 257).
GPIO High Speed Control (GPIOHSCTL)
Base 0x400F.E000
Offset 0x06C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PORTHHS PORTGHS PORTFHS PORTEHS PORTDHS PORTCHS PORTBHS PORTAHS
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0
7
PORTHHS
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Port H High-Speed
When set, the memory aperture for Port H is selected to be high speed
(single-cycle). Otherwise, the legacy aperture (two-cycle) is chosen.
6
PORTGHS
R/W
0
Port G High-Speed
When set, the memory aperture for Port H is selected to be high speed
(single-cycle). Otherwise, the legacy aperture (two-cycle) is chosen.
5
PORTFHS
R/W
0
Port F High-Speed
When set, the memory aperture for Port H is selected to be high speed
(single-cycle). Otherwise, the legacy aperture (two-cycle) is chosen.
4
PORTEHS
R/W
0
Port E High-Speed
When set, the memory aperture for Port H is selected to be high speed
(single-cycle). Otherwise, the legacy aperture (two-cycle) is chosen.
3
PORTDHS
R/W
0
Port D High-Speed
When set, the memory aperture for Port H is selected to be high speed
(single-cycle). Otherwise, the legacy aperture (two-cycle) is chosen.
2
PORTCHS
R/W
0
Port C High-Speed
When set, the memory aperture for Port H is selected to be high speed
(single-cycle). Otherwise, the legacy aperture (two-cycle) is chosen.
1
PORTBHS
R/W
0
Port B High-Speed
When set, the memory aperture for Port H is selected to be high speed
(single-cycle). Otherwise, the legacy aperture (two-cycle) is chosen.
April 08, 2008
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Preliminary
System Control
Bit/Field
Name
Type
Reset
0
PORTAHS
R/W
0
Description
Port A High-Speed
When set, the memory aperture for Port H is selected to be high speed
(single-cycle). Otherwise, the legacy aperture (two-cycle) is chosen.
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April 08, 2008
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LM3S3748 Microcontroller
Register 11: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields when the USERCC2 bit is set. This allows
RCC2 to be used to extend the capabilities, while also providing a means to be backward-compatible
to previous parts. The fields within the RCC2 register occupy the same bit positions as they do
within the RCC register as LSB-justified.
The SYSDIV2 field is wider so that additional larger divisors are possible. This allows a lower system
clock frequency for improved Deep Sleep power consumption.
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.6810
31
30
USERCC2
Type
Reset
29
28
27
26
reserved
24
23
22
RO
0
RO
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
1
RO
0
15
14
13
12
11
10
9
8
7
6
RO
0
R/W
1
21
20
R/W
1
RO
0
R/W
1
reserved
RO
0
19
18
17
16
reserved
R/W
0
reserved USBPWRDN PWRDN2 reserved BYPASS2
Type
Reset
25
SYSDIV2
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RO
0
RO
0
OSCSRC2
RO
0
Bit/Field
Name
Type
Reset
Description
31
USERCC2
R/W
0
Use RCC2
R/W
0
R/W
0
reserved
R/W
1
RO
0
RO
0
When set, overrides the RCC register fields.
30:29
reserved
RO
28:23
SYSDIV2
R/W
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0F 001111 System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
This field is wider than the RCC register SYSDIV field in order to provide
additional divisor values. This permits the system clock to be run at
much lower frequencies during Deep Sleep mode. For example, where
the RCC register SYSDIV encoding of 1111 provides /16, the RCC2
register SYSDIV2 encoding of 111111 provides /64.
22:15
reserved
RO
0x0
14
USBPWRDN
R/W
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Power-Down USB PLL
When set, powers down the USB PLL.
13
PWRDN2
R/W
1
Power-Down PLL
When set, powers down the PLL.
12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
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System Control
Bit/Field
Name
Type
Reset
Description
11
BYPASS2
R/W
1
Bypass PLL
When set, bypasses the PLL for the clock source.
10:7
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:4
OSCSRC2
R/W
0x1
Oscillator Source
Picks among the input sources for the OSC. The values are:
Value Description
3:0
reserved
RO
0
0x0
Main oscillator (MOSC)
0x1
Internal oscillator (IOSC)
0x2
Internal oscillator / 4
0x3
30 kHz internal oscillator
0x7
32 kHz external oscillator
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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April 08, 2008
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LM3S3748 Microcontroller
Register 12: Main Oscillator Control (MOSCCTL), offset 0x07C
This register provides control over the features of the main oscillator, including the ability to enable
the MOSC clock validation circuit. When enabled, this circuit monitors the energy on the MOSC
pins to provide a Clock Valid signal. If the clock goes invalid after being enabled, the part does a
hardware reset and reboots to the NMI handler.
Main Oscillator Control (MOSCCTL)
Base 0x400F.E000
Offset 0x07C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0
0
CVAL
R/W
0
RO
0
CVAL
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Validation for MOSC
When set, the monitor circuit is enabled.
April 08, 2008
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Preliminary
System Control
Register 13: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31
30
29
28
27
26
reserved
Type
Reset
25
24
23
22
21
20
DSDIVORIDE
18
17
16
reserved
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
19
RO
0
DSOSCSRC
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0x0
28:23
DSDIVORIDE
R/W
0x0F
R/W
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Divider Field Override
6-bit system divider field to override when Deep-Sleep occurs with PLL
running.
22:7
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:4
DSOSCSRC
R/W
0x0
Clock Source
Specifies the clock source during Deep-Sleep mode.
Value Description
0x0
NOORIDE
No override to the oscillator clock source is done.
0x1
IOSC
Use internal 12 MHz oscillator as source.
0x3
30kHz
Use 30 kHz internal oscillator.
0x7
32kHz
Use 32 kHz external oscillator.
3:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 14: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, and package type.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset 31
30
29
28
27
26
RO
0
15
25
24
23
22
21
20
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
14
13
12
11
10
9
8
7
6
5
4
RO
0
RO
0
RO
0
RO
0
RO
0
RO
-
RO
-
RO
-
VER
Type
Reset
FAM
PINCOUNT
Type
Reset
RO
0
RO
1
18
17
16
RO
1
RO
0
RO
0
RO
1
3
2
1
0
PARTNO
reserved
RO
0
19
TEMP
Bit/Field
Name
Type
Reset
31:28
VER
RO
0x1
RO
-
PKG
ROHS
RO
-
RO
1
QUAL
RO
-
RO
-
Description
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
0x1
27:24
FAM
RO
0x0
Second version of the DID1 register format.
Family
This field provides the family identification of the device within the
Luminary Micro product portfolio. The value is encoded as follows (all
other encodings are reserved):
Value Description
0x0
23:16
PARTNO
RO
0x49
Stellaris family of microcontollers, that is, all devices with
external part numbers starting with LM3S.
Part Number
This field provides the part number of the device within the family. The
value is encoded as follows (all other encodings are reserved):
Value Description
0x49 LM3S3748
15:13
PINCOUNT
RO
0x2
Package Pin Count
This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):
Value Description
0x2
100-pin package
April 08, 2008
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Preliminary
System Control
Bit/Field
Name
Type
Reset
Description
12:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5
TEMP
RO
-
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
4:3
PKG
RO
-
0x0
Commercial temperature range (0°C to 70°C)
0x1
Industrial temperature range (-40°C to 85°C)
0x2
Extended temperature range (-40°C to 105°C)
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
Value Description
2
ROHS
RO
1
0x0
SOIC package
0x1
LQFP package
0x2
BGA package
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
1:0
QUAL
RO
-
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0
Engineering Sample (unqualified)
0x1
Pilot Production (unqualified)
0x2
Fully Qualified
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April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 15: Device Capabilities 0 (DC0), offset 0x008
This register is predefined by the part and can be used to verify features.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x00FF.003F
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
SRAMSZ
Type
Reset
FLASHSZ
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
SRAMSZ
RO
0x00FF
SRAM Size
Indicates the size of the on-chip SRAM memory.
Value
Description
0x00FF 64 KB of SRAM
15:0
FLASHSZ
RO
0x003F
Flash Size
Indicates the size of the on-chip flash memory.
Value
Description
0x003F 128 KB of Flash
April 08, 2008
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Preliminary
System Control
Register 16: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features. The PWM, SARADC0,
MAXADCSPD, WDT, SWO, SWD, and JTAG bits mask the RCGC0, SCGC0, and DCGC0 registers.
Other bits are passed as 0. MAXADCSPD is clipped to the maximum value specified in DC1.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0011.33FF
31
30
29
28
27
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
1
RO
0
26
25
24
23
22
21
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
1
10
9
8
7
6
5
4
3
2
1
0
MPU
HIB
TEMPSNS
PLL
WDT
SWO
SWD
JTAG
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
reserved
Type
Reset
MINSYSDIV
Type
Reset
reserved
RO
1
RO
0
20
19
PWM
MAXADCSPD
RO
1
RO
1
18
17
reserved
16
ADC
Bit/Field
Name
Type
Reset
Description
31:21
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20
PWM
RO
1
PWM Module Present
When set, indicates that the PWM module is present.
19:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
ADC
RO
1
ADC Module Present. When set, indicates that the ADC module is
present.
15:12
MINSYSDIV
RO
0x3
System Clock Divider. Minimum 4-bit divider value for system clock.
The reset value is hardware-dependent. See the RCC register for how
to change the system clock divisor using the SYSDIV bit.
Value Description
0x3
11:10
reserved
RO
0
9:8
MAXADCSPD
RO
0x3
Specifies a 50-MHz CPU clock with a PLL divider of 4.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Max ADC Speed. This field indicates the maximum rate at which the
ADC samples data.
Value Description
0x3
7
MPU
RO
1
1M samples/second
MPU Present. When set, indicates that the Cortex-M3 Memory Protection
Unit (MPU) module is present. See the ARM Cortex-M3 Technical
Reference Manual for details on the MPU.
100
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
Description
6
HIB
RO
1
Hibernation Module Present. When set, indicates that the Hibernation
module is present.
5
TEMPSNS
RO
1
Temp Sensor Present. When set, indicates that the on-chip temperature
sensor is present.
4
PLL
RO
1
PLL Present. When set, indicates that the on-chip Phase Locked Loop
(PLL) is present.
3
WDT
RO
1
Watchdog Timer Present. When set, indicates that a watchdog timer is
present.
2
SWO
RO
1
SWO Trace Port Present. When set, indicates that the Serial Wire Output
(SWO) trace port is present.
1
SWD
RO
1
SWD Present. When set, indicates that the Serial Wire Debugger (SWD)
is present.
0
JTAG
RO
1
JTAG Present. When set, indicates that the JTAG debugger interface
is present.
April 08, 2008
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Preliminary
System Control
Register 17: Device Capabilities 2 (DC2), offset 0x014
This register is predefined by the part and can be used to verify features.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x030F.5133
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
RO
0
I2C1
reserved
I2C0
RO
1
RO
0
RO
1
reserved
Type
Reset
Type
Reset
25
24
COMP1
COMP0
RO
1
9
reserved
RO
0
RO
0
23
22
RO
1
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
SSI1
SSI0
RO
1
RO
1
QEI0
RO
0
RO
1
21
20
reserved
reserved
RO
0
RO
0
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
RO
1
RO
1
RO
1
RO
1
3
2
1
0
UART1
UART0
RO
1
RO
1
reserved
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
COMP1
RO
1
Analog Comparator 1 Present. When set, indicates that analog
comparator 1 is present.
24
COMP0
RO
1
Analog Comparator 0 Present. When set, indicates that analog
comparator 0 is present.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
RO
1
Timer 3 Present. When set, indicates that General-Purpose Timer
module 3 is present.
18
TIMER2
RO
1
Timer 2 Present. When set, indicates that General-Purpose Timer
module 2 is present.
17
TIMER1
RO
1
Timer 1 Present. When set, indicates that General-Purpose Timer
module 1 is present.
16
TIMER0
RO
1
Timer 0 Present. When set, indicates that General-Purpose Timer
module 0 is present.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
RO
1
I2C Module 1 Present. When set, indicates that I2C module 1 is present.
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
RO
1
I2C Module 0 Present. When set, indicates that I2C module 0 is present.
11:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
102
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
Description
8
QEI0
RO
1
QEI0 Present. When set, indicates that QEI module 0 is present.
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
RO
1
SSI1 Present. When set, indicates that SSI module 1 is present.
4
SSI0
RO
1
SSI0 Present. When set, indicates that SSI module 0 is present.
3:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
UART1
RO
1
UART1 Present. When set, indicates that UART module 1 is present.
0
UART0
RO
1
UART0 Present. When set, indicates that UART module 0 is present.
April 08, 2008
103
Preliminary
System Control
Register 18: Device Capabilities 3 (DC3), offset 0x018
This register is predefined by the part and can be used to verify features.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0xBFFF.86FF
Type
Reset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
32KHZ
reserved
CCP5
CCP4
CCP3
CCP2
CCP1
CCP0
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
RO
1
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
PWMFAULT
Type
Reset
RO
1
reserved
RO
0
C1PLUS C1MINUS reserved C0PLUS C0MINUS
RO
0
RO
1
RO
1
RO
0
RO
1
RO
1
Bit/Field
Name
Type
Reset
Description
31
32KHZ
RO
1
32KHz Pin Present. When set, indicates that the 32KHz pin is present.
30
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29
CCP5
RO
1
CCP5 Pin Present. When set, indicates that Capture/Compare/PWM
pin 5 is present.
28
CCP4
RO
1
CCP4 Pin Present. When set, indicates that Capture/Compare/PWM
pin 4 is present.
27
CCP3
RO
1
CCP3 Pin Present. When set, indicates that Capture/Compare/PWM
pin 3 is present.
26
CCP2
RO
1
CCP2 Pin Present. When set, indicates that Capture/Compare/PWM
pin 2 is present.
25
CCP1
RO
1
CCP1 Pin Present. When set, indicates that Capture/Compare/PWM
pin 1 is present.
24
CCP0
RO
1
CCP0 Pin Present. When set, indicates that Capture/Compare/PWM
pin 0 is present.
23
ADC7
RO
1
ADC7 Pin Present. When set, indicates that ADC pin 7 is present.
22
ADC6
RO
1
ADC6 Pin Present. When set, indicates that ADC pin 6 is present.
21
ADC5
RO
1
ADC5 Pin Present. When set, indicates that ADC pin 5 is present.
20
ADC4
RO
1
ADC4 Pin Present. When set, indicates that ADC pin 4 is present.
19
ADC3
RO
1
ADC3 Pin Present. When set, indicates that ADC pin 3 is present.
18
ADC2
RO
1
ADC2 Pin Present. When set, indicates that ADC pin 2 is present.
17
ADC1
RO
1
ADC1 Pin Present. When set, indicates that ADC pin 1 is present.
16
ADC0
RO
1
ADC0 Pin Present. When set, indicates that ADC pin 0 is present.
104
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
Description
15
PWMFAULT
RO
1
PWM Fault Pin Present. When set, indicates that a PWM Fault pin is
present. See DC5 for specific Fault pins on this device.
14:11
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
C1PLUS
RO
1
C1+ Pin Present. When set, indicates that the analog comparator 1 (+)
input pin is present.
9
C1MINUS
RO
1
C1- Pin Present. When set, indicates that the analog comparator 1 (-)
input pin is present.
8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
C0PLUS
RO
1
C0+ Pin Present. When set, indicates that the analog comparator 0 (+)
input pin is present.
6
C0MINUS
RO
1
C0- Pin Present. When set, indicates that the analog comparator 0 (-)
input pin is present.
5
PWM5
RO
1
PWM5 Pin Present. When set, indicates that the PWM pin 5 is present.
4
PWM4
RO
1
PWM4 Pin Present. When set, indicates that the PWM pin 4 is present.
3
PWM3
RO
1
PWM3 Pin Present. When set, indicates that the PWM pin 3 is present.
2
PWM2
RO
1
PWM2 Pin Present. When set, indicates that the PWM pin 2 is present.
1
PWM1
RO
1
PWM1 Pin Present. When set, indicates that the PWM pin 1 is present.
0
PWM0
RO
1
PWM0 Pin Present. When set, indicates that the PWM pin 0 is present.
April 08, 2008
105
Preliminary
System Control
Register 19: Device Capabilities 4 (DC4), offset 0x01C
This register is predefined by the part and can be used to verify features.
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x0000.F0FF
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
CCP7
CCP6
UDMA
ROM
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
reserved
Type
Reset
Type
Reset
reserved
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15
CCP7
RO
1
CCP7 Pin Present. When set, indicates that Capture/Compare/PWM
pin 7 is present.
14
CCP6
RO
1
CCP6 Pin Present. When set, indicates that Capture/Compare/PWM
pin 6 is present.
13
UDMA
RO
1
Micro-DMA is present
12
ROM
RO
1
Internal Code ROM is present
11:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
GPIOH
RO
1
GPIO Port H Present. When set, indicates that GPIO Port H is present.
6
GPIOG
RO
1
GPIO Port G Present. When set, indicates that GPIO Port G is present.
5
GPIOF
RO
1
GPIO Port F Present. When set, indicates that GPIO Port F is present.
4
GPIOE
RO
1
GPIO Port E Present. When set, indicates that GPIO Port E is present.
3
GPIOD
RO
1
GPIO Port D Present. When set, indicates that GPIO Port D is present.
2
GPIOC
RO
1
GPIO Port C Present. When set, indicates that GPIO Port C is present.
1
GPIOB
RO
1
GPIO Port B Present. When set, indicates that GPIO Port B is present.
0
GPIOA
RO
1
GPIO Port A Present. When set, indicates that GPIO Port A is present.
106
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 20: Device Capabilities 5 (DC5), offset 0x020
This register is predefined by the part and can be used to verify features.
Device Capabilities 5 (DC5)
Base 0x400F.E000
Offset 0x020
Type RO, reset 0x0F30.00FF
31
30
29
28
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
1
15
14
13
12
11
10
9
8
7
6
PWM7
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
27
26
25
24
RO
0
22
19
18
RO
1
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
reserved
PWMFAULT3 PWMFAULT2 PWMFAULT1 PWMFAULT0
reserved
Type
Reset
23
21
20
PWMEFLT PWMESYNC
17
16
reserved
Bit/Field
Name
Type
Reset
Description
31:28
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27
PWMFAULT3
RO
1
PWM Fault 3 Pin Present. When set, indicates that the PWM Fault 3
pin is present.
26
PWMFAULT2
RO
1
PWM Fault 2 Pin Present. When set, indicates that the PWM Fault 2
pin is present.
25
PWMFAULT1
RO
1
PWM Fault 1 Pin Present. When set, indicates that the PWM Fault 1
pin is present.
24
PWMFAULT0
RO
1
PWM Fault 0 Pin Present. When set, indicates that the PWM Fault 0
pin is present.
23:22
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
21
PWMEFLT
RO
1
PWM Extended Fault feature is active
20
PWMESYNC
RO
1
PWM Extended SYNC feature is active
19:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
PWM7
RO
1
PWM7 Pin Present. When set, indicates that the PWM pin 7 is present.
6
PWM6
RO
1
PWM6 Pin Present. When set, indicates that the PWM pin 6 is present.
5
PWM5
RO
1
PWM5 Pin Present. When set, indicates that the PWM pin 5 is present.
4
PWM4
RO
1
PWM4 Pin Present. When set, indicates that the PWM pin 4 is present.
3
PWM3
RO
1
PWM3 Pin Present. When set, indicates that the PWM pin 3 is present.
2
PWM2
RO
1
PWM2 Pin Present. When set, indicates that the PWM pin 2 is present.
1
PWM1
RO
1
PWM1 Pin Present. When set, indicates that the PWM pin 1 is present.
April 08, 2008
107
Preliminary
System Control
Bit/Field
Name
Type
Reset
0
PWM0
RO
1
Description
PWM0 Pin Present. When set, indicates that the PWM pin 0 is present.
108
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 21: Device Capabilities 6 (DC6), offset 0x024
This register is predefined by the part and can be used to verify features.
Device Capabilities 6 (DC6)
Base 0x400F.E000
Offset 0x024
Type RO, reset 0x0000.0002
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0
1:0
USB0
RO
0x2
USB0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
This specifies that USB0 is present and its capability
Value Description
0x2
USB is Device or Host.
April 08, 2008
109
Preliminary
System Control
Register 22: Device Capabilities 7 (DC7), offset 0x028
This register is predefined by the part and can be used to verify uDMA channel features.
Device Capabilities 7 (DC7)
Base 0x400F.E000
Offset 0x028
Type RO, reset 0x03C0.0F3F
31
30
29
RO
0
RO
0
RO
0
15
14
13
RO
0
RO
0
28
27
26
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
12
11
10
9
8
7
reserved
Type
Reset
reserved
Type
Reset
25
24
23
RO
0
21
20
19
RO
1
RO
0
RO
0
RO
0
6
5
4
3
SSI1_TX SSI1_RX UART1_TX UART1_RX
SSI0_TX SSI0_RX UART0_TX UART0_RX
RO
0
22
RO
1
RO
1
RO
1
RO
1
reserved
RO
0
RO
0
18
17
16
RO
0
RO
0
RO
0
2
1
0
reserved
USB_EP3_TX USB_EP3_RX USB_EP2_TX USB_EP2_RX USB_EP1_TX USB_EP1_RX
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
Description
31:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
SSI1_TX
RO
1
SSI1 TX on uDMA Ch25. When set, indicates uDMA channel 25 is
available and connected to the transmit path of SSI module 1.
24
SSI1_RX
RO
1
SSI1 RX on uDMA Ch24. When set, indicates uDMA channel 24 is
available and connected to the receive path of SSI module 1.
23
UART1_TX
RO
1
UART1 TX on uDMA Ch23. When set, indicates uDMA channel 23 is
available and connected to the transmit path of UART module 1.
22
UART1_RX
RO
1
UART1 RX on uDMA Ch22. When set, indicates uDMA channel 22 is
available and connected to the receive path of UART module 1.
21:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
SSI0_TX
RO
1
SSI0 TX on uDMA Ch11. When set, indicates uDMA channel 11 is
available and connected to the transmit path of SSI module 0.
10
SSI0_RX
RO
1
SSI0 RX on uDMA Ch10. When set, indicates uDMA channel 10 is
available and connected to the receive path of SSI module 0.
9
UART0_TX
RO
1
UART0 TX on uDMA Ch9. When set, indicates uDMA channel 9 is
available and connected to the transmit path of UART module 0.
8
UART0_RX
RO
1
UART0 RX on uDMA Ch8. When set, indicates uDMA channel 8 is
available and connected to the receive path of UART module 0.
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
USB_EP3_TX
RO
1
USB EP3 TX on uDMA Ch5. When set, indicates uDMA channel 5 is
available and connected to the transmit path of USB endpoint 3.
4
USB_EP3_RX
RO
1
USB EP3 RX on uDMA Ch4. When set, indicates uDMA channel 4 is
available and connected to the receive path of USB endpoint 2.
110
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
Description
3
USB_EP2_TX
RO
1
USB EP2 TX on uDMA Ch3. When set, indicates uDMA channel 3 is
available and connected to the transmit path of USB endpoint 2.
2
USB_EP2_RX
RO
1
USB EP2 RX on uDMA Ch2. When set, indicates uDMA channel 1 is
available and connected to the receive path of USB endpoint 2.
1
USB_EP1_TX
RO
1
USB EP1 TX on uDMA Ch1. When set, indicates uDMA channel 1 is
available and connected to the transmit path of USB endpoint 1.
0
USB_EP1_RX
RO
1
USB EP1 RX on uDMA Ch0. When set, indicates uDMA channel 0 is
available and connected to the receive path of USB endpoint 1.
April 08, 2008
111
Preliminary
System Control
Register 23: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
Type R/W, reset 0x00000040
31
30
29
28
27
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
26
25
24
23
22
21
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
20
19
PWM
MAXADCSPD
R/W
0
reserved
HIB
RO
0
R/W
0
reserved
RO
0
RO
0
18
17
reserved
WDT
R/W
0
16
ADC
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:21
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20
PWM
R/W
0
PWM Clock Gating Control. This bit controls the clock gating for the
PWM module. If set, the unit receives a clock and functions. Otherwise,
the unit is unclocked and disabled. If the unit is unclocked, a read or
write to the unit generates a bus fault.
19:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
ADC
R/W
0
ADC0 Clock Gating Control. This bit controls the clock gating for SAR
ADC module 0. If set, the unit receives a clock and functions. Otherwise,
the unit is unclocked and disabled. If the unit is unclocked, a read or
write to the unit generates a bus fault.
15:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
112
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LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
9:8
MAXADCSPD
R/W
0
Description
ADC Sample Speed. This field sets the rate at which the ADC samples
data. You cannot set the rate higher than the maximum rate. You can
set the sample rate by setting the MAXADCSPD bit as follows:
Value Description
0x3
1M samples/second
0x2
500K samples/second
0x1
250K samples/second
0x0
125K samples/second
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
HIB
R/W
0
HIB Clock Gating Control. This bit controls the clock gating for the
Hibernation module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT
R/W
0
WDT Clock Gating Control. This bit controls the clock gating for the
WDT module. If set, the unit receives a clock and functions. Otherwise,
the unit is unclocked and disabled. If the unit is unclocked, a read or
write to the unit generates a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
113
Preliminary
System Control
Register 24: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31
30
29
28
27
26
25
24
23
22
21
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
MAXADCSPD
RO
0
RO
0
20
19
PWM
R/W
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
5
4
7
6
reserved
HIB
RO
0
R/W
0
reserved
RO
0
RO
0
18
17
reserved
RO
0
RO
0
3
2
WDT
R/W
0
16
ADC
RO
0
R/W
0
1
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:21
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20
PWM
R/W
0
PWM Clock Gating Control. This bit controls the clock gating for the
PWM module. If set, the unit receives a clock and functions. Otherwise,
the unit is unclocked and disabled. If the unit is unclocked, a read or
write to the unit generates a bus fault.
19:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
ADC
R/W
0
ADC0 Clock Gating Control. This bit controls the clock gating for general
SAR ADC module 0. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled. If the unit is unclocked,
a read or write to the unit generates a bus fault.
15:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
9:8
MAXADCSPD
R/W
0
Description
ADC Sample Speed. This field sets the rate at which the ADC samples
data. You cannot set the rate higher than the maximum rate.You can
set the sample rate by setting the MAXADCSPD bit as follows:
Value Description
0x3
1M samples/second
0x2
500K samples/second
0x1
250K samples/second
0x0
125K samples/second
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
HIB
R/W
0
HIB Clock Gating Control. This bit controls the clock gating for the
Hibernation module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT
R/W
0
WDT Clock Gating Control. This bit controls the clock gating for the
WDT module. If set, the unit receives a clock and functions. Otherwise,
the unit is unclocked and disabled. If the unit is unclocked, a read or
write to the unit generates a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
115
Preliminary
System Control
Register 25: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
31
30
29
28
27
26
25
24
23
22
21
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
MAXADCSPD
RO
0
RO
0
20
19
PWM
R/W
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
5
4
7
6
reserved
HIB
RO
0
R/W
0
reserved
RO
0
RO
0
18
17
reserved
RO
0
RO
0
3
2
WDT
R/W
0
16
ADC
RO
0
R/W
0
1
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:21
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20
PWM
R/W
0
PWM Clock Gating Control. This bit controls the clock gating for the
PWM module. If set, the unit receives a clock and functions. Otherwise,
the unit is unclocked and disabled. If the unit is unclocked, a read or
write to the unit generates a bus fault.
19:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
ADC
R/W
0
ADC0 Clock Gating Control. This bit controls the clock gating for general
SAR ADC module 0. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled. If the unit is unclocked,
a read or write to the unit generates a bus fault.
15:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
9:8
MAXADCSPD
R/W
0
Description
ADC Sample Speed. This field sets the rate at which the ADC samples
data. You cannot set the rate higher than the maximum rate. You can
set the sample rate by setting the MAXADCSPD bit as follows:
Value Description
0x3
1M samples/second
0x2
500K samples/second
0x1
250K samples/second
0x0
125K samples/second
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
HIB
R/W
0
HIB Clock Gating Control. This bit controls the clock gating for the
Hibernation module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT
R/W
0
WDT Clock Gating Control. This bit controls the clock gating for the
WDT module. If set, the unit receives a clock and functions. Otherwise,
the unit is unclocked and disabled. If the unit is unclocked, a read or
write to the unit generates a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
117
Preliminary
System Control
Register 26: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type R/W, reset 0x00000000
31
30
29
RO
0
RO
0
RO
0
15
14
reserved
RO
0
28
27
26
RO
0
RO
0
RO
0
13
12
11
10
I2C1
reserved
I2C0
R/W
0
RO
0
R/W
0
reserved
Type
Reset
Type
Reset
25
24
COMP1
COMP0
R/W
0
9
reserved
RO
0
RO
0
23
22
R/W
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
SSI1
SSI0
R/W
0
R/W
0
QEI0
RO
0
R/W
0
21
20
reserved
reserved
RO
0
RO
0
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
UART1
UART0
R/W
0
R/W
0
reserved
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
COMP1
R/W
0
Analog Comparator 1 Clock Gating. This bit controls the clock gating
for analog comparator 1. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled. If the unit is unclocked,
reads or writes to the unit will generate a bus fault.
24
COMP0
R/W
0
Analog Comparator 0 Clock Gating. This bit controls the clock gating
for analog comparator 0. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled. If the unit is unclocked,
reads or writes to the unit will generate a bus fault.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 3. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
18
TIMER2
R/W
0
Timer 2 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 2. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
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LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
Description
17
TIMER1
R/W
0
Timer 1 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 1. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
16
TIMER0
R/W
0
Timer 0 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 0. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
R/W
0
I2C1 Clock Gating Control. This bit controls the clock gating for I2C
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control. This bit controls the clock gating for I2C
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
11:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
QEI0
R/W
0
QEI0 Clock Gating Control. This bit controls the clock gating for QEI
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Clock Gating Control. This bit controls the clock gating for SSI
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
4
SSI0
R/W
0
SSI0 Clock Gating Control. This bit controls the clock gating for SSI
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
3:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
UART1
R/W
0
UART1 Clock Gating Control. This bit controls the clock gating for UART
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
April 08, 2008
119
Preliminary
System Control
Bit/Field
Name
Type
Reset
0
UART0
R/W
0
Description
UART0 Clock Gating Control. This bit controls the clock gating for UART
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
120
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Preliminary
LM3S3748 Microcontroller
Register 27: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
COMP1
COMP0
RO
0
R/W
0
R/W
0
RO
0
RO
0
10
9
8
7
6
reserved
Type
Reset
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
11
15
14
13
12
reserved
I2C1
reserved
I2C0
RO
0
R/W
0
RO
0
R/W
0
reserved
RO
0
RO
0
QEI0
RO
0
R/W
0
23
22
21
20
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
reserved
reserved
RO
0
RO
0
RO
0
5
4
SSI1
SSI0
R/W
0
R/W
0
reserved
RO
0
RO
0
1
0
UART1
UART0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
COMP1
R/W
0
Analog Comparator 1 Clock Gating. This bit controls the clock gating
for analog comparator 1. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled. If the unit is unclocked,
reads or writes to the unit will generate a bus fault.
24
COMP0
R/W
0
Analog Comparator 0 Clock Gating. This bit controls the clock gating
for analog comparator 0. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled. If the unit is unclocked,
reads or writes to the unit will generate a bus fault.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 3. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
18
TIMER2
R/W
0
Timer 2 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 2. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
April 08, 2008
121
Preliminary
System Control
Bit/Field
Name
Type
Reset
Description
17
TIMER1
R/W
0
Timer 1 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 1. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
16
TIMER0
R/W
0
Timer 0 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 0. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
R/W
0
I2C1 Clock Gating Control. This bit controls the clock gating for I2C
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control. This bit controls the clock gating for I2C
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
11:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
QEI0
R/W
0
QEI0 Clock Gating Control. This bit controls the clock gating for QEI
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Clock Gating Control. This bit controls the clock gating for SSI
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
4
SSI0
R/W
0
SSI0 Clock Gating Control. This bit controls the clock gating for SSI
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
3:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
UART1
R/W
0
UART1 Clock Gating Control. This bit controls the clock gating for UART
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
122
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
0
UART0
R/W
0
Description
UART0 Clock Gating Control. This bit controls the clock gating for UART
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
April 08, 2008
123
Preliminary
System Control
Register 28: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
COMP1
COMP0
RO
0
R/W
0
R/W
0
RO
0
RO
0
10
9
8
7
6
reserved
Type
Reset
RO
0
Type
Reset
RO
0
RO
0
RO
0
RO
0
11
15
14
13
12
reserved
I2C1
reserved
I2C0
RO
0
R/W
0
RO
0
R/W
0
reserved
RO
0
RO
0
QEI0
RO
0
R/W
0
23
22
21
20
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
reserved
reserved
RO
0
RO
0
RO
0
5
4
SSI1
SSI0
R/W
0
R/W
0
reserved
RO
0
RO
0
1
0
UART1
UART0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
COMP1
R/W
0
Analog Comparator 1 Clock Gating. This bit controls the clock gating
for analog comparator 1. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled. If the unit is unclocked,
reads or writes to the unit will generate a bus fault.
24
COMP0
R/W
0
Analog Comparator 0 Clock Gating. This bit controls the clock gating
for analog comparator 0. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled. If the unit is unclocked,
reads or writes to the unit will generate a bus fault.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 3. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
18
TIMER2
R/W
0
Timer 2 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 2. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
124
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
Description
17
TIMER1
R/W
0
Timer 1 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 1. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
16
TIMER0
R/W
0
Timer 0 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 0. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
R/W
0
I2C1 Clock Gating Control. This bit controls the clock gating for I2C
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control. This bit controls the clock gating for I2C
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
11:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
QEI0
R/W
0
QEI0 Clock Gating Control. This bit controls the clock gating for QEI
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Clock Gating Control. This bit controls the clock gating for SSI
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
4
SSI0
R/W
0
SSI0 Clock Gating Control. This bit controls the clock gating for SSI
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
3:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
UART1
R/W
0
UART1 Clock Gating Control. This bit controls the clock gating for UART
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
April 08, 2008
125
Preliminary
System Control
Bit/Field
Name
Type
Reset
0
UART0
R/W
0
Description
UART0 Clock Gating Control. This bit controls the clock gating for UART
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
126
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 29: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
UDMA
R/W
0
reserved
RO
0
16
USB0
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
USB0
R/W
0
USB0 Clock Gating Control. This bit controls the clock gating for Port
H. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
15:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
UDMA
R/W
0
UDMA Clock Gating Control. This bit controls the clock gating for Port
H. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
12:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
GPIOH
R/W
0
Port H Clock Gating Control. This bit controls the clock gating for Port
H. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
April 08, 2008
127
Preliminary
System Control
Bit/Field
Name
Type
Reset
Description
6
GPIOG
R/W
0
Port G Clock Gating Control. This bit controls the clock gating for Port
G. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
5
GPIOF
R/W
0
Port F Clock Gating Control. This bit controls the clock gating for Port
F. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
4
GPIOE
R/W
0
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
3
GPIOD
R/W
0
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
2
GPIOC
R/W
0
Port C Clock Gating Control. This bit controls the clock gating for Port
C. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
1
GPIOB
R/W
0
Port B Clock Gating Control. This bit controls the clock gating for Port
B. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0
GPIOA
R/W
0
Port A Clock Gating Control. This bit controls the clock gating for Port
A. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
128
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 30: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 2 (SCGC2)
Base 0x400F.E000
Offset 0x118
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
reserved
Type
Reset
RO
0
RO
0
15
14
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
13
12
11
UDMA
R/W
0
RO
0
RO
0
RO
0
10
9
8
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
16
USB0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
7
6
5
4
3
2
1
0
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
USB0
R/W
0
USB0 Clock Gating Control. This bit controls the clock gating for Port
H. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
15:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
UDMA
R/W
0
UDMA Clock Gating Control. This bit controls the clock gating for Port
H. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
12:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
GPIOH
R/W
0
Port H Clock Gating Control. This bit controls the clock gating for Port
H. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
April 08, 2008
129
Preliminary
System Control
Bit/Field
Name
Type
Reset
Description
6
GPIOG
R/W
0
Port G Clock Gating Control. This bit controls the clock gating for Port
G. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
5
GPIOF
R/W
0
Port F Clock Gating Control. This bit controls the clock gating for Port
F. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
4
GPIOE
R/W
0
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
3
GPIOD
R/W
0
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
2
GPIOC
R/W
0
Port C Clock Gating Control. This bit controls the clock gating for Port
C. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
1
GPIOB
R/W
0
Port B Clock Gating Control. This bit controls the clock gating for Port
B. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0
GPIOA
R/W
0
Port A Clock Gating Control. This bit controls the clock gating for Port
A. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
130
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 31: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
reserved
Type
Reset
RO
0
RO
0
15
14
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
13
12
11
UDMA
R/W
0
RO
0
RO
0
RO
0
10
9
8
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
16
USB0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
7
6
5
4
3
2
1
0
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
USB0
R/W
0
USB0 Clock Gating Control. This bit controls the clock gating for Port
H. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
15:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
UDMA
R/W
0
UDMA Clock Gating Control. This bit controls the clock gating for Port
H. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
12:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
GPIOH
R/W
0
Port H Clock Gating Control. This bit controls the clock gating for Port
H. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
April 08, 2008
131
Preliminary
System Control
Bit/Field
Name
Type
Reset
Description
6
GPIOG
R/W
0
Port G Clock Gating Control. This bit controls the clock gating for Port
G. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
5
GPIOF
R/W
0
Port F Clock Gating Control. This bit controls the clock gating for Port
F. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
4
GPIOE
R/W
0
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
3
GPIOD
R/W
0
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
2
GPIOC
R/W
0
Port C Clock Gating Control. This bit controls the clock gating for Port
C. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
1
GPIOB
R/W
0
Port B Clock Gating Control. This bit controls the clock gating for Port
B. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0
GPIOA
R/W
0
Port A Clock Gating Control. This bit controls the clock gating for Port
A. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
132
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 32: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31
30
29
28
27
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
26
25
24
23
22
21
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
R/W
0
reserved
Type
Reset
RO
0
19
PWM
reserved
Type
Reset
20
HIB
reserved
RO
0
RO
0
18
17
reserved
WDT
R/W
0
16
ADC
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:21
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20
PWM
R/W
0
PWM Reset Control. Reset control for PWM module.
19:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
ADC
R/W
0
ADC0 Reset Control. Reset control for SAR ADC module 0.
15:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
HIB
R/W
0
HIB Reset Control. Reset control for the Hibernation module.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT
R/W
0
WDT Reset Control. Reset control for Watchdog unit.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 33: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
RO
0
I2C1
reserved
I2C0
R/W
0
RO
0
R/W
0
reserved
Type
Reset
Type
Reset
25
24
COMP1
COMP0
R/W
0
9
reserved
RO
0
RO
0
23
22
R/W
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
SSI1
SSI0
R/W
0
R/W
0
QEI0
RO
0
R/W
0
21
20
reserved
reserved
RO
0
RO
0
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
UART1
UART0
R/W
0
R/W
0
reserved
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
COMP1
R/W
0
Analog Comp 1 Reset Control. Reset control for analog comparator 1.
24
COMP0
R/W
0
Analog Comp 0 Reset Control. Reset control for analog comparator 0.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Reset Control. Reset control for General-Purpose Timer module
3.
18
TIMER2
R/W
0
Timer 2 Reset Control. Reset control for General-Purpose Timer module
2.
17
TIMER1
R/W
0
Timer 1 Reset Control. Reset control for General-Purpose Timer module
1.
16
TIMER0
R/W
0
Timer 0 Reset Control. Reset control for General-Purpose Timer module
0.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
R/W
0
I2C1 Reset Control. Reset control for I2C unit 1.
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Reset Control. Reset control for I2C unit 0.
11:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
QEI0
R/W
0
QEI0 Reset Control. Reset control for QEI unit 0.
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Bit/Field
Name
Type
Reset
Description
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Reset Control. Reset control for SSI unit 1.
4
SSI0
R/W
0
SSI0 Reset Control. Reset control for SSI unit 0.
3:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
UART1
R/W
0
UART1 Reset Control. Reset control for UART unit 1.
0
UART0
R/W
0
UART0 Reset Control. Reset control for UART unit 0.
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Register 34: Software Reset Control 2 (SRCR2), offset 0x048
Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
UDMA
R/W
0
reserved
RO
0
16
USB0
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
USB0
R/W
0
USB0 Reset Control. Reset control for USB unit 0.
15:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
UDMA
R/W
0
UDMA Reset Control. Reset control for uDMA unit.
12:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
GPIOH
R/W
0
Port H Reset Control. Reset control for GPIO Port H.
6
GPIOG
R/W
0
Port G Reset Control. Reset control for GPIO Port G.
5
GPIOF
R/W
0
Port F Reset Control. Reset control for GPIO Port F.
4
GPIOE
R/W
0
Port E Reset Control. Reset control for GPIO Port E.
3
GPIOD
R/W
0
Port D Reset Control. Reset control for GPIO Port D.
2
GPIOC
R/W
0
Port C Reset Control. Reset control for GPIO Port C.
1
GPIOB
R/W
0
Port B Reset Control. Reset control for GPIO Port B.
0
GPIOA
R/W
0
Port A Reset Control. Reset control for GPIO Port A.
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7
Hibernation Module
The Hibernation Module manages removal and restoration of power to the rest of the microcontroller
to provide a means for reducing power consumption. When the processor and peripherals are idle,
power can be completely removed with only the Hibernation Module remaining powered. Power
can be restored based on an external signal, or at a certain time using the built-in real-time clock
(RTC). The Hibernation module can be independently supplied from a battery or an auxiliary power
supply.
The Hibernation module has the following features:
■ Power-switching logic to discrete external regulator
■ Dedicated pin for waking from an external signal
■ Low-battery detection, signaling, and interrupt generation
■ 32-bit real-time counter (RTC)
■ Two 32-bit RTC match registers for timed wake-up and interrupt generation
■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal
■ RTC predivider trim for making fine adjustments to the clock rate
■ 64 32-bit words of non-volatile memory
■ Programmable interrupts for RTC match, external wake, and low battery events
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Hibernation Module
7.1
Block Diagram
Figure 7-1. Hibernation Module Block Diagram
HIBCTL.CLK32EN
XOSC0
XOSC1
Interrupts
HIBIM
HIBRIS
HIBMIS
HIBIC
Pre-Divider
/128
HIBRTCT
HIBCTL.CLKSEL
Non-Volatile
Memory
HIBDATA
RTC
HIBRTCC
HIBRTCLD
HIBRTCM0
HIBRTCM1
WAKE
MATCH0/1
LOWBAT
VDD
Low Battery
Detect
VBAT
HIBCTL.LOWBATEN
7.2
Interrupts
to CPU
Power
Sequence
Logic
HIB
HIBCTL.PWRCUT
HIBCTL.RTCWEN
HIBCTL.EXTWEN
HIBCTL.VABORT
Functional Description
The Hibernation module controls the power to the processor with an enable signal (HIB) that signals
an external voltage regulator to turn off. The Hibernation module power is determined dynamically.
The supply voltage of the Hibernation module is the larger of the main voltage source (VDD) or the
battery/auxilliary voltage source (VBAT). A voting circuit indicates the larger and an internal power
switch selects the appropriate voltage source. The Hibernation module also has a separate clock
source to maintain a real-time clock (RTC). Once in hibernation, the module signals an external
voltage regulator to turn back on the power when an external pin (WAKE) is asserted, or when the
internal RTC reaches a certain value. The Hibernation module can also detect when the battery
voltage is low, and optionally prevent hibernation when this occurs.
Power-up from a power cut to code execution is defined as the regulator turn-on time (specified at
tHIB_TO_VDD maximum) plus the normal chip POR (see “Hibernation Module” on page 697).
7.2.1
Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is tHIB_REG_WRITE, therefore software
must guarantee that a delay of tHIB_REG_WRITE is inserted between back-to-back writes to certain
Hibernation registers, or between a write followed by a read to those same registers. There is no
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April 08, 2008
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LM3S3748 Microcontroller
restriction on timing for back-to-back reads from the Hibernation module. Software may make use
of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. This bit is
cleared on a write operation and set once the write completes, indicating to software that another
write or read may be started safely. Software should poll HIBCTL for WRC=1 prior to accessing any
affected register. The following registers are subject to this timing restriction:
■ Hibernation RTC Counter (HIBRTCC)
■ Hibernation RTC Match 0 (HIBRTCM0)
■ Hibernation RTC Match 1 (HIBRTCM1)
■ Hibernation RTC Load (HIBRTCLD)
■ Hibernation RTC Trim (HIBRTCT)
■ Hibernation Data (HIBDATA)
7.2.2
Clock Source
The Hibernation module must be clocked by an external source, even if the RTC feature will not be
used. An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz
crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to
produce the 32.768-kHz clock reference. To use a more precise clock source, a 32.768-kHz oscillator
can be connected to the XOSC0 pin. See Figure 7-2 on page 140 and Figure 7-3 on page 141. Note
that these diagrams only show the connection to the Hibernation pins and not to the full system.
See “Hibernation Module” on page 697 for specific values.
The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock
source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a
32.768-kHz clock source. If the bit is set to 0, the input clock is divided by 128, resulting in a
32.768-kHz clock source. If a crystal is used for the clock source, the software must leave a delay
of tXOSC_SETTLE after setting the CLK32EN bit and before any other accesses to the Hibernation
module registers. The delay allows the crystal to power up and stabilize. If an oscillator is used for
the clock source, no delay is needed.
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Hibernation Module
Figure 7-2. Clock Source Using Crystal
Stellaris Microcontroller
Regulator
or Switch
Input
Voltage
IN
OUT
VDD
EN
XOSC0
X1
RL
XOSC1
C1
C2
HIB
WAKE
RPU
Note:
Open drain
external wake
up circuit
VBAT
GND
3V
Battery
RTERM = Optional series termination resistor.
RPU = Pull-up resistor (1 M½).
See “Hibernation Module” on page 697 for specific parameter values.
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LM3S3748 Microcontroller
Figure 7-3. Clock Source Using Dedicated Oscillator
Stellaris Microcontroller
Regulator
or Switch
Input
Voltage
IN
OUT
EN
VDD
Clock
Source
RTerm
XOSC0
(fEXT_OSC)
N.C.
XOSC1
HIB
WAKE
RPU
Note:
Open drain
external wake
up circuit
VBAT
GND
3V
Battery
X1 = Crystal frequency is fXOSC_XTAL.
RL = Load resistor is RXOSC_LOAD.
C1,2 = Capacitor value derived from crystal vendor load capacitance specifications.
RPU = Pull-up resistor (1 M½).
See “Hibernation Module” on page 697 for specific parameter values.
7.2.3
Battery Management
The Hibernation module can be independently powered by a battery or an auxiliary power source.
The module can monitor the voltage level of the battery and detect when the voltage drops below
2.35 V. When this happens, an interrupt can be generated. The module also can be configured so
that it will not go into Hibernate mode if the battery voltage drops below this threshold. Battery
voltage is not measured while in Hibernate mode.
Important: System level factors may affect the accuracy of the low battery detect circuit. The
designer should consider battery type, discharge characteristics, and a test load during
battery voltage measurements.
Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher
voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under
nominal conditions or else the Hibernation module draws power from the battery even when VDD
is available.
The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN
bit of the HIBCTL register. In this configuration, the LOWBAT bit of the HIBRIS register will be set
when the battery level is low. If the VABORT bit is also set, then the module is prevented from entering
Hibernation mode when a low battery is detected. The module can also be configured to generate
an interrupt for the low-battery condition (see “Interrupts and Status” on page 143).
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Hibernation Module
7.2.4
Real-Time Clock
The Hibernation module includes a 32-bit counter that increments once per second with a proper
clock source and configuration (see “Clock Source” on page 139). The 32.768-kHz clock signal is
fed into a predivider register which counts down the 32.768-kHz clock ticks to achieve a once per
second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock
source by using the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF,
and is used for one second out of every 64 seconds to divide the input clock. This allows the software
to make fine corrections to the clock rate by adjusting the predivider trim register up or down from
0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC
rate, and down from 0x7FFF in order to speed up the RTC rate.
The Hibernation module includes two 32-bit match registers that are compared to the value of the
RTC counter. The match registers can be used to wake the processor from hibernation mode, or
to generate an interrupt to the processor if it is not in hibernation.
The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be
set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading
and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust
the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1
registers. The RTC can be configured to generate interrupts by using the interrupt registers (see
“Interrupts and Status” on page 143).
7.2.5
Non-Volatile Memory
The Hibernation module contains 64 32-bit words of memory which are retained during hibernation.
This memory is powered from the battery or auxiliary power supply during hibernation. The processor
software can save state information in this memory prior to hibernation, and can then recover the
state upon waking. The non-volatile memory can be accessed through the HIBDATA registers.
7.2.6
Power Control
Important: The Hibernation Module requires special system implementation considerations since
it is intended to power-down all other sections of its host device. The system
power-supply distribution and interfaces of the system must be driven to 0 VDC or
powered down with the same regulator controlled by HIB. See “Hibernation
Module” on page 697 for more details.
The Hibernation module controls power to the processor through the use of the HIB pin, which is
intended to be connected to the enable signal of the external regulator(s) providing 3.3 V and/or
2.5 V to the microcontroller. When the HIB signal is asserted by the Hibernation module, the external
regulator is turned off and no longer powers the microcontroller. The Hibernation module remains
powered from the VBAT supply, which could be a battery or an auxiliary power source. Hibernation
mode is initiated by the microcontroller setting the HIBREQ bit of the HIBCTL register. Prior to doing
this, a wake-up condition must be configured, either from the external WAKE pin, or by using an RTC
match.
The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN
bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either
one or both of these bits can be set prior to going into hibernation. The WAKE pin includes a weak
internal pull-up. Note that both the HIB and WAKE pins use the Hibernation module's internal power
supply as the logic 1 reference.
When the Hibernation module wakes, the microcontroller will see a normal power-on reset. It can
detect that the power-on was due to a wake from hibernation by examining the raw interrupt status
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April 08, 2008
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LM3S3748 Microcontroller
register (see “Interrupts and Status” on page 143) and by looking for state data in the non-volatile
memory (see “Non-Volatile Memory” on page 142).
When the HIB signal deasserts, enabling the external regulator, the external regulator must reach
the operating voltage within tHIB_TO_VDD.
7.2.7
Interrupts and Status
The Hibernation module can generate interrupts when the following conditions occur:
■ Assertion of WAKE pin
■ RTC match
■ Low battery detected
All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate
module can only generate a single interrupt request to the controller at any given time. The software
interrupt handler can service multiple interrupt events by reading the HIBMIS register. Software can
also read the status of the Hibernation module at any time by reading the HIBRIS register which
shows all of the pending events. This register can be used at power-on to see if a wake condition
is pending, which indicates to the software that a hibernation wake occurred.
The events that can trigger an interrupt are configured by setting the appropriate bits in the HIBIM
register. Pending interrupts can be cleared by writing the corresponding bit in the HIBIC register.
7.3
Initialization and Configuration
The Hibernation module can be set in several different configurations. The following sections show
the recommended programming sequence for various scenarios. The examples below assume that
a 32.768-kHz oscillator is used, and thus always show bit 2 (CLKSEL) of the HIBCTL register set
to 1. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because the
Hibernation module runs at 32 kHz and is asynchronous to the rest of the system, software must
allow a delay of tHIB_REG_WRITE after writes to certain registers (see “Register Access
Timing” on page 138). The registers that require a delay are listed in a note in “Register Map” on page
145 as well as in each register description.
7.3.1
Initialization
The clock source must be enabled first, even if the RTC will not be used. If a 4.194304-MHz crystal
is used, perform the following steps:
1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128
input path.
2. Wait for a time of tXOSC_SETTLE for the crystal to power up and stabilize before performing any
other operations with the Hibernation module.
If a 32.678-kHz oscillator is used, then perform the following steps:
1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input.
2. No delay is necessary.
The above is only necessary when the entire system is initialized for the first time. If the processor
is powered due to a wake from hibernation, then the Hibernation module has already been powered
April 08, 2008
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Hibernation Module
up and the above steps are not necessary. The software can detect that the Hibernation module
and clock are already powered by examining the CLK32EN bit of the HIBCTL register.
7.3.2
RTC Match Functionality (No Hibernation)
Use the following steps to implement the RTC match functionality of the Hibernation module:
1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the
HIBIM register at offset 0x014.
4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting.
7.3.3
RTC Match/Wake-Up from Hibernation
Use the following steps to implement the RTC match and wake-up functionality of the Hibernation
module:
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the
HIBCTL register at offset 0x010.
7.3.4
External Wake-Up from Hibernation
Use the following steps to implement the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:
1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the
HIBCTL register at offset 0x010.
7.3.5
RTC/External Wake-Up from Hibernation
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F
to the HIBCTL register at offset 0x010.
7.3.6
Register Reset
The Hibernation module handles resets according to the following conditions:
■ Cold Reset
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April 08, 2008
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LM3S3748 Microcontroller
When the hibernation module has no externally applied voltage and detects a change to either
VDD or VBAT, it resets all hibernation module registers to the value in Table 7-1 on page 145.
■ Reset During Hibernation Module Disable
When the module has either not been enabled or has been disabled by software, the reset is
passed through to the Hibernation module circuitry and the internal state of the module is reset.
■ Reset While HIB Module is in Hibernation Mode
While in Hibernation mode, or while transitioning from Hibernation mode to run mode (leaving
the power cut), the reset generated by the POR circuitry of the device is suppressed, and the
state of the Hibernation module's registers is unaffected.
■ Reset While HIB Module is in Normal Mode
While in normal mode (not hibernating), any reset is suppressed, and the content/state of the
control and data registers is unaffected.
Software must initialize any control or data registers in this condition. Therefore, software is the
only mechanism to enable or disable the oscillator and real-time clock operation, or to clear
contents of the data memory. The only state that must be cleared by a reset operation while not
in Hibernation mode is any state that prevents software from managing the interface.
7.4
Register Map
Table 7-1 on page 145 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 138.
Table 7-1. Hibernation Module Register Map
Offset
Name
0x000
Description
See
page
Type
Reset
HIBRTCC
RO
0x0000.0000
Hibernation RTC Counter
147
0x004
HIBRTCM0
R/W
0xFFFF.FFFF
Hibernation RTC Match 0
148
0x008
HIBRTCM1
R/W
0xFFFF.FFFF
Hibernation RTC Match 1
149
0x00C
HIBRTCLD
R/W
0xFFFF.FFFF
Hibernation RTC Load
150
0x010
HIBCTL
R/W
0x0000.0000
Hibernation Control
151
0x014
HIBIM
R/W
0x0000.0000
Hibernation Interrupt Mask
154
0x018
HIBRIS
RO
0x0000.0000
Hibernation Raw Interrupt Status
155
0x01C
HIBMIS
RO
0x0000.0000
Hibernation Masked Interrupt Status
156
0x020
HIBIC
R/W1C
0x0000.0000
Hibernation Interrupt Clear
157
0x024
HIBRTCT
R/W
0x0000.7FFF
Hibernation RTC Trim
158
0x0300x12C
HIBDATA
R/W
0x0000.0000
Hibernation Data
159
April 08, 2008
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Hibernation Module
7.5
Register Descriptions
The remainder of this section lists and describes the Hibernation module registers, in numerical
order by address offset.
146
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LM3S3748 Microcontroller
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000
This register is the current 32-bit value of the RTC counter.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 138.
Hibernation RTC Counter (HIBRTCC)
Base 0x400F.C000
Offset 0x000
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RTCC
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RTCC
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
31:0
RTCC
RO
RO
0
Reset
RO
0
Description
0x0000.0000 RTC Counter
A read returns the 32-bit counter value. This register is read-only. To
change the value, use the HIBRTCLD register.
April 08, 2008
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Hibernation Module
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004
This register is the 32-bit match 0 register for the RTC counter.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 138.
Hibernation RTC Match 0 (HIBRTCM0)
Base 0x400F.C000
Offset 0x004
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RTCM0
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
RTCM0
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
RTCM0
R/W
R/W
1
Reset
R/W
1
Description
0xFFFF.FFFF RTC Match 0
A write loads the value into the RTC match register.
A read returns the current match value.
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LM3S3748 Microcontroller
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008
This register is the 32-bit match 1 register for the RTC counter.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 138.
Hibernation RTC Match 1 (HIBRTCM1)
Base 0x400F.C000
Offset 0x008
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RTCM1
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
RTCM1
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
RTCM1
R/W
R/W
1
Reset
R/W
1
Description
0xFFFF.FFFF RTC Match 1
A write loads the value into the RTC match register.
A read returns the current match value.
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Hibernation Module
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C
This register is the 32-bit value loaded into the RTC counter.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 138.
Hibernation RTC Load (HIBRTCLD)
Base 0x400F.C000
Offset 0x00C
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RTCLD
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
RTCLD
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
RTCLD
R/W
R/W
1
Reset
R/W
1
Description
0xFFFF.FFFF RTC Load
A write loads the current value into the RTC counter (RTCC).
A read returns the 32-bit load value.
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April 08, 2008
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LM3S3748 Microcontroller
Register 5: Hibernation Control (HIBCTL), offset 0x010
This register is the control register for the Hibernation module.
Hibernation Control (HIBCTL)
Base 0x400F.C000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WRC
Type
Reset
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
reserved
Type
Reset
23
RO
0
VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ
Bit/Field
Name
Type
Reset
31
WRC
RO
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RTCEN
R/W
0
Description
Write Complete/Capable
This bit indicates whether the hibernation module can receive a write
operation.
Value Description
0
The interface is processing a prior write and is busy. Any write
operation that is attempted while WRC is 0 results in
undetermined behavior.
1
The interface is ready to accept a write.
Software must poll this bit between write requests and defer writes until
WRC=1 to ensure proper operation.
This difference may be exploited by software at reset time to detect
which method of programming is appropriate: 0 = software delay loops
required; 1 = WRC paced available.
The bit name WRC means "Write Complete," which is the normal use
of the bit (between write accesses). However, because the bit is set
out-of-reset, the name can also mean "Write Capable" which simply
indicates that the interface may be written to by software. This meaning
also has more meaning to the out-of-reset sense.
30:8
reserved
RO
0x00
7
VABORT
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Power Cut Abort Enable
Value Description
0
Power cut occurs during a low-battery alert.
1
Power cut is aborted.
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Hibernation Module
Bit/Field
Name
Type
Reset
6
CLK32EN
R/W
0
Description
32-kHz Oscillator Enable
Value Description
0
Disabled
1
Enabled
This bit must be enabled to use the Hibernation module. If a crystal is
used, then software should wait 20 ms after setting this bit to allow the
crystal to power up and stabilize.
5
LOWBATEN
R/W
0
Low Battery Monitoring Enable
Value Description
0
Disabled
1
Enabled
When set, low battery voltage detection is enabled (VBAT < 2.35 V).
4
PINWEN
R/W
0
External WAKE Pin Enable
Value Description
0
Disabled
1
Enabled
When set, an external event on the WAKE pin will re-power the device.
3
RTCWEN
R/W
0
RTC Wake-up Enable
Value Description
0
Disabled
1
Enabled
When set, an RTC match event (RTCM0 or RTCM1) will re-power the
device based on the RTC counter value matching the corresponding
match register 0 or 1.
2
CLKSEL
R/W
0
Hibernation Module Clock Select
Value Description
1
HIBREQ
R/W
0
0
Use Divide by 128 output. Use this value for a 4-MHz crystal.
1
Use raw output. Use this value for a 32-kHz oscillator.
Hibernation Request
Value Description
0
Disabled
1
Hibernation initiated
After a wake-up event, this bit is cleared by hardware.
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April 08, 2008
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LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
0
RTCEN
R/W
0
Description
RTC Timer Enable
Value Description
0
Disabled
1
Enabled
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Hibernation Module
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014
This register is the interrupt mask register for the Hibernation module interrupt sources.
Hibernation Interrupt Mask (HIBIM)
Base 0x400F.C000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
EXTW
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x000.0000
3
EXTW
R/W
0
R/W
0
LOWBAT RTCALT1 RTCALT0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
External Wake-Up Interrupt Mask
Value Description
2
LOWBAT
R/W
0
0
Masked
1
Unmasked
Low Battery Voltage Interrupt Mask
Value Description
1
RTCALT1
R/W
0
0
Masked
1
Unmasked
RTC Alert1 Interrupt Mask
Value Description
0
RTCALT0
R/W
0
0
Masked
1
Unmasked
RTC Alert0 Interrupt Mask
Value Description
0
Masked
1
Unmasked
154
April 08, 2008
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LM3S3748 Microcontroller
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018
This register is the raw interrupt status for the Hibernation module interrupt sources.
Hibernation Raw Interrupt Status (HIBRIS)
Base 0x400F.C000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
EXTW
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x000.0000
3
EXTW
RO
0
External Wake-Up Raw Interrupt Status
2
LOWBAT
RO
0
Low Battery Voltage Raw Interrupt Status
1
RTCALT1
RO
0
RTC Alert1 Raw Interrupt Status
0
RTCALT0
RO
0
RTC Alert0 Raw Interrupt Status
LOWBAT RTCALT1 RTCALT0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Preliminary
Hibernation Module
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C
This register is the masked interrupt status for the Hibernation module interrupt sources.
Hibernation Masked Interrupt Status (HIBMIS)
Base 0x400F.C000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
EXTW
LOWBAT RTCALT1 RTCALT0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x000.0000
3
EXTW
RO
0
External Wake-Up Masked Interrupt Status
2
LOWBAT
RO
0
Low Battery Voltage Masked Interrupt Status
1
RTCALT1
RO
0
RTC Alert1 Masked Interrupt Status
0
RTCALT0
RO
0
RTC Alert0 Masked Interrupt Status
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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April 08, 2008
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LM3S3748 Microcontroller
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
Hibernation Interrupt Clear (HIBIC)
Base 0x400F.C000
Offset 0x020
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
reserved
Type
Reset
reserved
Type
Reset
EXTW
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x000.0000
3
EXTW
R/W1C
0
LOWBAT RTCALT1 RTCALT0
R/W1C
0
R/W1C
0
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
External Wake-Up Masked Interrupt Clear
Reads return an indeterminate value.
2
LOWBAT
R/W1C
0
Low Battery Voltage Masked Interrupt Clear
Reads return an indeterminate value.
1
RTCALT1
R/W1C
0
RTC Alert1 Masked Interrupt Clear
Reads return an indeterminate value.
0
RTCALT0
R/W1C
0
RTC Alert0 Masked Interrupt Clear
Reads return an indeterminate value.
April 08, 2008
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Hibernation Module
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024
This register contains the value that is used to trim the RTC clock predivider. It represents the
computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock
cycles.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 138.
Hibernation RTC Trim (HIBRTCT)
Base 0x400F.C000
Offset 0x024
Type R/W, reset 0x0000.7FFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
TRIM
Type
Reset
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TRIM
R/W
0x7FFF
RTC Trim Value
This value is loaded into the RTC predivider every 64 seconds. It is used
to adjust the RTC rate to account for drift and inaccuracy in the clock
source. The compensation is made by software by adjusting the default
value of 0x7FFF up or down.
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April 08, 2008
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LM3S3748 Microcontroller
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C
This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the
system processor in order to store any non-volatile state data and will not lose power during a power
cut operation.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 138.
Hibernation Data (HIBDATA)
Base 0x400F.C000
Offset 0x030-0x12C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RTD
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
RTD
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
RTD
R/W
R/W
0
Reset
R/W
0
Description
0x0000.0000 Hibernation Module NV Registers[63:0]
April 08, 2008
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Preliminary
Internal Memory
8
Internal Memory
The LM3S3748 microcontroller comes with 64 KB of bit-banded SRAM and 128 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.
8.1
Block Diagram
Figure 8-1 on page 160 illustrates the Flash functions. The dashed boxes in the figure indicate
registers residing in the System Control module rather than the Flash Control module.
Figure 8-1. Flash Block Diagram
ROM Control
ROM Array
ROMCTL
Flash Control
Icode Bus
Cortex-M3
FMA
FMD
FMC
FCRIS
FCIM
FCMISC
System
Bus
Dcode Bus
Flash Array
Flash Protection
Bridge
FMPREn
FMPPEn
Flash Timing
USECRL
User Registers
USER_DBG
USER_REG0
USER_REG1
USER_REG2
USER_REG3
SRAM Array
8.2
Functional Description
This section describes the functionality of the SRAM, ROM, and Flash memories.
8.2.1
SRAM Memory
Note:
The SRAM memory is implemented using two 32-bit wide SRAM banks (separate SRAM
arrays). The banks are partitioned so that one bank contains all even words (the even bank)
and the other contains all odd words (the odd bank). A write access that is followed
immediately by a read access to the same bank will incur a stall of a single clock cycle.
However, a write to one bank followed by a read of the other bank can occur in successive
clock cycles without incurring any delay.
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®
The internal SRAM of the Stellaris devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor,
certain regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3
Technical Reference Manual.
8.2.2
ROM Memory
®
The 16 KB of internal ROM of the Stellaris device is located at address 0x0100.0000 of the device
memory map and contains the following components:
■ A copy of the Serial Flash Loader and vector table
■ A copy of the peripheral driver library (DriverLib) release for product-specific peripherals and
interfaces
■ Some pre-loaded code provided for manufacturing tests
8.2.3
Flash Memory
The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be
programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB
blocks that can be individually protected. The protection allows blocks to be marked as read-only
or execute-only, providing different levels of code protection. Read-only blocks cannot be erased
or programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
8.2.3.1
Flash Memory Timing
The timing for the flash is automatically handled by the flash controller. However, in order to do so,
it must know the clock rate of the system in order to time its internal signals properly. The number
of clock cycles per microsecond must be provided to the flash controller for it to accomplish this
timing. It is software's responsibility to keep the flash controller updated with this information via the
USec Reload (USECRL) register.
On reset, the USECRL register is loaded with a value that configures the flash timing so that it works
with the maximum clock rate of the part. If software changes the system operating frequency, the
new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash
modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value
of 0x13 (20-1) must be written to the USECRL register.
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8.2.3.2
Flash Memory Protection
The user is provided two forms of flash protection per 2-KB flash blocks in two pairs of 32-bit wide
registers. The protection policy for each form is controlled by individual bits (per policy per block)
in the FMPPEn and FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed
(written) or erased. If cleared, the block may not be changed.
■ Flash Memory Protection Read Enable (FMPREn): If set, the block may be executed or read
by software or debuggers. If cleared, the block may only be executed and contents of the memory
block are prohibited from being accessed as data.
The policies may be combined as shown in Table 8-1 on page 162.
Table 8-1. Flash Protection Policy Combinations
FMPPEn FMPREn Protection
0
0
Execute-only protection. The block may only be executed and may not be written or erased. This mode
is used to protect code.
1
0
The block may be written, erased or executed, but not read. This combination is unlikely to be used.
0
1
Read-only protection. The block may be read or executed but may not be written or erased. This mode
is used to lock the block from further modification while allowing any read or execute access.
1
1
No protection. The block may be written, erased, executed or read.
An access that attempts to program or erase a PE-protected block is prohibited. A controller interrupt
may be optionally generated (by setting the AMASK bit in the FIM register) to alert software developers
of poorly behaving software during the development and debug phases.
An access that attempts to read an RE-protected block is prohibited. Such accesses return data
filled with all 0s. A controller interrupt may be optionally generated to alert software developers of
poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. This implements a policy of open access and programmability. The register bits may be
changed by writing the specific register bit. The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. Details on
programming these bits are discussed in “Nonvolatile Register Programming” on page 163.
8.3
Flash Memory Initialization and Configuration
8.3.1
Flash Programming
®
The Stellaris devices provide a user-friendly interface for flash programming. All erase/program
operations are handled via three registers: FMA, FMD, and FMC.
8.3.1.1
To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register.
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4. Poll the FMC register until the WRITE bit is cleared.
8.3.1.2
To perform an erase of a 1-KB page
1. Write the page address to the FMA register.
2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register.
3. Poll the FMC register until the ERASE bit is cleared.
8.3.1.3
To perform a mass erase of the flash
1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register.
2. Poll the FMC register until the MERASE bit is cleared.
8.3.2
Nonvolatile Register Programming
This section discusses how to update registers that are resident within the flash memory itself.
These registers exist in a separate space from the main flash array and are not affected by an
ERASE or MASS ERASE operation. These nonvolatile registers are updated by using the COMT bit
in the FMC register to activate a write operation. For the USER_DBG register, the data to be written
must be loaded into the FMD register before it is "committed". All other registers are R/W and can
have their operation tried before committing them to nonvolatile memory.
Important: These registers can only have bits changed from 1 to 0 by user programming, but can
be restored to their factory default values by performing the sequence described in the
section called “Recovering a "Locked" Device” on page 59. The mass erase of the main
flash array caused by the sequence is performed prior to restoring these registers.
In addition, the USER_REG0, USER_REG1, and USER_DBG use bit 31 (NW) of their respective
registers to indicate that they are available for user write. These three registers can only be written
once whereas the flash protection registers may be written multiple times. Table 8-2 on page 163
provides the FMA address required for commitment of each of the registers and the source of the
data to be written when the COMT bit of the FMC register is written with a value of 0xA442.0008.
After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to
complete.
a
Table 8-2. Flash Resident Registers
Register to be Committed FMA Value
Data Source
FMPRE0
0x0000.0000 FMPRE0
FMPRE1
0x0000.0002 FMPRE1
FMPRE2
0x0000.0004 FMPRE2
FMPRE3
0x0000.0008 FMPRE3
FMPPE0
0x0000.0001 FMPPE0
FMPPE1
0x0000.0003 FMPPE1
FMPPE2
0x0000.0005 FMPPE2
FMPPE3
0x0000.0007 FMPPE3
USER_REG0
0x8000.0000 USER_REG0
USER_REG1
0x8000.0001 USER_REG1
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Internal Memory
Register to be Committed FMA Value
USER_DBG
Data Source
0x7510.0000 FMD
®
a. Which FMPREn and FMPPEn registers are available depend on the flash size of your particular Stellaris device.
8.4
Register Map
Table 8-3 on page 164 lists the ROM Controller registers and the Flash memory and control registers.
The offset listed is a hexadecimal increment to the register's address. The ROM Controller registers
are relative to the System Control base address of 0x400F.E000. The FMA, FMD, FMC, FCRIS,
FCIM, and FCMISC registers are relative to the Flash control base address of 0x400F.D000. The
FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the System
Control base address of 0x400F.E000.
Table 8-3. Flash Register Map
Offset
Name
Type
Reset
Description
See
page
-
ROM Control
166
ROM Registers (System Control Offset)
0x0F0
RMCTL
R/W1C
Flash Registers (Flash Control Offset)
0x000
FMA
R/W
0x0000.0000
Flash Memory Address
167
0x004
FMD
R/W
0x0000.0000
Flash Memory Data
168
0x008
FMC
R/W
0x0000.0000
Flash Memory Control
169
0x00C
FCRIS
RO
0x0000.0000
Flash Controller Raw Interrupt Status
171
0x010
FCIM
R/W
0x0000.0000
Flash Controller Interrupt Mask
172
0x014
FCMISC
R/W1C
0x0000.0000
Flash Controller Masked Interrupt Status and Clear
173
Flash Registers (System Control Offset)
0x0F4
RMVER
RO
0x0000.0000
ROM Version Register
175
0x130
FMPRE0
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 0
176
0x200
FMPRE0
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 0
176
0x134
FMPPE0
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 0
177
0x400
FMPPE0
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 0
177
0x140
USECRL
R/W
0x31
USec Reload
174
0x1D0
USER_DBG
R/W
0xFFFF.FFFE
User Debug
178
0x1E0
USER_REG0
R/W
0xFFFF.FFFF
User Register 0
179
0x1E4
USER_REG1
R/W
0xFFFF.FFFF
User Register 1
180
0x1E8
USER_REG2
R/W
0xFFFF.FFFF
User Register 2
181
0x1EC
USER_REG3
R/W
0xFFFF.FFFF
User Register 3
182
0x204
FMPRE1
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 1
183
0x208
FMPRE2
R/W
0x0000.0000
Flash Memory Protection Read Enable 2
184
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Name
Type
Reset
0x20C
FMPRE3
R/W
0x0000.0000
Flash Memory Protection Read Enable 3
185
0x404
FMPPE1
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 1
186
0x408
FMPPE2
R/W
0x0000.0000
Flash Memory Protection Program Enable 2
187
0x40C
FMPPE3
R/W
0x0000.0000
Flash Memory Protection Program Enable 3
188
8.5
Description
See
page
Offset
ROM Register Descriptions (System Control Offset)
This section lists and describes the ROM Controller registers, in numerical order by address offset.
Registers in this section are relative to the System Control base address of 0x400F.E000.
April 08, 2008
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Internal Memory
Register 1: ROM Control (RMCTL), offset 0x0F0
This register provides control of the ROM controller state.
ROM Control (RMCTL)
Base 0x400F.E000
Offset 0x0F0
Type R/W1C, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
-
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0
0
BA
R/W1C
-
BA
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Boot Alias
■
The device has ROM.
■
The first two words of the Flash memory contain 0xFFFF.FFFF.
This bit is cleared by writing a 1 to this bit position.
When the BA bit is set, the boot alias is in effect and the ROM appears
at address 0x0. When the BA bit is clear, the Flash appears at address
0x0.
8.6
Flash Register Descriptions (Flash Control Offset)
This section lists and describes the Flash Memory registers, in numerical order by address offset.
Registers in this section are relative to the Flash control base address of 0x400F.D000.
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Register 2: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and specifies
which page is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
16
OFFSET
OFFSET
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16:0
OFFSET
R/W
0x0
Address Offset
Address offset in flash where operation is performed, except for
nonvolatile registers (see “Nonvolatile Register Programming” on page
163 for details on values for this field).
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Internal Memory
Register 3: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during the erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:0
DATA
R/W
0x0
Data Value
Data value for write operation.
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Register 4: Flash Memory Control (FMC), offset 0x008
When this register is written, the flash controller initiates the appropriate access cycle for the location
specified by the Flash Memory Address (FMA) register (see page 167). If the access is a write
access, the data contained in the Flash Memory Data (FMD) register (see page 168) is written.
This is the final register written and initiates the memory operation. There are four control bits in the
lower byte of this register that, when set, initiate the memory operation. The most used of these
register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
WRKEY
Type
Reset
reserved
Type
Reset
COMT
Bit/Field
Name
Type
Reset
31:16
WRKEY
WO
0x0
R/W
0
MERASE ERASE
R/W
0
R/W
0
WRITE
R/W
0
Description
Flash Write Key
This field contains a write key, which is used to minimize the incidence
of accidental flash writes. The value 0xA442 must be written into this
field for a write to occur. Writes to the FMC register without this WRKEY
value are ignored. A read of this field returns the value 0.
15:4
reserved
RO
0x0
3
COMT
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Commit Register Value
Commit (write) of register value to nonvolatile storage. A write of 0 has
no effect on the state of this bit.
If read, the state of the previous commit access is provided. If the
previous commit access is complete, a 0 is returned; otherwise, if the
commit access is not complete, a 1 is returned.
This can take up to 50 μs.
2
MERASE
R/W
0
Mass Erase Flash Memory
If this bit is set, the flash main memory of the device is all erased. A
write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is provided. If the
previous mass erase access is complete, a 0 is returned; otherwise, if
the previous mass erase access is not complete, a 1 is returned.
This can take up to 250 ms.
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Internal Memory
Bit/Field
Name
Type
Reset
1
ERASE
R/W
0
Description
Erase a Page of Flash Memory
If this bit is set, the page of flash main memory as specified by the
contents of FMA is erased. A write of 0 has no effect on the state of this
bit.
If read, the state of the previous erase access is provided. If the previous
erase access is complete, a 0 is returned; otherwise, if the previous
erase access is not complete, a 1 is returned.
This can take up to 25 ms.
0
WRITE
R/W
0
Write a Word into Flash Memory
If this bit is set, the data stored in FMD is written into the location as
specified by the contents of FMA. A write of 0 has no effect on the state
of this bit.
If read, the state of the previous write update is provided. If the previous
write access is complete, a 0 is returned; otherwise, if the write access
is not complete, a 1 is returned.
This can take up to 50 µs.
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LM3S3748 Microcontroller
Register 5: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled
if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
PRIS
ARIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0
1
PRIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Raw Interrupt Status
This bit indicates the current state of the programming cycle. If set, the
programming cycle completed; if cleared, the programming cycle has
not completed. Programming cycles are either write or erase actions
generated through the Flash Memory Control (FMC) register bits (see
page 169).
0
ARIS
RO
0
Access Raw Interrupt Status
This bit indicates if the flash was improperly accessed. If set, the program
tried to access the flash counter to the policy as set in the Flash Memory
Protection Read Enable (FMPREn) and Flash Memory Protection
Program Enable (FMPPEn) registers. Otherwise, no access has tried
to improperly access the flash.
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Internal Memory
Register 6: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
PMASK
AMASK
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0
1
PMASK
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the controller. If set, a programming-generated interrupt is promoted
to the controller. Otherwise, interrupts are recorded but suppressed from
the controller.
0
AMASK
R/W
0
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
controller. If set, an access-generated interrupt is promoted to the
controller. Otherwise, interrupts are recorded but suppressed from the
controller.
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April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 7: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0
1
PMISC
R/W1C
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
PMISC
AMISC
R/W1C
0
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because a
programming cycle completed and was not masked. This bit is cleared
by writing a 1. The PRIS bit in the FCRIS register (see page 171) is also
cleared when the PMISC bit is cleared.
0
AMISC
R/W1C
0
Access Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because an improper
access was attempted and was not masked. This bit is cleared by writing
a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC
bit is cleared.
8.7
Flash Register Descriptions (System Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the System Control base address of
0x400F.E000.
April 08, 2008
173
Preliminary
Internal Memory
Register 8: USec Reload (USECRL), offset 0x140
Note:
Offset is relative to System Control base address of 0x400F.E000
This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.
The internal flash has specific minimum and maximum requirements on the length of time the high
voltage write pulse can be applied. It is required that this register contain the operating frequency
(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this
value if the clocking conditions are changed for a flash erase/program operation.
USec Reload (USECRL)
Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x31
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
USEC
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
USEC
R/W
0x31
Microsecond Reload Value
MHz -1 of the controller clock when the flash is being erased or
programmed.
If the maximum system frequency is being used, USEC should be set to
0x31 (50 MHz) whenever the flash is being erased or programmed.
174
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 9: ROM Version Register (RMVER), offset 0x0F4
Note:
Offset is relative to System Control base address of 0x400FE000.
A 32-bit read-only register containing the ROM content version information.
ROM Version Register (RMVER)
Base 0x400F.E000
Offset 0x0F4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
CONT
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
6
5
4
VER
Type
Reset
RO
0
RO
0
RO
0
RO
0
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
SIZE
REV
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:24
CONT
RO
0x0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
ROM Contents
This field specifies the contents of the ROM.
Value Description
0x0
23:16
SIZE
RO
0x0
Stellaris Boot Loader & DriverLib
ROM Size
This field encodes the size of the ROM.
Value Description
0x0
11 KB
15:8
VER
RO
0x0
ROM Version
7:0
REV
RO
0x0
ROM Revision
April 08, 2008
175
Preliminary
Internal Memory
Register 10: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130
and 0x200
Note:
This register is aliased for backwards compatability.
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 0 (FMPRE0)
Base 0x400F.E000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Read Enable. Enables 2-KB flash blocks to be executed or read.
The policies may be combined as shown in the table “Flash Protection
Policy Combinations”.
Value
Description
0xFFFFFFFF Enables 128 KB of flash.
176
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 11: Flash Memory Protection Program Enable 0 (FMPPE0), offset
0x134 and 0x400
Note:
This register is aliased for backwards compatability.
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 0 (FMPPE0)
Base 0x400F.E000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PROG_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value
Description
0xFFFFFFFF Enables 128 KB of flash.
April 08, 2008
177
Preliminary
Internal Memory
Register 12: User Debug (USER_DBG), offset 0x1D0
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides a write-once mechanism to disable external debugger access to the device
in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory
and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0
disables any external debugger access to the device permanently, starting with the next power-up
cycle of the device. The NOTWRITTEN bit (bit 31) indicates that the register is available to be written
and is controlled through hardware to ensure that the register is only written once.
User Debug (USER_DBG)
Base 0x400F.E000
Offset 0x1D0
Type R/W, reset 0xFFFF.FFFE
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
1
0
DBG1
DBG0
R/W
1
R/W
0
Bit/Field
Name
Type
Reset
Description
31
NW
R/W
1
30:2
DATA
R/W
1
DBG1
R/W
1
Debug Control 1. The DBG1 bit must be 1 and DBG0 must be 0 for debug
to be available.
0
DBG0
R/W
0
Debug Control 0. The DBG1 bit must be 1 and DBG0 must be 0 for debug
to be available.
User Debug Not Written. Specifies that this 32-bit dword has not been
written.
0x1FFFFFFF User Data. Contains the user data value. This field is initialized to all 1s
and can only be written once.
178
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 13: User Register 0 (USER_REG0), offset 0x1E0
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 0 (USER_REG0)
Base 0x400F.E000
Offset 0x1E0
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
31
NW
R/W
1
30:0
DATA
R/W
R/W
1
Description
Not Written. Specifies that this 32-bit dword has not been written.
0x7FFFFFFF User Data. Contains the user data value. This field is initialized to all 1s
and can only be written once.
April 08, 2008
179
Preliminary
Internal Memory
Register 14: User Register 1 (USER_REG1), offset 0x1E4
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 1 (USER_REG1)
Base 0x400F.E000
Offset 0x1E4
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
31
NW
R/W
1
30:0
DATA
R/W
R/W
1
Description
Not Written. Specifies that this 32-bit dword has not been written.
0x7FFFFFFF User Data. Contains the user data value. This field is initialized to all 1s
and can only be written once.
180
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 15: User Register 2 (USER_REG2), offset 0x1E8
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 2 (USER_REG2)
Base 0x400F.E000
Offset 0x1E8
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
31
NW
R/W
1
30:0
DATA
R/W
R/W
1
Description
Not Written. Specifies that this 32-bit dword has not been written.
0x7FFFFFFF User Data. Contains the user data value. This field is initialized to all 1s
and can only be written once.
April 08, 2008
181
Preliminary
Internal Memory
Register 16: User Register 3 (USER_REG3), offset 0x1EC
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 3 (USER_REG3)
Base 0x400F.E000
Offset 0x1EC
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
31
NW
R/W
1
30:0
DATA
R/W
R/W
1
Description
Not Written. Specifies that this 32-bit dword has not been written.
0x7FFFFFFF User Data. Contains the user data value. This field is initialized to all 1s
and can only be written once.
182
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 17: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 1 (FMPRE1)
Base 0x400F.E000
Offset 0x204
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Read Enable. Enables 2-KB flash blocks to be executed or read.
The policies may be combined as shown in the table “Flash Protection
Policy Combinations”.
Value
Description
0xFFFFFFFF Enables 128 KB of flash.
April 08, 2008
183
Preliminary
Internal Memory
Register 18: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 2 (FMPRE2)
Base 0x400F.E000
Offset 0x208
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
0
Reset
R/W
0
R/W
0
Description
0x00000000 Flash Read Enable. Enables 2-KB flash blocks to be executed or read.
The policies may be combined as shown in the table “Flash Protection
Policy Combinations”.
Value
Description
0x00000000 Enables 128 KB of flash.
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Register 19: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 3 (FMPRE3)
Base 0x400F.E000
Offset 0x20C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
0
Reset
R/W
0
R/W
0
Description
0x00000000 Flash Read Enable. Enables 2-KB flash blocks to be executed or read.
The policies may be combined as shown in the table “Flash Protection
Policy Combinations”.
Value
Description
0x00000000 Enables 128 KB of flash.
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Internal Memory
Register 20: Flash Memory Protection Program Enable 1 (FMPPE1), offset
0x404
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 1 (FMPPE1)
Base 0x400F.E000
Offset 0x404
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Programming Enable. Configures 2-KB flash blocks to be execute
only. The policies may be combined as shown in the table “Flash
Protection Policy Combinations”.
Value
Description
0xFFFFFFFF Enables 128 KB of flash.
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Register 21: Flash Memory Protection Program Enable 2 (FMPPE2), offset
0x408
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 2 (FMPPE2)
Base 0x400F.E000
Offset 0x408
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
0
R/W
0
Description
0x00000000 Flash Programming Enable. Configures 2-KB flash blocks to be execute
only. The policies may be combined as shown in the table “Flash
Protection Policy Combinations”.
Value
Description
0x00000000 Enables 128 KB of flash.
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Preliminary
Internal Memory
Register 22: Flash Memory Protection Program Enable 3 (FMPPE3), offset
0x40C
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 3 (FMPPE3)
Base 0x400F.E000
Offset 0x40C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
0
R/W
0
Description
0x00000000 Flash Programming Enable. Configures 2-KB flash blocks to be execute
only. The policies may be combined as shown in the table “Flash
Protection Policy Combinations”.
Value
Description
0x00000000 Enables 128 KB of flash.
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9
Micro Direct Memory Access (μDMA)
The LM3S3748 microcontroller includes a Direct Memory Access (DMA) controller, known as
micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
Cortex-M3 processor, allowing for more effecient use of the processor and the expanded available
bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It
has dedicated channels for each supported peripheral and can be programmed to automatically
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller also supports sophisticated transfer modes such as ping-pong and
scatter-gather, which allows the processor to set up a list of transfer tasks for the controller.
The μDMA controller has the following features:
■ ARM PrimeCell® 32-channel configurable µDMA controller
■ Support for multiple transfer modes:
– Basic, for simple transfer scenarios
– Ping-pong, for continuous data flow to/from peripherals
– Scatter-gather, from a programmable list of arbitrary transfers initiated from a single request
■ Dedicated channels for supported peripherals
■ One channel each for receive and transmit path for bidirectional peripherals
■ Dedicated channel for software-initiated transfers
■ Independently configured and operated channels
■ Per-channel configurable bus arbitration scheme
■ Two levels of priority
■ Design optimizations for improved bus access performance between µDMA controller and the
processor core:
– µDMA controller access is subordinate to core access
– RAM striping
– Peripheral bus segmentation
■ Data sizes of 8, 16, and 32 bits
■ Source and destination address increment size of byte, half-word, word, or no increment
■ Maskable device requests
■ Optional software initiated requests for any channel
■ Interrupt on transfer completion, with a separate interrupt per channel
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Micro Direct Memory Access (μDMA)
9.1
Block Diagram
Figure 9-1. μDMA Block Diagram
uDMA
Controller
DMA error
System Memory
CH Control Table
Peripheral
DMA Channel 0
•
•
•
Peripheral
DMA Channel N-1
Nested
Vectored
Interrupt
Controller
(NVIC)
IRQ
General
Peripheral N
Registers
request
done
request
done
request
done
DMASTAT
DMACFG
DMACTLBASE
DMAALTBASE
DMAWAITSTAT
DMASWREQ
DMAUSEBURSTSET
DMAUSEBURSTCLR
DMAREQMASKSET
DMAREQMASKCLR
DMAENASET
DMAENACLR
DMAALTSET
DMAALTCLR
DMAPRIOSET
DMAPRIOCLR
DMAERRCLR
DMASRCENDP
DMADSTENDP
DMACHCTRL
•
•
•
DMASRCENDP
DMADSTENDP
DMACHCTRL
Transfer Buffers
Used by uDMA
ARM
Cortex-M3
9.2
Functional Description
The μDMA controller is a flexible and highly configurable DMA controller designed to work effeciently
with the microcontroller's Cortex-M3 processor core. It supports multiple data sizes and address
increment schemes, multiple levels of priority among DMA channels, and several transfer modes
to allow for sophisticated programmed data transfers. The DMA controller's usage of the bus is
always subordinate to the processor core, and so it will never hold up a bus transaction by the
processor. Because the μDMA controller is only using otherwise-idle bus cycles, the data transfer
bandwidth it provides is essentially free, with no impact on the rest of the system. The bus architecture
has been optimized to greatly reduce contention between the processor core and the μDMA controller,
thus improving performance. The optimizations include RAM striping and peripheral bus segmentation,
which in many cases allows both the processor core and the μDMA controller to access the bus
and perform simultaneous data transfers.
Each peripheral function that is supported has a dedicated channel on the μDMA controller that can
be configured independently.
The μDMA controller makes use of a unique configuration method by using channel control structures
that are maintained in system memory by the processor. While simple transfer modes are supported,
it is also possible to build up sophisticated "task" lists in memory that allow the controller to perform
arbitrary-sized transfers to and from arbitrary locations as part of a single transfer request. The
controller also supports the use of ping-pong buffering to accomodate constant streaming of data
to or from a peripheral.
Each channel also has a configurable arbitration size. The arbitration size is the number of items
that will be transferred in a burst before the controller rearbitrates for channel priority. Using the
arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral
each time it makes a DMA service request.
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9.2.1
Channel Assigments
μDMA channels 0-31 are assigned to peripherals according to the following table.
Note:
Channels that are not listed in the table may be assigned to peripherals in the future.
However, they are currently available for software use.
Table 9-1. DMA Channel Assignments
DMA Channel Peripheral Assigned
9.2.2
0
USB Endpoint 1 Receive
1
USB Endpoint 1 Transmit
2
USB Endpoint 2 Receive
3
USB Endpoint 2 Transmit
4
USB Endpoint 3 Receive
5
USB Endpoint 3 Transmit
8
UART0 Receive
9
UART0 Transmit
10
SSI0 Receive
11
SSI0 Transmit
22
UART1 Receive
23
UART1 Transmit
24
SSI1 Receive
25
SSI1 Transmit
30
Dedicated for software use
Priority
The μDMA controller assigns priority to each channel based on the channel number and the priority
level bit for the channel. Channel number 0 has the highest priority and as the channel number
increases, the priority of a channel decreases. Each channel has a priority level bit to provide two
levels of priority: default priority and high priority. If the priority level bit is set, then that channel has
higher priority than all other channels at default priority. If multiple channels are set for high priority,
then the channel number is used to determine relative priority among all the high priority channels.
The priority bit for a channel can be set using the DMA Channel Priority Set (DMAPRIOSET)
register, and cleared with the DMA Channel Priority Clear (DMAPRIOCLR) register.
9.2.3
Arbitration Size
When a μDMA channel requests a transfer, the μDMA controller arbitrates between all the channels
making a request and services the DMA channel with the highest priority. Once a transfer begins,
it continues for a selectable number of transfers before rearbitrating among the requesting channels
again. The arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers.
After the μDMA controller transfers the number of items specified by the arbitration size, it then
checks among all the channels making a request and services the channel with the highest priority.
If a lower priority DMA channel uses a large arbitration size, the latency for higher priority channels
will be increased because the μDMA controller will complete the lower priority burst before checking
for higher priority requests. Therefore, lower priority channels should not use a large arbitration size
for best response on high priority channels.
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Micro Direct Memory Access (μDMA)
The arbitration size can also be thought of as a burst size. It is the maximum number of items that
will be transferred at any one time in a burst. Here, the term arbitration refers to determination of
DMA channel priority, not arbitration for the bus. When the μDMA controller arbitrates for the bus,
the processor always takes priority. Furthermore, the μDMA controller will be held off whenever the
processor needs to perform a bus transaction on the same bus, even in the middle of a burst transfer.
9.2.4
Request Types
The μDMA controller responds to two types of requests from a peripheral: single or burst. Each
peripheral may support either or both types of requests. A single request means that the peripheral
is ready to transfer one item, while a burst request means that the peripheral is ready to transfer
multiple items.
The μDMA controller responds differently depending on whether the peripheral is making a single
request or a burst request. If both are asserted and the μDMA channel has been set up for a burst
transfer, then the burst request takes precedence. See Table 9-2 on page 192, which shows how
each peripheral supports the two request types.
Table 9-2. Request Type Support
Peripheral Single Request Signal Burst Request Signal
9.2.4.1
USB TX
None
FIFO TXRDY
USB RX
None
FIFO RXRDY
UART TX
TX FIFO Not Full
TX FIFO Level (configurable)
UART RX
RX FIFO Not Empty
RX FIFO Level (configurable)
SSI TX
TX FIFO Not Full
TX FIFO Level (fixed at 4)
SSI RX
RX FIFO Not Empty
RX FIFO Level (fixed at 4)
Single Request
When a single request is detected, and not a burst request, the μDMA controller will transfer one
item, and then stop and wait for another request.
9.2.4.2
Burst Request
When a burst request is detected, the μDMA controller will transfer the number of items that is the
lesser of the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration
size should be the same as the number of data items that the peripheral can accomodate when
making a burst request. For example, the UART will generate a burst request based on the FIFO
trigger level. In this case, the arbitration size should be set to the amount of data that the FIFO can
transfer when the trigger level is reached.
It may be desirable to use only burst transfers and not allow single transfers. For example, perhaps
the nature of the data is such that it only makes sense when transferred together as a single unit
rather than one piece at a time. The single request can be disabled by using the DMA Channel
Useburst Set (DMAUSEBURSTSET) register. By setting the bit for a channel in this register, the
μDMA controller will only respond to burst requests for that channel.
9.2.5
Channel Configuration
The μDMA controller uses an area of system memory to store a set of channel control structures
in a table. The control table may have one or two entries for each DMA channel. Each entry in the
table structure contains source and destination pointers, transfer size, and transfer mode. The
control table can be located anywhere in system memory, but it must be contiguous and aligned on
a 1024-byte boundary.
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LM3S3748 Microcontroller
Table 9-3 on page 193 shows the layout in memory of the channel control table. Each channel may
have one or two control structures in the contol table: a primary control structure and an optional
alternate control structure. The table is organized so that all of the primary entries are in the first
half of the table and all the alternate structures are in the second half of the table. The primary entry
is used for simple transfer modes where transfers can be reconfigured and restarted after each
transfer is complete. In this case, the alternate control structures are not used and therefore only
the first half of the table needs to be allocated in memory. The second half of the control table is
not needed and that memory can be used for something else. If a more complex transfer mode is
used such as ping-pong or scatter-gather, then the alternate control structure is also used and
memory space should be allocated for the entire table.
Any unused memory in the control table may be used by the application. This includes the control
structures for any channels that are unused by the application as well as the unused control word
for each channel.
Table 9-3. Control Structure Memory Map
Offset
Channel
0x0
0, Primary
0x10
1, Primary
...
...
0x1F0
31, Primary
0x200
0, Alternate
0x210
1, Alternate
...
...
0x3F0
31, Alternate
Table 9-4 on page 193 shows an individual control structure entry in the control table. Each entry
has a source and destination end pointer. These pointers point to the ending address of the transfer
and are inclusive. If the source or destination is non-incrementing (as for a peripheral register), then
the pointer should point to the transfer address.
Table 9-4. Channel Control Structure
Offset
Description
0x000
Source End Pointer
0x004
Destination End Pointer
0x008
Control Word
0x00C
Unused
The remaining part of the control structure is the control word. The control word contains the following
fields:
■ Source and destination data sizes
■ Source and destination address increment size
■ Number of transfers before bus arbitration
■ Total number of items to transfer
■ Useburst flag
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Micro Direct Memory Access (μDMA)
■ Transfer mode
The control word and each field are described in detail in “μDMA Channel Control
Structure” on page 210. The μDMA controller updates the transfer size and transfer mode fields as
the transfer is performed. At the end of a transfer, the transfer size will indicate 0, and the transfer
mode will indicate "stopped". Since the control word is modified by the μDMA controller, it must be
reconfigured before each new transfer. The source and destination end pointers are not modified
so they can be left unchanged if the source or destination addresses remain the same.
Prior to starting a transfer, a μDMA channel must be enabled by setting the appropriate bit in the
DMA Channel Enable Set ((DMAENASET) register. A channel can be disabled by setting the
channel bit in the DMA Channel Enable Clear (DMAENACLR) register. At the end of a complete
DMA transfer, the controller will automatically disable the channel.
9.2.6
Transfer Modes
The μDMA controller supports several transfer modes. Two of the modes support simple one-time
transfers. There are several complex modes that are meant to support a continuous flow of data.
9.2.6.1
Stop Mode
While Stop is not actually a transfer mode, it is a valid value for the mode field of the control word.
When the mode field has this value, the μDMA controller will not perform a transfer and will disable
the channel if it is enabled. At the end of a transfer, the μDMA controller will update the control word
to set the mode to Stop.
9.2.6.2
Basic Mode
In Basic mode, the μDMA controller will perform transfers as long as there are more items to transfer
and a transfer request is present. This mode is used with peripherals that assert a DMA request
signal whenever the peripheral is ready for a data transfer. Basic mode should not be used in any
situation where the request is momentary but the entire transfer should be completed. For example,
for a software initiated transfer, the request is momentary, and if Basic mode is used then only one
item will be transferred on a software request.
When all of the items have been transferred using Basic mode, the μDMA controller will set the
mode for that channel to Stop.
9.2.6.3
Auto Mode
Auto mode is similar to Basic mode, except that once a transfer request is received the transfer will
run to completion, even if the DMA request is removed. This mode is suitable for software-triggered
transfers. Generally, you would not use Auto mode with a peripheral.
When all the items have been transferred using Auto mode, the μDMA controller will set the mode
for that channel to Stop.
9.2.6.4
Ping-Pong
Ping-Pong mode is used to support a continuous data flow to or from a peripheral. To use Ping-Pong
mode, both the primary and alternate data structures are used. Both are set up by the processor
for data transfer between memory and a peripheral. Then the transfer is started using the primary
control structure. When the transfer using the primary control structure is complete, the μDMA
controller will then read the alternate control structure for that channel to continue the transfer. Each
time this happens, an interrupt is generated and the processor can reload the control structure for
the just-completed transfer. Data flow can continue indefinitely this way, using the primary and
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April 08, 2008
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LM3S3748 Microcontroller
alternate control structures to switch back and forth between buffers as the data flows to or from
the peripheral.
Refer to Figure 9-2 on page 195 for an example showing operation in Ping-Pong mode.
Figure 9-2. Example of Ping-Pong DMA Transaction
uDMA Controller
SOURCE
DEST
transfers using BUFFER A
transfer continues using alternate
Primary Structure
Cortex-M3 Processor
SOURCE
DEST
Pe
rip
Time
SOURCE
DEST
Alternate Structure
SOURCE
DEST
ral
/uD
nte
transfers using BUFFER B
rru
pt
BUFFER B
Process data in BUFFER A
Reload primary structure
Pe
rip
h
era
l/u
DM
AI
nte
transfers using BUFFER A
rru
pt
BUFFER A
Process data in BUFFER B
Reload alternate structure
transfer continues using alternate
Primary Structure
he
MA
I
transfer continues using primary
Alternate Structure
BUFFER A
Pe
rip
he
ral
/u
DM
AI
nte
transfers using BUFFER B
rru
pt
BUFFER B
Process data in BUFFER B
Reload alternate structure
April 08, 2008
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Preliminary
Micro Direct Memory Access (μDMA)
9.2.6.5
Memory Scatter-Gather
Memory Scatter-Gather mode is a complex mode used when data needs to be transferred to or
from varied locations in memory instead of a set of contiguous locations in a memory buffer. For
example, a gather DMA operation could be used to selectively read the payload of several stored
packets of a communication protocol, and store them together in sequence in a memory buffer.
In Memory Scatter-Gather mode, the primary control structure is used to program the alternate
control structure from a table in memory. The table is set up by the processor software and contains
a list of control structures, each containing the source and destination end pointers, and the control
word for a specific transfer. The mode of each control word must be set to Scatter-Gather mode.
Each entry in the table is copied in turn to the alternate structure where it is then executed. The
μDMA controller alternates between using the primary control structure to copy the next transfer
instruction from the list, and then executing the new transfer instruction. The end of the list is marked
by setting the control word for the last entry to use Basic transfer mode. Once the last transfer is
performed using Basic mode, the μDMA controller will stop. A completion interrupt will only be
generated after the last transfer. It is possible to loop the list by having the last entry copy the primary
control structure to point back to the beginning of the list (or to a new list). It is also possible to trigger
a set of other channels to perform a transfer, either directly by programming a write to the software
trigger for another channel, or indirectly by causing a peripheral action that will result in a μDMA
request.
By programming the μDMA controller using this method, a set of arbitrary transfers can be performed
based on a single DMA request.
Refer to Figure 9-3 on page 197 and Figure 9-4 on page 198, which show an example of operation
in Memory Scatter-Gather mode. This example shows a gather operation, where data in three
separate buffers in memory will be copied together into one buffer. Figure 9-3 on page 197 shows
how the application sets up a μDMA task list in memory that is used by the controller to perform
three sets of copy operations from different locations in memory. The primary control structure for
the channel that will be used for the operation is configured to copy from the task list to the alternate
control structure.
Figure 9-4 on page 198 shows the sequence as the μDMA controller peforms the three sets of copy
operations. First, using the primary control structure, the μDMA controller loads the alternate control
structure with task A. It then peforms the copy operation specified by task A, copying the data from
the source buffer A to the destination buffer. Next, the μDMA controller again uses the primary
control structure to load task B into the alternate control structure, and then performs the B operation
with the alternate control structure. The process is repeated for task C.
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Figure 9-3. Memory Scatter-Gather, Setup and Configuration
1
2
3
Source and Destination
Buffer in Memory
Task List in Memory
Channel Control
Table in Memory
4 WORDS (SRC A)
SRC
A
DST
“TASK” A
ITEMS=4
SRC
SRC
DST
DST
“TASK” B
ITEMS=12
Channel Primary
Control Structure
ITEMS=16
16 WORDS (SRC B)
B
SRC
DST
“TASK” C
ITEMS=1
SRC
DST
Channel Alternate
Control Structure
ITEMS=n
1 WORD (SRC C)
C
4 (DEST A)
16 (DEST B)
1 (DEST C)
NOTES:
1. Application has a need to copy data items from three separate location in memory into one combined buffer.
2. Application sets up uDMA “task list” in memory, which contains the pointers and control configuration for three
uDMA copy “tasks.”
3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the
alternate control structure, where it will be executed by the uDMA controller.
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Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence
Task List
in Memory
uDMA Control Table
in Memory
Buffers
in Memory
SRC A
SRC
SRC B
PRI
COPIED
DST
TASK A
TASK B
SRC C
SRC
ALT
COPIED
DST
TASK C
DEST A
DEST B
DEST C
Using the channel’s primary control structure, the uDMA
controller copies task A configuration to the channel’s
alternate control structure.
Task List
in Memory
Then, using the channel’s alternate control structure, the
uDMA controller copies data from the source buffer A to
the destination buffer.
uDMA Control Table
in Memory
Buffers
in Memory
SRC A
SRC B
SRC
PRI
DST
TASK A
TASK B
TASK C
SRC C
SRC
COPIED
ALT
COPIED
DST
DEST A
DEST B
DEST C
Using the channel’s primary control structure, the uDMA
controller copies task B configuration to the channel’s
alternate control structure.
Task List
in Memory
Then, using the channel’s alternate control structure, the
uDMA controller copies data from the source buffer B to
the destination buffer.
uDMA Control Table
in Memory
Buffers
in Memory
SRC A
SRC
SRC B
PRI
DST
TASK A
SRC C
SRC
TASK B
TASK C
ALT
DST
DEST A
COPIED
COPIED
DEST B
DEST C
Using the channel’s primary control structure, the uDMA
controller copies task C configuration to the channel’s
alternate control structure.
Then, using the channel’s alternate control structure, the
uDMA controller copies data from the source buffer C to
the destination buffer.
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9.2.6.6
Peripheral Scatter-Gather
Peripheral Scatter-Gather mode is very similar to Memory Scatter-Gather, except that the transfers
are controlled by a peripheral making a DMA request. Upon detecting a DMA request from the
peripheral, the μDMA controller will use the primary control structure to copy one entry from the list
to the alternate control structure, and then perform the transfer. At the end of this transfer, the next
transfer will only be started if the peripheral again asserts a DMA request. The μDMA controller will
continue to perform transfers from the list only when the peripheral is making a request, until the
last transfer is complete. A completion interrupt will only be generated after the last transfer.
By programming the μDMA controller using this method, data can be transferred to or from a
peripheral from a set of arbitrary locations whenever the peripheral is ready to transfer data.
Refer to Figure 9-5 on page 200 and Figure 9-6 on page 201, which show an example of operation
in Peripheral Scatter-Gather mode. This example shows a gather operation, where data from three
separate buffers in memory will be copied to a single peripheral data register. Figure 9-5 on page
200 shows how the application sets up a µDMA task list in memory that is used by the controller to
perform three sets of copy operations from different locations in memory. The primary control
structure for the channel that will be used for the operation is configured to copy from the task list
to the alternate control structure.
Figure 9-6 on page 201 shows the sequence as the µDMA controller peforms the three sets of copy
operations. First, using the primary control structure, the µDMA controller loads the alternate control
structure with task A. It then peforms the copy operation specified by task A, copying the data from
the source buffer A to the peripheral data register. Next, the µDMA controller again uses the primary
control structure to load task B into the alternate control structure, and then performs the B operation
with the alternate control structure. The process is repeated for task C.
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Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration
1
2
3
Source Buffer
in Memory
Task List in Memory
Channel Control
Table in Memory
4 WORDS (SRC A)
SRC
A
DST
“TASK” A
ITEMS=4
SRC
SRC
DST
DST
“TASK” B
ITEMS=12
Channel Primary
Control Structure
ITEMS=16
16 WORDS (SRC B)
B
SRC
DST
“TASK” C
ITEMS=1
SRC
DST
Channel Alternate
Control Structure
ITEMS=n
1 WORD (SRC C)
C
Peripheral Data
Register
DEST
NOTES:
1. Application has a need to copy data items from three separate location in memory into a peripheral data
register.
2. Application sets up uDMA “task list” in memory, which contains the pointers and control configuration for three
uDMA copy “tasks.”
3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the
alternate control structure, where it will be executed by the uDMA controller.
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Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence
Task List
in Memory
uDMA Control Table
in Memory
Buffers
in Memory
SRC A
SRC
SRC B
PRI
COPIED
DST
TASK A
TASK B
SRC C
SRC
ALT
COPIED
DST
TASK C
Using the channel’s primary control structure, the uDMA
controller copies task A configuration to the channel’s
alternate control structure.
Task List
in Memory
Peripheral
Data
Register
Then, using the channel’s alternate control structure, the
uDMA controller copies data from the source buffer A to
the peripheral data register.
uDMA Control Table
in Memory
Buffers
in Memory
SRC A
SRC
SRC B
PRI
DST
TASK A
TASK C
SRC C
SRC
TASK B
COPIED
ALT
COPIED
DST
Using the channel’s primary control structure, the uDMA
controller copies task B configuration to the channel’s
alternate control structure.
Task List
in Memory
Peripheral
Data
Register
Then, using the channel’s alternate control structure, the
uDMA controller copies data from the source buffer B to
the peripheral data register.
uDMA Control Table
in Memory
Buffers
in Memory
SRC A
SRC
SRC B
PRI
DST
TASK A
SRC C
SRC
TASK B
TASK C
ALT
DST
COPIED
COPIED
Using the channel’s primary control structure, the uDMA
controller copies task C configuration to the channel’s
alternate control structure.
Peripheral
Data
Register
Then, using the channel’s alternate control structure, the
uDMA controller copies data from the source buffer C to
the peripheral data register.
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9.2.7
Transfer Size and Increment
The μDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination
data size must be the same for any given transfer. The source and destination address can be
auto-incremented by bytes, half-words, or words, or can be set to no increment. The source and
destination address increment values can be set independently, and it is not necessary for the
address increment to match the data size as long as the increment is the same or larger than the
data size. For example, it is possible to perform a transfer using 8-bit data size, but using an address
increment of full words (4 bytes). The data to be transferred must be aligned in memory according
to the data size (8, 16, or 32 bits).
Table 9-5 on page 202 shows the configuration to read from a peripheral that supplies 8-bit data.
Table 9-5. μDMA Read Example: 8-Bit Peripheral
Field
Configuration
Source data size
8 bits
Destination data size
8 bits
Source address increment
No increment
Destination address increment Byte
9.2.8
Source end pointer
Peripheral read FIFO register
Destination end pointer
End of the data buffer in memory
Peripheral Interface
Each peripheral that supports μDMA has a DMA single request and/or burst request signal that is
asserted when the device is ready to transfer data. The request signal can be disabled or enabled
by using the DMA Channel Request Mask Set (DMAREQMASKSET) and DMA Channel Request
Mask Clear (DMAREQMASKCLR) registers. The DMA request signal is disabled, or masked, when
the channel request mask bit is set. When the request is not masked, the DMA channel is configured
correctly and enabled, and the peripheral asserts the DMA request signal, the μDMA controller will
begin the transfer.
When a DMA transfer is complete, the μDMA controller asserts a DMA Done signal, which is routed
through the interrupt vector of the peripheral. Therefore, if DMA is used to transfer data for a
peripheral and interrupts are used, then the interrupt handler for that peripheral must be designed
to handle the μDMA transfer completion interrupt. When DMA is enabled for a peripheral, the μDMA
controller will mask the normal interrupts for a peripheral. This means that when a large amount of
data is transferred using DMA, instead of receiving multiple interrupts from the peripheral as data
flows, the processor will only receive one interrupt when the transfer is complete.
The interrupt request from the μDMA controller is automatically cleared when the interrupt handler
is activated.
9.2.9
Software Request
There is a dedicated μDMA channel for software-initiated transfers. This channel also has a dedicated
interrupt to signal completion of a DMA transfer. A transfer is initiated by software by first configuring
and enabling the transfer, and then issuing a software request using the DMA Channel Software
Request (DMASWREQ) register. For software-based transfers, the Auto transfer mode should be
used.
It is possible to initiate a transfer on any channel using the DMASWREQ register. If a request is
initiated by software using a peripheral DMA channel, then the completion interrupt will occur on
the interrupt vector for the peripheral instead of the software interrupt vector. This means that any
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channel may be used for software requests as long as the corresponding peripheral is not using
μDMA.
9.2.10
Interrupts and Errors
When a DMA transfer is complete, the μDMA controller will generate a completion interrupt on the
interrupt vector of the peripheral. If the transfer uses the software DMA channel, then the completion
interrupt will occur on the dedicated software DMA interrupt vector.
If the μDMA controller encounters a bus or memory protection error as it attempts to perform a data
transfer, it will disable the DMA channel that caused the error, and generate an interrupt on the
μDMA Error interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR)
register to determine if an error is pending. The ERRCLR bit will be set if an error occurred. The error
can be cleared by writing a 1 to the ERRCLR bit.
Table 9-6 on page 203 shows the dedicated interrupt assignments for the μDMA controller.
Table 9-6. μDMA Interrupt Assignments
Interrupt Assignment
46
μDMA Software Channel Transfer
47
μDMA Error
9.3
Initialization and Configuration
9.3.1
Module Initialization
Before the μDMA controller can be used, it must be enabled in the System Control block and in the
peripheral. The location of the channel control structure must also be programmed.
The following steps should be performed one time during system initialization:
1. The μDMA peripheral must be enabled in the System Control block. To do this, set the UDMA
bit of the System Control RCGC2 register.
2. Enable the μDMA controller by setting the MASTEREN bit of the DMA Configuration (DMACFG)
register.
3. Program the location of the channel control table by writing the base address of the table to the
DMA Channel Control Base Pointer (DMACTLBASE) register. The base address must be
aligned on a 1024-byte boundary.
9.3.2
Configuring a Memory-to-Memory Transfer
μDMA channel 30 is dedicated for software-initiated transfers. However, any channel can be used
for software-initiated, memory-to-memory transfer if the associated peripheral is not being used.
9.3.2.1
Configure the Channel Attributes
First, configure the channel attributes:
1. Set bit 30 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear
(DMAPRIOCLR) registers to set the channel to High priority or Default priority.
2. Set bit 30 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the
primary channel control structure for this transfer.
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3. Set bit 30 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the
μDMA controller to respond to single and burst requests.
4. Set bit 30 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow
the μDMA controller to recognize requests for this channel.
9.3.2.2
Configure the Channel Control Structure
Now the channel control structure must be configured.
This example will transfer 256 32-bit words from one memory buffer to another. Channel 30 is used
for a software transfer, and the control structure for channel 30 is at offset 0x1E0 of the channel
control table. The channel control structure for channel 30 is located at the offsets shown in Table
9-7 on page 204.
Table 9-7. Channel Control Structure Offsets for Channel 30
Offset
Description
Control Table Base + 0x1E0 Channel 30 Source End Pointer
Control Table Base + 0x1E4 Channel 30 Destination End Pointer
Control Table Base + 0x1E8 Channel 30 Control Word
Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
1. Set the source end pointer at offset 0x1E0 to the address of the source buffer + 0x3FC.
2. Set the destination end pointer at offset 0x1E4 to the address of the destination buffer + 0x3FC.
The control word at offset 0x1E8 must be programmed according to Table 9-8 on page 204.
Table 9-8. Channel Control Word Configuration for Memory Transfer Example
Field in DMACHCTL
Bits
Value
DSTINC
31:30
2
32-bit destination address increment
DSTSIZE
29:28
2
32-bit destination data size
SRCINC
27:26
2
32-bit source address increment
SRCSIZE
25:24
2
32-bit source data size
reserved
23:18
0
Reserved
ARBSIZE
17:14
3
Arbitrates after 8 transfers
XFERSIZE
13:4
255
3
0
N/A for this transfer type
2:0
2
Use Auto-request transfer mode
NXTUSEBURST
XFERMODE
9.3.2.3
Description
Transfer 256 items
Start the Transfer
Now the channel is configured and is ready to start.
1. Enable the channel by setting bit 30 of the DMA Channel Enable Set (DMAENASET) register.
2. Issue a transfer request by setting bit 30 of the DMA Channel Software Request (DMASWREQ)
register.
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The DMA transfer will now take place. If the interrupt is enabled, then the processor will be notified
by interrupt when the transfer is complete. If needed, the status can be checked by reading bit 30
of the DMAENASET register. This bit will be automatically cleared when the transfer is complete.
The status can also be checked by reading the XFERMODE field of the channel control word at offset
0x1E8. This field will automatically be set to 0 at the end of the transfer.
9.3.3
Configuring a Peripheral for Simple Transmit
This example will set up the μDMA controller to transmit a buffer of data to a peripheral. The peripheral
has a transmit FIFO with a trigger level of 4. The example peripheral will use μDMA channel 7.
9.3.3.1
Configure the Channel Attributes
First, configure the channel attributes:
1. Set bit 7 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear
(DMAPRIOCLR) registers to set the channel to High priority or Default priority.
2. Set bit 7 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the
primary channel control structure for this transfer.
3. Set bit 7 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the
μDMA controller to respond to single and burst requests.
4. Set bit 7 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow
the μDMA controller to recognize requests for this channel.
9.3.3.2
Configure the Channel Control Structure
Now the channel control structure must be configured. This example will transfer 64 8-bit bytes from
a memory buffer to the peripheral's transmit FIFO register. This example uses μDMA channel 7,
and the control structure for channel 7 is at offset 0x070 of the channel control table. The channel
control structure for channel 7 is located at the offsets shown in Table 9-9 on page 205.
Table 9-9. Channel Control Structure Offsets for Channel 7
Offset
Description
Control Table Base + 0x070 Channel 7 Source End Pointer
Control Table Base + 0x074 Channel 7 Destination End Pointer
Control Table Base + 0x078 Channel 7 Control Word
Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
Since the peripheral pointer does not change, it simply points to the peripheral's data register.
1. Set the source end pointer at offset 0x070 to the address of the source buffer + 0x3F.
2. Set the destination end pointer at offset 0x074 to the address of the peripheral's transmit FIFO
register.
The control word at offset 0x078 must be programmed according to Table 9-10 on page 206.
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Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example
Field in DMACHCTL
Bits
Value
DSTINC
31:30
3
Destination address does not increment
DSTSIZE
29:28
0
8-bit destination data size
SRCINC
27:26
0
8-bit source address increment
SRCSIZE
25:24
0
8-bit source data size
reserved
23:18
0
Reserved
ARBSIZE
17:14
2
Arbitrates after 4 transfers
XFERSIZE
13:4
63
Transfer 64 items
3
0
N/A for this transfer type
2:0
1
Use Basic transfer mode
NXTUSEBURST
XFERMODE
Note:
9.3.3.3
Description
In this example, it is not important if the peripheral makes a single request or a burst request.
Since the peripheral has a FIFO that will trigger at a level of 4, the arbitration size is set to
4. If the peripheral does make a burst request, then 4 bytes will be transferred, which is
what the FIFO can accomodate. If the peripheral makes a single request (if there is any
space in the FIFO), then one byte will be transferred at a time. If it is important to the
application that transfers only be made in bursts, then the channel useburst SET[n] bit
should be set by writing a 1 to bit 7 of the DMA Channel Useburst Set
(DMAUSEBURSTSET) register.
Start the Transfer
Now the channel is configured and is ready to start.
1. Enable the channel by setting bit 7 of the DMA Channel Enable Set (DMAENASET) register.
The μDMA controller is now configured for transfer on channel 7. The controller will make transfers
to the peripheral whenever the peripheral asserts a DMA request. The transfers will continue until
the entire buffer of 64 bytes has been transferred. When that happens, the μDMA controller will
disable the channel and set the XFERMODE field of the channel control word to 0 (Stopped). The
status of the transfer can be checked by reading bit 7 of the DMA Channel Enable Set
(DMAENASET) register. This bit will be automatically cleared when the transfer is complete. The
status can also be checked by reading the XFERMODE field of the channel control word at offset
0x078. This field will automatically be set to 0 at the end of the transfer.
If peripheral interrupts were enabled, then the peripheral interrupt handler would receive an interrupt
when the entire transfer was complete.
9.3.4
Configuring a Peripheral for Ping-Pong Receive
This example will set up the μDMA controller to continuously receive 8-bit data from a peripheral
into a pair of 64 byte buffers. The peripheral has a receive FIFO with a trigger level of 8. The example
peripheral will use μDMA channel 8.
9.3.4.1
Configure the Channel Attributes
First, configure the channel attributes:
1. Set bit 7 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear
(DMAPRIOCLR) registers to set the channel to High priority or Default priority.
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2. Set bit 7 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the
primary channel control structure for this transfer.
3. Set bit 7 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the
μDMA controller to respond to single and burst requests.
4. Set bit 7 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow
the μDMA controller to recognize requests for this channel.
9.3.4.2
Configure the Channel Control Structure
Now the channel control structure must be configured. This example will transfer 8-bit bytes from
the peripheral's receive FIFO register into two memory buffers of 64 bytes each. As data is received,
when one buffer is full, the μDMA controller switches to use the other.
To use Ping-Pong buffering, both primary and alternate channel control structures must be used.
The primary control structure for channel 8 is at offset 0x080 of the channel control table, and the
alternate channel control structure is at offset 0x280. The channel control structures for channel 8
are located at the offsets shown in Table 9-11 on page 207.
Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8
Offset
Description
Control Table Base + 0x080 Channel 8 Primary Source End Pointer
Control Table Base + 0x084 Channel 8 Primary Destination End Pointer
Control Table Base + 0x088 Channel 8 Primary Control Word
Control Table Base + 0x280 Channel 8 Alternate Source End Pointer
Control Table Base + 0x284 Channel 8 Alternate Destination End Pointer
Control Table Base + 0x288 Channel 8 Alternate Control Word
Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
Since the peripheral pointer does not change, it simply points to the peripheral's data register. Both
the primary and alternate sets of pointers must be configured.
1. Set the primary source end pointer at offset 0x080 to the address of the peripheral's receive
buffer.
2. Set the primary destination end pointer at offset 0x084 to the address of ping-pong buffer A +
0x3F.
3. Set the alternate source end pointer at offset 0x280 to the address of the peripheral's receive
buffer.
4. Set the alternate destination end pointer at offset 0x284 to the address of ping-pong buffer B +
0x3F.
The primary control word at offset 0x088, and the alternate control word at offset 0x288 must be
programmed according to Table 9-10 on page 206. Both control words are initially programmed the
same way.
1. Program the primary channel control word at offset 0x088 according to Table 9-12 on page 208.
2. Program the alternate channel control word at offset 0x288 according to Table 9-12 on page 208.
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Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example
Field in DMACHCTL
Bits
Value
DSTINC
31:30
0
8-bit destination address increment
DSTSIZE
29:28
0
8-bit destination data size
SRCINC
27:26
3
Source address does not increment
SRCSIZE
25:24
0
8-bit source data size
reserved
23:18
0
Reserved
ARBSIZE
17:14
3
Arbitrates after 8 transfers
XFERSIZE
13:4
63
Transfer 64 items
3
0
N/A for this transfer type
2:0
3
Use Ping-Pong transfer mode
NXTUSEBURST
XFERMODE
Note:
9.3.4.3
Description
In this example, it is not important if the peripheral makes a single request or a burst request.
Since the peripheral has a FIFO that will trigger at a level of 8, the arbitration size is set to
8. If the peripheral does make a burst request, then 8 bytes will be transferred, which is
what the FIFO can accomodate. If the peripheral makes a single request (if there is any
data in the FIFO), then one byte will be transferred at a time. If it is important to the
application that transfers only be made in bursts, then the channel useburst SET[n] bit
should be set by writing a 1 to bit 8 of the DMA Channel Useburst Set
(DMAUSEBURSTSET) register.
Configure the Peripheral Interrupt
In order to use μDMA Ping-Pong mode, it is best to use an interrupt handler. (It is also possible to
use ping-pong mode without interrupts by polling). The interrupt handler will be triggered after each
buffer is complete.
1. Configure and enable an interrupt handler for the peripheral.
9.3.4.4
Enable the μDMA Channel
Now the channel is configured and is ready to start.
1. Enable the channel by setting bit 8 of the DMA Channel Enable Set (DMAENASET) register.
9.3.4.5
Process Interrupts
The μDMA controller is now configured and enabled for transfer on channel 8. When the peripheral
asserts the DMA request signal, the μDMA controller will make transfers into buffer A using the
primary channel control structure. When the primary transfer to buffer A is complete, it will switch
to the alternate channel control structure and make transfers into buffer B. At the same time, the
primary channel control word mode field will be set to indicate Stopped, and an interrupt will be
triggered.
When an interrupt is triggered, the interrupt handler must determine which buffer is complete and
process the data, or set a flag that the data needs to be processed by non-interrupt buffer processing
code. Then the next buffer transfer must be set up.
In the interrupt handler:
1. Read the primary channel control word at offset 0x088 and check the XFERMODE field. If the
field is 0, this means buffer A is complete. If buffer A is complete, then:
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a. Process the newly received data in buffer A, or signal the buffer processing code that buffer
A has data available.
b. Reprogram the primary channel control word at offset 0x88 according to Table
9-12 on page 208.
2. Read the alternate channel control word at offset 0x288 and check the XFERMODE field. If the
field is 0, this means buffer B is complete. If buffer B is complete, then:
a. Process the newly received data in buffer B, or signal the buffer processing code that buffer
B has data available.
b. Reprogram the alternate channel control word at offset 0x288 according to Table
9-12 on page 208.
9.4
Register Map
Table 9-13 on page 209 lists the μDMA channel control structures and registers. The channel control
structure shows the layout of one entry in the channel control table. The channel control table is
located in system memory, and the location is determined by the application, that is, the base
address is n/a (not applicable). In the table below, the offset for the channel control structures is the
offset from the entry in the channel control table. See “Channel Configuration” on page 192 and Table
9-3 on page 193 for a description of how the entries in the channel control table are located in memory.
The μDMA register addresses are given as a hexadecimal increment, relative to the μDMA base
address of 0x400F.F000.
Table 9-13. μDMA Register Map
Offset
Name
Type
Reset
Description
See
page
μDMA Channel Control Structure
0x000
DMASRCENDP
R/W
-
DMA Channel Source Address End Pointer
211
0x004
DMADSTENDP
R/W
-
DMA Channel Destination Address End Pointer
212
0x008
DMACHCTL
R/W
-
DMA Channel Control Word
213
DMA Status
217
DMA Configuration
219
μDMA Registers
0x000
DMASTAT
RO
0x001F.0000
0x004
DMACFG
WO
-
0x008
DMACTLBASE
R/W
0x0000.0000
DMA Channel Control Base Pointer
220
0x00C
DMAALTBASE
RO
0x0000.0200
DMA Alternate Channel Control Base Pointer
221
0x010
DMAWAITSTAT
RO
0x0000.0000
DMA Channel Wait on Request Status
222
0x014
DMASWREQ
WO
-
DMA Channel Software Request
223
0x018
DMAUSEBURSTSET
R/W
0x0000.0000
DMA Channel Useburst Set
224
0x01C
DMAUSEBURSTCLR
WO
-
DMA Channel Useburst Clear
226
0x020
DMAREQMASKSET
R/W
0x0000.0000
DMA Channel Request Mask Set
227
0x024
DMAREQMASKCLR
WO
-
DMA Channel Request Mask Clear
229
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Preliminary
Micro Direct Memory Access (μDMA)
Offset
Name
Type
Reset
0x028
DMAENASET
R/W
0x0000.0000
0x02C
DMAENACLR
WO
-
0x030
DMAALTSET
R/W
0x0000.0000
0x034
DMAALTCLR
WO
-
0x038
DMAPRIOSET
R/W
0x0000.0000
0x03C
DMAPRIOCLR
WO
-
0x04C
DMAERRCLR
R/W
0xFD0
DMAPeriphID4
0xFE0
Description
See
page
DMA Channel Enable Set
230
DMA Channel Enable Clear
232
DMA Channel Primary Alternate Set
233
DMA Channel Primary Alternate Clear
235
DMA Channel Priority Set
236
DMA Channel Priority Clear
238
0x0000.0000
DMA Bus Error Clear
239
RO
0x0000.0004
DMA Peripheral Identification 4
245
DMAPeriphID0
RO
0x0000.0030
DMA Peripheral Identification 0
241
0xFE4
DMAPeriphID1
RO
0x0000.00B2
DMA Peripheral Identification 1
242
0xFE8
DMAPeriphID2
RO
0x0000.000B
DMA Peripheral Identification 2
243
0xFEC
DMAPeriphID3
RO
0x0000.0000
DMA Peripheral Identification 3
244
0xFF0
DMAPCellID0
RO
0x0000.000D
DMA PrimeCell Identification 0
246
0xFF4
DMAPCellID1
RO
0x0000.00F0
DMA PrimeCell Identification 1
247
0xFF8
DMAPCellID2
RO
0x0000.0005
DMA PrimeCell Identification 2
248
0xFFC
DMAPCellID3
RO
0x0000.00B1
DMA PrimeCell Identification 3
249
9.5
μDMA Channel Control Structure
The μDMA Channel Control Structure holds the DMA transfer settings for a DMA channel. Each
channel has two control structures, which are located in a table in system memory. Refer to “Channel
Configuration” on page 192 for an explanation of the Channel Control Table and the Channel Control
Structure.
The channel control structure is one entry in the channel control table. There is a primary and
alternate structure for each channel. The primary control structures are located at offsets 0x0, 0x10,
0x20 and so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and
so on.
210
April 08, 2008
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LM3S3748 Microcontroller
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset
0x000
DMA Channel Source Address End Pointer (DMASRCENDP) is part of the Channel Control
Structure, and is used to specify the source address for a DMA transfer.
DMA Channel Source Address End Pointer (DMASRCENDP)
Base n/a
Offset 0x000
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
Name
Type
Reset
31:0
ADDR
R/W
-
R/W
-
Description
Source Address End Pointer
Points to the last address of the DMA transfer source (inclusive). If the
source address is not incrementing, then this points at the source
location itself (such as a peripheral data register).
April 08, 2008
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Preliminary
Micro Direct Memory Access (μDMA)
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP),
offset 0x004
DMA Channel Destination Address End Pointer (DMADSTENDP) is part of the Channel Control
Structure, and is used to specify the destination address for a DMA transfer.
DMA Channel Destination Address End Pointer (DMADSTENDP)
Base n/a
Offset 0x004
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
Name
Type
Reset
31:0
ADDR
R/W
-
R/W
-
Description
Destination Address End Pointer
Points to the last address of the DMA transfer destination (inclusive). If
the destination address is not incrementing, then this points at the
destination location itself (such as a peripheral data register).
212
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LM3S3748 Microcontroller
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008
DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure, and is used
to specify parameters of a DMA transfer.
DMA Channel Control Word (DMACHCTL)
Base n/a
Offset 0x008
Type R/W, reset 31
30
DSTINC
Type
Reset
29
28
DSTSIZE
27
26
SRCINC
24
23
22
21
SRCSIZE
20
19
18
17
reserved
16
ARBSIZE
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
ARBSIZE
Type
Reset
25
R/W
-
R/W
-
XFERSIZE
Bit/Field
Name
Type
Reset
31:30
DSTINC
R/W
-
XFERMODE
NXTUSEBURST
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Description
Destination Address Increment
Sets the bits to control the destination address increment.
The address increment value must be equal or greater than the value
of the destination size (DSTSIZE).
Value Description
0x0
Byte
Increment by 8-bit locations.
0x1
Half-word
Increment by 16-bit locations.
0x2
Word
Increment by 32-bit locations.
0x3
No increment
Address remains set to the value of the Destination Address
End Pointer (DMADSTENDP) for the channel.
29:28
DSTSIZE
R/W
-
Destination Data Size
Sets the destination item data size.
Note:
You must set DSTSIZE to be the same as SRCSIZE.
Value Description
0x0
Byte
8-bit data size.
0x1
Half-word
16-bit data size.
0x2
Word
32-bit data size.
0x3
Reserved
April 08, 2008
213
Preliminary
Micro Direct Memory Access (μDMA)
Bit/Field
Name
Type
Reset
27:26
SRCINC
R/W
-
Description
Source Address Increment
Sets the bits to control the source address increment.
The address increment value must be equal or greater than the value
of the source size (SRCSIZE).
Value Description
0x0
Byte
Increment by 8-bit locations.
0x1
Half-word
Increment by 16-bit locations.
0x2
Word
Increment by 32-bit locations.
0x3
No increment
Address remains set to the value of the Source Address End
Pointer (DMASRCENDP) for the channel.
25:24
SRCSIZE
R/W
-
Source Data Size
Sets the source item data size.
Note:
You must set DSTSIZE to be the same as SRCSIZE.
Value Description
0x0
Byte
8-bit data size.
0x1
Half-word
16-bit data size.
0x2
Word
32-bit data size.
0x3
23:18
reserved
R/W
-
Reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
214
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LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
17:14
ARBSIZE
R/W
-
Description
Arbitration Size
Sets the number of DMA transfers that can occur before the controller
re-arbitrates. The possible arbitration rate settings represent powers of
2 and are shown below.
Value
Description
0x0
1 Transfer
Arbitrates after each DMA transfer.
0x1
2 Transfers
0x2
4 Transfers
0x3
8 Transfers
0x4
16 Transfers
0x5
32 Transfers
0x6
64 Transfers
0x7
128 Transfers
0x8
256 Transfers
0x9
512 Transfers
0xA-0xF 1024 Transfers
This means that no arbitration occurs during the DMA transfer
because the maximum transfer size is 1024.
13:4
XFERSIZE
R/W
-
Transfer Size (minus 1)
Sets the total number of items to transfer. The value of this field is 1
less than the number to transfer (value 0 means transfer 1 item). The
maximum value for this 10-bit field is 1023 which represents a transfer
size of 1024 items.
The transfer size is the number of items, not the number of bytes. If the
data size is 32 bits, then this value is the number of 32-bit words to
transfer.
The controller updates this field immediately prior to it entering the
arbitration process, so it contains the number of outstanding DMA items
that are necessary to complete the DMA cycle.
3
NXTUSEBURST
R/W
-
Next Useburst
Controls whether the useburst SET[n] bit is automatically set for the
last transfer of a peripheral scatter-gather operation. Normally, for the
last transfer, if the number of remaining items to transfer is less than
the arbitration size, the controller will use single transfers to complete
the transaction. If this bit is set, then the controller will only use a burst
transfer to complete the last transfer.
April 08, 2008
215
Preliminary
Micro Direct Memory Access (μDMA)
Bit/Field
Name
Type
Reset
2:0
XFERMODE
R/W
-
Description
DMA Transfer Mode
Since this register is in system RAM, it has no reset value. Therefore,
this field should be initialized to 0 before the channel is enabled.
The operating mode of the DMA cycle. Refer to “Transfer
Modes” on page 194 for a detailed explanation of transfer modes.
Value Description
0x0
Stop
Channel is stopped, or configuration data is invalid.
0x1
Basic
The controller must receive a new request, prior to it entering
the arbitration process, to enable the DMA cycle to complete.
0x2
Auto-Request
The initial request (software- or peripheral-initiated) is sufficient
to complete the entire transfer of XFERSIZE items without any
further requests.
0x3
Ping-Pong
The controller performs a DMA cycle using one of the channel
control structures. After the DMA cycle completes, it performs
a DMA cycle using the other channel control structure. After the
next DMA cycle completes (and provided that the host processor
has updated the original channel control data structure), it
performs a DMA cycle using the original channel control data
structure. The controller continues to perform DMA cycles until
it either reads an invalid data structure or the host processor
changes this field to 0x1 or 0x2. See “Ping-Pong” on page 194.
0x4
Memory Scatter-Gather
When the controller operates in Memory Scatter-Gather mode,
you must only use this value in the primary channel control data
structure. See “Memory Scatter-Gather” on page 196.
0x5
Alternate Memory Scatter-Gather
When the controller operates in Memory Scatter-Gather mode,
you must only use this value in the alternate channel control
data structure.
0x6
Peripheral Scatter-Gather
When the controller operates in Peripheral Scatter-Gather mode,
you must only use this value in the primary channel control data
structure. See “Peripheral Scatter-Gather” on page 199.
0x7
Alternate Peripheral Scatter-Gather
When the controller operates in Peripheral Scatter-Gather mode,
you must only use this value in the alternate channel control
data structure.
9.6
μDMA Register Descriptions
The register addresses given are relative to the μDMA base address of 0x400F.F000.
216
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 4: DMA Status (DMASTAT), offset 0x000
The DMA Status (DMASTAT) register returns the status of the controller. You cannot read this
register when the controller is in the reset state.
DMA Status (DMASTAT)
Base 0x400F.F000
Offset 0x000
Type RO, reset 0x001F.0000
31
30
29
28
27
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
26
25
24
23
22
21
20
19
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
10
9
8
7
6
5
4
3
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
17
16
RO
1
RO
1
RO
1
2
1
0
DMACHANS
reserved
Type
Reset
18
STATE
reserved
RO
0
MASTEN
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:21
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20:16
DMACHANS
RO
0x1F
Available DMA Channels Minus 1
This bit contains a value equal to the number of DMA channels the
controller is configured to use, minus one. That is, 32 DMA channels.
15:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
217
Preliminary
Micro Direct Memory Access (μDMA)
Bit/Field
Name
Type
Reset
Description
7:4
STATE
RO
0x00
Control State Machine State
Current state of the control state machine. State can be one of the
following.
Value
Description
0x0
Idle
0x1
Read Chan Control Data
Reading channel controller data.
0x2
Read Source End Ptr
Reading source end pointer.
0x3
Read Dest End Ptr
Reading destination end pointer.
0x4
Read Source Data
Reading source data.
0x5
Write Dest Data
Writing destination data.
0x6
Wait for Req Clear
Waiting for DMA request to clear.
0x7
Write Chan Control Data
Writing channel controller data.
0x8
Stalled
0x9
Done
0xA-0xF Undefined
3:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
MASTEN
RO
0x00
Master Enable
Returns status of the controller.
Value Description
0
Disabled
1
Enabled
218
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 5: DMA Configuration (DMACFG), offset 0x004
The DMACFG register controls the configuration of the controller.
DMA Configuration (DMACFG)
Base 0x400F.F000
Offset 0x004
Type WO, reset 31
30
29
28
27
26
25
24
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
reserved
Type
Reset
reserved
Type
Reset
WO
-
MASTEN
WO
-
Bit/Field
Name
Type
Reset
Description
31:1
reserved
WO
-
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
MASTEN
WO
-
Controller Master Enable
Enables the controller.
Value Description
0
Disables
1
Enables
April 08, 2008
219
Preliminary
Micro Direct Memory Access (μDMA)
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008
The DMACTLBASE register must be configured so that the base pointer points to a location in
system memory.
The amount of system memory that you must assign to the controller depends on the number of
DMA channels used and whether you configure it to use the alternate channel control data structure.
See “Channel Configuration” on page 192 for details about the Channel Control Table. The base
address must be aligned on a 1024-byte boundary. You cannot read this register when the controller
is in the reset state.
DMA Channel Control Base Pointer (DMACTLBASE)
Base 0x400F.F000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
ADDR
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
reserved
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:10
ADDR
R/W
0x00
Channel Control Base Address
Pointer to the base address of the channel control table. The base
address must be 1024-byte aligned.
9:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
220
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE),
offset 0x00C
The DMAALTBASE register returns the base address of the alternate channel control data. This
register removes the necessity for application software to calculate the base address of the alternate
channel control structures. You cannot read this register when the controller is in the reset state.
DMA Alternate Channel Control Base Pointer (DMAALTBASE)
Base 0x400F.F000
Offset 0x00C
Type RO, reset 0x0000.0200
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
ADDR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
ADDR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
Bit/Field
Name
Type
Reset
Description
31:0
ADDR
RO
0x200
Alternate Channel Address Pointer
Provides the base address of the alternate channel control structures.
April 08, 2008
221
Preliminary
Micro Direct Memory Access (μDMA)
Register 8: DMA Channel Wait on Request Status (DMAWAITSTAT), offset
0x010
This read-only register indicates that the μDMA channel is waiting on a request. A peripheral can
pull this Low to hold off the μDMA from performing a single request until the peripheral is ready for
a burst request. The use of this feature is dependent on the design of the peripheral and is used to
enhance performance of the μDMA with that peripheral. You cannot read this register when the
controller is in the reset state.
DMA Channel Wait on Request Status (DMAWAITSTAT)
Base 0x400F.F000
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WAITREQ[n]
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WAITREQ[n]
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:0
WAITREQ[n]
RO
0x00
Channel [n] Wait Status
Channel wait on request status. For each channel 0 through 31, a 1 in
the corresponding bit field indicates that the channel is waiting on a
request.
222
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014
Each bit of the DMASWREQ register represents the corresponding DMA channel. When you set a
bit, it generates a request for the specified DMA channel.
DMA Channel Software Request (DMASWREQ)
Base 0x400F.F000
Offset 0x014
Type WO, reset 31
30
29
28
27
26
25
24
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
SWREQ[n]
Type
Reset
SWREQ[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
SWREQ[n]
WO
-
WO
-
Description
Channel [n] Software Request
For each channel 0 through 31, write a 1 to the corresponding bit field
to generate a software DMA request for that DMA channel. Writing a 0
does not create a DMA request for the corresponding channel.
April 08, 2008
223
Preliminary
Micro Direct Memory Access (μDMA)
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018
Each bit of the DMAUSEBURSTSET register represents the corresponding DMA channel. Writing
a 1 disables the peripheral's single request input from generating requests, and therefore only the
peripheral's burst request generates requests. Reading the register returns the status of useburst.
When there are fewer items remaining to transfer than the arbitration (burst) size, the controller
automatically clears the useburst bit to 0. This enables the remaining items to transfer using single
requests. This bit should not be set for a peripheral's channel that does not support the burst request
model.
Refer to “Request Types” on page 192 for more details about request types.
DMAUSEBURSTSET Reads
DMA Channel Useburst Set (DMAUSEBURSTSET)
Base 0x400F.F000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SET[n]
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
15
14
13
12
11
10
9
8
SET[n]
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit/Field
Name
Type
Reset
Description
31:0
SET[n]
R
0x00
Channel [n] Useburst Set
Returns the useburst status of channel [n].
Value Description
0
Single and Burst
DMA channel [n] responds to single or burst requests.
1
Burst Only
DMA channel [n] responds only to burst requests.
224
April 08, 2008
Preliminary
LM3S3748 Microcontroller
DMAUSEBURSTSET Writes
DMA Channel Useburst Set (DMAUSEBURSTSET)
Base 0x400F.F000
Offset 0x018
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
SET[n]
Type
Reset
SET[n]
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:0
SET[n]
W
0x00
Channel [n] Useburst Set
Sets useburst bit on channel [n].
Value Description
0
No Effect
Use the DMAUSEBURSTCLR register to clear bit [n] to 0.
1
Burst Only
DMA channel [n] responds only to burst requests.
April 08, 2008
225
Preliminary
Micro Direct Memory Access (μDMA)
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C
Each bit of the DMAUSEBURSTCLR register represents the corresponding DMA channel. Writing
a 1 enables dma_sreq[n] to generate requests.
DMA Channel Useburst Clear (DMAUSEBURSTCLR)
Base 0x400F.F000
Offset 0x01C
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
CLR[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
Description
Channel [n] Useburst Clear
Clears useburst bit on channel [n].
Value Description
0
No Effect
Use the DMAUSEBURSTSET to set bit [n] to 1.
1
Single and Burst
DMA channel [n] responds to single and burst requests.
226
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset
0x020
Each bit of the DMAREQMASKSET register represents the corresponding DMA channel. Writing
a 1 disables DMA requests for the channel. Reading the register returns the request mask status.
When a μDMA channel's request is masked, that means the peripheral can no longer request μDMA
transfers. The channel can then be used for software-initiated transfers.
DMAREQMASKSET Reads
DMA Channel Request Mask Set (DMAREQMASKSET)
Base 0x400F.F000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SET[n]
Type
Reset
SET[n]
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:0
SET[n]
R
0x00
Channel [n] Request Mask Set
Returns the channel request mask status.
Value Description
0
Enabled
External requests are not masked for channel [n].
1
Masked
External requests are masked for channel [n].
DMAREQMASKSET Writes
DMA Channel Request Mask Set (DMAREQMASKSET)
Base 0x400F.F000
Offset 0x020
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
SET[n]
Type
Reset
SET[n]
Type
Reset
April 08, 2008
227
Preliminary
Micro Direct Memory Access (μDMA)
Bit/Field
Name
Type
Reset
Description
31:0
SET[n]
W
0x00
Channel [n] Request Mask Set
Masks (disables) the corresponding channel [n] from generating DMA
requests.
Value Description
0
No Effect
Use the DMAREQMASKCLR register to clear the request mask.
1
Masked
Masks (disables) DMA requests on channel [n].
228
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset
0x024
Each bit of the DMAREQMASKCLR register represents the corresponding DMA channel. Writing
a 1 clears the request mask for the channel, and enables the channel to receive DMA requests.
DMA Channel Request Mask Clear (DMAREQMASKCLR)
Base 0x400F.F000
Offset 0x024
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLR[n]
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
Description
Channel [n] Request Mask Clear
Set the appropriate bit to clear the DMA request mask for channel [n].
This will enable DMA requests for the channel.
Value Description
0
No Effect
Use the DMAREQMASKSET register to set the request mask.
1
Clear Mask
Clears the request mask for the DMA channel. This enables
DMA requests for the channel.
April 08, 2008
229
Preliminary
Micro Direct Memory Access (μDMA)
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028
Each bit of the DMAENASET register represents the corresponding DMA channel. Writing a 1
enables the DMA channel. Reading the register returns the enable status of the channels. If a
channel is enabled but the request mask is set (DMAREQMASKSET), then the channel can be
used for software-initiated transfers.
DMAENASET Reads
DMA Channel Enable Set (DMAENASET)
Base 0x400F.F000
Offset 0x028
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SET[n]
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
15
14
13
12
11
10
9
8
SET[n]
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit/Field
Name
Type
Reset
Description
31:0
SET[n]
R
0x00
Channel [n] Enable Set
Returns the enable status of the channels.
Value Description
0
Disabled
1
Enabled
DMAENASET Writes
DMA Channel Enable Set (DMAENASET)
Base 0x400F.F000
Offset 0x028
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CHENSET[n]
Type
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
15
14
13
12
11
10
9
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
8
7
6
5
4
3
2
1
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
CHENSET[n]
Type
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
230
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
Description
31:0
CHENSET[n]
W
0x00
Channel [n] Enable Set
Enables the corresponding channels.
Note:
The controller disables a channel when it completes the DMA
cycle.
Value Description
0
No Effect
Use the DMAENACLR register to disable a channel.
1
Enable
Enables channel [n].
April 08, 2008
231
Preliminary
Micro Direct Memory Access (μDMA)
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C
Each bit of the DMAENACLR register represents the corresponding DMA channel. Writing a 1
disables the specified DMA channel.
DMA Channel Enable Clear (DMAENACLR)
Base 0x400F.F000
Offset 0x02C
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
CLR[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
Description
Clear Channel [n] Enable
Set the appropriate bit to disable the corresponding DMA channel.
Note:
The controller disables a channel when it completes the DMA
cycle.
Value Description
0
No Effect
Use the DMAENASET register to enable DMA channels.
1
Disable
Disables channel [n].
232
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030
Each bit of the DMAALTSET register represents the corresponding DMA channel. Writing a 1
configures the DMA channel to use the alternate control data structure. Reading the register returns
the status of which control data structure is in use for the corresponding DMA channel.
DMAALTSET Reads
DMA Channel Primary Alternate Set (DMAALTSET)
Base 0x400F.F000
Offset 0x030
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SET[n]
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
15
14
13
12
11
10
9
8
SET[n]
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit/Field
Name
Type
Reset
Description
31:0
SET[n]
R
0x00
Channel [n] Alternate Set
Returns the channel control data structure status.
Value Description
0
Primary
DMA channel [n] is using the primary control structure.
1
Alternate
DMA channel [n] is using the alternate control structure.
DMAALTSET Writes
DMA Channel Primary Alternate Set (DMAALTSET)
Base 0x400F.F000
Offset 0x030
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
7
6
5
4
3
2
1
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
SET[n]
Type
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
15
14
13
12
11
10
9
8
SET[n]
Type
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
April 08, 2008
233
Preliminary
Micro Direct Memory Access (μDMA)
Bit/Field
Name
Type
Reset
Description
31:0
SET[n]
W
0x00
Channel [n] Alternate Set
Selects the alternate channel control data structure for the corresponding
DMA channel.
Note:
For Ping-Pong and Scatter-Gather DMA cycle types, the
controller automatically sets these bits to select the alternate
channel control data structure.
Value Description
0
No Effect
Use the DMAALTCLR register to set bit [n] to 0.
1
Alternate
Selects the alternate control data structure for channel [n].
234
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset
0x034
Each bit of the DMAALTCLR register represents the corresponding DMA channel. Writing a 1
configures the DMA channel to use the primary control data structure.
DMA Channel Primary Alternate Clear (DMAALTCLR)
Base 0x400F.F000
Offset 0x034
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLR[n]
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
Description
Channel [n] Alternate Clear
Set the appropriate bit to select the primary control data structure for
the corresponding DMA channel.
Note:
For Ping-Pong and Scatter-Gather DMA cycle types, the
controller sets these bits to select the primary channel control
data structure.
Value Description
0
No Effect
Use the DMAALTSET register to select the alternate control
data structure.
1
Primary
Selects the primary control data structure for channel [n].
April 08, 2008
235
Preliminary
Micro Direct Memory Access (μDMA)
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038
Each bit of the the DMAPRIOSET register represents the corresponding DMA channel. Writing a
1 configures the DMA channel to have a high priority level. Reading the register returns the status
of the channel priority mask.
DMAPRIOSET Reads
DMA Channel Priority Set (DMAPRIOSET)
Base 0x400F.F000
Offset 0x038
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SET[n]
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
15
14
13
12
11
10
9
8
SET[n]
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit/Field
Name
Type
Reset
Description
31:0
SET[n]
R
0x00
Channel [n] Priority Set
Returns the channel priority status.
Value Description
0
Default Priority
DMA channel [n] is using the default priority level.
1
High Priority
DMA channel [n] is using a High Priority level.
DMAPRIOSET Writes
DMA Channel Priority Set (DMAPRIOSET)
Base 0x400F.F000
Offset 0x038
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
7
6
5
4
3
2
1
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
SET[n]
Type
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
15
14
13
12
11
10
9
8
SET[n]
Type
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
236
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
Description
31:0
SET[n]
W
0x00
Channel [n] Priority Set
Sets the channel priority to high.
Value Description
0
No Effect
Use the DMAPRIOCLR register to set channel [n] to the default
priority level.
1
High Priority
Sets DMA channel [n] to a High Priority level.
April 08, 2008
237
Preliminary
Micro Direct Memory Access (μDMA)
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C
Each bit of the DMAPRIOCLR register represents the corresponding DMA channel. Writing a 1
configures the DMA channel to have the default priority level.
DMA Channel Priority Clear (DMAPRIOCLR)
Base 0x400F.F000
Offset 0x03C
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
CLR[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
Description
Channel [n] Priority Clear
Set the appropriate bit to clear the high priority level for the specified
DMA channel.
Value Description
0
No Effect
Use the DMAPRIOSET register to set channel [n] to the High
priority level.
1
Default Priority
Sets DMA channel [n] to a Default priority level.
238
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C
The DMAERRCLR register is used to read and clear the DMA bus error status. The error status
will be set if the μDMA controller encountered a bus error while performing a DMA transfer. If a bus
error occurs on a channel, that channel will be automatically disabled by the μDMA controller. The
other channels are unaffected.
DMAERRCLR Reads
DMA Bus Error Clear (DMAERRCLR)
Base 0x400F.F000
Offset 0x04C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
ERRCLR
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
ERRCLR
R
0
DMA Bus Error Status
Value Description
0
Low
No bus error is pending.
1
High
Bus error is pending.
DMAERRCLR Writes
DMA Bus Error Clear (DMAERRCLR)
Base 0x400F.F000
Offset 0x04C
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
ERRCLR
RO
0
April 08, 2008
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
W
0
239
Preliminary
Micro Direct Memory Access (μDMA)
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
ERRCLR
W
0
DMA Bus Error Status
Clears the bus error.
Value Description
0
No Effect
Bus error status is unchanged.
1
Clear
Clears a pending bus error.
240
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 21: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0
The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset
values.
DMA Peripheral Identification 0 (DMAPeriphID0)
Base 0x400F.F000
Offset 0xFE0
Type RO, reset 0x0000.0030
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID0
RO
0x30
DMA Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
April 08, 2008
241
Preliminary
Micro Direct Memory Access (μDMA)
Register 22: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4
The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset
values.
DMA Peripheral Identification 1 (DMAPeriphID1)
Base 0x400F.F000
Offset 0xFE4
Type RO, reset 0x0000.00B2
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
1
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID1
RO
0xB2
DMA Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
242
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 23: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8
The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset
values.
DMA Peripheral Identification 2 (DMAPeriphID2)
Base 0x400F.F000
Offset 0xFE8
Type RO, reset 0x0000.000B
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID2
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID2
RO
0x0B
DMA Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
April 08, 2008
243
Preliminary
Micro Direct Memory Access (μDMA)
Register 24: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC
The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset
values.
DMA Peripheral Identification 3 (DMAPeriphID3)
Base 0x400F.F000
Offset 0xFEC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID3
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID3
RO
0x00
DMA Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
244
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 25: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0
The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset
values.
DMA Peripheral Identification 4 (DMAPeriphID4)
Base 0x400F.F000
Offset 0xFD0
Type RO, reset 0x0000.0004
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID4
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID4
RO
0x04
DMA Peripheral ID Register
Can be used by software to identify the presence of this peripheral.
April 08, 2008
245
Preliminary
Micro Direct Memory Access (μDMA)
Register 26: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0
The DMAPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
DMA PrimeCell Identification 0 (DMAPCellID0)
Base 0x400F.F000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID0
RO
0x0D
DMA PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
246
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 27: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4
The DMAPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
DMA PrimeCell Identification 1 (DMAPCellID1)
Base 0x400F.F000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID1
RO
0xF0
DMA PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
April 08, 2008
247
Preliminary
Micro Direct Memory Access (μDMA)
Register 28: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8
The DMAPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
DMA PrimeCell Identification 2 (DMAPCellID2)
Base 0x400F.F000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID2
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
DMA PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
248
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 29: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC
The DMAPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
DMA PrimeCell Identification 3 (DMAPCellID3)
Base 0x400F.F000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID3
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
DMA PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
April 08, 2008
249
Preliminary
General-Purpose Input/Outputs (GPIOs)
10
General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of eight physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, and Port H). The GPIO module
supports 3-61 programmable input/output pins, depending on the peripherals being used.
The GPIO module has the following features:
■ Two means of port access: either high speed (for single-cyle writes), or legacy for
backwards-compatibility with existing code
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ 5-V-tolerant input/outputs
■ Bit masking in both read and write operations through address lines
■ Pins configured as digital inputs are Schmitt-triggered.
■ Programmable control for GPIO pad configuration:
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured
with an 18-mA pad drive for high-current applications
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
10.1
Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the four JTAG/SWD pins (PC[3:0]). The
JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1
and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins
back to their default state.
Each GPIO port is a separate hardware instantiation of the same physical block(see Figure
10-1 on page 251 and Figure 10-2 on page 252). The LM3S3748 microcontroller contains eight ports
and thus eight of these physical GPIO blocks.
250
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Figure 10-1. Digital I/O Pads
Commit
Control
Mode
Control
GPIOLOCK
GPIOCR
GPIOAFSEL
Alternate Input
DEMUX
Alternate Output
Alternate Output Enable
MUX
Pad Output
MUX
Data
Control
Pad Input
Pad Output Enable
Digital
I/O Pad
Package I/O Pin
GPIO Input
GPIO Output
GPIODATA
GPIODIR
Interrupt
GPIO Output Enable
Interrupt
Control
Pad
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
April 08, 2008
251
Preliminary
General-Purpose Input/Outputs (GPIOs)
Figure 10-2. Analog/Digital I/O Pads
Commit
Control
Mode
Control
GPIOLOCK
GPIOCR
GPIOAFSEL
Alternate Input
DEMUX
Alternate Output
Alternate Output Enable
MUX
Pad Output
MUX
Data
Control
Pad Input
Pad Output Enable
Analog/Digital
I/O Pad
Package I/O Pin
GPIO Input
GPIO Output
GPIODATA
GPIODIR
Interrupt
GPIO Output Enable
Interrupt
Control
Pad
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
GPIOAMSEL
Analog Circuitry
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
10.1.1
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
ADC
(for PortE4 – 7 and
PortD4 – 7 pins that
connect to the ADC
input MUX)
Isolation
Circuit
Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
10.1.1.1 Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 260) is used to configure each individual pin as
an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and
the corresponding data register bit will capture and store the value on the GPIO port. When the data
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.
10.1.1.2 Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 259) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
252
April 08, 2008
Preliminary
LM3S3748 Microcontroller
During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 10-3 on page 253, where u is data unchanged by the write.
Figure 10-3. GPIODATA Write Example
ADDR[9:2]
0x098
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
1
1
0
1
0
0xEB
1
1
1
0
1
0
1
1
GPIODATA
u
u
1
u
u
0
1
u
7
6
5
4
3
2
1
0
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 10-4 on page 253.
Figure 10-4. GPIODATA Read Example
10.1.2
ADDR[9:2]
0x0C4
9
8
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
1
0
0
GPIODATA
1
0
1
1
1
1
1
0
Returned Value
0
0
1
1
0
0
0
0
7
6
5
4
3
2
1
0
Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
■ GPIO Interrupt Sense (GPIOIS) register (see page 261)
■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 262)
■ GPIO Interrupt Event (GPIOIEV) register (see page 263)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 264).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 265 and page 266). As the name implies, the GPIOMIS register only shows interrupt
April 08, 2008
253
Preliminary
General-Purpose Input/Outputs (GPIOs)
conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a
GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not
only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC
Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC
conversion is initiated.
If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts
and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt
handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC
interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC
registers until the conversion is completed.
Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR)
register (see page 268).
When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.
10.1.3
Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 269), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.
Note:
10.1.4
If any pin is to be used as an ADC input, the appropriate bit in GPIOAMSEL must be written
to 1 to disable the analog isolation circuit.
Commit Control
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 269), GPIO Pull-Up Select (GPIOPUR) register (see page 275), and GPIO Digital
Enable (GPIODEN) register (see page 278) are not committed to storage unless the GPIO Lock
(GPIOLOCK) register (see page 280) has been unlocked and the appropriate bits of the GPIO
Commit (GPIOCR) register (see page 281) have been set to 1.
10.1.5
Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable.
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package with the total number of high-current GPIO
outputs not exceeding four for the entire package.
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April 08, 2008
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LM3S3748 Microcontroller
10.1.6
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
10.2
Initialization and Configuration
The GPIO modules may be accessed via two different memory apertures. The legacy aperture is
backwards-compatible with previous Stellaris parts and offers two-cycle access time to all GPIO
registers. The high-speed aperture offers the same register map but provides single-cycle access
times. These apertures are mutually exclusive. The aperture enabled for a given GPIO port is
controlled by the appropriate bit in the GPIOHSCTL register (see page 91).
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the four JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 10-1 on page 255
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 10-2 on page 256 shows how a rising edge interrupt would be configured for
pin 2 of a GPIO port.
Table 10-1. GPIO Pad Configuration Examples
Configuration
a
GPIO Register Bit Value
AFSEL
DIR
ODR
DEN
PUR
PDR
DR2R
DR4R
DR8R
SLR
Digital Input (GPIO)
0
0
0
1
?
?
X
X
X
X
Digital Output (GPIO)
0
1
0
1
?
?
?
?
?
?
Open Drain Input
(GPIO)
0
0
1
1
X
X
X
X
X
X
Open Drain Output
(GPIO)
0
1
1
1
X
X
?
?
?
?
Open Drain
Input/Output (I2C)
1
X
1
1
X
X
?
?
?
?
Digital Input (Timer
CCP)
1
X
0
1
?
?
X
X
X
X
Digital Input (QEI)
1
X
0
1
?
?
X
X
X
X
Digital Output (PWM)
1
X
0
1
?
?
?
?
?
?
Digital Output (Timer
PWM)
1
X
0
1
?
?
?
?
?
?
Digital Input/Output
(SSI)
1
X
0
1
?
?
?
?
?
?
Digital Input/Output
(UART)
1
X
0
1
?
?
?
?
?
?
Analog Input
(Comparator)
0
0
0
0
0
0
X
X
X
X
Digital Output
(Comparator)
1
X
0
1
?
?
?
?
?
?
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
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Preliminary
General-Purpose Input/Outputs (GPIOs)
Table 10-2. GPIO Interrupt Configuration Example
Register
GPIOIS
Desired
Interrupt
Event
Trigger
a
Pin 2 Bit Value
7
0=edge
6
5
4
3
2
1
0
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
X
X
0
0
0
0
0
1
0
0
1=level
GPIOIBE
0=single
edge
1=both
edges
GPIOIEV
0=Low level,
or negative
edge
1=High level,
or positive
edge
GPIOIM
0=masked
1=not
masked
a. X=Ignored (don’t care bit)
10.3
Register Map
Table 10-3 on page 257 lists the GPIO registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that GPIO port’s base address:
■ GPIO Port A (legacy): 0x4000.4000
■ GPIO Port A (high-speed): 0x4005.8000
■ GPIO Port B (legacy): 0x4000.5000
■ GPIO Port B (high-speed): 0x4005.9000
■ GPIO Port C (legacy): 0x4000.6000
■ GPIO Port C (high-speed): 0x4005.A000
■ GPIO Port D (legacy): 0x4000.7000
■ GPIO Port D (high-speed): 0x4005.B000
■ GPIO Port E (legacy): 0x4002.4000
■ GPIO Port E (high-speed): 0x4005.C000
■ GPIO Port F (legacy): 0x4002.5000
■ GPIO Port F (high-speed): 0x4005.D000
■ GPIO Port G (legacy): 0x4002.6000
■ GPIO Port G (high-speed): 0x4005.E000
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LM3S3748 Microcontroller
■ GPIO Port H (legacy): 0x4002.7000
■ GPIO Port H (high-speed): 0x4005.F000
Important: The GPIO registers in this chapter are duplicated in each GPIO block, however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to those unconnected bits has no effect and reading those unconnected
bits returns no meaningful data.
Note:
The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are
0x0000.0000 for all GPIO pins, with the exception of the four JTAG/SWD pins (PC[3:0]).
These four pins default to JTAG/SWD functionality. Because of this, the default reset value
of these registers for Port C is 0x0000.000F.
The default register type for the GPIOCR register is RO for all GPIO pins, with the exception
of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). These five pins are
currently the only GPIOs that are protected by the GPIOCR register. Because of this, the
register type for GPIO Port B7 and GPIO Port C[3:0] is R/W.
The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the
exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). To ensure that
the JTAG port is not accidentally programmed as a GPIO, these four pins default to
non-committable. To ensure that the NMI pin is not accidentally programmed as the
non-maskable interrupt pin, it defaults to non-committable. Because of this, the default reset
value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR
for Port C is 0x0000.00F0.
Table 10-3. GPIO Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
GPIODATA
R/W
0x0000.0000
GPIO Data
259
0x400
GPIODIR
R/W
0x0000.0000
GPIO Direction
260
0x404
GPIOIS
R/W
0x0000.0000
GPIO Interrupt Sense
261
0x408
GPIOIBE
R/W
0x0000.0000
GPIO Interrupt Both Edges
262
0x40C
GPIOIEV
R/W
0x0000.0000
GPIO Interrupt Event
263
0x410
GPIOIM
R/W
0x0000.0000
GPIO Interrupt Mask
264
0x414
GPIORIS
RO
0x0000.0000
GPIO Raw Interrupt Status
265
0x418
GPIOMIS
RO
0x0000.0000
GPIO Masked Interrupt Status
266
0x41C
GPIOICR
W1C
0x0000.0000
GPIO Interrupt Clear
268
0x420
GPIOAFSEL
R/W
-
GPIO Alternate Function Select
269
0x500
GPIODR2R
R/W
0x0000.00FF
GPIO 2-mA Drive Select
271
0x504
GPIODR4R
R/W
0x0000.0000
GPIO 4-mA Drive Select
272
0x508
GPIODR8R
R/W
0x0000.0000
GPIO 8-mA Drive Select
273
0x50C
GPIOODR
R/W
0x0000.0000
GPIO Open Drain Select
274
0x510
GPIOPUR
R/W
-
GPIO Pull-Up Select
275
April 08, 2008
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Preliminary
General-Purpose Input/Outputs (GPIOs)
Name
Type
Reset
0x514
GPIOPDR
R/W
0x0000.0000
GPIO Pull-Down Select
276
0x518
GPIOSLR
R/W
0x0000.0000
GPIO Slew Rate Control Select
277
0x51C
GPIODEN
R/W
-
GPIO Digital Enable
278
0x520
GPIOLOCK
R/W
0x0000.0001
GPIO Lock
280
0x524
GPIOCR
-
-
GPIO Commit
281
0x528
GPIOAMSEL
R/W
0x0000.0000
GPIO Analog Mode Select
283
0xFD0
GPIOPeriphID4
RO
0x0000.0000
GPIO Peripheral Identification 4
285
0xFD4
GPIOPeriphID5
RO
0x0000.0000
GPIO Peripheral Identification 5
286
0xFD8
GPIOPeriphID6
RO
0x0000.0000
GPIO Peripheral Identification 6
287
0xFDC
GPIOPeriphID7
RO
0x0000.0000
GPIO Peripheral Identification 7
288
0xFE0
GPIOPeriphID0
RO
0x0000.0061
GPIO Peripheral Identification 0
289
0xFE4
GPIOPeriphID1
RO
0x0000.0000
GPIO Peripheral Identification 1
290
0xFE8
GPIOPeriphID2
RO
0x0000.0018
GPIO Peripheral Identification 2
291
0xFEC
GPIOPeriphID3
RO
0x0000.0001
GPIO Peripheral Identification 3
292
0xFF0
GPIOPCellID0
RO
0x0000.000D
GPIO PrimeCell Identification 0
293
0xFF4
GPIOPCellID1
RO
0x0000.00F0
GPIO PrimeCell Identification 1
294
0xFF8
GPIOPCellID2
RO
0x0000.0005
GPIO PrimeCell Identification 2
295
0xFFC
GPIOPCellID3
RO
0x0000.00B1
GPIO PrimeCell Identification 3
296
10.4
Description
See
page
Offset
Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.
258
April 08, 2008
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LM3S3748 Microcontroller
Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 260).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
DATA
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DATA
R/W
0x00
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and the data written to the
registers are masked by the eight address lines ipaddr[9:2]. Reads
from this register return its current state. Writes to this register only affect
bits that are not masked by ipaddr[9:2] and are configured as
outputs. See “Data Register Operation” on page 252 for examples of
reads and writes.
April 08, 2008
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Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure
the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are
cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x400
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DIR
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DIR
R/W
0x00
GPIO Data Direction
The DIR values are defined as follows:
Value Description
0
Pins are inputs.
1
Pins are outputs.
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April 08, 2008
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LM3S3748 Microcontroller
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the
corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits
are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x404
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
IS
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IS
R/W
0x00
GPIO Interrupt Sense
The IS values are defined as follows:
Value Description
0
Edge on corresponding pin is detected (edge-sensitive).
1
Level on corresponding pin is detected (level-sensitive).
April 08, 2008
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Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 261) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 263). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x408
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
IBE
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IBE
R/W
0x00
GPIO Interrupt Both Edges
The IBE values are defined as follows:
Value Description
0
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 263).
1
Both edges on the corresponding pin trigger an interrupt.
Note:
262
Single edge is determined by the corresponding bit
in GPIOIEV.
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value
in the GPIO Interrupt Sense (GPIOIS) register (see page 261). Clearing a bit configures the pin to
detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are
cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x40C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
IEV
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IEV
R/W
0x00
GPIO Interrupt Event
The IEV values are defined as follows:
Value Description
0
Falling edge or Low levels on corresponding pins trigger
interrupts.
1
Rising edge or High levels on corresponding pins trigger
interrupts.
April 08, 2008
263
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding
pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables
interrupt triggering on that pin. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x410
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
IME
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IME
R/W
0x00
GPIO Interrupt Mask Enable
The IME values are defined as follows:
Value Description
0
Corresponding pin interrupt is masked.
1
Corresponding pin interrupt is not masked.
264
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the
status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the
requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask
(GPIOIM) register (see page 264). Bits read as zero indicate that corresponding input pins have not
initiated an interrupt. All bits are cleared by a reset.
GPIO Raw Interrupt Status (GPIORIS)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x414
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RIS
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
RIS
RO
0x00
GPIO Interrupt Raw Status
Reflects the status of interrupt trigger condition detection on pins (raw,
prior to masking).
The RIS values are defined as follows:
Value Description
0
Corresponding pin interrupt requirements not met.
1
Corresponding pin interrupt has met requirements.
April 08, 2008
265
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not
only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC
Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC
conversion is initiated.
If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts
and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt
handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC
interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC
registers until the conversion is completed.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x418
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
MIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
266
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
Description
7:0
MIS
RO
0x00
GPIO Masked Interrupt Status
Masked value of interrupt due to corresponding pin.
The MIS values are defined as follows:
Value Description
0
Corresponding GPIO line interrupt not active.
1
Corresponding GPIO line asserting interrupt.
April 08, 2008
267
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.
GPIO Interrupt Clear (GPIOICR)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x41C
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
IC
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IC
W1C
0x00
GPIO Interrupt Clear
The IC values are defined as follows:
Value Description
0
Corresponding interrupt is unaffected.
1
Corresponding interrupt is cleared.
268
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore
no GPIO line is set to hardware control by default.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 269), GPIO Pull-Up Select (GPIOPUR) register (see page 275), and GPIO Digital
Enable (GPIODEN) register (see page 278) are not committed to storage unless the GPIO Lock
(GPIOLOCK) register (see page 280) has been unlocked and the appropriate bits of the GPIO
Commit (GPIOCR) register (see page 281) have been set to 1.
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the four JTAG/SWD pins (PC[3:0]). The
JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1
and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins
back to their default state.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x420
Type R/W, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
reserved
Type
Reset
RO
0
AFSEL
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
269
Preliminary
General-Purpose Input/Outputs (GPIOs)
Bit/Field
Name
Type
Reset
7:0
AFSEL
R/W
-
Description
GPIO Alternate Function Select
The AFSEL values are defined as follows:
Value Description
0
Software control of corresponding GPIO line (GPIO mode).
1
Hardware control of corresponding GPIO line (alternate
hardware function).
Note:
270
The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the four
JTAG/SWD pins (PC[3:0]). These four pins default
to JTAG/SWD functionality. Because of this, the
default reset value of these registers for Port C is
0x0000.000F.
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO
signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 2-mA Drive Select (GPIODR2R)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x500
Type R/W, reset 0x0000.00FF
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
DRV2
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DRV2
R/W
0xFF
Output Pad 2-mA Drive Enable
A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the
corresponding 2-mA enable bit. The change is effective on the second
clock cycle after the write if accessing GPIO via the legacy memory
aperture. If using high-speed access, the change is effective on the next
clock cycle.
April 08, 2008
271
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 4-mA Drive Select (GPIODR4R)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x504
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DRV4
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DRV4
R/W
0x00
Output Pad 4-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the
corresponding 4-mA enable bit. The change is effective on the second
clock cycle after the write if accessing GPIO via the legacy memory
aperture. If using high-speed access, the change is effective on the next
clock cycle.
272
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R
register are automatically cleared by hardware. The 8-mA setting is also used for high-current
operation.
Note:
There is no configuration difference between 8-mA and high-current operation. The additional
current capacity results from a shift in the VOH/VOL levels. See “Recommended DC Operating
Conditions” on page 691 for further information.
GPIO 8-mA Drive Select (GPIODR8R)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x508
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
DRV8
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DRV8
R/W
0x00
Output Pad 8-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the
corresponding 8-mA enable bit. The change is effective on the second
clock cycle after the write. if accessing GPIO via the legacy memory
aperture. If using high-speed access, the change is effective on the next
clock cycle.
April 08, 2008
273
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see
page 278). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R,
and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open
drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open drain output
when set to 1.
When using the I2C module, the GPIO Alternate Function Select (GPIOAFSEL) register bit for
PB2 and PB3 should be set to 1 (see examples in “Initialization and Configuration” on page 255).
GPIO Open Drain Select (GPIOODR)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x50C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
ODE
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
ODE
R/W
0x00
Output Pad Open Drain Enable
The ODE values are defined as follows:
Value Description
0
Open drain configuration is disabled.
1
Open drain configuration is enabled.
274
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up
resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 276). Write access
to this register is protected with the GPIOCR register. Bits in GPIOCR that are set to 0 will prevent
writes to the equivalent bit in this register.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 269), GPIO Pull-Up Select (GPIOPUR) register (see page 275), and GPIO Digital
Enable (GPIODEN) register (see page 278) are not committed to storage unless the GPIO Lock
(GPIOLOCK) register (see page 280) has been unlocked and the appropriate bits of the GPIO
Commit (GPIOCR) register (see page 281) have been set to 1.
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x510
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
PUE
RO
0
RO
0
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PUE
R/W
-
Pad Weak Pull-Up Enable
A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n]
enables. The change is effective on the second clock cycle after the
write.
Note:
April 08, 2008
The default reset value for the GPIOAFSEL, GPIOPUR, and
GPIODEN registers are 0x0000.0000 for all GPIO pins, with
the exception of the four JTAG/SWD pins (PC[3:0]). These
four pins default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for Port C is
0x0000.000F.
275
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak
pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 275).
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 269), GPIO Pull-Up Select (GPIOPUR) register (see page 275), and GPIO Digital
Enable (GPIODEN) register (see page 278) are not committed to storage unless the GPIO Lock
(GPIOLOCK) register (see page 280) has been unlocked and the appropriate bits of the GPIO
Commit (GPIOCR) register (see page 281) have been set to 1.
GPIO Pull-Down Select (GPIOPDR)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x514
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
PDE
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PDE
R/W
0x00
Pad Weak Pull-Down Enable
A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n]
enables. The change is effective on the second clock cycle after the
write.
276
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 273).
GPIO Slew Rate Control Select (GPIOSLR)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x518
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
SRL
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
SRL
R/W
0x00
Slew Rate Limit Enable (8-mA drive only)
The SRL values are defined as follows:
Value Description
0
Slew rate control disabled.
1
Slew rate control enabled.
April 08, 2008
277
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
Note:
Pins configured as digital inputs are Schmitt-triggered.
The GPIODEN register is the digital enable register. By default, with the exception of the GPIO
signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven
(tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not
allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or
alternate function), the corresponding GPIODEN bit must be set.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 269), GPIO Pull-Up Select (GPIOPUR) register (see page 275), and GPIO Digital
Enable (GPIODEN) register (see page 278) are not committed to storage unless the GPIO Lock
(GPIOLOCK) register (see page 280) has been unlocked and the appropriate bits of the GPIO
Commit (GPIOCR) register (see page 281) have been set to 1.
GPIO Digital Enable (GPIODEN)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x51C
Type R/W, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
reserved
Type
Reset
RO
0
DEN
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
278
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
7:0
DEN
R/W
-
Description
Digital Enable
The DEN values are defined as follows:
Value Description
0
Digital functions disabled.
1
Digital functions enabled.
Note:
April 08, 2008
The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the four
JTAG/SWD pins (PC[3:0]). These four pins default
to JTAG/SWD functionality. Because of this, the
default reset value of these registers for Port C is
0x0000.000F.
279
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 19: GPIO Lock (GPIOLOCK), offset 0x520
The GPIOLOCK register enables write access to the GPIOCR register (see page 281). Writing
0x0x4C4F.434B to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value
to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns
the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses
are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses
are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000.
GPIO Lock (GPIOLOCK)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x520
Type R/W, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
LOCK
Type
Reset
LOCK
Type
Reset
Bit/Field
Name
Type
31:0
LOCK
R/W
Reset
Description
0x0000.0001 GPIO Lock
A write of the value 0x4C4F.434B unlocks the GPIO Commit (GPIOCR)
register for write access.
A write of any other value or a write to the GPIOCR register reapplies
the lock, preventing any register updates. A read of this register returns
the following values:
Value
Description
0x0000.0001 locked
0x0000.0000 unlocked
280
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 20: GPIO Commit (GPIOCR), offset 0x524
The GPIOCR register is the commit register. The value of the GPIOCR register determines which
bits of the GPIOAFSEL, GPIOPUR, and GPIODEN registers are committed when a write to these
registers is performed. If a bit in the GPIOCR register is zero, the data being written to the
corresponding bit in the GPIOAFSEL, GPIOPUR, or GPIODEN registers cannot be committed and
retains its previous value. If a bit in the GPIOCR register is set, the data being written to the
corresponding bit of the GPIOAFSEL, GPIOPUR, or GPIODEN registers is committed to the register
and reflects the new value.
The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked.
Writes to the GPIOCR register are ignored if the GPIOLOCK register is locked.
Important: This register is designed to prevent accidental programming of the registers that control
connectivity to the NMI and JTAG/SWD debug hardware. By initializing the bits of the
GPIOCR register to 0 for PB7 and PC[3:0], the NMI and JTAG/SWD debug port can
only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK,
GPIOCR, and the corresponding registers.
Because this protection is currently only implemented on the NMI and JTAG/SWD pins
on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written
with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit
new values to the GPIOAFSEL, GPIOPUR, or GPIODEN register bits of these other
pins.
GPIO Commit (GPIOCR)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x524
Type -, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
-
-
-
-
-
-
-
-
reserved
Type
Reset
reserved
Type
Reset
RO
0
CR
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
281
Preliminary
General-Purpose Input/Outputs (GPIOs)
Bit/Field
Name
Type
Reset
7:0
CR
-
-
Description
GPIO Commit
On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL
bit to be set to its alternate function.
Note:
The default register type for the GPIOCR register is RO for
all GPIO pins, with the exception of the NMI pin and the four
JTAG/SWD pins (PB7 and PC[3:0]). These five pins are
currently the only GPIOs that are protected by the GPIOCR
register. Because of this, the register type for GPIO Port B7
and GPIO Port C[3:0] is R/W.
The default reset value for the GPIOCR register is
0x0000.00FF for all GPIO pins, with the exception of the NMI
pin and the four JTAG/SWD pins (PB7 and PC[3:0]). To
ensure that the JTAG port is not accidentally programmed as
a GPIO, these four pins default to non-committable. To ensure
that the NMI pin is not accidentally programmed as the
non-maskable interrupt pin, it defaults to non-committable.
Because of this, the default reset value of GPIOCR for GPIO
Port B is 0x0000.007F while the default reset value of
GPIOCR for Port C is 0x0000.00F0.
282
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528
Note:
If any pin is to be used as an ADC input, the appropriate bit in GPIOAMSEL must be written
to 1 to disable the analog isolation circuit.
The GPIOAMSEL register controls isolation circuits to the analog side of a unified I/O pad. Because
the GPIOs may be driven by a 5V source and affect analog operation, analog circuitry requires
isolation from the pins when not used in their analog function.
Each bit of this register controls the isolation circuitry for circuits that share the same pin as the
GPIO bit lane. The commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals.
Note:
This register is only valid for ports D and E.
GPIO Analog Mode Select (GPIOAMSEL)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x528
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
GPIOAMSEL
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
R/W
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4
GPIOAMSEL
R/W
0x00
GPIO Analog Mode Select
Value Description
0
Analog function of the pin is disabled, the isolation is enabled,
and the pin is capable of digital functions as specified by the
other GPIO configuration registers.
1
Analog function of the pin is enabled, the isolation is disabled,
and the pin is capable of analog functions.
Note:
This register and bits are required only for GPIO bit lanes that
share analog function through a unified I/O pad.
The reset state of this register is 0 for all bit lanes.
April 08, 2008
283
Preliminary
General-Purpose Input/Outputs (GPIOs)
Bit/Field
Name
Type
Reset
Description
3:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
284
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 22: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 4 (GPIOPeriphID4)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID4
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID4
RO
0x00
GPIO Peripheral ID Register[7:0]
April 08, 2008
285
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 23: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 5 (GPIOPeriphID5)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID5
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID5
RO
0x00
GPIO Peripheral ID Register[15:8]
286
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 24: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 6 (GPIOPeriphID6)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID6
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID6
RO
0x00
GPIO Peripheral ID Register[23:16]
April 08, 2008
287
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 25: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 7 (GPIOPeriphID7)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID7
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID7
RO
0x00
GPIO Peripheral ID Register[31:24]
288
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 26: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 0 (GPIOPeriphID0)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0xFE0
Type RO, reset 0x0000.0061
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID0
RO
0x61
GPIO Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
April 08, 2008
289
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 27: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 1 (GPIOPeriphID1)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID1
RO
0x00
GPIO Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
290
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 28: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 2 (GPIOPeriphID2)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID2
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID2
RO
0x18
GPIO Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
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General-Purpose Input/Outputs (GPIOs)
Register 29: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 3 (GPIOPeriphID3)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID3
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID3
RO
0x01
GPIO Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
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LM3S3748 Microcontroller
Register 30: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 0 (GPIOPCellID0)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID0
RO
0x0D
GPIO PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
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General-Purpose Input/Outputs (GPIOs)
Register 31: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 1 (GPIOPCellID1)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID1
RO
0xF0
GPIO PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
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LM3S3748 Microcontroller
Register 32: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 2 (GPIOPCellID2)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID2
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
GPIO PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
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General-Purpose Input/Outputs (GPIOs)
Register 33: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 3 (GPIOPCellID3)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID3
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
GPIO PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
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11
General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
®
The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks (Timer0, Timer1,
Timer 2, and Timer 3). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA
and TimerB) that can be configured to operate independently as timers or event counters, or
configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be
used to trigger analog-to-digital (ADC) conversions. The trigger signals from all of the general-purpose
timers are ORed together before reaching the ADC module, so only one timer should be used to
trigger ADC events.
®
The General-Purpose Timer Module is one timing resource available on the Stellaris microcontrollers.
Other timer resources include the System Timer (SysTick) (see “System Timer (SysTick)” on page 45)
and the PWM timer in the PWM module (see “PWM Timer” on page 604).
The following modes are supported:
■ 32-bit Timer modes
– Programmable one-shot timer
– Programmable periodic timer
– Real-Time Clock using 32.768-KHz input clock
– Software-controlled event stalling (excluding RTC mode)
■ 16-bit Timer modes
– General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)
– Programmable one-shot timer
– Programmable periodic timer
– Software-controlled event stalling
■ 16-bit Input Capture modes
– Input edge count capture
– Input edge time capture
■ 16-bit PWM mode
– Simple PWM mode with software-programmable output inversion of the PWM signal
11.1
Block Diagram
Note:
®
In Figure 11-1 on page 298, the specific CCP pins available depend on the Stellaris device.
See Table 11-1 on page 298 for the available CCPs.
April 08, 2008
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Preliminary
General-Purpose Timers
Figure 11-1. GPTM Module Block Diagram
0x0000 (Down Counter Modes)
TimerA Control
TA Comparator
GPTMTAPR
Clock / Edge
Detect
GPTMTAMATCHR
Interrupt / Config
TimerA
Interrupt
GPTMTAILR
GPTMAR
En
GPTMTAMR
GPTMCFG
GPTMCTL
GPTMIMR
TimerB
Interrupt
32 KHz or
Even CCP Pin
RTC Divider
GPTMRIS
GPTMMIS
TimerB Control
GPTMICR
GPTMTBR En
Clock / Edge
Detect
GPTMTBPR
GPTMTBMATCHR
Odd CCP Pin
TB Comparator
GPTMTBILR
GPTMTBMR
0x0000 (Down Counter Modes)
System
Clock
Table 11-1. Available CCP Pins
Timer
16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin
Timer 0 TimerA
TimerB
Timer 1 TimerA
TimerB
Timer 2 TimerA
TimerB
Timer 3 TimerA
TimerB
11.2
CCP0
-
-
CCP1
CCP2
-
-
CCP3
CCP4
-
-
CCP5
CCP6
-
-
CCP7
Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, and two 16-bit load/initialization registers and
their associated control functions. The exact functionality of each GPTM is controlled by software
and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 309),
the GPTM TimerA Mode (GPTMTAMR) register (see page 310), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 312). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
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11.2.1
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 323) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 324). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 327) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 328).
11.2.2
32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 323
■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 324
■ GPTM TimerA (GPTMTAR) register [15:0], see page 329
■ GPTM TimerB (GPTMTBR) register [15:0], see page 330
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
11.2.2.1 32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register
(see page 310), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.
When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 314), the
timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches
the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status
(GPTMRIS) register (see page 319), and holds it until it is cleared by writing the GPTM Interrupt
Clear (GPTMICR) register (see page 321). If the time-out interrupt is enabled in the GPTM Interrupt
Mask (GPTIMR) register (see page 317), the GPTM also sets the TATOMIS bit in the GPTM Masked
Interrupt Status (GPTMMIS) register (see page 320). The trigger is enabled by setting the TAOTE
bit in GPTMCTL, and can trigger SoC-level events such as ADC conversions.
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If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal
is deasserted.
11.2.2.2 32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is
loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA
Match (GPTMTAMATCHR) register (see page 325) by the controller.
The input clock on the CCP0, CCP2, or CCP4 pins is required to be 32.768 KHz in RTC mode. The
clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter.
When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its
preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until
either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs,
the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the
GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags
are cleared by writing the RTCCINT bit in GPTMICR.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
11.2.3
16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 309). This section describes each of the GPTM 16-bit modes of
operation. TimerA and TimerB have identical modes, so a single description is given using an n to
reference both.
11.2.3.1 16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR)
register.
When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting.
In addition to reloading the count value, the timer generates interrupts and triggers when it reaches
the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is
cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the GPTM
also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The trigger is enabled
by setting the TnOTE bit in the GPTMCTL register, and can trigger SoC-level events such as ADC
conversions.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
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LM3S3748 Microcontroller
If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal
is deasserted.
The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period).
Table 11-2. 16-Bit Timer With Prescaler Configurations
a
Prescale #Clock (T c) Max Time Units
00000000
1
1.3107
mS
00000001
2
2.6214
mS
00000010
3
3.9321
mS
------------
--
--
--
11111100
254
332.9229
mS
11111110
255
334.2336
mS
11111111
256
335.5443
mS
a. Tc is the clock period.
11.2.3.2 16-Bit Input Edge Count Mode
Note:
For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note:
The prescaler is not available in 16-Bit Input Edge Count mode.
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that
must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded
using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in
the GPTMCTL register. Once the event count has been reached, all further events are ignored until
TnEN is re-enabled by software.
Figure 11-2 on page 302 shows how input edge count mode works. In this case, the timer start value
is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four
edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMnMR register.
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Figure 11-2. 16-Bit Input Edge Count Mode Example
Timer reload
on next cycle
Count
Ignored
Ignored
0x000A
0x0009
0x0008
0x0007
0x0006
Timer stops,
flags
asserted
Input Signal
11.2.3.3 16-Bit Input Edge Time Mode
Note:
For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note:
The prescaler is not available in 16-Bit Input Edge Time mode.
In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value
loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of
either rising or falling edges, but not both. The timer is placed into Edge Time mode by setting the
TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined
by the TnEVENT fields of the GPTMCnTL register.
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR
register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and
the CnEMIS bit, if the interrupt is not masked).
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMnILR register.
Figure 11-3 on page 303 shows how input edge timing mode works. In the diagram, it is assumed
that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).
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Figure 11-3. 16-Bit Input Edge Time Mode Example
Count
0xFFFF
GPTMTnR=X
GPTMTnR=Y
GPTMTnR=Z
Z
X
Y
Time
Input Signal
11.2.3.4 16-Bit PWM Mode
Note:
The prescaler is not available in 16-Bit PWM mode.
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled
with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR
field to 0x2.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL
register. No interrupts or status bits are asserted in PWM mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern Match
Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
Figure 11-4 on page 304 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is
GPTMnMR=0x411A.
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Figure 11-4. 16-Bit PWM Mode Example
Count
GPTMTnR=GPTMnMR
GPTMTnR=GPTMnMR
0xC350
0x411A
Time
TnEN set
TnPWML = 0
Output
Signal
TnPWML = 1
11.3
Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0,
TIMER1, TIMER2, and TIMER3 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported timer
modes.
11.3.1
32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.
3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR).
5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
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7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
In One-Shot mode, the timer stops counting after step 7 on page 305. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
11.3.2
32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on its CCP0, CCP2, or CCP4
pins. To enable the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1.
3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).
4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.
5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded
with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared.
11.3.3
16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4.
3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register
(GPTMTnPR).
5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).
6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.
8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
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In One-Shot mode, the timer stops counting after step 8 on page 305. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
11.3.4
16-Bit Input Edge Count Mode
A timer is configured to Input Edge Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.
7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
In Input Edge Count Mode, the timer stops after the desired number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 306
through step 9 on page 306.
11.3.5
16-Bit Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
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Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timern (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
11.3.6
16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
11.4
Register Map
Table 11-3 on page 307 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:
■ Timer0: 0x4003.0000
■ Timer1: 0x4003.1000
■ Timer2: 0x4003.2000
■ Timer3: 0x4003.3000
Table 11-3. Timers Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
GPTMCFG
R/W
0x0000.0000
GPTM Configuration
309
0x004
GPTMTAMR
R/W
0x0000.0000
GPTM TimerA Mode
310
0x008
GPTMTBMR
R/W
0x0000.0000
GPTM TimerB Mode
312
0x00C
GPTMCTL
R/W
0x0000.0000
GPTM Control
314
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Description
See
page
Offset
Name
Type
Reset
0x018
GPTMIMR
R/W
0x0000.0000
GPTM Interrupt Mask
317
0x01C
GPTMRIS
RO
0x0000.0000
GPTM Raw Interrupt Status
319
0x020
GPTMMIS
RO
0x0000.0000
GPTM Masked Interrupt Status
320
0x024
GPTMICR
W1C
0x0000.0000
GPTM Interrupt Clear
321
0x028
GPTMTAILR
R/W
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
GPTM TimerA Interval Load
323
0x02C
GPTMTBILR
R/W
0x0000.FFFF
GPTM TimerB Interval Load
324
GPTM TimerA Match
325
0x030
GPTMTAMATCHR
R/W
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
0x034
GPTMTBMATCHR
R/W
0x0000.FFFF
GPTM TimerB Match
326
0x038
GPTMTAPR
R/W
0x0000.0000
GPTM TimerA Prescale
327
0x03C
GPTMTBPR
R/W
0x0000.0000
GPTM TimerB Prescale
328
0x048
GPTMTAR
RO
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
GPTM TimerA
329
0x04C
GPTMTBR
RO
0x0000.FFFF
GPTM TimerB
330
11.5
Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by address
offset.
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Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 16-bit mode.
GPTM Configuration (GPTMCFG)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
GPTMCFG
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0
GPTMCFG
R/W
0x0
GPTM Configuration
The GPTMCFG values are defined as follows:
Value
Description
0x0
32-bit timer configuration.
0x1
32-bit real-time clock (RTC) counter configuration.
0x2
Reserved
0x3
Reserved
0x4-0x7 16-bit timer configuration, function is controlled by bits 1:0 of
GPTMTAMR and GPTMTBMR.
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Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
GPTM TimerA Mode (GPTMTAMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
TAAMS
TACMR
R/W
0
R/W
0
0
TAMR
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TAAMS
R/W
0
GPTM TimerA Alternate Mode Select
The TAAMS values are defined as follows:
Value Description
0
Capture mode is enabled.
1
PWM mode is enabled.
Note:
2
TACMR
R/W
0
To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
GPTM TimerA Capture Mode
The TACMR values are defined as follows:
Value Description
0
Edge-Count mode
1
Edge-Time mode
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Bit/Field
Name
Type
Reset
1:0
TAMR
R/W
0x0
Description
GPTM TimerA Mode
The TAMR values are defined as follows:
Value Description
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer modes for
TimerA.
In 32-bit timer configuration, this register controls the mode and the
contents of GPTMTBMR are ignored.
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Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.
GPTM TimerB Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
TBAMS
TBCMR
R/W
0
R/W
0
0
TBMR
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TBAMS
R/W
0
GPTM TimerB Alternate Mode Select
The TBAMS values are defined as follows:
Value Description
0
Capture mode is enabled.
1
PWM mode is enabled.
Note:
2
TBCMR
R/W
0
To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.
GPTM TimerB Capture Mode
The TBCMR values are defined as follows:
Value Description
0
Edge-Count mode
1
Edge-Time mode
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Bit/Field
Name
Type
Reset
1:0
TBMR
R/W
0x0
Description
GPTM TimerB Mode
The TBMR values are defined as follows:
Value Description
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer modes
for TimerB.
In 32-bit timer configuration, this register’s contents are ignored and
GPTMTAMR is used.
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Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
15
14
13
reserved TBPWML TBOTE
Type
Reset
RO
0
R/W
0
RO
0
RO
0
RO
0
12
11
10
reserved
R/W
0
RO
0
TBEVENT
R/W
0
R/W
0
RO
0
RO
0
9
8
TBSTALL
TBEN
R/W
0
R/W
0
reserved TAPWML
RO
0
R/W
0
5
4
TAOTE
RTCEN
R/W
0
R/W
0
TAEVENT
R/W
0
R/W
0
1
0
TASTALL
TAEN
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:15
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
TBPWML
R/W
0
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
Value Description
13
TBOTE
R/W
0
0
Output is unaffected.
1
Output is inverted.
GPTM TimerB Output Trigger Enable
The TBOTE values are defined as follows:
Value Description
12
reserved
RO
0
0
The output TimerB trigger is disabled.
1
The output TimerB trigger is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
11:10
TBEVENT
R/W
0x0
Description
GPTM TimerB Event Mode
The TBEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
9
TBSTALL
R/W
0
GPTM TimerB Stall Enable
The TBSTALL values are defined as follows:
Value Description
8
TBEN
R/W
0
0
TimerB stalling is disabled.
1
TimerB stalling is enabled.
GPTM TimerB Enable
The TBEN values are defined as follows:
Value Description
0
TimerB is disabled.
1
TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
TAPWML
R/W
0
GPTM TimerA PWM Output Level
The TAPWML values are defined as follows:
Value Description
5
TAOTE
R/W
0
0
Output is unaffected.
1
Output is inverted.
GPTM TimerA Output Trigger Enable
The TAOTE values are defined as follows:
Value Description
0
The output TimerA trigger is disabled.
1
The output TimerA trigger is enabled.
April 08, 2008
315
Preliminary
General-Purpose Timers
Bit/Field
Name
Type
Reset
4
RTCEN
R/W
0
Description
GPTM RTC Enable
The RTCEN values are defined as follows:
Value Description
3:2
TAEVENT
R/W
0x0
0
RTC counting is disabled.
1
RTC counting is enabled.
GPTM TimerA Event Mode
The TAEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
1
TASTALL
R/W
0
GPTM TimerA Stall Enable
The TASTALL values are defined as follows:
Value Description
0
TAEN
R/W
0
0
TimerA stalling is disabled.
1
TimerA stalling is enabled.
GPTM TimerA Enable
The TAEN values are defined as follows:
Value Description
0
TimerA is disabled.
1
TimerA is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
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LM3S3748 Microcontroller
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x018
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
13
12
11
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
10
9
8
CBEIM
CBMIM
TBTOIM
R/W
0
R/W
0
R/W
0
reserved
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RTCIM
CAEIM
CAMIM
TATOIM
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
CBEIM
R/W
0
GPTM CaptureB Event Interrupt Mask
The CBEIM values are defined as follows:
Value Description
9
CBMIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM CaptureB Match Interrupt Mask
The CBMIM values are defined as follows:
Value Description
8
TBTOIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM TimerB Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
Value Description
7:4
reserved
RO
0
0
Interrupt is disabled.
1
Interrupt is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
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General-Purpose Timers
Bit/Field
Name
Type
Reset
3
RTCIM
R/W
0
Description
GPTM RTC Interrupt Mask
The RTCIM values are defined as follows:
Value Description
2
CAEIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM CaptureA Event Interrupt Mask
The CAEIM values are defined as follows:
Value Description
1
CAMIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM CaptureA Match Interrupt Mask
The CAMIM values are defined as follows:
Value Description
0
TATOIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM TimerA Time-Out Interrupt Mask
The TATOIM values are defined as follows:
Value Description
0
Interrupt is disabled.
1
Interrupt is enabled.
318
April 08, 2008
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LM3S3748 Microcontroller
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
13
12
11
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
CBERIS CBMRIS TBTORIS
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
3
RTCRIS
RO
0
RO
0
CAERIS CAMRIS TATORIS
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
CBERIS
RO
0
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
9
CBMRIS
RO
0
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
8
TBTORIS
RO
0
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
7:4
reserved
RO
0x0
3
RTCRIS
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
2
CAERIS
RO
0
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
1
CAMRIS
RO
0
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
0
TATORIS
RO
0
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
April 08, 2008
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General-Purpose Timers
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
13
12
11
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
CBEMIS CBMMIS TBTOMIS
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
RTCMIS CAEMIS CAMMIS TATOMIS
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
CBEMIS
RO
0
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
9
CBMMIS
RO
0
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
8
TBTOMIS
RO
0
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
7:4
reserved
RO
0x0
3
RTCMIS
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
2
CAEMIS
RO
0
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
1
CAMMIS
RO
0
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
0
TATOMIS
RO
0
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
320
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x024
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
13
12
11
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
CBECINT CBMCINT TBTOCINT
RO
0
RO
0
W1C
0
W1C
0
reserved
W1C
0
RO
0
RO
0
RO
0
RTCCINT CAECINT CAMCINT TATOCINT
RO
0
W1C
0
W1C
0
W1C
0
W1C
0
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
CBECINT
W1C
0
GPTM CaptureB Event Interrupt Clear
The CBECINT values are defined as follows:
Value Description
9
CBMCINT
W1C
0
0
The interrupt is unaffected.
1
The interrupt is cleared.
GPTM CaptureB Match Interrupt Clear
The CBMCINT values are defined as follows:
Value Description
8
TBTOCINT
W1C
0
0
The interrupt is unaffected.
1
The interrupt is cleared.
GPTM TimerB Time-Out Interrupt Clear
The TBTOCINT values are defined as follows:
Value Description
7:4
reserved
RO
0x0
0
The interrupt is unaffected.
1
The interrupt is cleared.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
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General-Purpose Timers
Bit/Field
Name
Type
Reset
3
RTCCINT
W1C
0
Description
GPTM RTC Interrupt Clear
The RTCCINT values are defined as follows:
Value Description
2
CAECINT
W1C
0
0
The interrupt is unaffected.
1
The interrupt is cleared.
GPTM CaptureA Event Interrupt Clear
The CAECINT values are defined as follows:
Value Description
1
CAMCINT
W1C
0
0
The interrupt is unaffected.
1
The interrupt is cleared.
GPTM CaptureA Match Raw Interrupt
This is the CaptureA match interrupt status after masking.
0
TATOCINT
W1C
0
GPTM TimerA Time-Out Raw Interrupt
The TATOCINT values are defined as follows:
Value Description
0
The interrupt is unaffected.
1
The interrupt is cleared.
322
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028
This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
GPTM TimerA Interval Load (GPTMTAILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x028
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TAILRH
Type
Reset
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
TAILRL
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:16
TAILRH
R/W
R/W
1
R/W
1
Reset
Description
0xFFFF
GPTM TimerA Interval Load Register High
(32-bit mode)
0x0000 (16-bit When configured for 32-bit mode via the GPTMCFG register, the GPTM
TimerB Interval Load (GPTMTBILR) register loads this value on a
mode)
write. A read returns the current value of GPTMTBILR.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBILR.
15:0
TAILRL
R/W
0xFFFF
GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the counter for
TimerA. A read returns the current value of GPTMTAILR.
April 08, 2008
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General-Purpose Timers
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C
This register is used to load the starting count value into TimerB. When the GPTM is configured to
a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.
GPTM TimerB Interval Load (GPTMTBILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
TBILRL
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TBILRL
R/W
0xFFFF
GPTM TimerB Interval Load Register
When the GPTM is not configured as a 32-bit timer, a write to this field
updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.
324
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerA Match (GPTMTAMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x030
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TAMRH
Type
Reset
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
TAMRL
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:16
TAMRH
R/W
R/W
1
R/W
1
Reset
Description
0xFFFF
GPTM TimerA Match Register High
(32-bit mode)
0x0000 (16-bit When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the upper half of
mode)
GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBMATCHR.
15:0
TAMRL
R/W
0xFFFF
GPTM TimerA Match Register Low
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the lower half of
GPTMTAR, to determine match events.
When configured for PWM mode, this value along with GPTMTAILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTAILR
minus this value.
April 08, 2008
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Preliminary
General-Purpose Timers
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 16-bit PWM and Input Edge Count modes.
GPTM TimerB Match (GPTMTBMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x034
Type R/W, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
TBMRL
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TBMRL
R/W
0xFFFF
GPTM TimerB Match Register Low
When configured for PWM mode, this value along with GPTMTBILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTBILR
minus this value.
326
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerA Prescale (GPTMTAPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
TAPSR
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
TAPSR
R/W
0x00
GPTM TimerA Prescale
The register loads this value on a write. A read returns the current value
of the register.
Refer to Table 11-2 on page 301 for more details and an example.
April 08, 2008
327
Preliminary
General-Purpose Timers
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerB Prescale (GPTMTBPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x03C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
TBPSR
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
TBPSR
R/W
0x00
GPTM TimerB Prescale
The register loads this value on a write. A read returns the current value
of this register.
Refer to Table 11-2 on page 301 for more details and an example.
328
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 15: GPTM TimerA (GPTMTAR), offset 0x048
This register shows the current value of the TimerA counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerA (GPTMTAR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x048
Type RO, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
1
RO
1
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
7
6
5
4
3
2
1
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
TARH
Type
Reset
RO
0
RO
1
RO
1
RO
0
RO
1
RO
0
RO
1
RO
1
15
14
13
12
11
10
9
8
TARL
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
31:16
TARH
RO
15:0
TARL
RO
RO
1
RO
1
Reset
Description
0xFFFF
GPTM TimerA Register High
(32-bit mode)
0x0000 (16-bit If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the
GPTMCFG is in a 16-bit mode, this is read as zero.
mode)
0xFFFF
GPTM TimerA Register Low
A read returns the current value of the GPTM TimerA Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
April 08, 2008
329
Preliminary
General-Purpose Timers
Register 16: GPTM TimerB (GPTMTBR), offset 0x04C
This register shows the current value of the TimerB counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerB (GPTMTBR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x04C
Type RO, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
TBRL
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TBRL
RO
0xFFFF
GPTM TimerB
A read returns the current value of the GPTM TimerB Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
330
April 08, 2008
Preliminary
LM3S3748 Microcontroller
12
Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
®
The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, a locking register, and user-enabled stalling.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
12.1
Block Diagram
Figure 12-1. WDT Module Block Diagram
WDTLOAD
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
Interrupt
WDTRIS
32-Bit Down
Counter
WDTMIS
0x00000000
WDTLOCK
System Clock
WDTTEST
Comparator
WDTVALUE
Identification Registers
12.2
WDTPCellID0
WDTPeriphID0
WDTPeriphID4
WDTPCellID1
WDTPeriphID1
WDTPeriphID5
WDTPCellID2
WDTPeriphID2
WDTPeriphID6
WDTPCellID3
WDTPeriphID3
WDTPeriphID7
Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the
April 08, 2008
331
Preliminary
Watchdog Timer
Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written,
which prevents the timer configuration from being inadvertently altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
12.3
Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.
12.4
Register Map
Table 12-1 on page 332 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.
Table 12-1. Watchdog Timer Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
WDTLOAD
R/W
0xFFFF.FFFF
Watchdog Load
334
0x004
WDTVALUE
RO
0xFFFF.FFFF
Watchdog Value
335
0x008
WDTCTL
R/W
0x0000.0000
Watchdog Control
336
0x00C
WDTICR
WO
-
Watchdog Interrupt Clear
337
0x010
WDTRIS
RO
0x0000.0000
Watchdog Raw Interrupt Status
338
0x014
WDTMIS
RO
0x0000.0000
Watchdog Masked Interrupt Status
339
0x418
WDTTEST
R/W
0x0000.0000
Watchdog Test
340
0xC00
WDTLOCK
R/W
0x0000.0000
Watchdog Lock
341
332
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Offset
Name
0xFD0
Reset
WDTPeriphID4
RO
0x0000.0000
Watchdog Peripheral Identification 4
342
0xFD4
WDTPeriphID5
RO
0x0000.0000
Watchdog Peripheral Identification 5
343
0xFD8
WDTPeriphID6
RO
0x0000.0000
Watchdog Peripheral Identification 6
344
0xFDC
WDTPeriphID7
RO
0x0000.0000
Watchdog Peripheral Identification 7
345
0xFE0
WDTPeriphID0
RO
0x0000.0005
Watchdog Peripheral Identification 0
346
0xFE4
WDTPeriphID1
RO
0x0000.0018
Watchdog Peripheral Identification 1
347
0xFE8
WDTPeriphID2
RO
0x0000.0018
Watchdog Peripheral Identification 2
348
0xFEC
WDTPeriphID3
RO
0x0000.0001
Watchdog Peripheral Identification 3
349
0xFF0
WDTPCellID0
RO
0x0000.000D
Watchdog PrimeCell Identification 0
350
0xFF4
WDTPCellID1
RO
0x0000.00F0
Watchdog PrimeCell Identification 1
351
0xFF8
WDTPCellID2
RO
0x0000.0005
Watchdog PrimeCell Identification 2
352
0xFFC
WDTPCellID3
RO
0x0000.00B1
Watchdog PrimeCell Identification 3
353
12.5
Description
See
page
Type
Register Descriptions
The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.
April 08, 2008
333
Preliminary
Watchdog Timer
Register 1: Watchdog Load (WDTLOAD), offset 0x000
This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.
Watchdog Load (WDTLOAD)
Base 0x4000.0000
Offset 0x000
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
WDTLoad
Type
Reset
WDTLoad
Type
Reset
Bit/Field
Name
Type
31:0
WDTLoad
R/W
Reset
R/W
1
Description
0xFFFF.FFFF Watchdog Load Value
334
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 2: Watchdog Value (WDTVALUE), offset 0x004
This register contains the current count value of the timer.
Watchdog Value (WDTVALUE)
Base 0x4000.0000
Offset 0x004
Type RO, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
23
22
21
20
19
18
17
16
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
7
6
5
4
3
2
1
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
WDTValue
Type
Reset
WDTValue
Type
Reset
Bit/Field
Name
Type
31:0
WDTValue
RO
Reset
RO
1
Description
0xFFFF.FFFF Watchdog Value
Current value of the 32-bit down counter.
April 08, 2008
335
Preliminary
Watchdog Timer
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
Watchdog Control (WDTCTL)
Base 0x4000.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
RESEN
INTEN
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
RESEN
R/W
0
Watchdog Reset Enable
The RESEN values are defined as follows:
Value Description
0
INTEN
R/W
0
0
Disabled.
1
Enable the Watchdog module reset output.
Watchdog Interrupt Enable
The INTEN values are defined as follows:
Value Description
0
Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
1
Interrupt event enabled. Once enabled, all writes are ignored.
336
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the Watchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is
indeterminate.
Watchdog Interrupt Clear (WDTICR)
Base 0x4000.0000
Offset 0x00C
Type WO, reset 31
30
29
28
27
26
25
24
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WDTIntClr
Type
Reset
WDTIntClr
Type
Reset
Bit/Field
Name
Type
Reset
31:0
WDTIntClr
WO
-
WO
-
Description
Watchdog Interrupt Clear
April 08, 2008
337
Preliminary
Watchdog Timer
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
Watchdog Raw Interrupt Status (WDTRIS)
Base 0x4000.0000
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
WDTRIS
RO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
WDTRIS
RO
0
Watchdog Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of WDTINTR.
338
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
Watchdog Masked Interrupt Status (WDTMIS)
Base 0x4000.0000
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
WDTMIS
RO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
WDTMIS
RO
0
Watchdog Masked Interrupt Status
Gives the masked interrupt state (after masking) of the WDTINTR
interrupt.
April 08, 2008
339
Preliminary
Watchdog Timer
Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Watchdog Test (WDTTEST)
Base 0x4000.0000
Offset 0x418
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
STALL
R/W
0
reserved
Bit/Field
Name
Type
Reset
Description
31:9
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
STALL
R/W
0
Watchdog Stall Enable
®
When set to 1, if the Stellaris microcontroller is stopped with a
debugger, the watchdog timer stops counting. Once the microcontroller
is restarted, the watchdog timer resumes counting.
7:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
340
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00
Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value
written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns
0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)).
Watchdog Lock (WDTLOCK)
Base 0x4000.0000
Offset 0xC00
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
WDTLock
Type
Reset
WDTLock
Type
Reset
Bit/Field
Name
Type
Reset
31:0
WDTLock
R/W
0x0000
R/W
0
Description
Watchdog Lock
A write of the value 0x1ACC.E551 unlocks the watchdog registers for
write access. A write of any other value reapplies the lock, preventing
any register updates.
A read of this register returns the following values:
Value
Description
0x0000.0001 Locked
0x0000.0000 Unlocked
April 08, 2008
341
Preliminary
Watchdog Timer
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 4 (WDTPeriphID4)
Base 0x4000.0000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID4
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID4
RO
0x00
WDT Peripheral ID Register[7:0]
342
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset
0xFD4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 5 (WDTPeriphID5)
Base 0x4000.0000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
PID5
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID5
RO
0x00
WDT Peripheral ID Register[15:8]
April 08, 2008
343
Preliminary
Watchdog Timer
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset
0xFD8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 6 (WDTPeriphID6)
Base 0x4000.0000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
PID6
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID6
RO
0x00
WDT Peripheral ID Register[23:16]
344
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset
0xFDC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 7 (WDTPeriphID7)
Base 0x4000.0000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
PID7
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID7
RO
0x00
WDT Peripheral ID Register[31:24]
April 08, 2008
345
Preliminary
Watchdog Timer
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset
0xFE0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 0 (WDTPeriphID0)
Base 0x4000.0000
Offset 0xFE0
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
PID0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID0
RO
0x05
Watchdog Peripheral ID Register[7:0]
346
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset
0xFE4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 1 (WDTPeriphID1)
Base 0x4000.0000
Offset 0xFE4
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
PID1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID1
RO
0x18
Watchdog Peripheral ID Register[15:8]
April 08, 2008
347
Preliminary
Watchdog Timer
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset
0xFE8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 2 (WDTPeriphID2)
Base 0x4000.0000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
PID2
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID2
RO
0x18
Watchdog Peripheral ID Register[23:16]
348
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset
0xFEC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 3 (WDTPeriphID3)
Base 0x4000.0000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
PID3
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID3
RO
0x01
Watchdog Peripheral ID Register[31:24]
April 08, 2008
349
Preliminary
Watchdog Timer
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 0 (WDTPCellID0)
Base 0x4000.0000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID0
RO
0x0D
Watchdog PrimeCell ID Register[7:0]
350
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 1 (WDTPCellID1)
Base 0x4000.0000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID1
RO
0xF0
Watchdog PrimeCell ID Register[15:8]
April 08, 2008
351
Preliminary
Watchdog Timer
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 2 (WDTPCellID2)
Base 0x4000.0000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID2
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
Watchdog PrimeCell ID Register[23:16]
352
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 3 (WDTPCellID3)
Base 0x4000.0000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID3
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
Watchdog PrimeCell ID Register[31:24]
April 08, 2008
353
Preliminary
Analog-to-Digital Converter (ADC)
13
Analog-to-Digital Converter (ADC)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
®
The Stellaris ADC module features 10-bit conversion resolution and supports eight input channels,
plus an internal temperature sensor. The ADC module contains a programmable sequencer which
allows for the sampling of multiple analog input sources without controller intervention. Each sample
sequence provides flexible programming with fully configurable input source, trigger events, interrupt
generation, and sequence priority.
®
The Stellaris ADC provides the following features:
■ Eight analog input channels
■ Single-ended and differential-input configurations
■ Internal temperature sensor
■ Sample rate of one million samples/second
■ Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
■ Flexible trigger control
– Controller (software)
– Timers
– Analog Comparators
– PWM
– GPIO
■ Hardware averaging of up to 64 samples for improved accuracy
■ An internal 3-V reference is used by the converter.
■ Power and ground for the analog circuitry is separate from the digital power and ground.
354
April 08, 2008
Preliminary
LM3S3748 Microcontroller
13.1
Block Diagram
Figure 13-1. ADC Module Block Diagram
Trigger Events
Comparator
GPIO (PB4)
Timer
PWM
Analog Inputs
SS3
Comparator
GPIO (PB4)
Timer
PWM
SS2
Control/Status
Sample
Sequencer 0
ADCACTSS
ADCSSMUX0
ADCOSTAT
ADCSSCTL0
ADCUSTAT
ADCSSFSTAT0
ADCSSPRI
Sample
Sequencer 1
ADCSSMUX1
Comparator
GPIO (PB4)
Timer
PWM
ADCSSCTL1
SS1
ADCSSFSTAT1
Hardware Averager
ADCSAC
Sample
Sequencer 2
Comparator
GPIO (PB4)
Timer
PWM
SS0
ADCSSMUX2
ADCSSCTL2
ADCSSFSTAT2
ADCEMUX
ADCPSSI
SS0 Interrupt
SS1 Interrupt
SS2 Interrupt
SS3 Interrupt
13.2
Analog-to-Digital
Converter
FIFO Block
ADCSSFIFO0
ADCSSFIFO1
Interrupt Control
Sample
Sequencer 3
ADCIM
ADCSSMUX3
ADCRIS
ADCSSCTL3
ADCISC
ADCSSFSTAT3
ADCSSFIFO2
ADCSSFIFO3
Functional Description
®
The Stellaris ADC collects sample data by using a programmable sequence-based approach
instead of the traditional single or double-sampling approach found on many ADC modules. Each
sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the
ADC to collect data from multiple input sources without having to be re-configured or serviced by
the controller. The programming of each sample in the sample sequence includes parameters such
as the input source and mode (differential versus single-ended input), interrupt generation on sample
completion, and the indicator for the last sample in the sequence.
13.2.1
Sample Sequencers
The sampling control and data capture is handled by the Sample Sequencers. All of the sequencers
are identical in implementation except for the number of samples that can be captured and the depth
of the FIFO. Table 13-1 on page 355 shows the maximum number of samples that each Sequencer
can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit
word, with the lower 10 bits containing the conversion result.
Table 13-1. Samples and FIFO Depth of Sequencers
Sequencer Number of Samples Depth of FIFO
SS3
1
1
SS2
4
4
SS1
4
4
SS0
8
8
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Preliminary
Analog-to-Digital Converter (ADC)
For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample
Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control
(ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn
nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits
corresponding to parameters such as temperature sensor selection, interrupt enable, end of
sequence, and differential input mode. Sample Sequencers are enabled by setting the respective
ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register, but can be configured
before being enabled.
When configuring a sample sequence, multiple uses of the same input pin within the same sequence
is allowed. In the ADCSSCTLn register, the Interrupt Enable (IE) bits can be set for any
combination of samples, allowing interrupts to be generated after every sample in the sequence if
necessary. Also, the END bit can be set at any point within a sample sequence. For example, if
Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth sample, allowing
Sequencer 0 to complete execution of the sample sequence after the fifth sample.
After a sample sequence completes execution, the result data can be retrieved from the ADC
Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers
that read a single address to "pop" result data. For software debug purposes, the positions of the
FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn)
registers along with FULL and EMPTY status flags. Overflow and underflow conditions are monitored
using the ADCOSTAT and ADCUSTAT registers.
13.2.2
Module Control
Outside of the Sample Sequencers, the remainder of the control logic is responsible for tasks such
as interrupt generation, sequence prioritization, and trigger configuration.
Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider
is configured automatically by hardware when the system XTAL is selected. The automatic clock
®
divider configuration targets 16.667 MHz operation for all Stellaris devices.
13.2.2.1 Interrupts
The Sample Sequencers dictate the events that cause interrupts, but they don't have control over
whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signal
is controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt
status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which
shows the raw status of a Sample Sequencer's interrupt signal, and the ADC Interrupt Status and
Clear (ADCISC) register, which shows the logical AND of the ADCRIS register’s INR bit and the
ADCIM register’s MASK bits. Interrupts are cleared by writing a 1 to the corresponding IN bit in
ADCISC.
13.2.2.2 Prioritization
When sampling events (triggers) happen concurrently, they are prioritized for processing by the
values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in
the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active Sample
Sequencer units with the same priority do not provide consistent results, so software must ensure
that all active Sample Sequencer units have a unique priority value.
13.2.2.3 Sampling Events
Sample triggering for each Sample Sequencer is defined in the ADC Event Multiplexer Select
®
(ADCEMUX) register. The external peripheral triggering sources vary by Stellaris family member,
356
April 08, 2008
Preliminary
LM3S3748 Microcontroller
but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by setting
the CH bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register.
When using the "Always" trigger, care must be taken. If a sequence's priority is too high, it is possible
to starve other lower priority sequences.
13.2.3
Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off and all data from the converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 373). There is a single averaging circuit and all input channels receive the same
amount of averaging whether they are single-ended or differential.
13.2.4
Analog-to-Digital Converter
The converter itself generates a 10-bit output value for selected analog input. Special analog pads
are used to minimize the distortion on the input. An internal 3 V reference is used by the converter
resulting in sample values ranging from 0x000 at 0 V input to 0x3FF at 3 V input when in single-ended
input mode.
13.2.5
Differential Sampling
In addition to traditional single-ended sampling, the ADC module supports differential sampling of
two analog input channels. To enable differential sampling, software must set the D bit (in the
ADCSSCTL0 register) in a step's configuration nibble.
When a sequence step is configured for differential sampling, its corresponding value in the
ADCSSMUX register must be set to one of the four differential pairs, numbered 0-3. Differential pair
0 samples analog inputs 0 and 1; differential pair 1 samples analog inputs 2 and 3; and so on (see
Table 13-2 on page 357). The ADC does not support other differential pairings such as analog input
0 with analog input 3. The number of differential pairs supported is dependent on the number of
analog inputs (see Table 13-2 on page 357).
Table 13-2. Differential Sampling Pairs
Differential Pair Analog Inputs
0
0 and 1
1
2 and 3
2
4 and 5
3
6 and 7
The voltage sampled in differential mode is the difference between the odd and even channels:
∆V (differential voltage) = VIN_EVEN (even channels) – VIN_ODD (odd channels), therefore:
■ If ∆V = 0, then the conversion result = 0x1FF
■ If ∆V > 0, then the conversion result > 0x1FF (range is 0x1FF–0x3FF)
■ If ∆V < 0, then the conversion result < 0x1FF (range is 0–0x1FF)
April 08, 2008
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Preliminary
Analog-to-Digital Converter (ADC)
The differential pairs assign polarities to the analog inputs: the even-numbered input is always
positive, and the odd-numbered input is always negative. In order for a valid conversion result to
appear, the negative input must be in the range of ± 1.5 V of the positive input. If an analog input
is greater than 3 V or less than 0 V (the valid range for analog inputs), the input voltage is clipped,
meaning it appears as either 3 V or 0 V, respectively, to the ADC.
Figure 13-2 on page 358 shows an example of the negative input centered at 1.5 V. In this
configuration, the differential range spans from -1.5 V to 1.5 V. Figure 13-3 on page 358 shows an
example where the negative input is centered at -0.75 V, meaning inputs on the positive input
saturate past a differential voltage of -0.75 V since the input voltage is less than 0 V. Figure
13-4 on page 359 shows an example of the negative input centered at 2.25 V, where inputs on the
positive channel saturate past a differential voltage of 0.75 V since the input voltage would be greater
than 3 V.
Figure 13-2. Differential Sampling Range, VIN_ODD = 1.5 V
ADC Conversion Result
0x3FF
0x1FF
0V
-1.5 V
1.5 V
0V
3.0 V VIN_EVEN
1.5 V V
VIN_ODD = 1.5 V
- Input Saturation
Figure 13-3. Differential Sampling Range, VIN_ODD = 0.75 V
ADC Conversion Result
0x3FF
0x1FF
0x0FF
-1.5 V
0V
-0.75 V
+0.75 V
+2.25 V
+1.5 V
VIN_EVEN
V
- Input Saturation
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April 08, 2008
Preliminary
LM3S3748 Microcontroller
Figure 13-4. Differential Sampling Range, VIN_ODD = 2.25 V
ADC Conversion Result
0x3FF
0x2FF
0x1FF
0.75 V
-1.5 V
2.25 V
3.0 V
0.75 V
1.5 V
VIN_EVEN
V
- Input Saturation
13.2.6
Internal Temperature Sensor
The internal temperature sensor provides an analog temperature reading as well as a reference
voltage. The voltage at the output terminal SENSO is given by the following equation:
SENSO = 2.7 - ((T + 55) / 75)
This relation is shown in Figure 13-5 on page 359.
Figure 13-5. Internal Temperature Sensor Characteristic
13.3
Initialization and Configuration
In order for the ADC module to be used, the PLL must be enabled and using a supported crystal
frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the
ADC module.
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Analog-to-Digital Converter (ADC)
13.3.1
Module Initialization
Initialization of the ADC module is a simple process with very few steps. The main steps include
enabling the clock to the ADC, disabling the analog isolation circuit associated with all inputs that
are to be used, and reconfiguring the Sample Sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:
1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC1 register (see page 118).
2. Disable the analog isolation circuit for all ADC input pins that are to be used by writing a 1 to
the appropriate bits of the GPIOAMSEL register (see page 283) in the associated GPIO block.
3. If required by the application, reconfigure the Sample Sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample
Sequencer 3 as the lowest priority.
13.3.2
Sample Sequencer Configuration
Configuration of the Sample Sequencers is slightly more complex than the module initialization
since each sample sequence is completely programmable.
The configuration for each Sample Sequencer should be as follows:
1. Ensure that the Sample Sequencer is disabled by writing a 0 to the corresponding ASEN bit in
the ADCACTSS register. Programming of the Sample Sequencers is allowed without having
them enabled. Disabling the Sequencer during programming prevents erroneous execution if
a trigger event were to occur during the configuration process.
2. Configure the trigger event for the Sample Sequencer in the ADCEMUX register.
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register.
6. Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the
ADCACTSS register.
13.4
Register Map
Table 13-3 on page 360 lists the ADC registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the ADC base address of 0x4003.8000.
Table 13-3. ADC Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
ADCACTSS
R/W
0x0000.0000
ADC Active Sample Sequencer
362
0x004
ADCRIS
RO
0x0000.0000
ADC Raw Interrupt Status
363
360
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LM3S3748 Microcontroller
Name
Type
Reset
0x008
ADCIM
R/W
0x0000.0000
ADC Interrupt Mask
364
0x00C
ADCISC
R/W1C
0x0000.0000
ADC Interrupt Status and Clear
365
0x010
ADCOSTAT
R/W1C
0x0000.0000
ADC Overflow Status
366
0x014
ADCEMUX
R/W
0x0000.0000
ADC Event Multiplexer Select
367
0x018
ADCUSTAT
R/W1C
0x0000.0000
ADC Underflow Status
370
0x020
ADCSSPRI
R/W
0x0000.3210
ADC Sample Sequencer Priority
371
0x028
ADCPSSI
WO
-
ADC Processor Sample Sequence Initiate
372
0x030
ADCSAC
R/W
0x0000.0000
ADC Sample Averaging Control
373
0x040
ADCSSMUX0
R/W
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 0
374
0x044
ADCSSCTL0
R/W
0x0000.0000
ADC Sample Sequence Control 0
376
0x048
ADCSSFIFO0
RO
0x0000.0000
ADC Sample Sequence Result FIFO 0
379
0x04C
ADCSSFSTAT0
RO
0x0000.0100
ADC Sample Sequence FIFO 0 Status
380
0x060
ADCSSMUX1
R/W
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 1
381
0x064
ADCSSCTL1
R/W
0x0000.0000
ADC Sample Sequence Control 1
382
0x068
ADCSSFIFO1
RO
0x0000.0000
ADC Sample Sequence Result FIFO 1
379
0x06C
ADCSSFSTAT1
RO
0x0000.0100
ADC Sample Sequence FIFO 1 Status
380
0x080
ADCSSMUX2
R/W
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 2
381
0x084
ADCSSCTL2
R/W
0x0000.0000
ADC Sample Sequence Control 2
382
0x088
ADCSSFIFO2
RO
0x0000.0000
ADC Sample Sequence Result FIFO 2
379
0x08C
ADCSSFSTAT2
RO
0x0000.0100
ADC Sample Sequence FIFO 2 Status
380
0x0A0
ADCSSMUX3
R/W
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 3
384
0x0A4
ADCSSCTL3
R/W
0x0000.0002
ADC Sample Sequence Control 3
385
0x0A8
ADCSSFIFO3
RO
0x0000.0000
ADC Sample Sequence Result FIFO 3
379
0x0AC
ADCSSFSTAT3
RO
0x0000.0100
ADC Sample Sequence FIFO 3 Status
380
13.5
Description
See
page
Offset
Register Descriptions
The remainder of this section lists and describes the ADC registers, in numerical order by address
offset.
April 08, 2008
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Preliminary
Analog-to-Digital Converter (ADC)
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000
This register controls the activation of the Sample Sequencers. Each Sample Sequencer can be
enabled/disabled independently.
ADC Active Sample Sequencer (ADCACTSS)
Base 0x4003.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
ASEN3
ASEN2
ASEN1
ASEN0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
ASEN3
R/W
0
ADC SS3 Enable
Specifies whether Sample Sequencer 3 is enabled. If set, the sample
sequence logic for Sequencer 3 is active. Otherwise, the Sequencer is
inactive.
2
ASEN2
R/W
0
ADC SS2 Enable
Specifies whether Sample Sequencer 2 is enabled. If set, the sample
sequence logic for Sequencer 2 is active. Otherwise, the Sequencer is
inactive.
1
ASEN1
R/W
0
ADC SS1 Enable
Specifies whether Sample Sequencer 1 is enabled. If set, the sample
sequence logic for Sequencer 1 is active. Otherwise, the Sequencer is
inactive.
0
ASEN0
R/W
0
ADC SS0 Enable
Specifies whether Sample Sequencer 0 is enabled. If set, the sample
sequence logic for Sequencer 0 is active. Otherwise, the Sequencer is
inactive.
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April 08, 2008
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LM3S3748 Microcontroller
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each Sample Sequencer. These bits
may be polled by software to look for interrupt conditions without having to generate controller
interrupts.
ADC Raw Interrupt Status (ADCRIS)
Base 0x4003.8000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
INR3
INR2
INR1
INR0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
INR3
RO
0
SS3 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL3 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN3 bit.
2
INR2
RO
0
SS2 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL2 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN2 bit.
1
INR1
RO
0
SS1 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL1 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN1 bit.
0
INR0
RO
0
SS0 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL0 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN0 bit.
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Analog-to-Digital Converter (ADC)
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the Sample Sequencer raw interrupt signals are promoted to controller
interrupts. The raw interrupt signal for each Sample Sequencer can be masked independently.
ADC Interrupt Mask (ADCIM)
Base 0x4003.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
MASK3
MASK2
MASK1
MASK0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
MASK3
R/W
0
SS3 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 3
(ADCRIS register INR3 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
2
MASK2
R/W
0
SS2 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 2
(ADCRIS register INR2 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
1
MASK1
R/W
0
SS1 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 1
(ADCRIS register INR1 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
0
MASK0
R/W
0
SS0 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 0
(ADCRIS register INR0 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
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April 08, 2008
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LM3S3748 Microcontroller
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
This register provides the mechanism for clearing interrupt conditions, and shows the status of
controller interrupts generated by the Sample Sequencers. When read, each bit field is the logical
AND of the respective INR and MASK bits. Interrupts are cleared by writing a 1 to the corresponding
bit position. If software is polling the ADCRIS instead of generating interrupts, the INR bits are still
cleared via the ADCISC register, even if the IN bit is not set.
ADC Interrupt Status and Clear (ADCISC)
Base 0x4003.8000
Offset 0x00C
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
IN3
IN2
IN1
IN0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
IN3
R/W1C
0
SS3 Interrupt Status and Clear
This bit is set by hardware when the MASK3 and INR3 bits are both 1,
providing a level-based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR3 bit.
2
IN2
R/W1C
0
SS2 Interrupt Status and Clear
This bit is set by hardware when the MASK2 and INR2 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR2 bit.
1
IN1
R/W1C
0
SS1 Interrupt Status and Clear
This bit is set by hardware when the MASK1 and INR1 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR1 bit.
0
IN0
R/W1C
0
SS0 Interrupt Status and Clear
This bit is set by hardware when the MASK0 and INR0 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR0 bit.
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Analog-to-Digital Converter (ADC)
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
This register indicates overflow conditions in the Sample Sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.
ADC Overflow Status (ADCOSTAT)
Base 0x4003.8000
Offset 0x010
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
OV3
OV2
OV1
OV0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
OV3
R/W1C
0
SS3 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 3 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
2
OV2
R/W1C
0
SS2 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 2 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
1
OV1
R/W1C
0
SS1 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 1 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
0
OV0
R/W1C
0
SS0 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 0 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
366
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LM3S3748 Microcontroller
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014
The ADCEMUX selects the event (trigger) that initiates sampling for each Sample Sequencer. Each
Sample Sequencer can be configured with a unique trigger source.
ADC Event Multiplexer Select (ADCEMUX)
Base 0x4003.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
EM3
Type
Reset
EM2
EM1
EM0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:12
EM3
R/W
0x00
SS3 Trigger Select
This field selects the trigger source for Sample Sequencer 3.
The valid configurations for this field are:
Value
Event
0x0
Controller (default)
0x1
Analog Comparator 0
0x2
Analog Comparator 1
0x3
Reserved
0x4
External (GPIO PB4)
0x5
Timer
0x6
PWM0
0x7
PWM1
0x8
PWM2
0x9-0xE reserved
0xF
April 08, 2008
Always (continuously sample)
367
Preliminary
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
Description
11:8
EM2
R/W
0x00
SS2 Trigger Select
This field selects the trigger source for Sample Sequencer 2.
The valid configurations for this field are:
Value
Event
0x0
Controller (default)
0x1
Analog Comparator 0
0x2
Analog Comparator 1
0x3
Reserved
0x4
External (GPIO PB4)
0x5
Timer
0x6
PWM0
0x7
PWM1
0x8
PWM2
0x9-0xE reserved
0xF
7:4
EM1
R/W
0x00
Always (continuously sample)
SS1 Trigger Select
This field selects the trigger source for Sample Sequencer 1.
The valid configurations for this field are:
Value
Event
0x0
Controller (default)
0x1
Analog Comparator 0
0x2
Analog Comparator 1
0x3
Reserved
0x4
External (GPIO PB4)
0x5
Timer
0x6
PWM0
0x7
PWM1
0x8
PWM2
0x9-0xE reserved
0xF
368
Always (continuously sample)
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
Description
3:0
EM0
R/W
0x00
SS0 Trigger Select
This field selects the trigger source for Sample Sequencer 0.
The valid configurations for this field are:
Value
Event
0x0
Controller (default)
0x1
Analog Comparator 0
0x2
Analog Comparator 1
0x3
Reserved
0x4
External (GPIO PB4)
0x5
Timer
0x6
PWM0
0x7
PWM1
0x8
PWM2
0x9-0xE reserved
0xF
April 08, 2008
Always (continuously sample)
369
Preliminary
Analog-to-Digital Converter (ADC)
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
This register indicates underflow conditions in the Sample Sequencer FIFOs. The corresponding
underflow condition can be cleared by writing a 1 to the relevant bit position.
ADC Underflow Status (ADCUSTAT)
Base 0x4003.8000
Offset 0x018
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
UV3
UV2
UV1
UV0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
UV3
R/W1C
0
SS3 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 3 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
2
UV2
R/W1C
0
SS2 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 2 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
1
UV1
R/W1C
0
SS1 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 1 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
0
UV0
R/W1C
0
SS0 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 0 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
370
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020
This register sets the priority for each of the Sample Sequencers. Out of reset, Sequencer 0 has
the highest priority, and sample sequence 3 has the lowest priority. When reconfiguring sequence
priorities, each sequence must have a unique priority or the ADC behavior is inconsistent.
ADC Sample Sequencer Priority (ADCSSPRI)
Base 0x4003.8000
Offset 0x020
Type R/W, reset 0x0000.3210
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
R/W
1
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
0
RO
0
RO
0
R/W
0
R/W
1
RO
0
RO
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
SS3
R/W
1
reserved
RO
0
SS2
R/W
1
reserved
SS1
reserved
SS0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:14
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13:12
SS3
R/W
0x3
SS3 Priority
The SS3 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 3. A priority encoding of 0 is highest
and 3 is lowest. The priorities assigned to the Sequencers must be
uniquely mapped. ADC behavior is not consistent if two or more fields
are equal.
11:10
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9:8
SS2
R/W
0x2
SS2 Priority
The SS2 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 2.
7:6
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
SS1
R/W
0x1
SS1 Priority
The SS1 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 1.
3:2
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1:0
SS0
R/W
0x0
SS0 Priority
The SS0 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 0.
April 08, 2008
371
Preliminary
Analog-to-Digital Converter (ADC)
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the Sample
Sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
ADC Processor Sample Sequence Initiate (ADCPSSI)
Base 0x4003.8000
Offset 0x028
Type WO, reset 31
30
29
28
27
26
25
24
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
8
7
6
5
4
3
2
1
0
SS3
SS2
SS1
SS0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
WO
-
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
SS3
WO
-
SS3 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 3, assuming the Sequencer is enabled in the ADCACTSS
register.
2
SS2
WO
-
SS2 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 2, assuming the Sequencer is enabled in the ADCACTSS
register.
1
SS1
WO
-
SS1 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 1, assuming the Sequencer is enabled in the ADCACTSS
register.
0
SS0
WO
-
SS0 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 0, assuming the Sequencer is enabled in the ADCACTSS
register.
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April 08, 2008
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LM3S3748 Microcontroller
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030
This register controls the amount of hardware averaging applied to conversion results. The final
conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified
ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6,
then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An
AVG = 7 provides unpredictable results.
ADC Sample Averaging Control (ADCSAC)
Base 0x4003.8000
Offset 0x030
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
AVG
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0
AVG
R/W
0x0
Hardware Averaging Control
Specifies the amount of hardware averaging that will be applied to ADC
samples. The AVG field can be any value between 0 and 6. Entering a
value of 7 creates unpredictable results.
Value Description
0x0
No hardware oversampling
0x1
2x hardware oversampling
0x2
4x hardware oversampling
0x3
8x hardware oversampling
0x4
16x hardware oversampling
0x5
32x hardware oversampling
0x6
64x hardware oversampling
0x7
Reserved
April 08, 2008
373
Preliminary
Analog-to-Digital Converter (ADC)
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0),
offset 0x040
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 0.
This register is 32-bits wide and contains information for eight possible samples.
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0)
Base 0x4003.8000
Offset 0x040
Type R/W, reset 0x0000.0000
31
30
reserved
Type
Reset
28
MUX7
27
26
reserved
25
24
MUX6
23
22
reserved
21
20
MUX5
19
18
reserved
17
16
MUX4
RO
0
R/W
0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
Type
Reset
29
RO
0
MUX3
R/W
0
R/W
0
reserved
R/W
0
RO
0
MUX2
R/W
0
R/W
0
reserved
R/W
0
RO
0
MUX1
R/W
0
R/W
0
reserved
R/W
0
RO
0
MUX0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30:28
MUX7
R/W
0
8th Sample Input Select
The MUX7 field is used during the eighth sample of a sequence executed
with the Sample Sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion. The value set here indicates
the corresponding pin, for example, a value of 1 indicates the input is
ADC1.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26:24
MUX6
R/W
0
7th Sample Input Select
The MUX6 field is used during the seventh sample of a sequence
executed with the Sample Sequencer and specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
23
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:20
MUX5
R/W
0
6th Sample Input Select
The MUX5 field is used during the sixth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
19
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
18:16
MUX4
R/W
0
Description
5th Sample Input Select
The MUX4 field is used during the fifth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14:12
MUX3
R/W
0
4th Sample Input Select
The MUX3 field is used during the fourth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
11
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:8
MUX2
R/W
0
3rd Sample Input Select
The MUX2 field is used during the third sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:4
MUX1
R/W
0
2nd Sample Input Select
The MUX1 field is used during the second sample of a sequence
executed with the Sample Sequencer and specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0
MUX0
R/W
0
1st Sample Input Select
The MUX0 field is used during the first sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
April 08, 2008
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Preliminary
Analog-to-Digital Converter (ADC)
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 0. When configuring a sample sequence, the END bit must be set at some point,
whether it be after the first sample, last sample, or any sample in between.
This register is 32-bits wide and contains information for eight possible samples.
ADC Sample Sequence Control 0 (ADCSSCTL0)
Base 0x4003.8000
Offset 0x044
Type R/W, reset 0x0000.0000
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TS7
IE7
END7
D7
TS6
IE6
END6
D6
TS5
IE5
END5
D5
TS4
IE4
END4
D4
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TS3
IE3
END3
D3
TS2
IE2
END2
D2
TS1
IE1
END1
D1
TS0
IE0
END0
D0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31
TS7
R/W
0
Description
8th Sample Temp Sensor Select
The TS7 bit is used during the eighth sample of the sample sequence
and specifies the input source of the sample. If set, the temperature
sensor is read. Otherwise, the input pin specified by the ADCSSMUX
register is read.
30
IE7
R/W
0
8th Sample Interrupt Enable
The IE7 bit is used during the eighth sample of the sample sequence
and specifies whether the raw interrupt signal (INR0 bit) is asserted at
the end of the sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to a controller-level interrupt.
When this bit is set, the raw interrupt is asserted, otherwise it is not. It
is legal to have multiple samples within a sequence generate interrupts.
29
END7
R/W
0
8th Sample is End of Sequence
The END7 bit indicates that this is the last sample of the sequence. It is
possible to end the sequence on any sample position. Samples defined
after the sample containing a set END are not requested for conversion
even though the fields may be non-zero. It is required that software write
the END bit somewhere within the sequence. (Sample Sequencer 3,
which only has a single sample in the sequence, is hardwired to have
the END0 bit set.)
Setting this bit indicates that this sample is the last in the sequence.
28
D7
R/W
0
8th Sample Diff Input Select
The D7 bit indicates that the analog input is to be differentially sampled.
The corresponding ADCSSMUXx nibble must be set to the pair number
"i", where the paired inputs are "2i and 2i+1". The temperature sensor
does not have a differential option. When set, the analog inputs are
differentially sampled.
27
TS6
R/W
0
7th Sample Temp Sensor Select
Same definition as TS7 but used during the seventh sample.
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LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
26
IE6
R/W
0
Description
7th Sample Interrupt Enable
Same definition as IE7 but used during the seventh sample.
25
END6
R/W
0
7th Sample is End of Sequence
Same definition as END7 but used during the seventh sample.
24
D6
R/W
0
7th Sample Diff Input Select
Same definition as D7 but used during the seventh sample.
23
TS5
R/W
0
6th Sample Temp Sensor Select
Same definition as TS7 but used during the sixth sample.
22
IE5
R/W
0
6th Sample Interrupt Enable
Same definition as IE7 but used during the sixth sample.
21
END5
R/W
0
6th Sample is End of Sequence
Same definition as END7 but used during the sixth sample.
20
D5
R/W
0
6th Sample Diff Input Select
Same definition as D7 but used during the sixth sample.
19
TS4
R/W
0
5th Sample Temp Sensor Select
Same definition as TS7 but used during the fifth sample.
18
IE4
R/W
0
5th Sample Interrupt Enable
Same definition as IE7 but used during the fifth sample.
17
END4
R/W
0
5th Sample is End of Sequence
Same definition as END7 but used during the fifth sample.
16
D4
R/W
0
5th Sample Diff Input Select
Same definition as D7 but used during the fifth sample.
15
TS3
R/W
0
4th Sample Temp Sensor Select
Same definition as TS7 but used during the fourth sample.
14
IE3
R/W
0
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
13
END3
R/W
0
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
12
D3
R/W
0
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
11
TS2
R/W
0
3rd Sample Temp Sensor Select
Same definition as TS7 but used during the third sample.
April 08, 2008
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Preliminary
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
10
IE2
R/W
0
Description
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
9
END2
R/W
0
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
8
D2
R/W
0
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
7
TS1
R/W
0
2nd Sample Temp Sensor Select
Same definition as TS7 but used during the second sample.
6
IE1
R/W
0
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
5
END1
R/W
0
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
4
D1
R/W
0
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
3
TS0
R/W
0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
2
IE0
R/W
0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
1
END0
R/W
0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
0
D0
R/W
0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
378
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset
0x0A8
This register contains the conversion results for samples collected with the Sample Sequencer (the
ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1,
ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return
conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the
FIFO is not properly handled by software, overflow and underflow conditions are registered in the
ADCOSTAT and ADCUSTAT registers.
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0)
Base 0x4003.8000
Offset 0x048
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DATA
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:10
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9:0
DATA
RO
0x00
Conversion Result Data
April 08, 2008
379
Preliminary
Analog-to-Digital Converter (ADC)
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset
0x04C
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset
0x06C
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset
0x08C
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset
0x0AC
This register provides a window into the Sample Sequencer, providing full/empty status information
as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty
FIFO. The ADCSSFSTAT0 register provides status on FIF0, ADCSSFSTAT1 on FIFO1,
ADCSSFSTAT2 on FIFO2, and ADCSSFSTAT3 on FIFO3.
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0)
Base 0x4003.8000
Offset 0x04C
Type RO, reset 0x0000.0100
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
FULL
RO
0
RO
0
reserved
RO
0
RO
0
EMPTY
RO
0
RO
1
HPTR
TPTR
Bit/Field
Name
Type
Reset
Description
31:13
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
FULL
RO
0
FIFO Full
When set, indicates that the FIFO is currently full.
11:9
reserved
RO
0x00
8
EMPTY
RO
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Empty
When set, indicates that the FIFO is currently empty.
7:4
HPTR
RO
0x00
FIFO Head Pointer
This field contains the current "head" pointer index for the FIFO, that is,
the next entry to be written.
3:0
TPTR
RO
0x00
FIFO Tail Pointer
This field contains the current "tail" pointer index for the FIFO, that is,
the next entry to be read.
380
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1),
offset 0x060
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2),
offset 0x080
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible
samples. See the ADCSSMUX0 register on page 374 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1)
Base 0x4003.8000
Offset 0x060
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
MUX3
R/W
0
R/W
0
reserved
R/W
0
RO
0
MUX2
R/W
0
R/W
0
reserved
R/W
0
RO
0
MUX1
R/W
0
R/W
0
reserved
R/W
0
RO
0
MUX0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:15
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14:12
MUX3
R/W
0
4th Sample Input Select
11
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:8
MUX2
R/W
0
3rd Sample Input Select
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:4
MUX1
R/W
0
2nd Sample Input Select
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0
MUX0
R/W
0
1st Sample Input Select
April 08, 2008
381
Preliminary
Analog-to-Digital Converter (ADC)
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
These registers contain the configuration information for each sample for a sequence executed with
Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some
point, whether it be after the first sample, last sample, or any sample in between. This register is
16-bits wide and contains information for four possible samples. See the ADCSSCTL0 register on
page 376 for detailed bit descriptions.
ADC Sample Sequence Control 1 (ADCSSCTL1)
Base 0x4003.8000
Offset 0x064
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
TS3
IE3
END3
D3
TS2
IE2
END2
D2
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
TS1
IE1
END1
D1
TS0
IE0
END0
D0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15
TS3
R/W
0
4th Sample Temp Sensor Select
Same definition as TS7 but used during the fourth sample.
14
IE3
R/W
0
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
13
END3
R/W
0
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
12
D3
R/W
0
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
11
TS2
R/W
0
3rd Sample Temp Sensor Select
Same definition as TS7 but used during the third sample.
10
IE2
R/W
0
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
9
END2
R/W
0
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
8
D2
R/W
0
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
382
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
7
TS1
R/W
0
Description
2nd Sample Temp Sensor Select
Same definition as TS7 but used during the second sample.
6
IE1
R/W
0
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
5
END1
R/W
0
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
4
D1
R/W
0
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
3
TS0
R/W
0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
2
IE0
R/W
0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
1
END0
R/W
0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
0
D0
R/W
0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
April 08, 2008
383
Preliminary
Analog-to-Digital Converter (ADC)
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3),
offset 0x0A0
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 3. This register is 4-bits wide and contains information for one possible sample.
See the ADCSSMUX0 register on page 374 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)
Base 0x4003.8000
Offset 0x0A0
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
MUX0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0
MUX0
R/W
0
1st Sample Input Select
384
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer.
This register is 4-bits wide and contains information for one possible sample. See the ADCSSCTL0
register on page 376 for detailed bit descriptions.
ADC Sample Sequence Control 3 (ADCSSCTL3)
Base 0x4003.8000
Offset 0x0A4
Type R/W, reset 0x0000.0002
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
TS0
IE0
END0
D0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
1
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TS0
R/W
0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
2
IE0
R/W
0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
1
END0
R/W
1
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
0
D0
R/W
0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
April 08, 2008
385
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
14
Universal Asynchronous Receivers/Transmitters
(UARTs)
®
The Stellaris Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable,
16C550-type serial interface characteristics. The LM3S3748 controller is equipped with two UART
modules.
Each UART has the following features:
■ Separate transmit and receive FIFOs
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Programmable baud-rate generator allowing rates up to 3.125 Mbps
■ Standard asynchronous communication bits for start, stop, and parity
■ False start bit detection
■ Line-break generation and detection
■ Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing:
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
■ Dedicated DMA transmit and receive channels
386
April 08, 2008
Preliminary
LM3S3748 Microcontroller
14.1
Block Diagram
Figure 14-1. UART Module Block Diagram
System Clock
DMA Request
DMA Control
UARTDMACTL
Interrupt
Interrupt Control
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
14.2
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
TxFIFO
16 x 8
.
.
.
Transmitter
(with SIR
Transmit
Encoder)
UnTx
Baud Rate
Generator
UARTDR
UARTIBRD
UARTFBRD
Receiver
(with SIR
Receive
Decoder)
Control/Status
RxFIFO
16 x 8
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
.
.
.
UnRx
Functional Description
®
Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 406). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
14.2.1
Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 14-2 on page 388 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
April 08, 2008
387
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Figure 14-2. UART Character Frame
UnTX
LSB
1
5-8 data bits
0
n
Start
14.2.2
1-2
stop bits
MSB
Parity bit
if enabled
Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 402) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 403). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.)
BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
where UARTSysClk is the system clock connected to the UART.
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error
detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 404), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■ UARTIBRD write, UARTFBRD write, and UARTLCRH write
■ UARTFBRD write, UARTIBRD write, and UARTLCRH write
■ UARTIBRD write and UARTLCRH write
■ UARTFBRD write and UARTLCRH write
14.2.3
Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
388
April 08, 2008
Preliminary
LM3S3748 Microcontroller
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 399) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 (described in “Transmit/Receive Logic” on page 387).
The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is
detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR)
register (see page 397). If the start bit was valid, successive data bits are sampled on every 16th
cycle of Baud16 (that is, one bit period later) according to the programmed length of the data
characters. The parity bit is then checked if parity mode was enabled. Data length and parity are
defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When
a full word is received, the data is stored in the receive FIFO, with any error bits associated with
that word.
14.2.4
Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream, and half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output, and decoded input to the UART. The UART signal pins can be
connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block
has two modes of operation:
■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW. This drives the UART input pin LOW.
■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCR register. See page 401 for more
information on IrDA low-power pulse-duration configuration.
Figure 14-3 on page 390 shows the UART transmit and receive signals, with and without IrDA
modulation.
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Figure 14-3. IrDA Data Modulation
Data bits
Start
bit
UnTx
1
0
0
0
1
Stop
bit
0
0
1
1
1
UnTx with IrDA
3
16 Bit period
Bit period
UnRx with IrDA
UnRx
0
1
0
1
Start
0
0
1
1
0
Data bits
1
Stop
In both normal and low-power IrDA modes:
■ During transmission, the UART data bit is used as the base for encoding
■ During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay
between transmission and reception. This delay must be generated by software because it is not
automatically supported by the UART. The delay is required because the infrared receiver electronics
might become biased, or even saturated from the optical power coupled from the adjacent transmitter
LED. This delay is known as latency, or receiver setup time.
14.2.5
FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 395). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 404).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 399) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the
UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 408). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For
example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt
after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the
½ mark.
14.2.6
Interrupts
The UART can generate interrupts when the following conditions are observed:
■ Overrun Error
■ Break Error
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■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 413).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 410) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 412).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 414).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO
becomes empty through reading all the data (or by reading the holding register), or when a 1 is
written to the corresponding bit in the UARTICR register.
14.2.7
Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 406). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
14.2.8
DMA Operation
The UART provides an interface connected to the μDMA controller. The DMA operation of the UART
is enabled through the UART DMA Control (UARTDMACTL) register. When DMA operation is
enabled, the UART will assert a DMA request on the receive or transmit channel when the associated
FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever
there is any data in the receive FIFO. A burst transfer request is asserted whenever the amount of
data in the receive FIFO is at or above the FIFO trigger level. For the transmit channel, a single
transfer request is asserted whenever there is at least one empty location in the transmit FIFO. The
burst request is asserted whenever the transmit FIFO contains fewer characters than the FIFO
trigger level. The single and burst DMA transfer requests are handled automatically by the μDMA
controller depending how the DMA channel is configured.
To enable DMA operation for the receive channel, the RXDMAE bit of the DMA Control
(UARTDMACTL) register should be set. To enable DMA operation for the transmit channel, the
TXDMAE bit of UARTDMACTL should be set. The UART can also be configured to stop using DMA
for the receive channel if a receive error occurs. If the DMAERR bit of UARTDMACR is set, then
when a receive error occurs, the DMA receive requests will be automatically disabled. This error
condition can be cleared by clearing the UART error interrupt.
If DMA is enabled, then the μDMA controller will trigger an interrupt when a transfer is complete.
The interrupt will occur on the UART interrupt vector. Therefore, if interrupts are used for UART
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operation and DMA is enabled, the UART interrupt handler must be designed to handle the μDMA
completion interrupt.
See “Micro Direct Memory Access (μDMA)” on page 189 for more details about programming the
μDMA controller.
14.2.9
IrDA SIR block
The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the
SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR
transceiver.
The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same
time. Transmission must be stopped before data can be received. The IrDA SIR physical layer
specifies a minimum 10-ms delay between transmission and reception.
14.3
Initialization and Configuration
To use the UARTs, the peripheral clock must be enabled by setting the UART0 or UART1 bits in the
RCGC1 register.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz and the desired UART configuration is:
■ 115200 baud rate
■ Data length of 8 bits
■ One stop bit
■ No parity
■ FIFOs disabled
■ No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the
equation described in “Baud-Rate Generation” on page 388, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 402) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 403) is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
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5. Optionally, configure the uDMA channel (see “Micro Direct Memory Access (μDMA)” on page 189)
and enable the DMA option(s) in the UARTDMACTL register.
6. Enable the UART by setting the UARTEN bit in the UARTCTL register.
14.4
Register Map
Table 14-1 on page 393 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
Note:
The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 406)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 14-1. UART Register Map
Offset
Name
Type
Reset
Description
See
page
0x000
UARTDR
R/W
0x0000.0000
UART Data
395
0x004
UARTRSR/UARTECR
R/W
0x0000.0000
UART Receive Status/Error Clear
397
0x018
UARTFR
RO
0x0000.0090
UART Flag
399
0x020
UARTILPR
R/W
0x0000.0000
UART IrDA Low-Power Register
401
0x024
UARTIBRD
R/W
0x0000.0000
UART Integer Baud-Rate Divisor
402
0x028
UARTFBRD
R/W
0x0000.0000
UART Fractional Baud-Rate Divisor
403
0x02C
UARTLCRH
R/W
0x0000.0000
UART Line Control
404
0x030
UARTCTL
R/W
0x0000.0300
UART Control
406
0x034
UARTIFLS
R/W
0x0000.0012
UART Interrupt FIFO Level Select
408
0x038
UARTIM
R/W
0x0000.0000
UART Interrupt Mask
410
0x03C
UARTRIS
RO
0x0000.000F
UART Raw Interrupt Status
412
0x040
UARTMIS
RO
0x0000.0000
UART Masked Interrupt Status
413
0x044
UARTICR
W1C
0x0000.0000
UART Interrupt Clear
414
0x048
UARTDMACTL
R/W
0x0000.0000
UART DMA Control
416
0xFD0
UARTPeriphID4
RO
0x0000.0000
UART Peripheral Identification 4
417
0xFD4
UARTPeriphID5
RO
0x0000.0000
UART Peripheral Identification 5
418
0xFD8
UARTPeriphID6
RO
0x0000.0000
UART Peripheral Identification 6
419
0xFDC
UARTPeriphID7
RO
0x0000.0000
UART Peripheral Identification 7
420
0xFE0
UARTPeriphID0
RO
0x0000.0011
UART Peripheral Identification 0
421
0xFE4
UARTPeriphID1
RO
0x0000.0000
UART Peripheral Identification 1
422
0xFE8
UARTPeriphID2
RO
0x0000.0018
UART Peripheral Identification 2
423
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Offset
Name
0xFEC
Reset
UARTPeriphID3
RO
0x0000.0001
UART Peripheral Identification 3
424
0xFF0
UARTPCellID0
RO
0x0000.000D
UART PrimeCell Identification 0
425
0xFF4
UARTPCellID1
RO
0x0000.00F0
UART PrimeCell Identification 1
426
0xFF8
UARTPCellID2
RO
0x0000.0005
UART PrimeCell Identification 2
427
0xFFC
UARTPCellID3
RO
0x0000.00B1
UART PrimeCell Identification 3
428
14.5
Description
See
page
Type
Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
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Register 1: UART Data (UARTDR), offset 0x000
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
OE
BE
PE
FE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DATA
Bit/Field
Name
Type
Reset
Description
31:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
OE
RO
0
UART Overrun Error
The OE values are defined as follows:
Value Description
10
BE
RO
0
0
There has been no data loss due to a FIFO overrun.
1
New data was received when the FIFO was full, resulting in
data loss.
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the receive data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state) and the next valid start bit is received.
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Bit/Field
Name
Type
Reset
9
PE
RO
0
Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
8
FE
RO
0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
7:0
DATA
R/W
0
Data Transmitted or Received
When written, the data that is to be transmitted via the UART. When
read, the data that was received by the UART.
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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.
Read-Only Receive Status (UARTRSR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
OE
BE
PE
FE
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
OE
RO
0
UART Overrun Error
When this bit is set to 1, data is received and the FIFO is already full.
This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must now read the data in order to empty the FIFO.
2
BE
RO
0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the received data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
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Bit/Field
Name
Type
Reset
1
PE
RO
0
Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
0
FE
RO
0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
Write-Only Error Clear (UARTECR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
8
7
6
5
4
3
2
1
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
reserved
Type
Reset
reserved
Type
Reset
WO
0
DATA
Bit/Field
Name
Type
Reset
Description
31:8
reserved
WO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DATA
WO
0
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
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Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x018
Type RO, reset 0x0000.0090
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
TXFE
RXFF
TXFF
RXFE
BUSY
RO
1
RO
0
RO
0
RO
1
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
TXFE
RO
1
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding
register is empty.
If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO
is empty.
6
RXFF
RO
0
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is full.
If the FIFO is enabled, this bit is set when the receive FIFO is full.
5
TXFF
RO
0
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding register
is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is full.
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Bit/Field
Name
Type
Reset
4
RXFE
RO
1
Description
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is empty.
3
BUSY
RO
0
UART Busy
When this bit is 1, the UART is busy transmitting data. This bit remains
set until the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor
value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk).
All the bits are cleared to 0 when reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power
divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode
is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is
calculated as follows:
ILPDVSR = SysClk / FIrLPBaud16
where FIrLPBaud16 is nominally 1.8432 MHz.
You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power
pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency
of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that
pulses greater than 1.4 μs are accepted as valid pulses.
Note:
Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
ILPDVSR
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0
7:0
ILPDVSR
R/W
0x00
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
IrDA Low-Power Divisor
This is an 8-bit low-power divisor value.
April 08, 2008
401
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 388
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
DIVINT
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0
15:0
DIVINT
R/W
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Integer Baud-Rate Divisor
402
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 388
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x028
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DIVFRAC
R/W
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:0
DIVFRAC
R/W
0x000
Fractional Baud-Rate Divisor
April 08, 2008
403
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 7: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x02C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
SPS
RO
0
RO
0
RO
0
R/W
0
5
WLEN
R/W
0
R/W
0
4
3
2
1
0
FEN
STP2
EPS
PEN
BRK
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
SPS
R/W
0
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
6:5
WLEN
R/W
0
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
Value Description
0x3 8 bits
0x2 7 bits
0x1 6 bits
0x0 5 bits (default)
4
FEN
R/W
0
UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO
mode).
When cleared to 0, FIFOs are disabled (Character mode). The FIFOs
become 1-byte-deep holding registers.
404
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
3
STP2
R/W
0
Description
UART Two Stop Bits Select
If this bit is set to 1, two stop bits are transmitted at the end of a frame.
The receive logic does not check for two stop bits being received.
2
EPS
R/W
0
UART Even Parity Select
If this bit is set to 1, even parity generation and checking is performed
during transmission and reception, which checks for an even number
of 1s in data and parity bits.
When cleared to 0, then odd parity is performed, which checks for an
odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.
1
PEN
R/W
0
UART Parity Enable
If this bit is set to 1, parity checking and generation is enabled; otherwise,
parity is disabled and no parity bit is added to the data frame.
0
BRK
R/W
0
UART Send Break
If this bit is set to 1, a Low level is continually output on the UnTX output,
after completing transmission of the current character. For the proper
execution of the break command, the software must set this bit for at
least two frames (character periods). For normal use, this bit must be
cleared to 0.
April 08, 2008
405
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are written.
If the UART is disabled during a transmit or receive operation, the current transaction is completed
prior to the UART stopping.
Note:
The UARTCTL register should not be changed while the UART is enabled or else the results
are unpredictable. The following sequence is recommended for making changes to the
UARTCTL register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register (UARTLCRH).
4. Reprogram the control register.
5. Enable the UART.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x030
Type R/W, reset 0x0000.0300
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RXE
TXE
LBE
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
1
R/W
1
R/W
0
SIRLP
SIREN
UARTEN
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
reserved
Bit/Field
Name
Type
Reset
Description
31:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9
RXE
R/W
1
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled. When
the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note:
8
TXE
R/W
1
To enable reception, the UARTEN bit must also be set.
UART Transmit Enable
If this bit is set to 1, the transmit section of the UART is enabled. When
the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note:
406
To enable transmission, the UARTEN bit must also be set.
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
7
LBE
R/W
0
Description
UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
6:3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
SIRLP
R/W
0
UART SIR Low Power Mode
This bit selects the IrDA encoding mode. If this bit is cleared to 0,
low-level bits are transmitted as an active High pulse with a width of
3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted
with a pulse width which is 3 times the period of the IrLPBaud16 input
signal, regardless of the selected bit rate. Setting this bit uses less power,
but might reduce transmission distances. See page 401 for more
information.
1
SIREN
R/W
0
UART SIR Enable
If this bit is set to 1, the IrDA SIR block is enabled, and the UART will
transmit and receive data using SIR protocol.
0
UARTEN
R/W
0
UART Enable
If this bit is set to 1, the UART is enabled. When the UART is disabled
in the middle of transmission or reception, it completes the current
character before stopping.
April 08, 2008
407
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x034
Type R/W, reset 0x0000.0012
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RXIFLSEL
R/W
1
TXIFLSEL
R/W
1
R/W
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:3
RXIFLSEL
R/W
0x2
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
Value
Description
0x0
RX FIFO ≥ 1/8 full
0x1
RX FIFO ≥ ¼ full
0x2
RX FIFO ≥ ½ full (default)
0x3
RX FIFO ≥ ¾ full
0x4
RX FIFO ≥ 7/8 full
0x5-0x7 Reserved
408
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
2:0
TXIFLSEL
R/W
0x2
Description
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
Value
Description
0x0
TX FIFO ≤ 1/8 full
0x1
TX FIFO ≤ ¼ full
0x2
TX FIFO ≤ ½ full (default)
0x3
TX FIFO ≤ ¾ full
0x4
TX FIFO ≤ 7/8 full
0x5-0x7 Reserved
April 08, 2008
409
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
13
12
11
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
OEIM
BEIM
PEIM
FEIM
RTIM
TXIM
RXIM
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OEIM
R/W
0
UART Overrun Error Interrupt Mask
On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller.
9
BEIM
R/W
0
UART Break Error Interrupt Mask
On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller.
8
PEIM
R/W
0
UART Parity Error Interrupt Mask
On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller.
7
FEIM
R/W
0
UART Framing Error Interrupt Mask
On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller.
6
RTIM
R/W
0
UART Receive Time-Out Interrupt Mask
On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller.
5
TXIM
R/W
0
UART Transmit Interrupt Mask
On a read, the current mask for the TXIM interrupt is returned.
Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller.
410
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
4
RXIM
R/W
0
Description
UART Receive Interrupt Mask
On a read, the current mask for the RXIM interrupt is returned.
Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller.
3:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
411
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x03C
Type RO, reset 0x0000.000F
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
OERIS
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BERIS
PERIS
FERIS
RTRIS
TXRIS
RXRIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
reserved
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OERIS
RO
0
UART Overrun Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
9
BERIS
RO
0
UART Break Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
8
PERIS
RO
0
UART Parity Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
7
FERIS
RO
0
UART Framing Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
6
RTRIS
RO
0
UART Receive Time-Out Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
5
TXRIS
RO
0
UART Transmit Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
4
RXRIS
RO
0
UART Receive Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
3:0
reserved
RO
0xF
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
412
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x040
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
OEMIS
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BEMIS
PEMIS
FEMIS
RTMIS
TXMIS
RXMIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
reserved
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OEMIS
RO
0
UART Overrun Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
9
BEMIS
RO
0
UART Break Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
8
PEMIS
RO
0
UART Parity Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
7
FEMIS
RO
0
UART Framing Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
6
RTMIS
RO
0
UART Receive Time-Out Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
5
TXMIS
RO
0
UART Transmit Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
4
RXMIS
RO
0
UART Receive Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
3:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
413
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x044
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
OEIC
RO
0
RO
0
RO
0
RO
0
W1C
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BEIC
PEIC
FEIC
RTIC
TXIC
RXIC
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
reserved
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OEIC
W1C
0
Overrun Error Interrupt Clear
The OEIC values are defined as follows:
Value Description
9
BEIC
W1C
0
0
No effect on the interrupt.
1
Clears interrupt.
Break Error Interrupt Clear
The BEIC values are defined as follows:
Value Description
8
PEIC
W1C
0
0
No effect on the interrupt.
1
Clears interrupt.
Parity Error Interrupt Clear
The PEIC values are defined as follows:
Value Description
0
No effect on the interrupt.
1
Clears interrupt.
414
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
7
FEIC
W1C
0
Description
Framing Error Interrupt Clear
The FEIC values are defined as follows:
Value Description
6
RTIC
W1C
0
0
No effect on the interrupt.
1
Clears interrupt.
Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
5
TXIC
W1C
0
0
No effect on the interrupt.
1
Clears interrupt.
Transmit Interrupt Clear
The TXIC values are defined as follows:
Value Description
4
RXIC
W1C
0
0
No effect on the interrupt.
1
Clears interrupt.
Receive Interrupt Clear
The RXIC values are defined as follows:
Value Description
3:0
reserved
RO
0x00
0
No effect on the interrupt.
1
Clears interrupt.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
415
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 14: UART DMA Control (UARTDMACTL), offset 0x048
The UARTDMACTL register is the DMA control register.
UART DMA Control (UARTDMACTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x048
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DMAERR TXDMAE RXDMAE
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
DMAERR
R/W
0
DMA on Error
If this bit is set to 1, DMA receive requests are automatically disabled
when a receive error occurs.
1
TXDMAE
R/W
0
Transmit DMA Enable
If this bit is set to 1, DMA for the transmit FIFO is enabled.
0
RXDMAE
R/W
0
Receive DMA Enable
If this bit is set to 1, DMA for the receive FIFO is enabled.
416
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 15: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID4
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID4
RO
0x0000
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
April 08, 2008
417
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 16: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID5
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID5
RO
0x0000
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
418
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 17: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID6
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID6
RO
0x0000
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
April 08, 2008
419
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 18: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID7
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0
7:0
PID7
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
420
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 19: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFE0
Type RO, reset 0x0000.0011
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID0
RO
0x11
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
April 08, 2008
421
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 20: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID1
RO
0x00
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
422
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 21: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID2
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID2
RO
0x18
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
April 08, 2008
423
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 22: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID3
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID3
RO
0x01
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
424
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 23: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID0
RO
0x0D
UART PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
April 08, 2008
425
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 24: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 1 (UARTPCellID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID1
RO
0xF0
UART PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
426
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 25: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 2 (UARTPCellID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID2
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
UART PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
April 08, 2008
427
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 26: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 3 (UARTPCellID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID3
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
UART PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
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15
Synchronous Serial Interface (SSI)
®
The Stellaris microcontroller includes two Synchronous Serial Interface (SSI) modules. Each SSI
is a master or slave interface for synchronous serial communication with peripheral devices that
have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces.
®
Each Stellaris SSI module has the following features:
■ Master or slave operation
■ Support for Direct Memory Access (DMA)
■ Programmable clock bit rate and prescale
■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
15.1
Block Diagram
Figure 15-1. SSI Module Block Diagram
DMA Request
DMA Control
SSIDMACTL
Interrupt
Interrupt Control
SSIIM
SSIMIS
SSIRIS
SSIICR
Control/Status
TxFIFO
8 x 16
.
.
.
SSITx
SSICR0
SSICR1
SSISR
Transmit/
Receive
Logic
SSIDR
RxFIFO
8 x 16
System Clock
Clock Prescaler
SSIPeriphID0
SSIPeriphID1
SSIPeriphID2
SSIPeriphID3
SSIClk
SSIFss
.
.
.
SSICPSR
Identification Registers
SSIPCellID0
SSIPCellID1
SSIPCellID2
SSIPCellID3
SSIRx
SSIPeriphID4
SSIPeriphID5
SSIPeriphID6
SSIPeriphID7
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15.2
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes. The SSI also supports the DMA interface. The transmit and receive FIFOs can
be programmed as destination/source addresses in the DMA module. DMA operation is enabled
by setting the appropriate bit(s) in the SSIDMACTL register (see page 455).
15.2.1
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 449). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 442).
The frequency of the output clock SSIClk is defined by:
SSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note:
Although the SSIClk transmit clock can theoretically be 25 MHz, the module may not be
able to operate at that speed. For master mode, the system clock must be at least two times
faster than the SSIClk. For slave mode, the system clock must be at least 12 times faster
than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 698 to view SSI timing parameters.
15.2.2
FIFO Operation
15.2.2.1 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 446), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
15.2.2.2 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
15.2.3
Interrupts
The SSI can generate interrupts when the following conditions are observed:
■ Transmit FIFO service
■ Receive FIFO service
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■ Receive FIFO time-out
■ Receive FIFO overrun
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
can only generate a single interrupt request to the controller at any given time. You can mask each
of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask
(SSIIM) register (see page 450). Setting the appropriate mask bit to 1 enables the interrupt.
Provision of the individual outputs, as well as a combined interrupt output, allows use of either a
global interrupt service routine, or modular device drivers to handle interrupts. The transmit and
receive dynamic dataflow interrupts have been separated from the status interrupts so that data
can be read or written in response to the FIFO trigger levels. The status of the individual interrupt
sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status
(SSIMIS) registers (see page 452 and page 453, respectively).
15.2.4
Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:
■ Texas Instruments synchronous serial
■ Freescale SPI
■ MICROWIRE
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and
latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique, which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
15.2.4.1 Texas Instruments Synchronous Serial Frame Format
Figure 15-2 on page 432 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
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Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk
SSIFss
SSITx/SSIRx
MSB
LSB
4 to 16 bits
In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is
pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data
is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 15-3 on page 432 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer)
SSIClk
SSIFss
SSITx/SSIRx
MSB
LSB
4 to 16 bits
15.2.4.2 Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition
before the first data capture edge. When the SPH phase control bit is Low, data is captured on the
first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition.
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15.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 15-4 on page 433 and Figure 15-5 on page 433.
Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx
MSB
LSB
Q
4 to 16 bits
MSB
SSITx
Note:
LSB
Q is undefined.
Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx LSB
MSB
LSB
MSB
4 to 16 bits
SSITx LSB
MSB
LSB
MSB
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto
the SSIRx input line of the master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further half
SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
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serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
15.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
15-6 on page 434, which covers both single and continuous transfers.
Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1
SSIClk
SSIFss
SSIRx
Q
LSB
MSB
Q
4 to 16 bits
SSITx
Note:
MSB
LSB
Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After
a further one half SSIClk period, both master and slave valid data is enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
15.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 15-7 on page 435 and Figure 15-8 on page 435.
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Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSIRx
MSB
LSB
Q
4 to 16 bits
SSITx
MSB
Note:
Q is undefined.
LSB
Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSITx/SSIRxLSB
MSB
LSB
MSB
4 to 16 bits
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low, which causes slave data to be immediately
transferred onto the SSIRx line of the master. The master SSITx output pad is enabled.
One half period later, valid master data is transferred to the SSITx line. Now that both the master
and slave data have been set, the SSIClk master clock pin becomes Low after one further half
SSIClk period. This means that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
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15.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
15-9 on page 436, which covers both single and continuous transfers.
Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1
SSIClk
SSIFss
SSIRx
Q
LSB
MSB
Q
4 to 16 bits
SSITx
MSB
Note:
Q is undefined.
LSB
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
15.2.4.7 MICROWIRE Frame Format
Figure 15-10 on page 437 shows the MICROWIRE frame format, again for a single frame. Figure
15-11 on page 438 shows the same format when back-to-back frames are transmitted.
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Figure 15-10. MICROWIRE Frame Format (Single Frame)
SSIClk
SSIFss
SSITx
MSB
LSB
8-bit control
SSIRx
0
MSB
LSB
4 to 16 bits
output data
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex, using a master-slave message passing technique. Each serial transmission begins with
an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the
SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains
tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of
each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a
one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven
onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising
edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one
clock period after the last bit has been latched in the receive serial shifter, which causes the data
to be transferred to the receive FIFO.
Note:
The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.
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Figure 15-11. MICROWIRE Frame Format (Continuous Transfer)
SSIClk
SSIFss
SSITx
LSB
MSB
LSB
8-bit control
SSIRx
0
MSB
LSB
MSB
4 to 16 bits
output data
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 15-12 on page 438 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
tSetup=(2*tSSIClk)
tHold=tSSIClk
SSIClk
SSIFss
SSIRx
First RX data to be
sampled by SSI slave
15.2.5
DMA Operation
The SSI peripheral provides an interface connected to the μDMA controller. The DMA operation of
the SSI is enabled through the SSI DMA Control (SSIDMACTL) register. When DMA operation is
enabled, the SSI will assert a DMA request on the receive or transmit channel when the associated
FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever
there is any data in the receive FIFO. A burst transfer request is asserted whenever the amount of
data in the receive FIFO is 4 or more items. For the transmit channel, a single transfer request is
asserted whenever there is at least one empty location in the transmit FIFO. The burst request is
asserted whenever the transmit FIFO has 4 or more empty slots. The single and burst DMA transfer
requests are handled automatically by the μDMA controller depending how the DMA channel is
configured. To enable DMA operation for the receive channel, the RXDMAE bit of the DMA Control
(SSIDMACTL) register should be set. To enable DMA operation for the transmit channel, the TXDMAE
bit of SSIDMACTL should be set. If DMA is enabled, then the μDMA controller will trigger an interrupt
when a transfer is complete. The interrupt will occur on the SSI interrupt vector. Therefore, if interrupts
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are used for SSI operation and DMA is enabled, the SSI interrupt handler must be designed to
handle the μDMA completion interrupt.
See “Micro Direct Memory Access (μDMA)” on page 189 for more details about programming the
μDMA controller.
15.3
Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
4. Write the SSICR0 register with the following configuration:
■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■ The data size (DSS)
5. Optionally, configure the uDMA channel (see “Micro Direct Memory Access (μDMA)” on page 189)
and enable the DMA option(s) in the SSIDMACTL register.
6. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
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The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
15.4
Register Map
Table 15-1 on page 440 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
■ SSI1: 0x4000.9000
Note:
The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 15-1. SSI Register Map
Offset
Name
Type
Reset
Description
See
page
0x000
SSICR0
R/W
0x0000.0000
SSI Control 0
442
0x004
SSICR1
R/W
0x0000.0000
SSI Control 1
444
0x008
SSIDR
R/W
0x0000.0000
SSI Data
446
0x00C
SSISR
RO
0x0000.0003
SSI Status
447
0x010
SSICPSR
R/W
0x0000.0000
SSI Clock Prescale
449
0x014
SSIIM
R/W
0x0000.0000
SSI Interrupt Mask
450
0x018
SSIRIS
RO
0x0000.0008
SSI Raw Interrupt Status
452
0x01C
SSIMIS
RO
0x0000.0000
SSI Masked Interrupt Status
453
0x020
SSIICR
W1C
0x0000.0000
SSI Interrupt Clear
454
0x024
SSIDMACTL
R/W
0x0000.0000
SSI DMA Control
455
0xFD0
SSIPeriphID4
RO
0x0000.0000
SSI Peripheral Identification 4
456
0xFD4
SSIPeriphID5
RO
0x0000.0000
SSI Peripheral Identification 5
457
0xFD8
SSIPeriphID6
RO
0x0000.0000
SSI Peripheral Identification 6
458
0xFDC
SSIPeriphID7
RO
0x0000.0000
SSI Peripheral Identification 7
459
0xFE0
SSIPeriphID0
RO
0x0000.0022
SSI Peripheral Identification 0
460
0xFE4
SSIPeriphID1
RO
0x0000.0000
SSI Peripheral Identification 1
461
0xFE8
SSIPeriphID2
RO
0x0000.0018
SSI Peripheral Identification 2
462
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April 08, 2008
Preliminary
LM3S3748 Microcontroller
Offset
Name
0xFEC
Reset
SSIPeriphID3
RO
0x0000.0001
SSI Peripheral Identification 3
463
0xFF0
SSIPCellID0
RO
0x0000.000D
SSI PrimeCell Identification 0
464
0xFF4
SSIPCellID1
RO
0x0000.00F0
SSI PrimeCell Identification 1
465
0xFF8
SSIPCellID2
RO
0x0000.0005
SSI PrimeCell Identification 2
466
0xFFC
SSIPCellID3
RO
0x0000.00B1
SSI PrimeCell Identification 3
467
15.5
Description
See
page
Type
Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
April 08, 2008
441
Preliminary
Synchronous Serial Interface (SSI)
Register 1: SSI Control 0 (SSICR0), offset 0x000
SSICR0 is control register 0 and contains bit fields that control various functions within the SSI
module. Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
SPH
SPO
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
SCR
Type
Reset
FRF
R/W
0
DSS
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8
SCR
R/W
0x0000
SSI Serial Clock Rate
The value SCR is used to generate the transmit and receive bit rate of
the SSI. The bit rate is:
BR=FSSIClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
7
SPH
R/W
0
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. It has the most impact on the first bit transmitted by
either allowing or not allowing a clock transition before the first data
capture edge.
When the SPH bit is 0, data is captured on the first clock edge transition.
If SPH is 1, data is captured on the second clock edge transition.
6
SPO
R/W
0
SSI Serial Clock Polarity
This bit is only applicable to the Freescale SPI Format.
When the SPO bit is 0, it produces a steady state Low value on the
SSIClk pin. If SPO is 1, a steady state High value is placed on the
SSIClk pin when data is not being transferred.
442
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
5:4
FRF
R/W
0x0
Description
SSI Frame Format Select
The FRF values are defined as follows:
Value Frame Format
0x0 Freescale SPI Frame Format
0x1 Texas Intruments Synchronous Serial Frame Format
0x2 MICROWIRE Frame Format
0x3 Reserved
3:0
DSS
R/W
0x00
SSI Data Size Select
The DSS values are defined as follows:
Value
Data Size
0x0-0x2 Reserved
0x3
4-bit data
0x4
5-bit data
0x5
6-bit data
0x6
7-bit data
0x7
8-bit data
0x8
9-bit data
0x9
10-bit data
0xA
11-bit data
0xB
12-bit data
0xC
13-bit data
0xD
14-bit data
0xE
15-bit data
0xF
16-bit data
April 08, 2008
443
Preliminary
Synchronous Serial Interface (SSI)
Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
SOD
MS
SSE
LBM
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
SOD
R/W
0
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
The SOD values are defined as follows:
Value Description
2
MS
R/W
0
0
SSI can drive SSITx output in Slave Output mode.
1
SSI must not drive the SSITx output in Slave mode.
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
SSI is disabled (SSE=0).
The MS values are defined as follows:
Value Description
0
Device configured as a master.
1
Device configured as a slave.
444
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
1
SSE
R/W
0
Description
SSI Synchronous Serial Port Enable
Setting this bit enables SSI operation.
The SSE values are defined as follows:
Value Description
0
SSI operation disabled.
1
SSI operation enabled.
Note:
0
LBM
R/W
0
This bit must be set to 0 before any control registers
are reprogrammed.
SSI Loopback Mode
Setting this bit enables Loopback Test mode.
The LBM values are defined as follows:
Value Description
0
Normal serial port operation enabled.
1
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
April 08, 2008
445
Preliminary
Synchronous Serial Interface (SSI)
Register 3: SSI Data (SSIDR), offset 0x008
SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO
(pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI
receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed
to by the current FIFO write pointer).
When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written
to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is
loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed
bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DATA
R/W
0x0000
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
446
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x00C
Type RO, reset 0x0000.0003
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BSY
RFF
RNE
TNF
TFE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
R0
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:5
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
BSY
RO
0
SSI Busy Bit
The BSY values are defined as follows:
Value Description
3
RFF
RO
0
0
SSI is idle.
1
SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
SSI Receive FIFO Full
The RFF values are defined as follows:
Value Description
2
RNE
RO
0
0
Receive FIFO is not full.
1
Receive FIFO is full.
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
Value Description
0
Receive FIFO is empty.
1
Receive FIFO is not empty.
April 08, 2008
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Preliminary
Synchronous Serial Interface (SSI)
Bit/Field
Name
Type
Reset
1
TNF
RO
1
Description
SSI Transmit FIFO Not Full
The TNF values are defined as follows:
Value Description
0
TFE
R0
1
0
Transmit FIFO is full.
1
Transmit FIFO is not full.
SSI Transmit FIFO Empty
The TFE values are defined as follows:
Value Description
0
Transmit FIFO is not empty.
1
Transmit FIFO is empty.
448
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
CPSDVSR
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CPSDVSR
R/W
0x00
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.
April 08, 2008
449
Preliminary
Synchronous Serial Interface (SSI)
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
TXIM
RXIM
RTIM
RORIM
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TXIM
R/W
0
SSI Transmit FIFO Interrupt Mask
The TXIM values are defined as follows:
Value Description
2
RXIM
R/W
0
0
TX FIFO half-full or less condition interrupt is masked.
1
TX FIFO half-full or less condition interrupt is not masked.
SSI Receive FIFO Interrupt Mask
The RXIM values are defined as follows:
Value Description
1
RTIM
R/W
0
0
RX FIFO half-full or more condition interrupt is masked.
1
RX FIFO half-full or more condition interrupt is not masked.
SSI Receive Time-Out Interrupt Mask
The RTIM values are defined as follows:
Value Description
0
RX FIFO time-out interrupt is masked.
1
RX FIFO time-out interrupt is not masked.
450
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
0
RORIM
R/W
0
Description
SSI Receive Overrun Interrupt Mask
The RORIM values are defined as follows:
Value Description
0
RX FIFO overrun interrupt is masked.
1
RX FIFO overrun interrupt is not masked.
April 08, 2008
451
Preliminary
Synchronous Serial Interface (SSI)
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x018
Type RO, reset 0x0000.0008
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
TXRIS
RXRIS
RTRIS
RORRIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TXRIS
RO
1
SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
2
RXRIS
RO
0
SSI Receive FIFO Raw Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
1
RTRIS
RO
0
SSI Receive Time-Out Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
0
RORRIS
RO
0
SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
452
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
TXMIS
RXMIS
RTMIS
RORMIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TXMIS
RO
0
SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
2
RXMIS
RO
0
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
1
RTMIS
RO
0
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
0
RORMIS
RO
0
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
April 08, 2008
453
Preliminary
Synchronous Serial Interface (SSI)
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x020
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RTIC
RORIC
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
W1C
0
W1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
RTIC
W1C
0
SSI Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0
RORIC
W1C
0
0
No effect on interrupt.
1
Clears interrupt.
SSI Receive Overrun Interrupt Clear
The RORIC values are defined as follows:
Value Description
0
No effect on interrupt.
1
Clears interrupt.
454
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024
The SSIDMACTL register is the DMA control register.
SSI DMA Control (SSIDMACTL)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
TXDMAE RXDMAE
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
TXDMAE
R/W
0
Transmit DMA Enable
If this bit is set to 1, DMA for the transmit FIFO is enabled.
0
RXDMAE
R/W
0
Receive DMA Enable
If this bit is set to 1, DMA for the receive FIFO is enabled.
April 08, 2008
455
Preliminary
Synchronous Serial Interface (SSI)
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID4
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID4
RO
0x00
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
456
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 5 (SSIPeriphID5)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID5
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID5
RO
0x00
SSI Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
April 08, 2008
457
Preliminary
Synchronous Serial Interface (SSI)
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 6 (SSIPeriphID6)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID6
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID6
RO
0x00
SSI Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
458
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 7 (SSIPeriphID7)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID7
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID7
RO
0x00
SSI Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
April 08, 2008
459
Preliminary
Synchronous Serial Interface (SSI)
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 0 (SSIPeriphID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE0
Type RO, reset 0x0000.0022
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
1
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0
7:0
PID0
RO
0x22
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
460
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 1 (SSIPeriphID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID1
RO
0x00
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
April 08, 2008
461
Preliminary
Synchronous Serial Interface (SSI)
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 2 (SSIPeriphID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID2
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID2
RO
0x18
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
462
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 3 (SSIPeriphID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
PID3
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID3
RO
0x01
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
April 08, 2008
463
Preliminary
Synchronous Serial Interface (SSI)
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID0
RO
0x0D
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
464
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 1 (SSIPCellID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID1
RO
0xF0
SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
April 08, 2008
465
Preliminary
Synchronous Serial Interface (SSI)
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 2 (SSIPCellID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID2
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
466
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 3 (SSIPCellID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
CID3
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
SSI PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
April 08, 2008
467
Preliminary
Inter-Integrated Circuit (I2C) Interface
16
Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C
bus may also be used for system testing and diagnostic purposes in product development and
manufacture. The LM3S3748 microcontroller includes two I2C modules, providing the ability to
interact (both send and receive) with other I2C devices on the bus.
®
Devices on the I2C bus can be designated as either a master or a slave. Each Stellaris I2C module
supports both sending and receiving data as either a master or a slave, and also supports the
simultaneous operation as both a master and a slave. There are a total of four I2C modes: Master
®
Transmit, Master Receive, Slave Transmit, and Slave Receive. The Stellaris I2C modules can
operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I2C master and slave can generate interrupts; the I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error) and the I2C slave generates
interrupts when data has been sent or requested by a master.
16.1
Block Diagram
Figure 16-1. I2C Block Diagram
I2CSCL
I2C Control
Interrupt
I2CMSA
I2CSOAR
I2CMCS
I2CSCSR
I2CMDR
I2CSDR
I2CMTPR
I2CSIM
I2CMIMR
I2CSRIS
I2CMRIS
I2CSMIS
I2CMMIS
I2CSICR
2
I C Master Core
I2CSCL
2
I C I/O Select
I2CSDA
I2CSCL
I2C Slave Core
I2CMICR
I2CSDA
I2CMCR
16.2
I2CSDA
Functional Description
Each I2C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I2C bus configuration is shown in Figure 16-2 on page 469.
See “I2C” on page 696 for I2C timing diagrams.
468
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Figure 16-2. I2C Bus Configuration
RPUP
SCL
SDA
I2C Bus
I2CSCL
I2CSDA
StellarisTM
16.2.1
RPUP
SCL
SDA
3rd Party Device
with I2C Interface
SCL
SDA
3rd Party Device
with I2C Interface
I2C Bus Functional Overview
®
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are high.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 469) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
16.2.1.1 START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP.
A high-to-low transition on the SDA line while the SCL is high is defined as a START condition, and
a low-to-high transition on the SDA line while SCL is high is defined as a STOP condition. The bus
is considered busy after a START condition and free after a STOP condition. See Figure
16-3 on page 469.
Figure 16-3. START and STOP Conditions
SDA
SDA
SCL
SCL
START
condition
STOP
condition
When operating in slave mode, two bits in the I2CRIS register indicate detection of start and stop
conditions on the bus; while two bits in the I2CSMIS register allow start and stop conditions to be
promoted to controller interrupts (when interrupts are enabled).
16.2.1.2 Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 16-4 on page 470. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction
bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates
a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a
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STOP condition. Various combinations of receive/send formats are then possible within a single
transfer.
Figure 16-4. Complete Data Transfer with a 7-Bit Address
SDA
MSB
SCL
1
2
LSB
R/S
ACK
7
8
9
Slave address
MSB
1
2
7
LSB
ACK
8
9
Data
The first seven bits of the first byte make up the slave address (see Figure 16-5 on page 470). The
eighth bit determines the direction of the message. A zero in the R/S position of the first byte means
that the master will write (send) data to the selected slave, and a one in this position means that
the master will receive data from the slave.
Figure 16-5. R/S Bit in First Byte
MSB
LSB
R/S
Slave address
16.2.1.3 Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is low (see Figure 16-6 on page 470).
Figure 16-6. Data Validity During Bit Transfer on the I2C Bus
SDA
SCL
Data line Change
stable
of data
allowed
16.2.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data
validity requirements described in “Data Validity” on page 470.
When a slave receiver does not acknowledge the slave address, SDA must be left high by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Since the master controls the number of bytes in the transfer, it signals the end
of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave
transmitter must then release SDA to allow the master to generate the STOP or a repeated START
condition.
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16.2.1.5 Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is high. During arbitration, the first of the
competing master devices to place a '1' (high) on SDA while another master transmits a '0' (low)
will switch off its data output stage and retire until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
16.2.2
Available Speed Modes
The I2C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP.
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see
page 488).
The I2C clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
Table 16-1 on page 471 gives examples of timer period, system clock, and speed mode (Standard
or Fast).
Table 16-1. Examples of I2C Master Timer Period versus Speed Mode
System Clock Timer Period Standard Mode Timer Period Fast Mode
4 Mhz
0x01
100 Kbps
-
-
6 Mhz
0x02
100 Kbps
-
-
12.5 Mhz
0x06
89 Kbps
0x01
312 Kbps
16.7 Mhz
0x08
93 Kbps
0x02
278 Kbps
20 Mhz
0x09
100 Kbps
0x02
333 Kbps
25 Mhz
0x0C
96.2 Kbps
0x03
312 Kbps
33Mhz
0x10
97.1 Kbps
0x04
330 Kbps
40Mhz
0x13
100 Kbps
0x04
400 Kbps
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System Clock Timer Period Standard Mode Timer Period Fast Mode
50Mhz
16.2.3
0x18
100 Kbps
0x06
357 Kbps
Interrupts
The I2C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master transaction error
■ Slave transaction received
■ Slave transaction requested
■ Stop condition on bus detected
■ Start condition on bus detected
There is a separate interrupt signal for the I2C master and I2C slave modules. While both modules
can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
16.2.3.1 I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or
receive), or when an error occurs during a transaction. To enable the I2C master interrupt, software
must write a '1' to the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition
is met, software must check the ERROR bit in the I2C Master Control/Status (I2CMCS) register to
verify that an error didn't occur during the last transaction. An error condition is asserted if the last
transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of
the bus due to a lost arbitration round with another master. If an error is not detected, the application
can proceed with the transfer. The interrupt is cleared by writing a '1' to the I2C Master Interrupt
Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Master Raw Interrupt Status (I2CMRIS) register.
16.2.3.2 I2C Slave Interrupts
The slave module generates interrupts as it receives data and transmit requests from an I2C master.
The slave module also generates interrupts when a start and stop condition is detected. To enable
an I2C slave interrupt, write a '1' to the appropriate bit in the I2C Slave Interrupt Mask (I2CSIMR)
register. Software determines whether the module should write (transmit) or read (receive) data
from the I2C Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave
Control/Status (I2CSCSR) register. If the slave module is in receive mode and the first byte of a
transfer is received, the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a
'1' to the I2C Slave Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Slave Raw Interrupt Status (I2CSRIS) register.
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16.2.4
Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This
is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In
loopback mode, the SDA and SCL signals from the master and slave modules are tied together.
16.2.5
Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and
slave mode.
16.2.5.1 I2C Master Command Sequences
The figures that follow show the command sequences available for the I2C master.
Figure 16-7. Master Single SEND
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Write data to
I2CMDR
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write ---0-111 to
I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Idle
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Figure 16-8. Master Single RECEIVE
Idle
Write Slave
Address to
I2CMSA
Sequence may be
omitted in a Single
Master system
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write ---00111 to
I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Read data from
I2CMDR
Idle
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Figure 16-9. Master Burst SEND
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Read I2CMCS
Write data to
I2CMDR
BUSY bit=0?
YES
Read I2CMCS
ERROR bit=0?
NO
NO
NO
BUSBSY bit=0?
YES
Write data to
I2CMDR
YES
Write ---0-011 to
I2CMCS
NO
ARBLST bit=1?
YES
Write ---0-001 to
I2CMCS
NO
Index=n?
YES
Write ---0-101 to
I2CMCS
Write ---0-100 to
I2CMCS
Error Service
Idle
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Idle
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Figure 16-10. Master Burst RECEIVE
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Read I2CMCS
BUSY bit=0?
Read I2CMCS
NO
YES
NO
BUSBSY bit=0?
ERROR bit=0?
NO
YES
Write ---01011 to
I2CMCS
NO
Read data from
I2CMDR
ARBLST bit=1?
YES
Write ---01001 to
I2CMCS
NO
Write ---0-100 to
I2CMCS
Index=m-1?
Error Service
YES
Write ---00101 to
I2CMCS
Idle
Read I2CMCS
BUSY bit=0?
NO
YES
NO
ERROR bit=0?
YES
Error Service
Read data from
I2CMDR
Idle
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Figure 16-11. Master Burst RECEIVE after Burst SEND
Idle
Master operates in
Master Transmit mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---01011 to
I2CMCS
Repeated START
condition is generated
with changing data
direction
Master operates in
Master Receive mode
Idle
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Figure 16-12. Master Burst SEND after Burst RECEIVE
Idle
Master operates in
Master Receive mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---0-011 to
I2CMCS
Repeated START
condition is generated
with changing data
direction
Master operates in
Master Transmit mode
Idle
16.2.5.2 I2C Slave Command Sequences
Figure 16-13 on page 479 presents the command sequence available for the I2C slave.
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Figure 16-13. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1 to
I2CSCSR
Read I2CSCSR
NO
TREQ bit=1?
YES
Write data to
I2CSDR
16.3
NO
RREQ bit=1?
FBR is
also valid
YES
Read data from
I2CSDR
Initialization and Configuration
The following example shows how to configure the I2C module to send a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation.
4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020.
5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
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TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;
TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
6. Specify the slave address of the master and that the next operation will be a Send by writing
the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired
data.
8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x0000.0007 (STOP, START, RUN).
9. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
16.4
I2C Register Map
Table 16-2 on page 480 lists the I2C registers. All addresses given are relative to the I2C base
addresses for the master and slave:
■ I2C Master 0: 0x4002.0000
■ I2C Slave 0: 0x4002.0800
■ I2C Master 1: 0x4002.1000
■ I2C Slave 1: 0x4002.1800
Table 16-2. Inter-Integrated Circuit (I2C) Interface Register Map
Offset
Description
See
page
Name
Type
Reset
0x000
I2CMSA
R/W
0x0000.0000
I2C Master Slave Address
482
0x004
I2CMCS
R/W
0x0000.0000
I2C Master Control/Status
483
0x008
I2CMDR
R/W
0x0000.0000
I2C Master Data
487
0x00C
I2CMTPR
R/W
0x0000.0001
I2C Master Timer Period
488
0x010
I2CMIMR
R/W
0x0000.0000
I2C Master Interrupt Mask
489
0x014
I2CMRIS
RO
0x0000.0000
I2C Master Raw Interrupt Status
490
0x018
I2CMMIS
RO
0x0000.0000
I2C Master Masked Interrupt Status
491
0x01C
I2CMICR
WO
0x0000.0000
I2C Master Interrupt Clear
492
0x020
I2CMCR
R/W
0x0000.0000
I2C Master Configuration
493
I2CSOAR
R/W
0x0000.0000
I2C Slave Own Address
495
I2C Master
I2C
Slave
0x000
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Offset
Name
0x004
Reset
I2CSCSR
RO
0x0000.0000
I2C Slave Control/Status
496
0x008
I2CSDR
R/W
0x0000.0000
I2C Slave Data
498
0x00C
I2CSIMR
R/W
0x0000.0000
I2C Slave Interrupt Mask
499
0x010
I2CSRIS
RO
0x0000.0000
I2C Slave Raw Interrupt Status
500
0x014
I2CSMIS
RO
0x0000.0000
I2C Slave Masked Interrupt Status
501
0x018
I2CSICR
WO
0x0000.0000
I2C Slave Interrupt Clear
502
16.5
Description
See
page
Type
Register Descriptions (I2C Master)
The remainder of this section lists and describes the I2C master registers, in numerical order by
address offset. See also “Register Descriptions (I2C Slave)” on page 494.
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Register 1: I2C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Send (Low).
I2C Master Slave Address (I2CMSA)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
SA
R/S
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:1
SA
R/W
0
I2C Slave Address
This field specifies bits A6 through A0 of the slave address.
0
R/S
R/W
0
Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or Send
(Low).
Value Description
0
Send.
1
Receive.
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Register 2: I2C Master Control/Status (I2CMCS), offset 0x004
This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I2C bus
controller.
The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes
the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed
(or aborted due an error), the interrupt pin becomes active and the data may be read from the
I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set
normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after
each byte. This bit must be reset when the I2C bus controller requires no further data to be sent
from the slave transmitter.
Read-Only Status Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BUSBSY
IDLE
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
ARBLST DATACK ADRACK ERROR
RO
0
RO
0
RO
0
RO
0
BUSY
RO
0
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
BUSBSY
RO
0
Bus Busy
This bit specifies the state of the I2C bus. If set, the bus is busy;
otherwise, the bus is idle. The bit changes based on the START and
STOP conditions.
5
IDLE
RO
0
I2C Idle
This bit specifies the I2C controller state. If set, the controller is idle;
otherwise the controller is not idle.
4
ARBLST
RO
0
Arbitration Lost
This bit specifies the result of bus arbitration. If set, the controller lost
arbitration; otherwise, the controller won arbitration.
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Bit/Field
Name
Type
Reset
3
DATACK
RO
0
Description
Acknowledge Data
This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data was
acknowledged.
2
ADRACK
RO
0
Acknowledge Address
This bit specifies the result of the last address operation. If set, the
transmitted address was not acknowledged; otherwise, the address was
acknowledged.
1
ERROR
RO
0
Error
This bit specifies the result of the last bus operation. If set, an error
occurred on the last operation; otherwise, no error was detected. The
error can be from the slave address not being acknowledged, the
transmit data not being acknowledged, or because the controller lost
arbitration.
0
BUSY
RO
I2C Busy
0
This bit specifies the state of the controller. If set, the controller is busy;
otherwise, the controller is idle. When the BUSY bit is set, the other status
bits are not valid.
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
reserved
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
3
2
1
0
ACK
STOP
START
RUN
WO
0
WO
0
WO
0
WO
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
WO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
ACK
WO
0
Data Acknowledge Enable
When set, causes received data byte to be acknowledged automatically
by the master. See field decoding in Table 16-3 on page 485.
2
STOP
WO
0
Generate STOP
When set, causes the generation of the STOP condition. See field
decoding in Table 16-3 on page 485.
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Bit/Field
Name
Type
Reset
1
START
WO
0
Description
Generate START
When set, causes the generation of a START or repeated START
condition. See field decoding in Table 16-3 on page 485.
0
RUN
WO
I2C Master Enable
0
When set, allows the master to send or receive data. See field decoding
in Table 16-3 on page 485.
Table 16-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3)
Current I2CMSA[0]
State
R/S
Idle
I2CMCS[3:0]
ACK
Description
STOP
START
RUN
0
X
a
0
1
1
0
X
1
1
1
START condition followed by a SEND and STOP
condition (master remains in Idle state).
1
0
0
1
1
START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
1
0
1
1
1
START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
1
1
0
1
1
START condition followed by RECEIVE (master goes to
the Master Receive state).
1
1
1
1
1
Illegal.
START condition followed by SEND (master goes to the
Master Transmit state).
All other combinations not listed are non-operations. NOP.
Master
Transmit
X
X
0
0
1
SEND operation (master remains in Master Transmit
state).
X
X
1
0
0
STOP condition (master goes to Idle state).
X
X
1
0
1
SEND followed by STOP condition (master goes to Idle
state).
0
X
0
1
1
Repeated START condition followed by a SEND (master
remains in Master Transmit state).
0
X
1
1
1
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
1
0
0
1
1
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
1
0
1
1
1
Repeated START condition followed by a SEND and
STOP condition (master goes to Idle state).
1
1
0
1
1
Repeated START condition followed by RECEIVE (master
goes to Master Receive state).
1
1
1
1
1
Illegal.
All other combinations not listed are non-operations. NOP.
April 08, 2008
485
Preliminary
Inter-Integrated Circuit (I2C) Interface
Current I2CMSA[0]
State
R/S
Master
Receive
I2CMCS[3:0]
Description
ACK
STOP
START
RUN
X
0
0
0
1
RECEIVE operation with negative ACK (master remains
in Master Receive state).
X
X
1
0
0
STOP condition (master goes to Idle state).
X
0
1
0
1
RECEIVE followed by STOP condition (master goes to
Idle state).
X
1
0
0
1
RECEIVE operation (master remains in Master Receive
state).
X
1
1
0
1
Illegal.
1
0
0
1
1
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
1
0
1
1
1
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
1
1
0
1
1
Repeated START condition followed by RECEIVE (master
remains in Master Receive state).
0
X
0
1
1
Repeated START condition followed by SEND (master
goes to Master Transmit state).
0
X
1
1
1
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
b
All other combinations not listed are non-operations. NOP.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
486
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 3: I2C Master Data (I2CMDR), offset 0x008
This register contains the data to be transmitted when in the Master Transmit state, and the data
received when in the Master Receive state.
I2C Master Data (I2CMDR)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DATA
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DATA
R/W
0x00
Data Transferred
Data transferred during transaction.
April 08, 2008
487
Preliminary
Inter-Integrated Circuit (I2C) Interface
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C
This register specifies the period of the SCL clock.
I2C Master Timer Period (I2CMTPR)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x00C
Type R/W, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
TPR
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
TPR
R/W
0x1
SCL Clock Period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 255).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
488
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
IM
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
IM
R/W
0
Interrupt Mask
This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.
April 08, 2008
489
Preliminary
Inter-Integrated Circuit (I2C) Interface
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RIS
RO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RIS
RO
0
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I2C
master block. If set, an interrupt is pending; otherwise, an interrupt is
not pending.
490
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
MIS
RO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
MIS
RO
0
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I2C master
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
April 08, 2008
491
Preliminary
Inter-Integrated Circuit (I2C) Interface
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C
This register clears the raw interrupt.
I2C Master Interrupt Clear (I2CMICR)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x01C
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
IC
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
IC
WO
0
Interrupt Clear
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise, a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.
492
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 9: I2C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
SFE
MFE
RO
0
RO
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
reserved
RO
0
RO
0
LPBK
RO
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SFE
R/W
0
I2C Slave Function Enable
This bit specifies whether the interface may operate in Slave mode. If
set, Slave mode is enabled; otherwise, Slave mode is disabled.
4
MFE
R/W
0
I2C Master Function Enable
This bit specifies whether the interface may operate in Master mode. If
set, Master mode is enabled; otherwise, Master mode is disabled and
the interface clock is disabled.
3:1
reserved
RO
0x00
0
LPBK
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Loopback
This bit specifies whether the interface is operating normally or in
Loopback mode. If set, the device is put in a test mode loopback
configuration; otherwise, the device operates normally.
April 08, 2008
493
Preliminary
Inter-Integrated Circuit (I2C) Interface
16.6
Register Descriptions (I2C Slave)
The remainder of this section lists and describes the I2C slave registers, in numerical order by
address offset. See also “Register Descriptions (I2C Master)” on page 481.
494
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000
®
This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus.
I2C Slave Own Address (I2CSOAR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
OAR
R/W
0
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:0
OAR
R/W
0x00
I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
April 08, 2008
495
Preliminary
Inter-Integrated Circuit (I2C) Interface
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First
®
Byte Received (FBR) bit is set only after the Stellaris device detects its own slave address
and receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates
®
that the Stellaris I2C device has received a data byte from an I2C master. Read one data byte from
the I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit
®
indicates that the Stellaris I2C device is addressed as a Slave Transmitter. Write one data byte
2
into the I C Slave Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
®
Stellaris I2C slave operation.
Read-Only Status Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
FBR
TREQ
RREQ
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
FBR
RO
0
First Byte Received
Indicates that the first byte following the slave’s own address is received.
This bit is only valid when the RREQ bit is set, and is automatically cleared
when data has been read from the I2CSDR register.
Note:
1
TREQ
RO
0
This bit is not used for slave transmit operations.
Transmit Request
This bit specifies the state of the I2C slave with regards to outstanding
transmit requests. If set, the I2C unit has been addressed as a slave
transmitter and uses clock stretching to delay the master until data has
been written to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
496
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
0
RREQ
RO
0
Description
Receive Request
This bit specifies the status of the I2C slave with regards to outstanding
receive requests. If set, the I2C unit has outstanding receive data from
the I2C master and uses clock stretching to delay the master until the
data has been read from the I2CSDR register. Otherwise, no receive
data is outstanding.
Write-Only Control Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
DA
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DA
WO
0
Device Active
Value Description
0
Disables the I2C slave operation.
1
Enables the I2C slave operation.
April 08, 2008
497
Preliminary
Inter-Integrated Circuit (I2C) Interface
Register 12: I2C Slave Data (I2CSDR), offset 0x008
This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DATA
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DATA
R/W
0x0
Data for Transfer
This field contains the data for transfer during a slave receive or transmit
operation.
498
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
STOPIM STARTIM DATAIM
RO
0
RO
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
STOPIM
RO
0
Stop Condition Interrupt Mask
This bit controls whether the raw interrupt for detection of a stop condition
on the I2C bus is promoted to a controller interrupt. If set, the interrupt
is not masked and the interrupt is promoted; otherwise, the interrupt is
masked.
1
STARTIM
RO
0
Start Condition Interrupt Mask
This bit controls whether the raw interrupt for detection of a start condition
on the I2C bus is promoted to a controller interrupt. If set, the interrupt
is not masked and the interrupt is promoted; otherwise, the interrupt is
masked.
0
DATAIM
R/W
0
Data Interrupt Mask
This bit controls whether the raw interrupt for data received and data
requested is promoted to a controller interrupt. If set, the interrupt is not
masked and the interrupt is promoted; otherwise, the interrupt is masked.
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Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
STOPRIS STARTRIS DATARIS
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
STOPRIS
RO
0
Stop Condition Raw Interrupt Status
This bit specifies the raw interrupt state for stop condition detect (prior
to masking) of the I2C slave block. If set, an interrupt is pending;
otherwise, an interrupt is not pending.
1
STARTRIS
RO
0
Start Condition Raw Interrupt Status
This bit specifies the raw interrupt state for start condition detect (prior
to masking) of the I2C slave block. If set, an interrupt is pending;
otherwise, an interrupt is not pending.
0
DATARIS
RO
0
Data Raw Interrupt Status
This bit specifies the raw interrupt state for data received and data
requested (prior to masking) of the I2C slave block. If set, an interrupt
is pending; otherwise, an interrupt is not pending.
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Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
STOPMIS STARTMIS DATAMIS
RW
0
RW
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
STOPMIS
RW
0
Stop Condition Masked Interrupt Status
This bit specifies the interrupt state for stop condition detect (after
masking) of the I2C slave block. If set, an interrupt was signaled;
otherwise, an interrupt has not been generated since the bit was last
cleared.
1
STARTMIS
RW
0
Start Condition Masked Interrupt Status
This bit specifies the interrupt state for start condition detect (after
masking) of the I2C slave block. If set, an interrupt was signaled;
otherwise, an interrupt has not been generated since the bit was last
cleared.
0
DATAMIS
RO
0
Data Masked Interrupt Status
This bit specifies the interrupt state for data received and data requested
(after masking) of the I2C slave block. If set, an interrupt was signaled;
otherwise, an interrupt has not been generated since the bit was last
cleared.
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Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018
This register clears the raw interrupt. A read of this register returns no meaningful data.
I2C Slave Interrupt Clear (I2CSICR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x018
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
STOPIC STARTIC DATAIC
WO
0
WO
0
WO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
STOPIC
WO
0
Stop Condition Interrupt Clear
This bit controls the clearing of the raw interrupt for stop condition detect.
When set, it clears the STOPRIS interrupt bit; otherwise, it has no effect
on the STOPRIS bit value.
1
STARTIC
WO
0
Start Condition Interrupt Clear
This bit controls the clearing of the raw interrupt for start condition detect.
When set, it clears the STARTRIS interrupt bit; otherwise, it has no effect
on the STARTRIS bit value.
0
DATAIC
WO
0
Data Interrupt Clear
This bit controls the clearing of the raw interrupt for data received and
data requested. When set, it clears the DATARIS interrupt bit; otherwise,
it has no effect on the DATARIS bit value.
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LM3S3748 Microcontroller
17
Univeral Serial Bus (USB) Controller
®
The Stellaris USB controller operates as a function controller for a full-speed or low-speed host or
device in point-to-point or multipoint (hub) communications with USB functions. The controller
complies with the USB 2.0 standard, which includes suspend and resume signaling. Three
configurable endpoints (1-3) with a dynamic sizable FIFO support multiple packet queueing. DMA
access to the FIFO allows minimal interference from system software. The controller has the capability
to access an external power regulator through a power enable pad output (USB0EPEN) and power
fault detect pad input (USB0PFLT).
®
The Stellaris USB module has the following features:
■ Standards-based
■ USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation
■ USB Host mode
■ Integrated PHY
■ 4 transfer types: control, interrupt, bulk, and isochronous
■ 1 dedicated bi-directional control endpoint
■ 3 receive and 3 transmit configurable endpoints
■ 4 KB dedicated endpoint memory
– Direct Memory Access
– One endpoint may be defined for double-buffered 1023-byte isochronous packet size
17.1
Block Diagram
Figure 17-1. USB Module Block Diagram
Endpoint Control
DMA
Requests
Transmit
EP0 – 3
Control
Receive
CPU Interface
Combine
Endpoints
Host
Transaction
Scheduler
Interrupt
Control
Interrupts
EP Reg.
Decoder
UTM
Synchronization
Packet
Encode/Decode
Packet Encode
USB PHY
FIFO RAM
Controller
Rx
Rx
Buff
Buff
Data Sync
Packet Decode
USB Data Lines
D+ and D-
USB FS/LS
PHY
Tx
Buff
April 08, 2008
AHB bus –
Slave mode
Cycle
Control
Tx
Buff
Timers
CRC Gen/Check
Common
Regs
Cycle Control
FIFO
Decoder
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Univeral Serial Bus (USB) Controller
17.2
Functional Description
®
The Stellaris USB controller provides the ability for the controller to switch from host controller to
device controller functionality. The USB controller requires both A and B connectors in the system
to provide host or device connectivity. If both connectors are present, the controller provides external
signals to enable or disable power to the USB0VBUS pin on the USB connector when not in use.
The controller can only be used in host or device mode and cannot be used in both modes
simultaneously. However, the controller can be manually switched at run time if the system requires
both host and device functionality.
17.2.1
Operation as a Device
®
This section describes the Stellaris USB controller's actions when it is being used as a USB device.
IN endpoints, OUT endpoints, entry into and exit from Suspend mode, and recognition of Start of
Frame (SOF) are all described.
When in device mode, IN transactions are controlled by an endpoint’s transmit interface and use
the transmit endpoint registers for the given endpoint. OUT transactions are handled with an
endpoint's receive interface and use the receive endpoint registers for the given endpoint.
When configuring the size of the FIFOs for endpoints, take into account the maximum packet size
for an endpoint.
■ Bulk. Bulk endpoints should be sized to be multiples of the maximum packet size (up to 64
bytes). For instance, if maximum packet size is 64 bytes, the FIFO should be configured to a
multiple of 64-byte packets (64, 128, 192, or 256 bytes). This allows for efficient use of double
buffering or packet splitting (described further in the following sections).
■ Interrupt. Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or
twice the maximum packet size if double buffering is used.
■ Isochronous.
Isochronous endpoints are more flexible and can be up to 1023 bytes.
■ Control. It is also possible to specify a separate control endpoint for a USB device. However,
in most cases the USB device should use the dedicated control endpoint on the USB controller’s
endpoint 0.
17.2.1.1 Endpoints
When operating as a device, there is a single dedicated bidirectional control endpoint on endpoint
0 and three additional endpoints that can be used for both IN and OUT communications with a host
controller. The endpoint number associated with an endpoint is directly related to its register
designation. For example, when the host is communicating with endpoint 1, all events will occur in
the endpoint 1 register interface.
Endpoint 0 is a dedicated control endpoint used for all control transactions to endpoint 0 during
enumeration or when any other control requests are made to endpoint 0. Endpoint 0 uses the first
64 bytes of the USB controller's FIFO RAM as a shared memory for both IN and OUT transactions.
The remaining three endpoints can be configured as control, bulk, interrupt or isochronous endpoints.
They should be treated as three OUT and three IN endpoints with endpoint numbers 1, 2, and 3.
The endpoints are not required to have the same type for their IN and OUT endpoint configuration.
For example, the OUT portion of an endpoint could be a bulk endpoint, while the IN portion could
be an interrupt endpoint. The address and size of the FIFOs attached to each endpoint can be
modified to fit the application's needs.
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17.2.1.2 IN Transactions
When operating as a USB device, data for IN transactions is handled through the FIFOs attached
to transmit endpoints. The sizes of the FIFOs for endpoints 1 to 3 are determined by the
USBTXFIFOADD register. The maximum size of a data packet that may be placed in a transmit
endpoint’s FIFO for transmission is programmable and is determined by the value written to the
USBTXMAXPn register for that endpoint. The endpoint’s FIFO can also be configured to use
double-packet or single-packet buffering. When double-packet buffering is enabled, two data packets
can be buffered in the FIFO, which also requires that the FIFO is at least two packets in size. When
double-packet buffering is disabled, only one packet can be buffered, even if the packet size is less
than half the FIFO size. The USB controller also supports a special mode for bulk endpoints that
allows automatic splitting of a larger FIFO into multiple packets that are maximum packet size
transfers.
Note:
The maximum packet size set for any endpoint must not exceed the FIFO size. The
USBTXMAXPn register should not be written to while there is data in the FIFO as unexpected
results may occur.
Single-Packet Buffering
If the size of the transmit endpoint's FIFO is less than twice the maximum packet size for this endpoint
(as set in the USBTXFIFOSZ register), only one packet can be buffered in the FIFO and single-packet
buffering is required. When each packet is completely loaded into the transmit FIFO, the TXRDY bit
in the USBTXCSRLn register needs to be set. If the AUTOSET bit in the USBTXCSRHn register is
set, the TXRDY bit is automatically set when a maximum sized packet is loaded into the FIFO. For
packet sizes less than the maximum, the TXRDY bit must be set manually. When the TXRDY bit is
set, either manually or automatically, the packet is ready to be sent. When the packet has been
successfully sent, both TXRDY and FIFONE are cleared and the appropriate transmit endpoint
interrupt signaled. At this point, the next packet can be loaded into the FIFO.
Double-Packet Buffering
If the size of the transmit endpoint's FIFO is at least twice the maximum packet size for this endpoint,
two packets can be buffered in the FIFO and double-packet buffering is allowed. As each packet is
loaded into the transmit FIFO, the TXRDY bit in in the USBTXCSRLn register needs to be set. If the
AUTOSET bit in the USBTXCSRHn register is set, the TXRDY bit is automatically set when a maximum
sized packet is loaded into the FIFO. For packet sizes less than the maximum, TXRDY must be set
manually. When the TXRDY bit is set, either manually or automatically, the packet is ready to be
sent. After the first packet is loaded, TXRDY is immediately cleared and an interrupt is generated.
A second packet can now be loaded into the transmit FIFO and TXRDY set again (either manually
or automatically if the packet is the maximum size). At this point, both packets are ready to be sent.
After each packet has been successfully sent, TXRDY is cleared and the appropriate transmit endpoint
interrupt signaled to indicate that another packet can now be loaded into the transmit FIFO. The
state of the FIFONE bit at this point indicates how many packets may be loaded. If the FIFONE bit
is set, then there is another packet in the FIFO and only one more packet can be loaded. If the
FIFONE bit is clear, then there are no packets in the FIFO and two more packets can be loaded.
Note:
Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the
USBTXDPKTBUFDIS register. This bit is set by default, so it must be cleared to enable
double-packet buffering.
Special Bulk Handling
The packets transferred in bulk operations are defined by the USB specification to be 8, 16, 32 or
64 bytes in size. For some system designs, however, it may be more convenient for the application
April 08, 2008
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software to write larger amounts of data to an endpoint in a single operation than can be transferred
in a single USB operation.
®
To simplify this case, the Stellaris USB controller includes a packet-splitting feature that allows
larger data packets to be written to bulk transmit endpoints, which are then split into packets of an
appropriate size for transfer across the USB bus. With this option, the USBTXMAXPn register uses
the bottom 11 bits to define the payload for each individual transfer, while the top 5 bits define a
multiplier. The application software can then write data packets of size multiplier × payload to the
FIFO, which the USB controller then splits into individual packets of the stated payload for
transmission over the USB bus. From the application software’s point-of-view, the resulting operation
does not differ from the transmission of a single USB packet except in the size of the packet written.
Note:
Packet-splitting can only be used with bulk endpoints and, in accordance with the USB
specification, the payload must be 8, 16, 32, or 64. The payload recorded in the
USBTXMAXPn register must also match the wMaxPacketSize field of the Standard
Endpoint Descriptor for the endpoint (see chapter 9 of the USB specification). The associated
FIFO must also be large enough to accommodate the data packet prior to being split.
17.2.1.3 OUT Transactions as a Device
When in device mode, OUT transactions are handled through the USB controller receive FIFOs.
The sizes of the receive FIFOs for endpoints 1-3 are determined by the USBRXFIFOADD register.
The maximum amount of data received by an endpoint in any packet is determined by the value
written to the USBRXMAXPn register for that endpoint. When double-packet buffering is enabled,
two data packets can be buffered in the FIFO. When double-packet buffering is disabled, only one
®
packet can be buffered even if the packet is less than half the FIFO size. The Stellaris USB controller
also supports a special mode for bulk endpoints that allows automatic splitting of a larger FIFO into
multiple maximum packet size transfers.
Note:
In all cases, the maximum packet size must not exceed the FIFO size.
Single-Packet Buffering
If the size of the receive endpoint FIFO is less than twice the maximum packet size for an endpoint,
only one data packet can be buffered in the FIFO and single-packet buffering is required. When a
packet is received and placed in the receive FIFO, the RXRDY and FULL bits in the USBRXCSRLn
register are set and the appropriate receive endpoint is signaled, indicating that a packet can now
be unloaded from the FIFO. After the packet has been unloaded, the RXRDY bit needs to be cleared
in order to allow further packets to be received. This action also generates the acknowledge signaling
to the host controller. If the AUTOCL bit in the USBRXCSRHn register is set and a maximum-sized
packet is unloaded from the FIFO, the RXRDY and FULL bits are cleared automatically. For packet
sizes less than the maximum, RXRDY must be cleared manually.
Double-Packet Buffering
If the size of the receive endpoint FIFO is at least twice the maximum packet size for the endpoint,
two data packets can be buffered and double-packet buffering can be used. When the first packet
is received and loaded into the receive FIFO, the RXRDY bit in the USBRXCSRLn register is set
and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now be
unloaded from the FIFO.
Note:
The FULL bit in USBRXCSRLn is not set when the first packet is received. It is only set if
a second packet is received and loaded into the receive FIFO.
After each packet has been unloaded, the RXRDY bit needs to be cleared in order to allow further
packets to be received. If the AUTOCL bit in the USBRXCSRHn register is set and a maximum-sized
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April 08, 2008
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LM3S3748 Microcontroller
packet is unloaded from the FIFO, the RXRDY bit is cleared automatically. For packet sizes less than
the maximum, RXRDY must be cleared manually. If the FULL bit was set when RXRDY is cleared,
the USB controller first clears the FULL bit. It then sets RXRDY again to indicate that there is another
packet waiting in the FIFO to be unloaded.
Note:
Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the
USBRXDPKTBUFDIS register. This bit is set by default, so it must be cleared to enable
double-packet buffering.
Special Bulk Handling
The packets transferred in bulk operations are defined by the USB specification to be 8, 16, 32, or
64 bytes in size. For some system designs, however, it may be more convenient for the application
software to read larger amounts of data from an endpoint in a single operation than can be transferred
in a single USB operation.
®
To simplify this case, the Stellaris USB controller includes a packet-combining feature that combines
the packets received across the USB bus into larger data packets prior to being read by the
application software. With this option, the USBRXMAXPn register uses the bottom 11 bits to define
the payload for each individual transfer, while the top 5 bits define a multiplier. The USB controller
then combines the appropriate number of USB packets it receives into a single data packet of size
multiplier × payload within the FIFO before asserting RXRDY to alert the application software that a
packet in the FIFO is ready to be read. The size of the resulting packet is reported in the
USBRXCOUNTn register. From the application software’s point-of-view, the resulting operation
does not differ from the receipt of a single USB packet except in the size of the packet read.
Note:
Packet-combining can only be used with bulk endpoints. The payload recorded in the
USBRXMAXPn register must also match the wMaxPacketSize field of the Standard
Endpoint Descriptor for the endpoint (see chapter 9 of the USB specification). The associated
FIFO must also be large enough to accommodate the combined data packet.
The RXRDY bit is only set when either the specified number of packets have been received or a
“short” USB packet is received (that is, a packet of less than the specified payload for the endpoint).
If a protocol is being used in which the endpoint receives bulk transfers that are a multiple of the
recorded payload size with no short packet to terminate it, the USBRXMAXPn register should not
be programmed to expect more packets than there are in the transfer (otherwise, the software will
not be interrupted at the end of the transfer).
17.2.1.4 Scheduling
The device has no control over the scheduling of transactions as this is determined by the host
®
controller. The Stellaris USB controller can set up a transaction at any time. The USB controller
will wait for the request from the host controller and generate an interrupt when the transaction is
complete or if it was terminated due to some error. If the host controller makes a request and the
device controller is not ready, the USB controller sends a busy response (NAK) to all requests until
it is ready.
17.2.1.5 Additional Actions
The USB controller responds automatically to certain conditions on the USB bus or actions by the
host controller: when the USB controller automatically stalls a control transfer and unexpected zero
length OUT data packets.
Stalled Control Transfer
The USB controller automatically issues a STALL handshake to a control transfer under the following
conditions:
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1. The host sends more data during an OUT data phase of a control transfer than was specified
in the device request during the SETUP phase. This condition is detected by the USB controller
when the host sends an OUT token (instead of an IN token) after the last OUT packet has been
unloaded and the DATAEND bit in the USBCSRL0 register has been set.
2. The host requests more data during an IN data phase of a control transfer than was specified
in the device request during the SETUP phase. This condition is detected by the USB controller
when the host sends an IN token (instead of an OUT token) after the CPU has cleared TXRDY
and set DATAEND in response to the ACK issued by the host to what should have been the last
packet.
3. The host sends more than USBRXMAXPn bytes of data with an OUT data token.
4. The host sends more than a zero length data packet for the OUT status phase.
Zero Length OUT Data Packets
A zero-length OUT data packet is used to indicate the end of a control transfer. In normal operation,
such packets should only be received after the entire length of the device request has been
transferred.
However, if the host sends a zero-length OUT data packet before the entire length of device request
has been transferred, it is signaling the premature end of the transfer. In this case, the USB controller
automatically flushes any IN token ready for the data phase from the FIFO and sets the SETUP bit
in the USBCSRL0 register.
17.2.1.6 Device Mode Suspend
When no activity has occurred on the USB bus for 3 ms, the USB controller automatically enters
Suspend mode. If the Suspend interrupt has been enabled, an interrupt is generated at this time.
When in Suspend mode, the PHY also goes into Suspend mode. When Resume signaling is detected,
the USB controller exits Suspend mode and takes the PHY out of Suspend. If the Resume interrupt
is enabled, an interrupt is generated. The USB controller can also be forced to exit Suspend mode
by setting the RESUME bit in the USBPOWER register. When this bit is set, the USB controller exits
Suspend mode and drives Resume signaling onto the bus. The RESUME bit is cleared after 10 ms
(a maximum of 15 ms) to end Resume signaling.
To meet USB power requirements, the controller can be put into Deep Sleep. This keeps the controller
in a static state. The USB controller is not able to Hibernate since this will cause all the internal
states to be lost.
17.2.1.7 Start-of-Frame
When the USB controller is operating in device mode, it receives a Start-Of-Frame packet from the
host once every millisecond. When the SOF packet is received, the 11-bit frame number contained
in the packet is written into the USBFRAME register and an SOF interrupt is also signaled and can
be handled by the application. Once the USB controller has started to receive SOF packets, it
expects one every millisecond. If no SOF packet is received after 1.00358 ms, it is assumed that
the packet has been lost and the USBFRAME register is not updated. The USB controller continues
and resynchronizes these pulses to the received SOF packets when these packets are successfully
received again.
17.2.1.8 USB Reset
When the USB controller is in device mode and a reset condition is detected on the USB bus, the
USB controller automatically performs the following actions:
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April 08, 2008
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LM3S3748 Microcontroller
■ Clears the USBFADDR register.
■ Clears the USBEPIDX register.
■ Flushes all endpoint FIFOs.
■ Clears all control/status registers.
■ Enables all endpoint interrupts.
■ Generates a reset interrupt.
When the application software driving the USB controller receives a reset interrupt, it closes any
open pipes and waits for bus enumeration to begin.
17.2.1.9 Connect/Disconnect
The USB controller connection to the USB bus is controlled by software. The USB PHY can be
switched between normal mode and non-driving mode by setting or clearing the SOFTCONN bit of
the USBPOWER register. When this SOFTCONN bit is set, the PHY is placed in its normal mode
and the USB0DP/USB0DM lines of the USB bus are enabled. At the same time, the USB controller
is placed into a state, in which it will not respond to any USB signaling except a USB reset.
When the SOFTCONN bit is cleared, the PHY is put into non-driving mode, USB0DP and USB0DM are
tristated, and the USB controller appears to other devices on the USB bus as if it has been
disconnected. This is the default so the USB controller appears disconnected until the SOFTCONN
bit has been set. The application software can then choose when to set the PHY into its normal
mode. Systems with a lengthy initialization procedure may use this to ensure that initialization is
complete and the system is ready to perform enumeration before connecting to the USB. Once the
SOFTCONN bit has been set, the USB controller can be disconnected by clearing this bit.
Note:
17.2.2
The USB controller does not generate an interrupt when the device is connected to the
host. However, an interrupt is generated when the host terminates a session.
Operation as a Host
®
When the Stellaris USB controller is operating in host mode, it can either be used for point-to-point
communications with another USB device or, when attached to a hub, for communication with
multiple devices. Full-speed and low-speed USB devices are supported, both for point-to-point
communication and for operation through a hub. The USB controller automatically carries out the
necessary transaction translation needed to allow a low-speed or full-speed device to be used with
a USB 2.0 hub. Control, bulk, isochronous and interrupt transactions are supported. This section
describes the USB host controller’s actions with regards to transmit endpoints, receive endpoints,
transaction scheduling, entry into and exit from Suspend mode, and reset.
When in host mode, IN transactions are controlled by an endpoint’s receive interface. All IN
transactions use the receive endpoint registers and all OUT endpoints use the transmit endpoint
registers for a given endpoint. As in device mode, the FIFOs for endpoints should take into account
the maximum packet size for an endpoint.
■ Bulk. Bulk endpoints should be sized to be multiples of the maximum packet size (up to 64
bytes). For instance, if maximum packet size is 64 bytes, the FIFO should be configured to a
multiple of 64-byte packets (64, 128, 192, or 256 bytes). This allows for efficient use of double
buffering or packet splitting (described further in the following sections).
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■ Interrupt. Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or
twice the maximum packet size if double buffering is used.
■ Isochronous.
Isochronous endpoints are more flexible and can be up to 1023 bytes.
■ Control. It is also possible to specify a separate control endpoint to communicate with a device.
However, in most cases the USB controller should use the dedicated control endpoint to
communicate with a device’s endpoint 0.
17.2.2.1 Endpoints
The endpoint registers are used to control the USB endpoint interfaces used to communicate with
device(s) that are connected. There is a dedicated bidirectional control IN/OUT interface, three
configurable OUT interfaces, and three configurable IN interfaces.
The dedicated control interface can only be used for control transactions to endpoint 0 of devices.
These control transactions are used during enumeration or other control functions that communicate
using endpoint 0 of devices. This control endpoint shares the first 64 bytes of the USB controller’s
FIFO RAM for IN and OUT transactions. The remaining IN and OUT interfaces can be configured
to communicate with control, bulk, interrupt, or isochronous device endpoints.
These USB interfaces can be used to simultaneously schedule as many as three independent OUT
and three independent IN transactions to any endpoints on any device. The IN and OUT controls
are paired in three sets of registers. However, they can be configured to communicate with different
types of endpoints and different endpoints on devices. For example, the first pair of endpoint controls
can be split so that the OUT portion is communicating with a device’s bulk OUT endpoint 1, while
the IN portion is communicating with a device’s interrupt IN endpoint 2.
Before accessing any device, whether for point-to-point communications or for communications via
a hub, the relevant USBRXFUNCADDRn or USBTXFUNCADDRn registers need to be set for each
receive or transmit endpoint to record the address of the device being accessed.
The USB controller also supports connections to devices through a USB hub by providing a register
that specifies the hub address and port of each USB transfer. The FIFO address and size are
customizable and can be specified for each USB IN and OUT transfer. This includes allowing one
FIFO per transaction, sharing a FIFO across transactions, and allowing for double-buffered FIFOs.
17.2.2.2 IN Transactions as a Host
IN transactions are handled in a similar manner to the way in which OUT transactions are handled
when the USB controller is in Device mode except that the transaction first needs to be initiated by
setting the REQPKT bit in USBCSRL0. This indicates to the transaction scheduler that there is an
active transaction on this endpoint. The transaction scheduler then sends an IN token to the target
device. When the packet is received and placed in the receive FIFO, the RXRDY bit in USBCSRL0
is set and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now
be unloaded from the FIFO.
When the packet has been unloaded, RXRDY should be cleared. The AUTOCL bit in the
USBRXCSRHn register can be used to have RXRDY automatically cleared when a maximum-sized
packet has been unloaded from the FIFO. There is also an AUTORQ bit in USBRXCSRHn which
causes the REQPKT bit to be automatically set when the RXRDY bit is cleared. The AUTOCL and
AUTORQ bits can be used with DMA accesses to perform complete bulk transfers without main
processor intervention. When the RXRDY bit is cleared, the controller will send an acknowledge to
the device. When there is a known number of packets to be transferred, the USBRQPKTCOUNTn
register associated with the endpoint should be set to the number of packets to be transferred. The
USB controller decrements the value in the USBRQPKTCOUNTn register following each request.
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When the USBRQPKTCOUNTn value decrements to 0, the AUTORQ bit is cleared to prevent any
further transactions being attempted. For cases where the size of the transfer is unknown,
USBRQPKTCOUNTn should be left set to zero. AUTORQ then remains set until cleared by the
reception of a short packet (that is, less than MaxP) such as may occur at the end of a bulk transfer.
If the device responds to a bulk or interrupt IN token with a NAK, the USB host controller keeps
retrying the transaction until any NAK Limit that has been set has been reached. If the target device
responds with a STALL, however, the USB host controller does not retry the transaction but interrupts
the CPU with the STALLED bit in the USBCSRL0 register set. If the target device does not respond
to the IN token within the required time, or there was a CRC or bit-stuff error in the packet, the USB
host controller retries the transaction. If after three attempts the target device has still not responded,
the USB host controller clears the REQPKT bit and interrupts the CPU by setting the ERROR bit in
the USBCSRL0 register.
17.2.2.3 Out Transactions as a Host
OUT transactions are handled in a similar manner to the way in which IN transactions are handled
when the USB controller is in Device mode. The TXRDY bit in the USBTXCSRLn register needs to
be set as each packet is loaded into the transmit FIFO. Again, setting the AUTOSET bit in the
USBTXCSRHn register automatically sets TXRDY when a maximum-sized packet has been loaded
into the FIFO. Furthermore, AUTOSET can be used with a DMA controller to perform complete bulk
transfers without software intervention.
If the target device responds to the OUT token with a NAK, the USB host controller keeps retrying
the transaction until the NAK Limit that has been set has been reached. However, if the target device
responds with a STALL, the USB controller does not retry the transaction but interrupts the main
processor by setting the STALLED bit in the USBTXCSRLn register. If the target device does not
respond to the OUT token within the required time, or there was a CRC or bit-stuff error in the packet,
the USB host controller retries the transaction. If after three attempts the target device has still not
responded, the USB controller flushes the FIFO and interrupts the main processor by setting the
ERROR bit in the USBTXCSRLn register.
17.2.2.4 Transaction Scheduling
Scheduling of transactions is handled automatically by the USB host controller. The host controller
allows configuration of the endpoint communication scheduling based on the type of endpoint
transaction. Interrupt transactions can be scheduled to occur in the range of every frame to every
255 frames in 1 frame increments. Bulk endpoints do not allow scheduling parameters, but do allow
for a NAK timeout in the event an endpoint on a device is not responding. Isochronous endpoints
can be scheduled from every frame to every 216 frames, in powers of 2.
The USB controller maintains a frame counter. If the target device is a full-speed device, the USB
controller automatically sends an SOF packet at the start of each frame and increments the frame
counter. If the target device is a low-speed device, a ‘K’ state is transmitted on the bus to act as a
“keep-alive” to stop the low-speed device from going into Suspend mode.
After the SOF packet has been transmitted, the USB host controller cycles through all the configured
endpoints looking for active transactions. An active transaction is defined as a receive endpoint for
which the REQPKT bit is set or a transmit endpoint for which the TXRDY bit and/or the FIFONE bit is
set.
An active isochronous or interrupt transaction starts only if it is found on the first transaction scheduler
cycle of a frame and if the interval counter for that endpoint has counted down to zero. This ensures
that only one interrupt or isochronous transaction occurs per endpoint every n frames, where n is
the interval set via the USBTXINTERVALn or USBRXINTERVALn register for that endpoint.
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An active bulk transaction starts immediately, provided there is sufficient time left in the frame to
complete the transaction before the next SOF packet is due. If the transaction needs to be retried
(for example, because a NAK was received or the target device did not respond), then the transaction
is not retried until the transaction scheduler has first checked all the other endpoints for active
transactions. This ensures that an endpoint that is sending a lot of NAKs does not block other
transactions on the bus. The core also allows the user to specify a limit to the length of time for
NAKs to be received from a target device before the endpoint times out.
17.2.2.5 USB Hubs
The following setup requirements apply to the USB host controller only if it is used with a USB hub.
When a full- or low-speed device is connected to the USB controller via a USB 2.0 hub, details of
the hub address and the hub port also need to be recorded in the corresponding USBRXHUBADDRn
and USBRXHUBPORTn or the USBTXHUBADDRn and USBTXHUBPORTn registers. In addition,
the speed at which the device operates (full or low) needs to be recorded in the USBTYPE0 (endpoint
0), USBTXTYPEn, or USBRXTYPEn registers for each endpoint that is accessed by the device.
For hub communications, the settings in these registers record the current allocation of the endpoints
to the attached USB devices. To maximize the number of devices supported, the USB host controller
allows this allocation to be changed dynamically by simply updating the address and speed
information recorded in these registers. Any changes in the allocation of endpoints to device functions
need to be made following the completion of any on-going transactions on the endpoints affected.
17.2.2.6 Babble
The USB host controller does not start a transaction until the bus has been inactive for at least the
minimum inter-packet delay. It also does not start a transaction unless it can be finished before the
end of the frame. If the bus is still active at the end of a frame, then the USB host controller assumes
that the target device to which it is connected has malfunctioned and the USB controller suspends
all transactions and generates a babble interrupt.
17.2.2.7 Host Suspend
If the SUSPEND bit in the USBPOWER register is set, the USB host controller completes the current
transaction then stops the transaction scheduler and frame counter. No further transactions are
started and no SOF packets are generated.
To exit Suspend mode, the RESUME bit is set and the SUSPEND bit is cleared. While the RESUME bit
is High, the USB host controller generates Resume signaling on the bus. After 20 ms, the RESUME
bit should be cleared, at which point the frame counter and transaction scheduler start. However,
if remote wake-up is to be supported, power to the PHY will be maintained so that the USB controller
can detect Resume signaling on the bus.
17.2.2.8 USB Reset
If the RESET bit in the USBPOWER register is set, the USB host controller generates USB Reset
signaling on the bus. The RESET bit should be set for at least 20 ms to ensure correct resetting of
the target device. After the CPU has cleared the bit, the USB host controller starts its frame counter
and transaction scheduler.
17.2.2.9 Connect/Disconnect
A session is started by setting the SESSION bit in the USBDEVCTL register. This enables the USB
controller to wait for a device to be connected. When a device is detected, a connect interrupt is
generated. The speed of the device that has been connected can be determined by reading the
USBDEVCTL register where the FSDEV bit is High for a full-speed device and the LSDEV bit is High
for a low-speed device. The USB controller should generate a reset to the device and then the USB
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host controller can begin device enumeration. If the device is disconnected while a session is in
progress, a disconnect interrupt is generated.
17.3
Initialization and Configuration
The initial configuration in all cases requires that the processor enable the USB controller before
setting any registers. The next step is to enable the USB PLL so that the correct clocking is provided
to the USB controller’s physical layer interface (PHY). To ensure that voltage is not supplied to the
bus incorrectly, the external power control signal, USB0EPEN, should be de-asserted on start up.
This requires setting the USB0EPEN and USB0PFLT pins to be controlled by the USB controller and
not have their default GPIO behavior.
The USB controller provides a method to set the current operating mode of the USB controller. This
register should be written with the desired default mode so that the controller can respond to external
USB events.
17.3.1
Pin Configuration
When using the device controller portion of the USB controller in a system that also provides host
functionality, the power to VBUS must be disabled to allow the external host controller to supply
power. Usually, the USB0EPEN signal is used to control the external regulator and should be
de-asserted to avoid having two devices driving the USB0VBUS power pin on the USB connector.
When the USB controller is acting as a host, it is in control of two signals that are attached to an
external voltage supply that provides power to VBUS. The host controller uses the USB0EPEN signal
to enable or disable power to the USB0VBUS pin on the USB connector. There is also an input pin,
USB0PFLT, which provides feedback when there has been a power fault on VBUS. The USB0PFLT
signal can be configured to either automatically de-assert the USB0EPEN signal to disable power,
and/or it can generate an interrupt to the main processor to allow it to handle the power fault condition.
The polarity and actions related to both USB0EPEN and USB0PFLT are fully configurable in the USB
controller. The controller also provides interrupts on device insertion and removal to allow the host
controller code to respond to these external events.
17.3.2
Endpoint Configuration
In order to start communication on host or device mode, the endpoint registers must first be
configured. In Host mode, this provides a connection between an endpoint register and an endpoint
on a device. In Device mode, this provides the setup for a given endpoint before enumerating to
the host controller.
In both cases, the endpoint 0 configuration is limited as this is a fixed function, fixed FIFO size
endpoint. In Device and Host modes, the endpoint requires little setup but does require a
software-based state machine to progress through the setup, data, and status phases of a standard
control transaction. In Device mode, the configuration of the remaining endpoints is done once
before enumerating and then only changed if an alternate configuration is selected by the host
controller. In Host mode, the endpoints must be configured to operate as control, bulk, interrupt or
isochronous mode. Once the type of endpoint is configured, a FIFO area must be assigned to each
endpoint. In the case of bulk, control and interrupt endpoints, each has a maximum of 64 bytes per
transaction. Isochronous endpoints can have packets with up to 1023 bytes per packet. In either
mode, the maximum packet size for the given endpoint must be set prior to sending or receiving
data.
Configuring each endpoint’s FIFO involves reserving a portion of the overall USB FIFO RAM to
each endpoint. The total FIFO RAM available is 4 bytes with the first 64 bytes in use by endpoint
0. The endpoint’s FIFO does not have to be the same size as the maximum packet size in all cases
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as the controller can automatically split for bulk transactions if the FIFO is larger than the maximum
packet size. The FIFO can also be configured as a double-buffered FIFO so that interrupts occur
at the end of each packet and allow filling the other half of the FIFO.
If operating as a device, the USB device controllers' soft connect should be enabled when the device
is ready to start communications. This indicates to the host controller that the device is ready to
start the enumeration process. If operating as a host controller, the device soft connect should be
disabled and power should be provided to VBUS via the USB0EPEN signal.
17.4
Register Map
Table 17-1 on page 514 lists the registers. All addresses given are relative to the USB base address
of 0x4005.0000.
Table 17-1. Univeral Serial Bus (USB) Controller Register Map
See
page
Offset
Name
Type
Reset
Description
0x000
USBFADDR
R/W
0x00
USB Device Functional Address
518
0x001
USBPOWER
R/W
0x20
USB Power
519
0x002
USBTXIS
RO
0x0000
USB Transmit Interrupt Status
521
0x004
USBRXIS
RO
0x0000
USB Receive Interrupt Status
522
0x006
USBTXIE
R/W
0x000F
USB Transmit Interrupt Enable
523
0x008
USBRXIE
R/W
0x000E
USB Receive Interrupt Enable
524
0x00A
USBIS
RO
0x00
USB General Interrupt Status
525
0x00B
USBIE
R/W
0x06
USB Interrupt Enable
527
0x00C
USBFRAME
RO
0x0000
USB Frame Value
529
0x00F
USBTEST
R/W
0x00
USB Test Mode
531
0x020
USBFIFO0
R/W
0x0000.0000
USB FIFO Endpoint 0
533
0x024
USBFIFO1
R/W
0x0000.0000
USB FIFO Endpoint 1
533
0x028
USBFIFO2
R/W
0x0000.0000
USB FIFO Endpoint 2
533
0x02C
USBFIFO3
R/W
0x0000.0000
USB FIFO Endpoint 3
533
0x060
USBDEVCTL
R/W
0x80
USB Device Control
534
0x062
USBTXFIFOSZ
R/W
0x00
USB Transmit Dynamic FIFO Sizing
536
0x063
USBRXFIFOSZ
R/W
0x00
USB Receive Dynamic FIFO Sizing
536
0x064
USBTXFIFOADD
R/W
0x0000
USB Transmit FIFO Start Address
537
0x066
USBRXFIFOADD
R/W
0x0000
USB Receive FIFO Start Address
537
0x07A
USBCONTIM
R/W
0x5C
USB Connect Timing
538
0x07D
USBFSEOF
R/W
0x77
USB Full-Speed Last Transaction to End of Frame Timing
539
0x07E
USBLSEOF
R/W
0x72
USB Low-Speed Last Transaction to End of Frame
Timing
540
0x080
USBTXFUNCADDR0
R/W
0x00
USB Transmit Functional Address Endpoint 0
541
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See
page
Offset
Name
Type
Reset
Description
0x082
USBTXHUBADDR0
R/W
0x00
USB Transmit Hub Address Endpoint 0
542
0x083
USBTXHUBPORT0
R/W
0x00
USB Transmit Hub Port Endpoint 0
543
0x088
USBTXFUNCADDR1
R/W
0x00
USB Transmit Functional Address Endpoint 1
541
0x08A
USBTXHUBADDR1
R/W
0x00
USB Transmit Hub Address Endpoint 1
542
0x08B
USBTXHUBPORT1
R/W
0x00
USB Transmit Hub Port Endpoint 1
543
0x08C
USBRXFUNCADDR1
R/W
0x00
USB Receive Functional Address Endpoint 1
544
0x08E
USBRXHUBADDR1
R/W
0x00
USB Receive Hub Address Endpoint 1
545
0x08F
USBRXHUBPORT1
R/W
0x00
USB Receive Hub Port Endpoint 1
546
0x090
USBTXFUNCADDR2
R/W
0x00
USB Transmit Functional Address Endpoint 2
541
0x092
USBTXHUBADDR2
R/W
0x00
USB Transmit Hub Address Endpoint 2
542
0x093
USBTXHUBPORT2
R/W
0x00
USB Transmit Hub Port Endpoint 2
543
0x094
USBRXFUNCADDR2
R/W
0x00
USB Receive Functional Address Endpoint 2
544
0x096
USBRXHUBADDR2
R/W
0x00
USB Receive Hub Address Endpoint 2
545
0x097
USBRXHUBPORT2
R/W
0x00
USB Receive Hub Port Endpoint 2
546
0x098
USBTXFUNCADDR3
R/W
0x00
USB Transmit Functional Address Endpoint 3
541
0x09A
USBTXHUBADDR3
R/W
0x00
USB Transmit Hub Address Endpoint 3
542
0x09B
USBTXHUBPORT3
R/W
0x00
USB Transmit Hub Port Endpoint 3
543
0x09C
USBRXFUNCADDR3
R/W
0x00
USB Receive Functional Address Endpoint 3
544
0x09E
USBRXHUBADDR3
R/W
0x00
USB Receive Hub Address Endpoint 3
545
0x09F
USBRXHUBPORT3
R/W
0x00
USB Receive Hub Port Endpoint 3
546
0x0E
USBEPIDX
R/W
0x0000
USB Endpoint Index
530
0x102
USBCSRL0
W1C
0x00
USB Control and Status Endpoint 0 Low
548
0x103
USBCSRH0
W1C
0x00
USB Control and Status Endpoint 0 High
551
0x108
USBCOUNT0
RO
0x00
USB Receive Byte Count Endpoint 0
553
0x10A
USBTYPE0
R/W
0x00
USB Type Endpoint 0
554
0x10B
USBNAKLMT
R/W
0x00
USB NAK Limit
555
0x110
USBTXMAXP1
R/W
0x0000
USB Maximum Transmit Data Endpoint 1
547
0x112
USBTXCSRL1
R/W
0x00
USB Transmit Control and Status Endpoint 1 Low
556
0x113
USBTXCSRH1
R/W
0x00
USB Transmit Control and Status Endpoint 1 High
559
0x114
USBRXMAXP1
R/W
0x0000
USB Maximum Receive Data Endpoint 1
562
0x116
USBRXCSRL1
R/W
0x00
USB Receive Control and Status Endpoint 1 Low
563
0x117
USBRXCSRH1
R/W
0x00
USB Receive Control and Status Endpoint 1 High
566
0x118
USBRXCOUNT1
RO
0x0000
USB Receive Byte Count Endpoint 1
571
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See
page
Offset
Name
Type
Reset
Description
0x11A
USBTXTYPE1
R/W
0x00
USB Host Transmit Configure Type Endpoint 1
572
0x11B
USBTXINTERVAL1
R/W
0x00
USB Host Transmit Interval Endpoint 1
574
0x11C
USBRXTYPE1
R/W
0x00
USB Host Configure Receive Type Endpoint 1
575
0x11D
USBRXINTERVAL1
R/W
0x00
USB Host Receive Polling Interval Endpoint 1
577
0x120
USBTXMAXP2
R/W
0x0000
USB Maximum Transmit Data Endpoint 2
547
0x122
USBTXCSRL2
R/W
0x00
USB Transmit Control and Status Endpoint 2 Low
556
0x123
USBTXCSRH2
R/W
0x00
USB Transmit Control and Status Endpoint 2 High
559
0x124
USBRXMAXP2
R/W
0x0000
USB Maximum Receive Data Endpoint 2
562
0x126
USBRXCSRL2
R/W
0x00
USB Receive Control and Status Endpoint 2 Low
563
0x127
USBRXCSRH2
R/W
0x00
USB Receive Control and Status Endpoint 2 High
566
0x128
USBRXCOUNT2
RO
0x0000
USB Receive Byte Count Endpoint 2
571
0x12A
USBTXTYPE2
R/W
0x00
USB Host Transmit Configure Type Endpoint 2
572
0x12B
USBTXINTERVAL2
R/W
0x00
USB Host Transmit Interval Endpoint 2
574
0x12C
USBRXTYPE2
R/W
0x00
USB Host Configure Receive Type Endpoint 2
575
0x12D
USBRXINTERVAL2
R/W
0x00
USB Host Receive Polling Interval Endpoint 2
577
0x130
USBTXMAXP3
R/W
0x0000
USB Maximum Transmit Data Endpoint 3
547
0x132
USBTXCSRL3
R/W
0x00
USB Transmit Control and Status Endpoint 3 Low
556
0x133
USBTXCSRH3
R/W
0x00
USB Transmit Control and Status Endpoint 3 High
559
0x134
USBRXMAXP3
R/W
0x0000
USB Maximum Receive Data Endpoint 3
562
0x136
USBRXCSRL3
R/W
0x00
USB Receive Control and Status Endpoint 3 Low
563
0x137
USBRXCSRH3
R/W
0x00
USB Receive Control and Status Endpoint 3 High
566
0x138
USBRXCOUNT3
RO
0x0000
USB Receive Byte Count Endpoint 3
571
0x13A
USBTXTYPE3
R/W
0x00
USB Host Transmit Configure Type Endpoint 3
572
0x13B
USBTXINTERVAL3
R/W
0x00
USB Host Transmit Interval Endpoint 3
574
0x13C
USBRXTYPE3
R/W
0x00
USB Host Configure Receive Type Endpoint 3
575
0x13D
USBRXINTERVAL3
R/W
0x00
USB Host Receive Polling Interval Endpoint 3
577
0x304
USBRQPKTCOUNT1
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
1
578
0x308
USBRQPKTCOUNT2
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
2
578
0x30C
USBRQPKTCOUNT3
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
3
578
0x340
USBRXDPKTBUFDIS
R/W
0x0000
USB Receive Double Packet Buffer Disable
579
0x342
USBTXDPKTBUFDIS
R/W
0x0000
USB Transmit Double Packet Buffer Disable
580
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Name
Type
Reset
0x400
USBEPC
R/W
0x0000.0000
USB External Power Control
581
0x404
USBEPCRIS
RO
0x0000.0000
USB External Power Control Raw Interrupt Status
584
0x408
USBEPCIM
R/W
0x0000.0000
USB External Power Control Interrupt Mask
585
0x40C
USBEPCISC
R/W
0x0000.0000
USB External Power Control Interrupt Status and Clear
586
0x410
USBDRRIS
RO
0x0000.0000
USB Device Resume Raw Interrupt Status
587
0x414
USBDRIM
R/W
0x0000.0000
USB Device Resume Interrupt Mask
588
0x418
USBDRISC
W1C
0x0000.0000
USB Device Resume Interrupt Status and Clear
589
0x41C
USBGPCS
R/W
0x0000.0000
USB General-Purpose Control and Status
590
17.5
Description
See
page
Offset
Register Descriptions
The LM3S3748 USB controller is configured to the communication mode specified in the USB0 bit
field in the DC6 register:
■ Host or device (USB0 set to 0x2)
April 08, 2008
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Preliminary
Univeral Serial Bus (USB) Controller
Register 1: USB Device Functional Address (USBFADDR), offset 0x000
Device
USBFADDR is an 8-bit register that should be written with the 7-bit address of the device part of
the transaction.
When the USB controller is being used in Device mode (HOST bit in USBDEVCTL register is 0),
this register should be written with the address received through a SET_ADDRESS command,
which is then used for decoding the function address in subsequent token packets.
USB Device Functional Address (USBFADDR)
Base 0x4005.0000
Offset 0x000
Type R/W, reset 0x00
7
6
5
4
reserved
Type
Reset
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
FUNCADDR
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
FUNCADDR
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Function Address
Function Address of Device as received through SET_ADDRESS.
518
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 2: USB Power (USBPOWER), offset 0x001
USBPOWER is an 8-bit register that is used for controlling Suspend and Resume signaling, and
some basic operational aspects of the USB controller.
Host
Device
USBPOWER Host Mode
USB Power (USBPOWER)
Base 0x4005.0000
Offset 0x001
Type R/W, reset 0x20
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
3
2
1
0
RESET RESUME SUSPEND PWRDNPHY
RO
1
RO
0
R/W
0
R/W
0
R/W1S
0
R/W
0
Bit/Field
Name
Type
Reset
Description
7:4
reserved
RO
0x02
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
RESET
R/W
0
Reset
This bit is set to enable Reset signaling on the bus and cleared to end
Reset signaling on the bus.
2
RESUME
R/W
0
Resume Signaling
Set by the CPU to generate Resume signaling when the device is in
Suspend mode. The CPU should clear this bit after 20 ms.
1
SUSPEND
R/W1S
0
Suspend Mode
This bit is written to 1 by the CPU to enter Suspend mode. Writing a 0
does nothing.
0
PWRDNPHY
R/W
0
Power Down PHY
Set by the CPU to power down the internal USB PHY.
USBPOWER Device Mode
USB Power (USBPOWER)
Base 0x4005.0000
Offset 0x001
Type R/W, reset 0x20
7
6
ISOUP SOFTCONN
Type
Reset
R/W
0
R/W
0
5
4
reserved
RO
1
RO
0
3
2
1
0
RESET RESUME SUSPEND PWRDNPHY
RO
0
R/W
0
RO
0
R/W
0
April 08, 2008
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Preliminary
Univeral Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
Description
7
ISOUP
R/W
0
ISO Update
When set by the CPU, the USB controller waits for an SOF token from
the time TXRDY is set before sending the packet. If an IN token is
received before an SOF token, then a zero-length data packet is sent.
Note:
6
SOFTCONN
R/W
0
Only valid for isochronous transfers.
Soft Connect/Disconnect
The USB D+/D- lines are enabled when this bit is set by the CPU, and
tri-stated when this bit is cleared by the CPU.
5:4
reserved
RO
0x2
3
RESET
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Reset
This bit is set when Reset signaling is present on the bus.
2
RESUME
R/W
0
Resume Signaling
Set by the CPU to generate Resume signaling when the device is in
Suspend mode. The CPU should clear this bit after 10 ms (a maximum
of 15 ms) to end Resume signaling.
1
SUSPEND
RO
0
Suspend Mode
This bit is set on entry into Suspend mode. It is cleared when the CPU
reads the interrupt register or sets the RESUME bit above.
0
PWRDNPHY
R/W
0
Power Down PHY
Set by the CPU to power down the internal USB PHY.
520
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 3: USB Transmit Interrupt Status (USBTXIS), offset 0x002
USBTXIS is a 16-bit read-only register that indicates which interrupts are currently active for endpoint
0 and the transmit endpoints 1–3.
Host
Note:
Bits relating to endpoints that have not been configured always return 0. Note also that all
active interrupts are cleared when this register is read.
Device
USB Transmit Interrupt Status (USBTXIS)
Base 0x4005.0000
Offset 0x002
Type RO, reset 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
EP3
EP2
EP1
EP0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
15:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
EP3
RO
0
TX Endpoint 3 Interrupt
2
EP2
RO
0
TX Endpoint 2 Interrupt
1
EP1
RO
0
TX Endpoint 1 Interrupt
0
EP0
RO
0
TX and RX Endpoint 0 Interrupt
April 08, 2008
521
Preliminary
Univeral Serial Bus (USB) Controller
Register 4: USB Receive Interrupt Status (USBRXIS), offset 0x004
USBRXIS is a 16-bit read-only register that indicates which of the interrupts for receive endpoints
1–3 are currently active.
Host
Note:
Bits relating to endpoints that have not been configured always return 0. Note also that all
active interrupts are cleared when this register is read.
Device
USB Receive Interrupt Status (USBRXIS)
Base 0x4005.0000
Offset 0x004
Type RO, reset 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
EP3
EP2
EP1
reserved
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
15:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
EP3
RO
0
RX Endpoint 3 Interrupt
2
EP2
RO
0
RX Endpoint 2 Interrupt
1
EP1
RO
0
RX Endpoint 1 Interrupt
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
522
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 5: USB Transmit Interrupt Enable (USBTXIE), offset 0x006
Host
Device
USBTXIE is a 16-bit register that provides interrupt enable bits for the interrupts in USBTXIS. When
a bit in USBTXIE is set to 1, the USB interrupt to the processor is asserted when the corresponding
interrupt bit in the USBTXIS register is set. When a bit is cleared to 0, the interrupt in USBTXIS is
still set but the USB interrupt to the processor is not asserted. On reset, the bits corresponding to
endpoint 0 and transmit endpoints 1-3 are set to 1, while the remaining bits are set to 0.
USB Transmit Interrupt Enable (USBTXIE)
Base 0x4005.0000
Offset 0x006
Type R/W, reset 0x000F
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
EP3
EP2
EP1
EP0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
2
1
0
Bit/Field
Name
Type
Reset
Description
15:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
EP3
R/W
1
TX Endpoint 3 Interrupt Enable
2
EP2
R/W
1
TX Endpoint 2 Interrupt Enable
1
EP1
R/W
1
TX Endpoint 1 Interrupt Enable
0
EP0
R/W
1
TX and RX Endpoint 0 Interrupt Enable
April 08, 2008
523
Preliminary
Univeral Serial Bus (USB) Controller
Register 6: USB Receive Interrupt Enable (USBRXIE), offset 0x008
Host
Device
USBRXIE is a 16-bit register that provides interrupt enable bits for the interrupts in USBRXIS. When
a bit in USBRXIE is set to 1, the USB interrupt to the processor is asserted when the corresponding
interrupt bit in the USBRXIS register is set. When a bit is cleared to 0, the interrupt in USBRXIS is
still set but the USB interrupt to the processor is not asserted. On reset, the bits corresponding to
receive endpoints 1-3 are set to 1, while the remaining bits are set to 0.
USB Receive Interrupt Enable (USBRXIE)
Base 0x4005.0000
Offset 0x008
Type R/W, reset 0x000E
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
EP3
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
1
reserved
Type
Reset
2
1
0
EP2
EP1
reserved
R/W
1
R/W
1
RO
0
Bit/Field
Name
Type
Reset
Description
15:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
EP3
R/W
1
RX Endpoint 3 Interrupt Enable
2
EP2
R/W
1
RX Endpoint 2 Interrupt Enable
1
EP1
R/W
1
RX Endpoint 1 Interrupt Enable
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
524
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 7: USB General Interrupt Status (USBIS), offset 0x00A
USBIS is an 8-bit read-only register that indicates which USB interrupts are currently active. All
active interrupts are cleared when this register is read.
Host
Device
USBIS Host Mode
USB General Interrupt Status (USBIS)
Base 0x4005.0000
Offset 0x00A
Type RO, reset 0x00
7
6
reserved
Type
Reset
RO
0
RO
0
5
4
3
DISCON
CONN
SOF
RO
0
RO
0
RO
0
2
1
0
BABBLE RESUME reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
DISCON
RO
0
Session Disconnect
Set when a device disconnect is detected.
4
CONN
RO
0
Session Connect
Set when a device connection is detected.
3
SOF
RO
0
Start of Frame
Set when a new frame starts.
2
BABBLE
RO
0
Babble Detected
Set when babble is detected. Only active after first SOF has been sent.
1
RESUME
RO
0
Resume Signal Detected
Set when Resume signaling is detected on the bus while the USB
controller is in Suspend mode.
This can only be used if the USB's system clock is enabled. If the user
disables the clock programming, the USBDRCRIS, USBDRCIM, and
USBISC registers should be used.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
525
Preliminary
Univeral Serial Bus (USB) Controller
USBIS Device Mode
USB General Interrupt Status (USBIS)
Base 0x4005.0000
Offset 0x00A
Type RO, reset 0x00
7
6
reserved
Type
Reset
RO
0
RO
0
5
4
DISCON reserved
RO
0
RO
0
3
SOF
RO
0
2
1
0
RESET RESUME SUSPEND
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
DISCON
RO
0
Session Disconnect
Set when a session ends. Valid at all transaction speeds.
4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
SOF
RO
0
Start of Frame
Set when a new frame starts.
2
RESET
RO
0
Reset Signal Detected
Set when Reset signaling is detected on the bus.
1
RESUME
RO
0
Resume Signal Detected
Set when Resume signaling is detected on the bus while the USB
controller is in Suspend mode.
This can only be used if the USB's system clock is enabled. If the user
disables the clock programming, the USBDRCRIS, USBDRCIM, and
USBISC registers should be used.
0
SUSPEND
RO
0
Suspend Signal Detected
Set when Suspend signaling is detected on the bus.
526
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 8: USB Interrupt Enable (USBIE), offset 0x00B
USBIE is an 8-bit register that provides interrupt enable bits for each of the interrupts in USBIS. By
default, interrupt 1 and 2 are enabled.
Host
Device
USBIE Host Mode
USB Interrupt Enable (USBIE)
Base 0x4005.0000
Offset 0x00B
Type R/W, reset 0x06
7
6
reserved
Type
Reset
RO
0
RO
0
5
4
3
DISCON
CONN
SOF
R/W
0
R/W
0
R/W
0
2
1
0
RESET RESUME SUSPND
R/W
1
R/W
1
R/W
0
Bit/Field
Name
Type
Reset
Description
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
DISCON
R/W
0
Enable Disconnect Interrupt
Set by CPU to enable DISCON in USBIS.
4
CONN
R/W
0
Enable Connect Interrupt
Set by CPU to enable CONN in USBIS.
3
SOF
R/W
0
Enable Start-of-Frame Interrupt
Set by CPU to enable SOF in USBIS.
2
RESET
R/W
1
Enable Reset Interrupt
Set by CPU to enable RESET in USBIS.
1
RESUME
R/W
1
Enable Resume Interrupt
Set by CPU to enable RESUME in USBIS.
0
SUSPND
R/W
0
Enable Suspend Interrupt
Set by CPU to enable SUSPEND in USBIS.
USBIE Device Mode
USB Interrupt Enable (USBIE)
Base 0x4005.0000
Offset 0x00B
Type R/W, reset 0x06
7
6
reserved
Type
Reset
RO
0
RO
0
5
4
3
DISCON
CONN
SOF
R/W
0
R/W
0
R/W
0
2
1
0
BABBLE RESUME SUSPND
R/W
1
R/W
1
R/W
0
April 08, 2008
527
Preliminary
Univeral Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
Description
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
DISCON
R/W
0
Enable Disconnect Interrupt
Set by CPU to enable DISCON in USBIS.
4
CONN
R/W
0
Enable Connect Interrupt
Set by CPU to enable CONN in USBIS.
3
SOF
R/W
0
Enable Start-of-Frame Interrupt
Set by CPU to enable SOF in USBIS.
2
BABBLE
R/W
1
Enable Babble Interrupt
Set by CPU to enable BABBLE in USBIS.
1
RESUME
R/W
1
Enable Resume Interrupt
Set by CPU to enable RESUME in USBIS.
0
SUSPND
R/W
0
Enable Suspend Interrupt
Set by CPU to enable SUSPEND in USBIS.
528
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 9: USB Frame Value (USBFRAME), offset 0x00C
USBFRAME is a 16-bit read-only register that holds the last received frame number.
Host
USB Frame Value (USBFRAME)
Device
Base 0x4005.0000
Offset 0x00C
Type RO, reset 0x0000
15
14
RO
0
RO
0
13
12
11
10
9
8
7
6
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
Frame
RO
0
Bit/Field
Name
Type
Reset
Description
15:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:0
Frame
RO
0x00
Frame Number
April 08, 2008
529
Preliminary
Univeral Serial Bus (USB) Controller
Register 10: USB Endpoint Index (USBEPIDX), offset 0x0E
Each endpoint's buffer can be accessed by configuring a FIFO size and starting address. The
USBEPIDX 16-bit register is used with the USBTXFIFOSZ, USBRXFIFOSZ, USBTXFIFOADD,
and USBRXFIFOADD registers.
Host
Device
USB Endpoint Index (USBEPIDX)
Base 0x4005.0000
Offset 0x0E
Type R/W, reset 0x0000
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
1
0
R/W
0
R/W
0
EPIDX
Bit/Field
Name
Type
Reset
Description
15:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0
EPIDX
R/W
0x00
Endpoint Index
This sets which endpoint is accessed when reading or writing to one of
the USB controller's indexed registers.
530
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 11: USB Test Mode (USBTEST), offset 0x00F
Host
USBTESTMODE is an 8-bit register that is primarily used to put the USB controller into one of the
four test modes for operation described in the USB 2.0 specification, in response to a SET FEATURE:
USBTESTMODE command. It is not used in normal operation.
Device
Note:
Only one of these bits should be set at any time.
USBTEST Host Mode
USB Test Mode (USBTEST)
Base 0x4005.0000
Offset 0x00F
Type R/W, reset 0x00
7
6
5
4
3
FORCEH FIFOACC FORCEFS
Type
Reset
R/W
0
R/W1S
0
R/W
0
2
1
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
7
FORCEH
R/W
0
Description
Force Host Mode
The CPU sets this bit to instruct the core to enter Host mode when the
Session bit is set, regardless of whether it is connected to any peripheral.
The state of the USBD+ and USBD- are ignored. The core then remains
in Host mode until the SESSION bit is cleared, even if a device is
disconnected, and if the FORCEH bit remains set, re-enters Host mode
the next time the SESSION bit is set.
While in this mode, status of the bus connection may be read from the
DEV bit of the USBDEVCTL register. The operating speed is determined
from the FORCEFS bit.
6
FIFOACC
R/W1S
0
FIFO Access
The CPU sets this bit to transfer the packet in the endpoint 0 transmit
FIFO to the endpoint 0 receive FIFO. It is cleared automatically.
5
FORCEFS
R/W
0
Force Full-Speed Mode
The CPU sets this bit to force the USB controller into Full-Speed mode
when it receives a USB reset. When 0, the USB controller operates at
Low Speed.
4:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USBTEST Device Mode
USB Test Mode (USBTEST)
Base 0x4005.0000
Offset 0x00F
Type R/W, reset 0x00
7
6
5
4
3
RO
0
RO
0
reserved FIFOACC FORCEFS
Type
Reset
RO
0
R/W1S
0
R/W
0
2
1
0
RO
0
RO
0
reserved
RO
0
April 08, 2008
531
Preliminary
Univeral Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
Description
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
FIFOACC
R/W1S
0
FIFO Access
The CPU sets this bit to transfer the packet in the endpoint 0 transmit
FIFO to the endpoint 0 receive FIFO. It is cleared automatically.
5
FORCEFS
R/W
0
Force Full Speed
The CPU sets this bit to force the USB controller into Full-Speed mode
when it receives a USB reset. When 0, the USB controller operates at
Low Speed.
4:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
532
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 12: USB FIFO Endpoint 0 (USBFIFO0), offset 0x020
Register 13: USB FIFO Endpoint 1 (USBFIFO1), offset 0x024
Register 14: USB FIFO Endpoint 2 (USBFIFO2), offset 0x028
Register 15: USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C
These 32-bit registers provide an address for CPU access to the FIFOs for each endpoint. Writing
to these addresses loads data into the Transmit FIFO for the corresponding endpoint. Reading from
these addresses unloads data from the Receive FIFO for the corresponding endpoint.
Host
Device
Transfers to and from FIFOs may be 8-bit, 16-bit or 32-bit as required, and any combination of
access is allowed provided the data accessed is contiguous. All transfers associated with one packet
must be of the same width so that the data is consistently byte-, word- or double-word-aligned.
However, the last transfer may contain fewer bytes than the previous transfers in order to complete
an odd-byte or odd-word transfer.
Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support
either single-packet or double-packet buffering. Burst writing of multiple packets is not supported
as flags need to be set after each packet is written.
Following a STALL response or a transmit error on endpoint 1–3, the associated FIFO is completely
flushed.
USB FIFO Endpoint 0 (USBFIFO0)
Base 0x4005.0000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
EPDATA
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
EPDATA
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:0
EPDATA
R/W
0x00
Endpoint Data
Writing to this register loads the data into the Transmit FIFO and reading
unloads data from the Receive FIFO.
April 08, 2008
533
Preliminary
Univeral Serial Bus (USB) Controller
Register 16: USB Device Control (USBDEVCTL), offset 0x060
USBDEVCTL provides the status information for the current operating mode (host or device) of the
USB controller. If the USB controller is in host mode, this register also indicates if a full- or low-speed
device has been connected.
Host
Device
USBDEVCTL Host
USB Device Control (USBDEVCTL)
Base 0x4005.0000
Offset 0x060
Type R/W, reset 0x80
Type
Reset
7
6
5
DEV
FSDEV
LSDEV
4
RO
1
RO
0
RO
0
3
2
reserved
RO
0
1
HOST
RO
0
RO
0
0
reserved
RO
0
Bit/Field
Name
Type
Reset
7
DEV
RO
1
RO
0
Description
Device Mode
When set, this bit indicates the controller is operating as a device.
Note:
6
FSDEV
RO
0
This value is only valid while a session is in progress.
Full-Speed Device Detected
This read-only bit is set when a full-speed device has been detected on
the port.
5
LSDEV
RO
0
Low-Speed Device Detected
This read-only bit is set when a low-speed device has been detected
on the port.
4:3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
HOST
RO
0
Host Mode
This read-only bit is set when the USB controller is acting as a Host.
1:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USBDEVCTL Device Mode
USB Device Control (USBDEVCTL)
Base 0x4005.0000
Offset 0x060
Type R/W, reset 0x80
7
6
5
4
RO
0
RO
0
RO
0
DEV
Type
Reset
RO
1
3
2
1
0
RO
0
RO
0
RO
0
reserved
RO
0
534
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
7
DEV
RO
1
Description
Device Mode
When set, this bit indicates the controller is operating as a device.
Note:
6:0
reserved
RO
0x00
This value is only valid while a session is in progress.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
535
Preliminary
Univeral Serial Bus (USB) Controller
Register 17: USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062
Register 18: USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063
These 8-bit registers allow the selected TX/RX endpoint FIFOs to be dynamically sized. USBEPIDX
is used to configure each transmit endpoint's FIFO size.
Host
Device
USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ)
Base 0x4005.0000
Offset 0x062
Type R/W, reset 0x00
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
3
2
R/W
0
R/W
0
DPB
RO
0
R/W
0
1
0
R/W
0
R/W
0
SIZE
Bit/Field
Name
Type
Reset
Description
7:5
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
DPB
R/W
0
Double Packet Buffer Support
Defines whether double-packet buffering is supported. When 1,
double-packet buffering is supported. When 0, only single-packet
buffering is supported.
3:0
SIZE
R/W
0x0
Max Packet Size
Maximum packet size to be allowed for (before any splitting within the
FIFO of bulk/high-bandwidth packets prior to transmission.
If DPB = 0, the FIFO also is this size; if DPB = 1, the FIFO is twice this
size.
Value
Packet Size (Bytes)
0x0
8
0x1
16
0x2
32
0x3
64
0x4
128
0x5
256
0x6
512
0x7
1024
0x8
2048
0x9-0xF Reserved
536
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 19: USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064
Register 20: USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066
USBTXFIFOADD is a 16-bit register that controls the start address of the selected transmit endpoint
FIFO. USBRXFIFOADD is a 14-bit register that controls the start address of the selected receive
endpoint FIFO.
Host
Device
USB Transmit FIFO Start Address (USBTXFIFOADD)
Base 0x4005.0000
Offset 0x064
Type R/W, reset 0x0000
15
14
13
12
11
10
9
8
7
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
ADDR
R/W
0
Bit/Field
Name
Type
Reset
Description
15:13
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12:0
ADDR
R/W
0x00
Transmit/Receive Start Address
Start address of the endpoint FIFO in units of 8 bytes.
Value
Start Address
0x0
0
0x1
8
0x2
16
0x3
32
0x4
64
0x5
128
0x6
256
0x7
512
0x8
1024
0x9
2048
0xA-0x1FFF Reserved
April 08, 2008
537
Preliminary
Univeral Serial Bus (USB) Controller
Register 21: USB Connect Timing (USBCONTIM), offset 0x07A
This 8-bit configuration register allows some delays to be specified.
Host
USB Connect Timing (USBCONTIM)
Device
Base 0x4005.0000
Offset 0x07A
Type R/W, reset 0x5C
7
6
R/W
0
R/W
1
5
4
3
2
R/W
0
R/W
1
RO
0
RO
0
WTCON
Type
Reset
1
0
RO
0
RO
0
reserved
Bit/Field
Name
Type
Reset
7:4
WTCON
R/W
0x5
Description
Connect Wait
Sets the wait to be applied to allow for the user’s connect/disconnect
filter, in units of 533.3 ns. (The default setting corresponds to 2.667µs.)
3:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
538
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 22: USB Full-Speed Last Transaction to End of Frame Timing
(USBFSEOF), offset 0x07D
This 8-bit configuration register sets the minimum time gap that is to be allowed between the start
of the last transaction and the EOF for full-speed transactions.
Host
Device
USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF)
Base 0x4005.0000
Offset 0x07D
Type R/W, reset 0x77
7
6
5
4
3
2
1
0
R/W
0
R/W
1
R/W
1
R/W
1
FSEOFG
Type
Reset
R/W
0
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
7:0
FSEOFG
R/W
0x77
Full-Speed End-of-Frame Gap
Used during full-speed transactions, to set the gap between the last
transaction and the End-of-Frame (EOF), in units of 533.3 ns. The default
corresponds to 63.46 µs.
April 08, 2008
539
Preliminary
Univeral Serial Bus (USB) Controller
Register 23: USB Low-Speed Last Transaction to End of Frame Timing
(USBLSEOF), offset 0x07E
This 8-bit configuration register sets the minimum time gap that is to be allowed between the start
of the last transaction and the EOF for low-speed transactions.
Host
Device
USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF)
Base 0x4005.0000
Offset 0x07E
Type R/W, reset 0x72
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
1
R/W
0
LSEOFG
Type
Reset
R/W
0
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
7:0
LSEOFG
R/W
0x72
Low-Speed End-of-Frame Gap
Used during low-speed transactions, to set the gap between the last
transaction and the End-of-Frame (EOF), in units of 1.067 µs. The default
corresponds to 121.6 µs.
540
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 24: USB Transmit Functional Address Endpoint 0
(USBTXFUNCADDR0), offset 0x080
Register 25: USB Transmit Functional Address Endpoint 1
(USBTXFUNCADDR1), offset 0x088
Register 26: USB Transmit Functional Address Endpoint 2
(USBTXFUNCADDR2), offset 0x090
Register 27: USB Transmit Functional Address Endpoint 3
(USBTXFUNCADDR3), offset 0x098
USBTXFUNCADDRn is an 8-bit read/write register that records the address of the target function
that is to be accessed through the associated endpoint (EPn). USBTXFUNCADDRn needs to be
defined for each transmit endpoint that is used.
Host
Note:
USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0.
USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0)
Base 0x4005.0000
Offset 0x080
Type R/W, reset 0x00
7
6
5
4
reserved
Type
Reset
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
ADDR
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
ADDR
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Device Address
USB bus address for the target device.
April 08, 2008
541
Preliminary
Univeral Serial Bus (USB) Controller
Register 28: USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0),
offset 0x082
Register 29: USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1),
offset 0x08A
Register 30: USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2),
offset 0x092
Register 31: USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3),
offset 0x09A
USBTXHUBADDRn is an 8-bit read/write register that, like USBTXHUBPORTn, only needs to be
written when a full- or low-speed device is connected to transmit endpoint EPn via a high-speed
USB 2.0 hub. This register provides the necessary transaction translation to convert between
high-speed transmission and full-/low-speed transmission. This register records the address of that
USB 2.0 hub through which the target associated with the endpoint is accessed. This information,
together with the hub port in USBTXHUBPORTn, allows the USB controller to support split
transactions.
Host
Note:
USBTXHUBADDR0 is used for both receive and transmit for endpoint 0.
USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0)
Base 0x4005.0000
Offset 0x082
Type R/W, reset 0x00
7
6
5
4
MULTTRAN
Type
Reset
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
ADDR
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
7
MULTTRAN
R/W
0
Description
Multiple Translators
Indicates whether the hub has multiple transaction translators. Clear to
0 if single transaction translator; set to 1 if multiple transaction translators.
6:0
ADDR
R/W
0x00
Hub Address
USB bus address for the USB 2.0 hub.
542
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 32: USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset
0x083
Register 33: USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset
0x08B
Register 34: USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset
0x093
Register 35: USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset
0x09B
USBTXHUBPORTn is an 8-bit read/write register that, like USBTXHUBADDRn, only needs to be
written when a full- or low-speed device is connected to transmit endpoint EPn via a high-speed
USB 2.0 hub. This register provides the necessary transaction translation to convert between
high-speed transmission and full-/low-speed transmission. This register records the port of that USB
2.0 hub through which the target associated with the endpoint is accessed. This information, together
with the hub address in USBTXHUBADDRn, allows the USB controller to support split transactions.
Host
Note:
USBTXHUBPORT0 is used for both receive and transmit for endpoint 0.
USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0)
Base 0x4005.0000
Offset 0x083
Type R/W, reset 0x00
7
6
5
4
reserved
Type
Reset
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
PORT
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
PORT
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Hub Port
USB hub port number.
April 08, 2008
543
Preliminary
Univeral Serial Bus (USB) Controller
Register 36: USB Receive Functional Address Endpoint 1
(USBRXFUNCADDR1), offset 0x08C
Register 37: USB Receive Functional Address Endpoint 2
(USBRXFUNCADDR2), offset 0x094
Register 38: USB Receive Functional Address Endpoint 3
(USBRXFUNCADDR3), offset 0x09C
USBRXFUNCADDRn is an 8-bit read/write register that records the address of the target function
that is to be accessed through the associated endpoint (EPn). USBRXFUNCADDRn needs to be
defined for each receive endpoint that is used.
Host
Note:
USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0.
USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1)
Base 0x4005.0000
Offset 0x08C
Type R/W, reset 0x00
7
6
5
4
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
ADDR
R/W
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
ADDR
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Device Address
USB bus address for the target device.
544
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 39: USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1),
offset 0x08E
Register 40: USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2),
offset 0x096
Register 41: USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3),
offset 0x09E
USBRXHUBADDRn is an 8-bit read/write register that, like USBRXHUBPORTn, only needs to be
written when a full- or low-speed device is connected to receive endpoint EPn via a high-speed USB
2.0 hub. This register provides the necessary transaction translation to convert between high-speed
transmission and full-/low-speed transmission. This register records the address of that USB 2.0
hub through which the target associated with the endpoint is accessed. This information, together
with the hub port in USBRXHUBPORTn, allows the USB controller to support split transactions.
Host
Note:
USBTXHUBADDR0 is used for both receive and transmit for endpoint 0.
USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1)
Base 0x4005.0000
Offset 0x08E
Type R/W, reset 0x00
7
6
5
4
R/W
0
R/W
0
R/W
0
MULTTRAN
Type
Reset
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
ADDR
R/W
0
Bit/Field
Name
Type
Reset
7
MULTTRAN
R/W
0
Description
Multiple Translators
Indicates whether the hub has multiple transaction translators. Clear to
0 if single transaction translator; set to 1 if multiple transaction translators.
6:0
ADDR
R/W
0x00
Hub Address
USB bus address for the USB 2.0 hub.
April 08, 2008
545
Preliminary
Univeral Serial Bus (USB) Controller
Register 42: USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset
0x08F
Register 43: USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset
0x097
Register 44: USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset
0x09F
USBRXHUBPORTn is an 8-bit read/write register that, like USBRXHUBADDRn, only needs to be
written when a full- or low-speed device is connected to receive endpoint EPn via a high-speed USB
2.0 hub. This register provides the necessary transaction translation to convert between high-speed
transmission and full-/low-speed transmission. This register records the port of that USB 2.0 hub
through which the target associated with the endpoint is accessed. This information, together with
the hub address in USBTXHUBADDRn, allows the USB controller to support split transactions.
Host
Note:
USBTXHUBPORT0 is used for both receive and transmit for endpoint 0.
USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1)
Base 0x4005.0000
Offset 0x08F
Type R/W, reset 0x00
7
6
5
4
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
PORT
R/W
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
PORT
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Hub Port
USB hub port number.
546
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 45: USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset
0x110
Register 46: USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset
0x120
Register 47: USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset
0x130
Host
The USBTXMAXPn 16-bit register defines the maximum amount of data that can be transferred
through the transmit endpoint in a single operation.
Device
Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set
can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet
sizes for bulk, interrupt and isochronous transfers in full-speed operation.
The MULT bit field contains the multiplication factor for the number of bytes in a given transaction.
For a single 64-byte bulk transfer, the multiplication factor is 1 so MULT should be written with 0. If
packet splitting is used, the multiplication factor allows for more than one transfer to be loaded into
the FIFO. A multiplication factor of 2 (MULT written to 1) allows two 64-byte packets to be written in
this endpoint's FIFO.
The total amount of data represented by the value written to this register (specified payload × m)
must not exceed the FIFO size for the transmit endpoint, and should not exceed half the FIFO size
if double-buffering is required.
If this register is changed after packets have been sent from the endpoint, the transmit endpoint
FIFO should be completely flushed (using the FLUSH bit in USBTXCSRL1n) after writing the new
value to this register.
Note:
USBTXMAXPn must be set to an even number of bytes for proper interrupt generation in
DMA Mode 1.
USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1)
Base 0x4005.0000
Offset 0x110
Type R/W, reset 0x0000
15
14
R/W
0
R/W
0
13
12
11
10
9
8
7
6
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MULT
Type
Reset
R/W
0
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MAXLOAD
Bit/Field
Name
Type
Reset
Description
15:11
MULT
R/W
0x00
Multiplier
R/W
0
Defines the maximum number of USB packets (that is, packets for
transmission over the USB) of the specified payload into which a single
data packet placed in the FIFO should be split, prior to transfer. The
value written to this register is one less than the desired multiplier. For
example, a value of 0 is a multiplier of 1.
10:0
MAXLOAD
R/W
0x00
Maximum Payload
The maximum payload in bytes per transaction.
April 08, 2008
547
Preliminary
Univeral Serial Bus (USB) Controller
Register 48: USB Control and Status Endpoint 0 Low (USBCSRL0), offset
0x102
USBCSRL0 is an 8-bit register that provides control and status bits for endpoint 0.
Host
Device
USBCSRL0 Host Mode
USB Control and Status Endpoint 0 Low (USBCSRL0)
Base 0x4005.0000
Offset 0x102
Type W1C, reset 0x00
7
NAKTO
Type
Reset
R/W0C
0
6
5
4
STATUS REQPKT ERROR
R/W
0
R/W
0
R/W0C
0
3
2
1
0
SETUP STALLED TXRDY
RXRDY
R/W1S
0
R/W0C
0
R/W0C
0
R/W1S
0
Bit/Field
Name
Type
Reset
7
NAKTO
R/W0C
0
Description
NAK Timeout
This bit is set by the USB controller when endpoint 0 is halted following
the receipt of NAK responses for longer than the time set by the
USBNAKLMT register. The CPU should clear this bit by writing a 0 to
it to allow the endpoint to continue.
6
STATUS
R/W
0
Status Packet
The CPU sets this bit at the same time as the TXRDY or REQPKT bit is
set, to perform a status stage transaction. Setting this bit ensures DT is
set to 1 so that a DATA1 packet is used for the Status Stage transaction.
5
REQPKT
R/W
0
Request Packet
The CPU sets this bit to request an IN transaction. It is cleared when
RXRDY is set.
4
ERROR
R/W0C
0
Error
This bit is set by the USB controller when three attempts have been
made to perform a transaction with no response from the peripheral.
The CPU should clear this bit. An interrupt is generated when this bit is
set.
3
SETUP
R/W1S
0
Setup Packet
The CPU sets this bit, at the same time as the TXRDY bit is set, to send
a SETUP token instead of an OUT token for the transaction. This always
resets the data toggle and sends a DATA0 packet.
2
STALLED
R/W0C
0
Endpoint Stalled
This bit is set when a STALL handshake is received. The CPU should
clear this bit.
548
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
1
TXRDY
R/W1S
0
Description
Transmit Packet Ready
The CPU sets this bit after loading a data packet into the FIFO. It is
cleared automatically when a data packet has been transmitted. An
interrupt is also generated at this point.
0
RXRDY
R/W0C
0
Receive Packet Ready
This bit is set when a data packet has been received. An interrupt is
generated when this bit is set. The CPU should clear this bit, by writing
a 0 when the packet has been read from the FIFO. This acknowledges
that data has been read from the FIFO.
USBCSRL0 Device Mode
USB Control and Status Endpoint 0 Low (USBCSRL0)
Base 0x4005.0000
Offset 0x102
Type W1C, reset 0x00
7
6
SETENDC RXRDYC
Type
Reset
W1C
0
W1C
0
5
4
STALL
3
2
1
0
SETEND DATAEND STALLED TXRDY
W1C
0
RO
0
W1C
0
R/W0C
0
R/W1S
0
Bit/Field
Name
Type
Reset
7
SETENDC
W1C
0
RXRDY
RO
0
Description
Setup End Clear
The CPU writes a 1 to this bit to clear the SETEND bit.
6
RXRDYC
W1C
0
RXRDY Clear
The CPU writes a 1 to this bit to clear the RXRDY bit.
5
STALL
W1C
0
Send Stall
The CPU writes a 1 to this bit to terminate the current transaction. The
STALL handshake is transmitted, and then this bit is cleared
automatically.
4
SETEND
RO
0
Setup End
This bit is set when a control transaction ends before the DataEnd bit
has been set. An interrupt is generated and the FIFO flushed at this
time. The bit is cleared by the CPU writing a 1 to the SETENDC bit.
3
DATAEND
W1C
0
Data End
The CPU sets this bit:
■
When setting TXRDY for the last data packet
■
When clearing RXRDY after unloading the last data packet
■
When setting TXRDY for a zero-length data packet
It is cleared automatically.
April 08, 2008
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Preliminary
Univeral Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
2
STALLED
R/W0C
0
Description
Endpoint Stalled
This bit is set when a STALL handshake is transmitted. The CPU should
clear this bit by writing a 0. This bit can only be cleared. Setting this bit
does nothing.
1
TXRDY
R/W1S
0
Transmit Packet Ready
The CPU writes a 1 to this bit after loading a data packet into the FIFO.
It is cleared automatically when the data packet has been transmitted.
An interrupt is also generated at this point.
0
RXRDY
RO
0
Receive Packet Ready
This bit is set when a data packet has been received. An interrupt is
generated when this bit is set. The CPU clears this bit by setting the
RXRDYC bit.
550
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 49: USB Control and Status Endpoint 0 High (USBCSRH0), offset
0x103
USBSR0H is an 8-bit register that provides control and status bits for endpoint 0.
Host
Device
USBCSRH0 Host
USB Control and Status Endpoint 0 High (USBCSRH0)
Base 0x4005.0000
Offset 0x103
Type W1C, reset 0x00
7
6
RO
0
RO
0
5
4
3
RO
0
RO
0
reserved
Type
Reset
RO
0
2
1
0
DTWE
DT
FLUSH
W1S
0
R/W
0
W1C
0
Bit/Field
Name
Type
Reset
Description
7:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
DTWE
W1S
0
Data Toggle Write Enable
The CPU writes a 1 to this bit to enable the current state of the endpoint
0 data toggle to be written (see DT bit). This bit is automatically cleared
once the new value is written.
1
DT
R/W
0
Data Toggle
When read, this bit indicates the current state of the endpoint 0 data
toggle. If DTWE is High, this bit may be written with the required setting
of the data toggle. If DTWE is Low, this cannot be written.
0
FLUSH
W1C
0
Flush FIFO
The CPU writes a 1 to this bit to flush the next packet to be
transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset
and the TXRDY/RXRDY bit is cleared.
Important:
FLUSH should only be used when TXRDY/RXRDY is set.
At other times, it may cause data to be corrupted.
USBCSRH0 Device Mode
USB Control and Status Endpoint 0 High (USBCSRH0)
Base 0x4005.0000
Offset 0x103
Type W1C, reset 0x00
7
6
5
RO
0
RO
0
RO
0
4
3
2
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
0
FLUSH
W1S
0
April 08, 2008
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Univeral Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
Description
7:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
FLUSH
W1S
0
Flush FIFO
The CPU writes a 1 to this bit to flush the next packet to be
transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset
and the TXRDY/RXRDY bit is cleared.
Important:
552
FLUSH should only be used when TXRDY/RXRDY is set.
At other times, it may cause data to be corrupted.
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 50: USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108
USBCOUNT0 is an 8-bit read-only register that indicates the number of received data bytes in the
endpoint 0 FIFO. The value returned changes as the contents of the FIFO change and is only valid
while RXRDY is set.
Host
Device
USB Receive Byte Count Endpoint 0 (USBCOUNT0)
Base 0x4005.0000
Offset 0x108
Type RO, reset 0x00
7
6
5
4
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
3
2
1
0
RO
0
RO
0
RO
0
COUNT
RO
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
COUNT
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Count
Count is a read-only value that indicates the number of received data
bytes in the endpoint 0 FIFO.
April 08, 2008
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Preliminary
Univeral Serial Bus (USB) Controller
Register 51: USB Type Endpoint 0 (USBTYPE0), offset 0x10A
This is an 8-bit register that should be written with the operating speed of the targeted device being
communicated with using endpoint 0.
Host
USB Type Endpoint 0 (USBTYPE0)
Base 0x4005.0000
Offset 0x10A
Type R/W, reset 0x00
7
6
5
4
3
R/W
0
RO
0
RO
0
RO
0
SPEED
Type
Reset
R/W
0
2
1
0
RO
0
RO
0
RO
0
reserved
Bit/Field
Name
Type
Reset
Description
7:6
SPEED
R/W
0x00
Operating Speed
Operating speed of the target device. If selected, the target is assumed
to have the same connection speed as the core.
Value Description
5:0
reserved
RO
0x00
00
Reserved
01
Reserved
10
Full
11
Low
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
554
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Register 52: USB NAK Limit (USBNAKLMT), offset 0x10B
USBNAKLMT is an 8-bit register that sets the number of frames after which endpoint 0 should time
out on receiving a stream of NAK responses. (Equivalent settings for other endpoints can be made
through their USBTXINTERVALn and USBRXINTERVALn registers.)
Host
(m-1)
The number of frames selected is 2
(where m is the value set in the register, with valid values
of 2–16). If the host receives NAK responses from the target for more frames than the number
represented by the limit set in this register, the endpoint is halted.
Note:
A value of 0 or 1 disables the NAK timeout function.
USB NAK Limit (USBNAKLMT)
Base 0x4005.0000
Offset 0x10B
Type R/W, reset 0x00
7
6
5
4
3
RO
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
2
1
0
R/W
0
R/W
0
NAKLMT
R/W
0
Bit/Field
Name
Type
Reset
Description
7:5
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4:0
NAKLMT
R/W
0x00
EP0 NAK Limit
Number of frames after receiving a stream of NAK responses.
April 08, 2008
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Preliminary
Univeral Serial Bus (USB) Controller
Register 53: USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1),
offset 0x112
Register 54: USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2),
offset 0x122
Register 55: USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3),
offset 0x132
USBTXCSRLn is an 8-bit register that provides control and status bits for transfers through the
currently selected transmit endpoint.
Host
Device
USBTXCSRL1 Host Mode
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1)
Base 0x4005.0000
Offset 0x112
Type R/W, reset 0x00
7
NAKTO /
INCTX
Type
Reset
R/W0C
0
6
5
4
CLRDT STALLED SETUP
W1S
0
R/W0C
0
R/W
0
3
2
1
0
FLUSH
ERROR
FIFONE
TXRDY
W1C
0
R/W0C
0
R/W0C
0
R/W0C
0
Bit/Field
Name
Type
Reset
7
NAKTO / INCTX
R/W0C
0
Description
NAK Timeout / Incomplete TX
Bulk endpoints only: This bit is set when the transmit endpoint is halted
following the receipt of NAK responses for longer than the time set as
the NAK Limit by the USBTXINTERVALn register. The CPU should
clear this bit to allow the endpoint to continue.
High-bandwidth interrupt endpoints only: This bit is set if no response
is received from the device to which the packet is being sent.
6
CLRDT
W1S
0
Clear Data Toggle
The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.
5
STALLED
R/W0C
0
Endpoint Stalled
This bit is set when a STALL handshake is received. When this bit is
set, any DMA request that is in progress is stopped, the FIFO is
completely flushed, and the TXRDY bit is cleared. The CPU should clear
this bit.
4
SETUP
R/W
0
Setup Packet
The CPU sets this bit, at the same time as the TXRDY bit is set, to send
a SETUP token instead of an OUT token for the transaction.
Note:
556
Setting this bit also clears DT.
April 08, 2008
Preliminary
LM3S3748 Microcontroller
Bit/Field
Name
Type
Reset
Description
3
FLUSH
W1C
0
Flush FIFO
The CPU writes a 1 to this bit to flush the latest packet from the endpoint
transmit FIFO. The FIFO pointer is reset, the TXRDY bit is cleared, and
an interrupt is generated. FLUSH may be set simultaneously with TXRDY
to abort the packet that is currently being loaded into the FIFO.
Note:
2
ERROR
R/W0C
0
FLUSH should only be used when TXRDY is set. At other times,
it may cause data to be corrupted. Also note that, if the FIFO
is double-buffered, FLUSH may need to be set twice to
completely clear the FIFO.
Error
The USB sets this bit when three attempts have been made to send a
packet and no handshake packet has been received. When the bit is
set, an interrupt is generated, TXRDY is cleared, and the FIFO is
completely flushed. The CPU should clear this bit.
Note:
1
FIFONE
R/W0C
0
This is valid only when the endpoint is operating in Bulk or
Interrupt mode.
FIFO Not Empty
The USB controller sets this bit when there is at least one packet in the
transmit FIFO.
0
TXRDY
R/W0C
0
Transmit Packet Ready
The CPU sets this bit after loading a data packet into the FIFO. It is
cleared automatically when a data packet has been transmitted. An
interrupt is generated at this point. TXRDY is also automatically cleared
prior to loading a second packet into a double-buffered FIFO.
USBTXCSRL1 Device Mode
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1)
Base 0x4005.0000
Offset 0x112
Type R/W, reset 0x00
7
INCTX
Type
Reset
R/W0C
0
6
5
CLRDT STALLED
W1S
0
R/W0C
0
4
3
2
1
0
STALL
FLUSH
UNDRN
FIFONE
TXRDY
R/W
0
W1C
0
R/W0C
0
R/W0C
0
R/W1S
0
Bit/Field
Name
Type
Reset
7
INCTX
R/W0C
0
Description
Incomplete Transmit
When the endpoint is being used for high-bandwidth isochronous
transfers, this bit is set to indicate where a large packet has been split
into 2 or 3 packets for transmission but insufficient IN tokens have been
received to send all the parts.
Note:
6
CLRDT
W1S
0
Only valid for isochronous transfers.
Clear Data Toggle
The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.
April 08, 2008
557
Preliminary
Univeral Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
5
STALLED
R/W0C
0
Description
Endpoint Stalled
This bit is set when a STALL handshake is transmitted. The FIFO is
flushed and the TXRDY bit is cleared. The CPU should clear this bit.
4
STALL
R/W
0
Send Stall
The CPU writes a 1 to this bit to issue a STALL handshake to an IN
token. The CPU clears this bit to terminate the stall conditi
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