NSC LM4846

LM4846
Output Capacitor-less Audio Subsystem with
Programmable National 3D
General Description
Key Specifications
The LM4846 is an audio power amplifier capable of delivering 500mW of continuous average power into a mono 8Ω
bridged-tied load (BTL) with 1% THD+N, 25mW per channel
of continuous average power into stereo 32Ω single-ended
(SE) loads with 1% THD+N, or an output capacitor-less
(OCL) configuration with identical specification as the SE
configuration, from a 3.3V power supply.
The LM4846 features a 32-step digital volume control and
eight distinct output modes. The digital volume control, 3D
enhancement, and output modes (mono/SE/OCL) are programmed through a two-wire I2C or a three-wire SPI compatible interface that allows flexibility in routing and mixing
audio channels. The LM4846 has three input channels: one
pair for a two-channel stereo signal and the third for a
single-channel mono input.
The LM4846 is designed for cellular phone, PDA, and other
portable handheld applications. It delivers high quality output
power from a surface-mount package and requires only
seven external components in the OCL mode (two additional
components in SE mode).
j THD+N at 1kHz, 500mW
into 8Ω BTL (3.3V)
1.0% (typ)
j THD+N at 1kHz, 30mW
into 32Ω SE (3.3V)
1.0% (typ)
j Single Supply Operation (VDD)
2.7 to 5.5V
j I2C/SPI Single Supply Operation
2.2 to 5.5V
Features
n I2C/SPI Control Interface
n I2C/SPI programmable National 3D Audio
n I2C/SPI controlled 32 step digital volume control (-54dB
to +18dB)
n Three independent volume channels (Left, Right, Mono)
n Eight distinct output modes
n microSMD surface mount packaging
n “Click and Pop” suppression circuitry
n Thermal shutdown protection
n Low shutdown current (0.1uA, typ)
Applications
n Moblie Phones
n PDAs
Boomer ® is a registered trademark of National Semiconductor Corporation.
© 2005 National Semiconductor Corporation
DS201668
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LM4846 Output Capacitor-less Audio Subsystem with Programmable National 3D
December 2005
LM4846
Typical Application
20166866
FIGURE 1. Typical Audio Amplifier Application Circuit-Output Capacitor-less
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2
LM4846
Typical Application
(Continued)
20166867
FIGURE 2. Typical Audio Amplifier Application Circuit-Single Ended
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LM4846
Connection Diagrams
25-Bump micro SMD
201668K0
Top View
XY - Date Code
TT - Die Traceability
G - Boomer Family
G5 - LM4846TL
201668K1
Top View
Pin Descriptions
Bump
Name
1
A1
SDA
Description
2
A2
I2CSPI_VDD
3
A3
RHP3D2
4
A4
RHP3D1
5
A5
VOC
6
B1
MONO-
7
B2
SCL
8
B3
ID_ENB
9
B4
Phone_In
Mono Input
No Connect
I2C or SPI Data
I2C or SPI Interface Power Supply
Right Headphone 3D Input 2
Right Headphone 3D Input 1
Center Amplifier Output
Loudspeaker Negative Output
I2C or SPI Clock
Address Identification/Enable Bar
10
B5
NC
11
C1
GND
Ground
12
C2
VDD
Power Supply
13
C3
VDD
Power Supply
14
C4
VDD
Power Supply
15
C5
GND
GND
16
D1
MONO+
17
D2
NC
18
D3
LHP3D1
19
D4
RIN
20
D5
ROUT
21
E1
I2C SPI_SEL
22
E2
CBYPASS
23
E3
LHP3D2
24
E4
LIN
25
E5
LOUT
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Loudspeaker Positive Output
No Connect
Left Headphone 3D Input 1
Right Input Channel
Right Headphone Output
I2C or SPI Select
Half-Supply Bypass
Left Headphone 3D Input 2
Left Input Channel
Left Headphone Output
4
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Vapor Phase (60 sec.)
215˚C
Infrared (15 sec.)
220˚C
Thermal Resistance
θJA (typ) - TLA25CBA
65˚C/W (Note 8)
6.0V
Storage Temperature
−65˚C to +150˚C
Input Voltage
−0.3 to VDD +0.3
ESD Susceptibility (Note 3)
ESD Machine model (Note 6)
Junction Temperature (TJ)
Operating Ratings (Note 2)
2.0kV
Temperature Range
200V
Supply Voltage (VDD)
2.7V ≤ VDD ≤ 5.5V
Supply Voltage (I2C/SPI)
2.2V ≤ VDD ≤ 5.5V
150˚C
−40˚C to 85˚C
Solder Information (Note 1)
Electrical Characteristics 3.3V (Notes 2, 7)
The following specifications apply for VDD = 3.3V, TA = 25˚C unless otherwise specified. [AV = 2 (BTL), AV = 1 (SE)]
Symbol
IDD
Parameter
Supply Current
Conditions
Output Modes 2, 4, 6
VIN = 0V; No load,
OCL = 0 (Table 2)
Output Modes 1, 3, 5, 7
VIN = 0V; No load, BTL,
OCL = 0 (Table 2)
LM4846
Units
(Limits)
Typical
(Note 4)
Limits
(Note 5)
3.3
6.5
mA (max)
6
11
mA (max)
ISD
Shutdown Current
Output Mode 0
0.1
1
µA (max)
VOS
Output Offset Voltage
VIN = 0V, Mode 5 (Note 10)
10
50
mV (max)
MONO OUT; RL = 8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1
500
400
mW (min)
ROUT and LOUT; RL = 32Ω
THD+N = 1%; f = 1kHz, SE, Mode 4
42
20
mW (min)
MONOOUT
f = 20Hz to 20kHz
POUT = 250mW; RL = 8Ω, BTL, Mode 1
0.5
%
ROUT and LOUT
f = 20Hz to 20kHz
POUT = 12mW; RL = 32Ω, SE, Mode 4
0.5
%
26
µV
Output Mode 1,7
71
dB
Output Mode 3
68
dB
Output Mode 5
63
dB
Output Mode 2
88
dB
Output Mode 4
76
dB
Output Mode 6, 7
76
dB
PO
THD+N
NOUT
Output Power
Total Harmonic Distortion Plus
Noise
Output Noise
Power Supply Rejection Ratio
MONOOUT
PSRR
Power Supply Rejection Ratio
ROUT and LOUT
A-weighted (Note 9), Mode 5, BTL
input referred
VRIPPLE = 200mVPP; f = 217Hz,
CB = 2.2µF, BTL
All audio inputs terminated into 50Ω;
output referred gain = 6dB (BTL)
VRIPPLE = 200mVPP; f = 217Hz
CB = 2.2µF, SE, CO = 100µF
All audio inputs terminated into 50Ω;
output referred gain,
OCL = 0 (Table 2)
5
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LM4846
Absolute Maximum Ratings (Note 2)
LM4846
Electrical Characteristics 3.3V (Notes 2, 7)
(Continued)
The following specifications apply for VDD = 3.3V, TA = 25˚C unless otherwise specified. [AV = 2 (BTL), AV = 1 (SE)]
Symbol
Parameter
Digital Volume Range
(RIN and LIN)
Mute Attenuation
MONO_IN Input Impedance
RIN and LIN Input Impedance
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Conditions
LM4846
Units
(Limits)
Typical
(Note 4)
Limits
(Note 5)
Input referred maximum attenuation
-54
–53.25
–54.75
dB (min)
dB (max)
Input referred maximum gain
18
17.25
18.75
dB (min)
dB (max)
Output Mode 1, 3, 5
80
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
dB
Maximum gain setting
11
8
14
Maximum attenuation setting
100
75
125
6
LM4846
Electrical Characteristics 5.0V (Notes 3, 7)
The following specifications apply for VDD = 5.0V, TA = 25˚C unless otherwise specified. [AV = 2 (BTL), AV = 1 (SE)].
Symbol
Parameter
Conditions
LM4846
Typical
(Note 4)
IDD
Supply Current
Limits
(Notes 5,
10)
Units
(Limits)
Output Modes 2, 4, 6
VIN = 0V; No load,
OCL = 0 (Table 2)
3.6
mA
Output Modes 1, 3, 5, 7
VIN = 0V; No Load,
OCL = 0 (Table 2)
6.8
mA
ISD
Shutdown Current
Output Mode 0
0.1
µA
VOS
Output Offset Voltage
VIN = 0V, Mode 5 (Note 10)
PO
THD+N
NOUT
Output Power
Total Harmonic Distortion Plus
Noise
Output Noise
Power Supply Rejection Ratio
MONOOUT
PSRR
Power Supply Rejection Ratio
ROUT and LOUT
Digital Volume Range
(RIN and LIN)
Mute Attenuation
MONO_IN Input Impedance
RIN and LIN Input Impedance
10
mV
MONOOUT; RL = 8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1
1.15
W
ROUT and LOUT; RL = 32Ω
THD+N = 1%; f = 1kHz, SE, Mode 4
75
mW
MONOOUT
f = 20Hz to 20kHz
POUT = 500mW; RL = 8Ω, BTL, Mode 1
0.5
%
ROUT and LOUT
f = 20Hz to 20kHz
POUT = 30mW; RL = 32Ω,SE, Mode 4
0.5
%
26
µV
Output Mode 1, 7
71
dB
Output Mode 3
68
dB
Output Mode 5
63
dB
Output Mode 2
88
dB
Output Mode 4
76
dB
Output Mode 6, 7
76
dB
Input referred maximum attenuation
-54
–53.25
–54.75
dB
dB
Input referred maximum gain
18
17.25
18.75
dB
dB
Output Mode 1, 3, 5
80
dB
Maximum gain setting
11
kΩ
kΩ
Minimum gain setting
100
kΩ
kΩ
A-weighted (Note 9), Mode 5, BTL
input referred
VRIPPLE = 200mVPP; f = 217Hz,
CB = 2.2µF, BTL
All audio inputs terminated into 50Ω;
output referred gain = 6dB (BTL)
VRIPPLE = 200mVPP; f = 217Hz,
CB = 2.2µF, SE, CO = 100µF
All audio inputs terminated into 50Ω;
output referred gain,
OCL = 0 (Table 2)
7
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LM4846
I2C/SPI (Notes 2, 7)
The following specifications apply for VDD = 5.0V and 3.3V, TA = 25˚C unless otherwise specified.
Symbol
Parameter
Conditions
LM4846
Typical
(Note 4)
Limits
(Notes 5,
10)
Units
(Limits)
t1
I2C Clock Period
2.5
µs (max)
t2
I2C Clock Setup Time
100
ns (min)
t3
I2C Data Hold Time
100
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition Time
100
ns (min)
fSPI
Maximum SPI Frequency
1000
kHz (max)
tEL
SPI ENB Low Time
100
ns (min)
tDS
SPI Data Setup Time
100
µs (max)
tES
SPI ENB Setup Time
100
ns (min)
tDH
SPI Data Hold Time
100
ns (min)
tEH
SPI Enable Hold Time
100
ns (min)
tCL
SPI Clock Low Time
500
ns (min)
tCH
SPI Clock High Time
500
ns (min)
tCS
SPI Clock Transition Time
100
ns (min)
VIH
I2C/SPI Input Voltage High
0.7xI2CSPI
VDD
V (min)
VIL
I2C/SPI Input Voltage Low
0.3xI2CSPI
VDD
V (max)
Note 1: See AN-450 "Surface Mounting and their effects on Product Reliability" for other methods of soldering surface mount devices.
Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 3: Human body model, 100pF discharged through a 1.5kΩ resistor.
Note 4: Typical specifications are specified at +25˚C and represent the most likely parametric norm.
Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 6: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50Ω).
Note 7: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 8: The given θJA for an LM4846ITL mounted on a demonstration board with a 9in2 area of 1oz printed circuit board copper ground plane.
Note 9: Datasheet min/max specifications are guaranteed by design, test, or statistical analysis.
Note 10: Potentially worse case: All three input stages are DC coupled to the BTL output stage.
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I2C PIN DESCRIPTION
For I2C interface operation, the I2CSPI_SEL pin needs to be
tied LOW (and tied high for SPI operation).
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
After the last bit of the address bit is sent, the master
releases the data line HIGH (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the
LM4846 has received the address correctly, then it holds the
data line LOW during the clock pulse. If the data line is not
held LOW during the acknowledge clock pulse, then the
master should abort the rest of the data transfer to the
LM4846.
ID_ENB: This is the address select input pin.
I2CSPI_SEL: This is tied LOW for I2C mode.
I2C COMPATIBLE INTERFACE
The LM4846 uses a serial bus which conforms to the I2C
protocol to control the chip’s functions with two wires: clock
(SCL) and data (SDA). The clock line is uni-directional. The
data line is bi-directional (open-collector). The maximum
clock frequency specified by the I2C standard is 400kHz. In
this discussion, the master is the controlling microcontroller
and the slave is the LM4846.
The I2C address for the LM4846 is determined using the
ID_ENB pin. The LM4846’s two possible I2C chip addresses
are of the form 111110X10 (binary), where X1 = 0, if ID_ENB
is logic LOW; and X1 = 1, if ID_ENB is logic HIGH. If the I2C
interface is used to address a number of chips in a system,
the LM4846’s chip address can be changed to avoid any
possible address conflicts.
The bus format for the I2C interface is shown in Figure 3. The
bus format diagram is broken up into six major sections:
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
HIGH.
After the data byte is sent, the master must check for another
acknowledge to see if the LM4846 received the data.
If the master has more data bytes to send to the LM4846,
then the master can repeat the previous two steps until all
data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data
signal goes HIGH while the clock signal is HIGH. The data
line should be held HIGH when not in use.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM4846’s I2C interface is powered up through the
I2CVDD pin. The LM4846’s I2C interface operates at a voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This is ideal
whenever logic levels for the I2C interface are dictated by a
microcontroller or microprocessor that is operating at a lower
supply voltage than the main battery of a portable system.
The "start" signal is generated by lowering the data signal
while the clock signal is HIGH. The start signal will alert all
devices attached to the I2C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first.
The data is latched in on the rising edge of the clock. Each
address bit must be stable while the clock level is HIGH.
201668F5
FIGURE 3. I2C Bus Format
9
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LM4846
Application Information
LM4846
Application Information
(Continued)
201668F4
FIGURE 4. I2C Timing Diagram
7. If ID_ENB remains HIGH for more than 100ns before all 8
bits are transmitted then the data latch will be aborted.
8. If ID_ENB is LOW for more than 8 CLK pulses then only
the first 8 data bits will be latched and activated when
ID_ENB transitions to logic-high.
9. ID_ENB must remain HIGH for at least 100ns (tEL ) to latch
in the data.
SPI DESCRIPTION
0. I2CSPI_SEL: This pin is tied HIGH for SPI mode.
1. The data bits are transmitted with the MSB first.
2. The maximum clock rate is 1MHz for the CLK pin.
3. CLK must remain HIGH for at least 500ns (tCH ) after the
rising edge of CLK, and CLK must remain LOW for at least
500ns (tCL) after the falling edge of CLK.
4. The serial data bits are sampled at the rising edge of CLK.
Any transition on DATA must occur at least 100ns (tDS)
before the rising edge of CLK. Also, any transition on DATA
must occur at least 100ns (tDH) after the rising edge of CLK
and stabilize before the next rising edge of CLK.
10. Coincidental rising or falling edges of CLK and ID_ENB
are not allowed. If CLK is to be held HIGH after the data
transmission, the falling edge of CLK must occur at least
100ns (tCS) before ID_ENB transitions to LOW for the next
set of data.
5.ID_ENB should be LOW only during serial data transmission.
6. ID_ENB must be LOW at least 100ns (tES ) before the first
rising edge of CLK, and ID_ENB has to remain LOW at least
100ns (tEH) after the eighth rising edge of CLK.
20166824
FIGURE 5. SPI Timing Diagram
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10
LM4846
Application Information
(Continued)
TABLE 1. Chip Address
A7
A6
A5
A4
A3
A2
A1
A0
Chip
Address
1
1
1
1
1
0
EC
0
ID_ENB = 0
1
1
1
1
1
0
0
0
ID_ENB = 1
1
1
1
1
1
0
1
0
TABLE 2. Control Registers
D7
D6
D5
D4
D3
D2
D1
D0
Mode Control
0
0
0
0
OCL
MC2
MC1
MC0
Programmable 3D
0
1
0
0
N3D3
N3D2
N3D1
N3D0
Mono Volume
Control
1
0
0
MVC4
MVC3
MVC2
MVC1
MVC0
Left Volume Control
1
1
0
LVC4
LVC3
LVC2
LVC1
LVC0
Right Volume
Control
1
1
1
RVC4
RVC3
RVC2
RVC1
RVC0
1.
2.
3.
4.
5.
6.
7.
8.
Bits MVC0 — MVC4 control 32 step volume control for MONO input
Bits LVC0 — LVC4 control 32 step volume control for LEFT input
Bits RVC0 — RVC4 control 32 step volume control for RIGHT input
Bits MC0 — MC2 control 8 distinct modes
Bits N3D3, N3D2, N3D1, N3D0 control programmable 3D function
N3D0 turns the 3D function ON (N3D0 = 1) or OFF (N3D0 = 0), and N3D1 = 0 provides a “wider” aural effect or N3D1 = 1 a “narrower” aural effect
Bit OCL selects between SE with output capacitor (OCL = 0) or SE without output capacitors (OCL = 1). Default is OCL = 0
N3D1 selects between two different 3D configurations
TABLE 3. Programmable National 3D Audio
N3D3
N3D2
Low
0
0
Medium
0
1
High
1
0
Maximum
1
1
TABLE 4. Output Mode Selection
Output
Mode
Number
MC2
MC1
MC0
0
0
0
0
SD
SD
SD
1
0
0
1
2 x GP x P
MUTE
MUTE
GP x P
Handsfree Speaker
Output
Right HP Output
Left HP Output
2
0
1
0
SD
GP x P
3
0
1
1
2 x (GL x L + GR x R)
MUTE
MUTE
4
1
0
0
SD
GR x R
GL x L
5
1
0
1
2 x (GL x L + GR x R +
GP x P)
MUTE
MUTE
6
1
1
0
SD
GR x R + GP x P
GL x L + GP x P
7
1
1
1
2 x (GR x R + GL x L)
GR x R
GL x L
On initial POWER ON, the default mode is 000
P = Phone in
R = RIN
L = LIN
SD = Shutdown
MUTE = Mute Mode
GP = Phone In (Mono) volume control gain
GR = Right stereo volume control gain
GL = Left stereo volume control gain
11
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LM4846
Application Information
(Continued)
TABLE 5. Volume Control Table
1.
2.
Volume Step
xVC4
xVC3
xVC2
xVC1
xVC0
Headphone
Gain, dB
Speaker
Gain, dB
(BTL)
1
0
0
0
0
0
–54.00
–48.00
2
0
0
0
0
1
–46.50
–40.50
3
0
0
0
1
0
–40.50
–34.50
4
0
0
0
1
1
–34.50
–28.50
5
0
0
1
0
0
–30.00
–24.00
6
0
0
1
0
1
–27.00
–21.00
7
0
0
1
1
0
–24.00
–18.00
8
0
0
1
1
1
–21.00
–15.00
9
0
1
0
0
0
–18.00
–12.00
10
0
1
0
0
1
–15.00
–9.00
11
0
1
0
1
0
–13.50
–7.50
12
0
1
0
1
1
–12.00
–6.00
13
0
1
1
0
0
–10.50
–4.50
14
0
1
1
0
1
–9.00
–3.00
15
0
1
1
1
0
–7.50
–1.50
16
0
1
1
1
1
–6.00
0.00
17
1
0
0
0
0
–4.50
1.50
18
1
0
0
0
1
–3.00
3.00
19
1
0
0
1
0
–1.50
4.50
20
1
0
0
1
1
0.00
6.00
21
1
0
1
0
0
1.50
7.50
22
1
0
1
0
1
3.00
9.00
23
1
0
1
1
0
4.50
10.50
24
1
0
1
1
1
6.00
12.00
25
1
1
0
0
0
7.50
13.50
26
1
1
0
0
1
9.00
15.00
27
1
1
0
1
0
10.50
16.50
28
1
1
0
1
1
12.00
18.00
29
1
1
1
0
0
13.50
19.50
30
1
1
1
0
1
15.00
21.00
31
1
1
1
1
0
16.50
22.50
32
1
1
1
1
1
18.00
24.00
x = M, L, or R
Gain / Attenuation is from input to output
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f3DR(-3dB) = 1 / 2π * 20kΩ * C3DR
(Continued)
NATIONAL 3D ENHANCEMENT
(2)
Optional resistors R3DL and R3DR can also be added (Figure
7) to affect the -3dB frequency and 3D magnitude.
The LM4846 features a stereo headphone, 3D audio enhancement effect that widens the perceived soundstage
from a stereo audio signal. The 3D audio enhancement
creates a perceived spatial effect optimized for stereo headphone listening. The LM4846 can be programmed for a
“narrow” or “wide” soundstage perception. The narrow
soundstage has a more focused approaching sound direction, while the wide soundstage has a spatial, theater-like
effect. Within each of these two modes, four discrete levels
of 3D effect that can be programmed: low, medium, high,
and maximum (Table 2), each level with an ever increasing
aural effect, respectively. The difference between each level
is 3dB.
The external capacitors, shown in Figure 6, are required to
enable the 3D effect. The value of the capacitors set the
cutoff frequency of the 3D effect, as shown by Equations 1
and 2. Note that the internal 20kΩ resistor is nominal
( ± 25%).
20166894
FIGURE 7. External RC Network with Optional R3DL
and R3DR Resistors
f3DL(-3dB) = 1 / 2π * (20kΩ + R3DL) * C3DL
(3)
f3DR(-3dB) = 1 / 2π * 20kΩ + R3DR) * C3DR
(4)
∆AV (change in AC gain) = 1 / 1 + M, where M represents
some ratio of the nominal internal resistor, 20kΩ (see example below).
20166895
f3dB (3D) = 1 / 2π (1 + M)(20kΩ * C3D)
(5)
CEquivalent (new) = C3D / 1 + M
(6)
FIGURE 6. External 3D Effect Capacitors
f3DL(-3dB) = 1 / 2π * 20kΩ * C3DL
(1)
TABLE 6. Pole Locations
R3D (kΩ)
(optional)
C3D (nF)
M
∆AV (dB)
f-3dB (3D)
(Hz)
0
68
0
0
117
1
68
0.05
–0.4
5
68
0.25
–1.9
10
68
0.50
20
68
1.00
Value of C3D
to keep same
pole location
(nF)
new Pole
Location
(Hz)
111
64.8
117
94
54.4
117
–3.5
78
45.3
117
–6.0
59
34.0
117
PCB LAYOUT AND SUPPLY REGULATION
CONSIDERATIONS FOR DRIVING 8Ω LOAD
Power dissipated by a load is a function of the voltage swing
across the load and the load’s impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance
between the amplifier output pins and the load’s connections. Residual trace resistance causes a voltage drop,
which results in power dissipated in the trace and not in the
load as desired. For example, 0.1Ω trace resistance reduces
the output power dissipated by an 8Ω load from 158.3mW to
156.4mW. The problem of decreased load dissipation is
exacerbated as load impedance decreases. Therefore, to
maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load
must be as wide as possible.
Poor power supply regulation adversely affects maximum
output power. A poorly regulated supply’s output voltage
decreases with increasing load current. Reduced supply
voltage causes decreased headroom, output signal clipping,
13
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LM4846
Application Information
LM4846
Application Information
(Continued)
The maximum internal power dissipation of the LM4846
occurs when all 3 amplifiers pairs are simultaneously on; and
is given by Equation (11).
and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor
supply regulation. Therefore, making the power supply
traces as wide as possible helps maintain full output voltage
swing.
PDMAX-TOTAL =
PDMAX-SPKROUT + PDMAX-LOUT + PDMAX-ROUT
BRIDGE CONFIGURATION EXPLANATION
The maximum power dissipation point given by Equation
(11) must not exceed the power dissipation given by Equation (12):
(12)
PDMAX = (TJMAX - TA) / θJA
The LM4846 drives a load, such as a speaker, connected
between outputs, MONO+ and MONO-.
This results in both amplifiers producing signals identical in
magnitude, but 180˚ out of phase. Taking advantage of this
phase difference, a load is placed between MONO- and
MONO+ and driven differentially (commonly referred to as
”bridge mode”). This results in a differential or BTL gain of:
AVD = 2(Rf / Ri) = 2
The LM4846’s TJMAX = 150˚C. In the ITL package, the
LM4846’s θJA is 65˚C/W. At any given ambient temperature
TA, use Equation (12) to find the maximum internal power
dissipation supported by the IC packaging. Rearranging
Equation (12) and substituting PDMAX-TOTAL for PDMAX’ results in Equation (13). This equation gives the maximum
ambient temperature that still allows maximum stereo power
dissipation without violating the LM4846’s maximum junction
temperature.
(13)
TA = TJMAX - PDMAX-TOTAL θJA
(7)
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier’s output and ground. For a given supply voltage, bridge
mode has a distinct advantage over the single-ended configuration: its differential output doubles the voltage swing
across the load. Theoretically, this produces four times the
output power when compared to a single-ended amplifier
under the same conditions. This increase in attainable output
power assumes that the amplifier is not current limited and
that the output signal is not clipped.
Another advantage of the differential bridge output is no net
DC voltage across the load. This is accomplished by biasing
MONO- and MONO+ outputs at half-supply. This eliminates
the coupling capacitor that single supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a
typical single-ended configuration forces a single-supply amplifier’s half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently
damage loads such as speakers.
For a typical application with a 5V power supply and an 8Ω
load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 104˚C for the
ITL package.
(14)
TJMAX = PDMAX-TOTAL θJA + TA
Equation (14) gives the maximum junction temperature TJMAX. If the result violates the LM4846’s 150˚C, reduce the
maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface
mount part operating around the maximum power dissipation
point. Since internal power dissipation is a function of output
power, higher ambient temperatures are allowed as output
power or duty cycle decreases. If the result of Equation (11)
is greater than that of Equation (12), then decrease the
supply voltage, increase the load impedance, or reduce the
ambient temperature. If these measures are insufficient, a
heat sink can be added to reduce θJA. The heat sink can be
created using additional copper area around the package,
with connections to the ground pin(s), supply pin and amplifier output pins. External, solder attached SMT heatsinks
such as the Thermalloy 7106D can also improve power
dissipation. When adding a heat sink, the θJA is the sum of
θJC, θCS, and θSA. (θJC is the junction-to-case thermal impedance, θCS is the case-to-sink thermal impedance, and
θSA is the sink-to-ambient thermal impedance). Refer to the
Typical Performance Characteristics curves for power dissipation information at lower output power levels.
POWER DISSIPATION
Power dissipation is a major concern when designing a
successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to
the load by a bridge amplifier is higher internal power dissipation. The LM4846 has a pair of bridged-tied amplifiers
driving a handsfree speaker, MONO. The maximum internal
power dissipation operating in the bridge mode is twice that
of a single-ended amplifier. From Equation (8), assuming a
5V power supply and an 8Ω load, the maximum MONO
power dissipation is 634mW.
PDMAX-SPKROUT = 4(VDD)2 / (2π2 RL): Bridge Mode (8)
The LM4846 also has a pair of single-ended amplifiers driving stereo headphones, ROUT and LOUT. The maximum internal power dissipation for ROUT and LOUT is given by
equation (9) and (10). From Equations (9) and (10), assuming a 5V power supply and a 32Ω load, the maximum power
dissipation for LOUT and ROUT is 40mW, or 80mW total.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically
use a 1µF in parallel with a 0.1µF filter capacitors to stabilize
the regulator’s output, reduce noise on the supply line, and
improve the supply’s transient response. However, their
presence does not eliminate the need for a local 1.1µF
tantalum bypass capacitance connected between the
PDMAX-LOUT = (VDD)2 / (2π2 RL): Single-ended Mode (9)
PDMAX-ROUT = (VDD)2 / (2π2 RL): Single-ended Mode(10)
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(11)
14
(Continued)
fc = 1 / (2πRiCi)
LM4846’s supply pins and ground. Keep the length of leads
and traces that connect capacitors between the LM4846’s
power supply pin and ground as short as possible. Connecting a 2.2µF capacitor, CB, between the BYPASS pin and
ground improves the internal bias voltage’s stability and
improves the amplifier’s PSRR. The PSRR improvements
increase as the bypass pin capacitor value increases. Too
large, however, increases turn-on time and can compromise
the amplifier’s click and pop performance. The selection of
bypass capacitor values, especially CB, depends on desired
PSRR requirements, click and pop performance (as explained in the section, Proper Selection of External Components), system cost, and size constraints.
(15)
As an example when using a speaker with a low frequency
limit of 150Hz, Ci, using Equation (15) is 0.053µF. The
0.22µF Ci shown in Figure 1 allows the LM4846 to drive high
efficiency, full range speaker whose response extends below
40Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor connected to the BYPASS bump. Since CB determines how fast
the LM4846 settles to quiescent operation, its value is critical
when minimizing turn-on pops. The slower the LM4846’s
outputs ramp to their quiescent DC voltage (nominally VDD/
2), the smaller the turn-on pop. Choosing CB equal to 1.0µF
along with a small value of Ci (in the range of 0.1µF to
0.39µF), produces a click-less and pop-less shutdown function. As discussed above, choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and
pops. CB’s value should be in the range of 5 times to 7 times
the value of Ci. This ensures that output transients are
eliminated when power is first applied or the LM4846 resumes operation after shutdown.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value
input coupling capacitor (Ci in Figures 1 & 2). A high value
capacitor can be expensive and may compromise space
efficiency in portable designs. In many cases, however, the
speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz.
Applications using speakers with this limited frequency response reap little improvement by using large input capacitor.
The internal input resistor (Ri), nominal 20kΩ, and the input
capacitor (Ci) produce a high pass filter cutoff frequency that
is found using Equation (15).
15
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LM4846
Application Information
LM4846
Application Information
(Continued)
LM4846 TL DEMO BOARD ARTWORK
Top Overlay
20166806
Top Layer
20166805
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16
LM4846
Application Information
(Continued)
Bottom Layer
20166804
17
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LM4846
Revision History
www.national.com
Rev
Date
Description
1.0
8/22/05
1st PDF by copying LM4845
(DS201059)
1.1
8/25/05
Edited Figures 201668 94, 95, and
K0.
1.2
8/31/05
Added the clause, N3D1 = 0.......on
item #6, below Table 2.
1.3
9/08/05
Fixed Pin Desc table (pg 4), pin 2
1.4
9/20/05
Added the 3 (new) boards.
1.5
9/26/05
Edited the “NATIONAL 3D
ENHANCEMENT” paragraph per
Allan.
1.6
11/03/05
Edited 201668 K0 and few text
edits.
1/7
11/10/05
1st WEB released.
1.8
12/21/05
Edited the X1, X2, and X3 in the
mktg ouline, then re-released D/S
to the WEB.
18
inches (millimeters) unless otherwise noted
25 – Bump micro SMD
Order Number LM4846TL
NS Package Number TLA25CBA
Dimensions are in millimeters
X1 = 2.543 ± 0.03 X2 = 2.517 ± 0.03 X3 = 0.600 ± 0.075
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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LM4846 Output Capacitor-less Audio Subsystem with Programmable National 3D
Physical Dimensions