NSC LM80CIMT-51 Serial interface acpi-compatible microprocessor system hardware monitor Datasheet

LM80
Serial Interface ACPI-Compatible Microprocessor System
Hardware Monitor
General Description
The LM80 provides 7 positive voltage inputs, temperature
measurement, fan speed measurement, and hardware
monitoring on an I2C™ interface. The LM80 performs
WATCHDOG™ comparisons of all measured values and an
open-drain interrupt output becomes active when any values
exceed programmed limits. A Chassis Intrusion input is provided to monitor and reset an external circuit designed to
latch a chassis intrusion event.
The LM80 is especially suited to interface to both linear and
digital temperature sensors. The 10 mV LSB and 2.56 volt
input range is ideal for accepting inputs from a linear sensor
such as the LM50. The BTI is used as an input from either
digital or thermostat sensors such as LM75 and LM56.
The LM80’s 2.8V to 5.75V supply voltage range, low supply
current, and I2C interface make it ideal for a wide range of
applications. These include hardware monitoring and protection applications in personal computers, electronic test
equipment, and office electronics.
n WATCHDOG comparison of all monitored values
n Separate input to show status in Interrupt Status
Register of additional external temperature sensors such
as the LM56 or LM75
n I2C Serial Bus interface compatibility
n Shutdown mode to minimize power consumption
n Programmable RST_OUT/OS pin: RST_OUT provides a
Reset output; OS provides an Interrupt Output activated
by an Overtemperature Shutdown event
Key Specifications
± 1% (max)
n Voltage monitoring Error
n Temperature Error
−25˚C to +125˚C
± 3˚C (max)
n Supply Voltage Range
n Supply Current
2.8V to
5.75V
Operating:
0.2 mA typ
Shutdown:
15 µA typ
Features
n ADC Resolution
8 Bits
Temperature sensing
7 positive voltage inputs
2 programmable fan speed monitoring inputs
10 mV LSB and 2.56V input range accepts outputs from
linear temperature sensors such as the LM50
n Chassis Intrusion Detector input
n Temperature Resolution
0.5˚C
n
n
n
n
Applications
n System Thermal and Hardware Monitoring for Servers
and PCs
n Office Electronics
n Electronic Test Equipment and Instrumentation
Typical Application
DS100040-1
# Indicates Active Low (“Not”)
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
WATCHDOG™ is a trademark of National Semiconductor Corporation.
I2C ® is a registered trademark of the Philips Corporation.
© 1999 National Semiconductor Corporation
DS100040
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LM80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
June 1999
Ordering Information
Temperature Range
NS
Package
Number
−25˚C ≤ TA ≤ +125˚C
Order Number
LM80CIMT-31
LM80CIMTX-3 2
Connection Diagram
Device
Marking
Specified
Power
Supply
Voltage
LM80CIMT-3
MTC24B
3.3V
LM80CIMT-5
MTC24B
5.0V
1
LM80CIMT-5
LM80CIMTX-52
Note:
1-Rail
transport media, 62 parts per rail
2-Tape
and reel transport media, 3400 parts per reel
DS100040-2
Block Diagram
DS100040-3
Pin Descriptions
Pin
Name(s)
Pin
Number
Number
of Pins
INT_IN
1
1
Digital Input
This is an active low input that propagates the INT_IN signal to the
INT output of the LM80 via Interrupt Mask Register 1 Bit 7 and INT
enable Bit 1 of the Configuration Register.
SDA
2
1
Digital I/O
Serial Bus bidirectional Data. Open-drain output.
SCL
3
1
Digital Input
Serial Bus Clock.
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Type
Description
2
Pin Descriptions
Pin
Name(s)
Pin
Number
(Continued)
Number
of Pins
Type
Description
+
4-5
2
Digital Inputs
0 to V fan tachometer inputs.
BTI
6
1
Digital Input
Board Temperature Interrupt driven by O.S. outputs of additional
temperature sensors such as LM75. Provides internal pull-up of
10 kΩ.
CI (Chassis
Intrusion)
7
1
Digital I/O
An active high input from an external circuit which latches a Chassis
Intrusion event. This line can go high without any clamping action
regardless of the powered state of the LM80. The LM80 provides an
internal open drain on this line, controlled by Bit 5 of the
Configuration Register, to provide a minimum 10 ms reset of this
line.
FAN1-FAN2
GND
8
1
GROUND
Internally connected to all of the digital circuitry.
V+ (+2.8V to
+5.75V)
9
1
POWER
+3.3V or +5V V+ power. Bypass with the parallel combination of
10 µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass
capacitors.
INT
10
1
Digital Output
Non-Maskable Interrupt (open source)/Interrupt Request (open
drain). The mode is selected with Bit 5 of the Configuration Register
and the output is enabled when Bit 1 of the Configuration Register
is set to 1. The default state is disabled.
GPO (Power
Switch Bypass)
11
1
Digital Output
An active low open drain output intended to drive an external
P-channel power MOSFET for software power control.
NTEST_IN/
RESET_IN
12
1
Digital Input
An active-low input that enables NAND Tree board-level connectivity
testing. Refer to Section 10.0 on NAND Tree testing. Whenever
NAND Tree connectivity is enabled the LM80 is also reset to its
power on state.
RST_OUT/OS
13
1
Digital Output
Master Reset, 5 mA driver (open drain), active low output with a
10 ms minimum pulse width. Available when enabled via Bit 4 in
Configuration Register and Bit 7 of the Fan Divisor/RST_OUT/OS
Register. Bit 6 of the Fan Divisor/RST_OUT/OS Register enables
this output as an active low Overtemperature Shutdown (OS).
GNDA
14
1
GROUND
Internally connected to all analog circuitry. The ground reference for
all analog inputs. This pin needs to be taken to a low noise analog
ground plane for optimum performance.
IN6-IN0
15-21
7
Analog Inputs
0V to 2.56V full scale range Analog Inputs.
22
1
Digital I/O
The lowest order bit of the Serial Bus Address. This pin functions as
an output when doing a NAND Tree test.
2
Digital Inputs
The two highest order bits of the Serial Bus Address.
A0/NTEST_OUT
A1-A2
TOTAL PINS
23-24
24
3
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Absolute Maximum Ratings (Notes 1, 2)
Soldering Information
MTC24B Package (Note 6) :
Vapor Phase (60 seconds)
Infrared (15 seconds)
Storage Temperature
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage (V+)
Voltage on Any Input or Output Pin
Ground Difference (GND - GNDA)
Input Current at any Pin (Note 3)
Package Input Current (Note 3)
Maximum Junction Temperature
(TJ max)
ESD Susceptibility(Note 5)
Human Body Model
Machine Model
6.5V
−0.3V to (V++0.3V)
± 300 mV
± 5 mA
± 20 mA
215˚C
235˚C
−65˚C to +150˚C
Operating Ratings(Notes 1, 2)
Operating Temperature Range
TMIN ≤ TA ≤ TMAX
LM80CIMT-3, LM80CIMT-5
−25˚C ≤ TA ≤ +125˚C
Specified Temperature Range
TMIN ≤ TA ≤ TMAX
LM80CIMT-3, LM80CIMT-5
−25˚C ≤ TA ≤ +125˚C
Junction to Ambient Thermal Resistance (θJA(Note 4) )
NS Package Number: MTC24B
95˚C/W
+2.8V to +5.75V
Supply Voltage (V+)
Ground Difference
(|GND − GNDA|)
≤ 100 mV
−0.05V to V+ + 0.05V
VIN Voltage Range:
150˚C
2000V
125V
DC Electrical Characteristics
The following specifications apply for +2.8 VDC ≤V+ ≤ +3.8 VDC for LM80CIMT-3, +4.25 VDC ≤V+ ≤ +5.75 VDC for LM80CIMT-5,
IN0-IN6 RS = 25Ω, unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ =
25˚C.(Note 7)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 8)
(Note 9)
(Limits)
Interface Inactive and
V+ = 5.75V
0.2
2.0
mA (max)
Interface Inactive and
V+ = 3.8V
0.18
1.5
mA (max)
POWER SUPPLY CHARACTERISTICS
I+
Supply Current
Shutdown Mode
15
µA
TEMPERATURE-to-DIGITAL CONVERTER CHARACTERISTICS
Temperature Error
−25˚C ≤ TA ≤ +125˚C
Resolution
±3
˚C (max)
0.5
˚C (min)
±1
±1
% (max)
ANALOG-to-DIGITAL CONVERTER CHARACTERISTICS
Resolution (8 bits with full-scale at 2.56V)
TUE
Total Unadjusted Error
DNL
Differential Non-Linearity
PSS
Power Supply Sensitivity
tC
Total Monitoring Cycle Time
10
(Note 10)
mV
±1
(Note 11)
9-bit Temp resolution
12-bit Temp resolution
LSB
(max)
%/V
1.0
1.5
2
sec (max)
sec (max)
On Resistance
0.5
10
kΩ (max)
Input Current (On Channel Leakage Current)
±1
±1
MULTIPLEXER/ADC INPUT CHARACTERISTICS
Off Channel Leakage Current
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4
µA
µA
DC Electrical Characteristics
(Continued)
The following specifications apply for +2.8 VDC ≤V+ ≤ +3.8 VDC for LM80CIMT-3, +4.25 VDC ≤V+ ≤ +5.75 VDC for LM80CIMT-5,
IN0-IN6 RS = 25Ω, unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ =
25˚C.(Note 7)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 8)
(Note 9)
(Limits)
± 10
± 15
± 20
% (max)
255
(max)
FAN RPM-to-DIGITAL CONVERTER
Fan RPM Error
+25˚C ≤ TA ≤ +75˚C
−10˚C ≤ TA ≤ +100˚C
−25˚C ≤ TA ≤ +125˚C
Full-scale Count
FAN1 and FAN2 Nominal Input
RPM (See Section 6.0)
Internal Clock Frequency
Divisor = 1,
(Note 12)
Divisor = 2,
(Note 12)
Divisor = 3,
(Note 12)
Divisor = 4,
(Note 12)
% (max)
% (max)
Fan Count = 153
8800
RPM
Fan Count = 153
4400
RPM
Fan Count = 153
2200
RPM
Fan Count = 153
1100
RPM
+25˚C ≤ TA ≤ +75˚C
−10˚C ≤ TA ≤ +100˚C
22.5
22.5
20.2
kHz (min)
24.8
kHz (max)
19.1
kHz (min)
25.9
kHz (max)
18
kHz (min)
27
kHz (max)
IOUT = +5.0 mA at
V+ = +4.25V, IOUT = +3.0 mA
at V+ = +2.8V
IOUT = −5.0 mA at
V+ = +5.75V, IOUT = −3.0 mA
at V+ = +3.8V
2.4
V (min)
0.4
V (max)
IOUT = − 5.0 mA
at V+ = +5.75V,
IOUT = −3.0 mA at V+ = +3.8V
VOUT = V+
0.4
V (min)
0.1
100
µA (max)
30
10
ms (min)
0.4
V (min)
100
µA (max)
−25˚C ≤ TA ≤ +125˚C
22.5
DIGITAL OUTPUTS: A0/NTEST_OUT, INT
VOUT(1)
Logical “1” Output Voltage
VOUT(0)
Logical “0” Output Voltage
OPEN DRAIN OUTPUTS: GPO, RST_OUT/OS, CI
VOUT(0)
IOH
Logical “0” Output Voltage
High Level Output Current
RST_OUT/OS, CI
Pulse Width
OPEN DRAIN SERIAL BUS OUTPUT: SDA
VOUT(0)
Logical “0” Output Voltage
IOH
High Level Output Current
IOUT = −3.0 mA at
+
V = +5.75V, IOUT = −3.0 mA
at V+ = +3.8V
VOUT = V+
0.1
DIGITAL INPUTS: A0/NTEST_Out, A1-A2, BTI, CI (Chassis Intrusion), INT_IN, and NTEST_IN/Reset_IN
VIN(1)
Logical “1” Input Voltage
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
0.8
V (max)
SERIAL BUS INPUTS (SCL, SDA) and FAN TACH PULSE INPUTS (FAN1, FAN2)
VIN(1)
Logical “1” Input Voltage
0.7 x V+
V (min)
VIN(0)
Logical “0” Input Voltage
0.3 x V+
V (max)
ALL DIGITAL INPUTS Except for BTI
IIN(1)
Logical “1” Input Current
IIN(0)
Logical “0” Input Current
CIN
Digital Input Capacitance
VIN = V+
VIN = 0 VDC
−0.005
−1
µA (min)
0.005
1
µA (max)
20
5
pF
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DC Electrical Characteristics
(Continued)
The following specifications apply for +2.8 VDC ≤V+ ≤ +3.8 VDC for LM80CIMT-3, +4.25 VDC ≤V+ ≤ +5.75 VDC for LM80CIMT-5,
IN0-IN6 RS = 25Ω, unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ =
25˚C.(Note 7)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 8)
(Note 9)
(Limits)
BTI Digital Input
IIN(1)
Logical “1” Input Current
IIN(0)
Logical “0” Input Current
CIN
Digital Input Capacitance
VIN = V+
VIN = 0 VDC
−1
−10
µA (min)
500
2000
µA (max)
20
pF
AC Electrical Characteristics
The following specifications apply for +2.8 VDC ≤V+ ≤ +3.8 VDC for LM80CIMT-3, +4.25 VDC ≤V+ ≤ +5.75 VDC for
LM80CIMT-5, unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
(Note 13)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 8)
(Note 9)
(Limits)
µs (min)
SERIAL BUS TIMING CHARACTERISTICS
t1
SCL (Clock) Period
2.5
t2
Data In Setup Time to SCL High
100
ns (min)
t3
Data Out Stable After SCL Low
0
ns (min)
t4
SDA Low Setup Time to SCL Low (start)
100
ns (min)
t5
SDA High Hold Time After SCL High (stop)
100
ns (min)
DS100040-4
FIGURE 1. Serial Bus Timing Diagram
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6
AC Electrical Characteristics
(Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < (GND or GNDA) or VIN > V +), the current at that pin should be limited to 5 mA.
The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJmax−T A)/θJA.
Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin.
Note 6: See the section titled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Each input and output is protected by a nominal 6.5V breakdown voltage zener diode to GND; as shown below, input voltage magnitude up to 0.3V above
V+ or 0.3V below GND will not damage the LM80. There are parasitic diodes that exist between the inputs and the power supply rails. Errors in the ADC conversion
can occur if these diodes are forward biased by more than 50 mV. As an example, if V+ is 4.50 VDC, input voltage must be ≤ 4.55 VDC, to ensure accurate conversions.
DS100040-5
An x indicates that the diode exists.
Pin Name
D1
D2
D3
x
x
x
NTEST_IN/
Reset_IN
CI
x
x
IN0-IN6
x
x
x
GPO
x
x
BTI
x
x
x
FAN1–FAN2
x
INT
x
x
x
SCL
x
A1-A2
x
x
x
x
A0/NTEST_Out
x
x
x
INT_IN
SDA
x
RST_OUT/OS
x
Pin Name
D1
D2
D3
x
FIGURE 2. ESD Protection Input Structure
Note 8: Typicals are at TJ = TA = 25˚C and represent most likely parametric norm.
Note 9: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC.
Note 11: Total Monitoring Cycle Time includes temperature conversion, 7 analog input voltage conversions and 2 tachometer readings. Each input voltage conversion takes 100 ms typical and 112 ms maximum. 8-plus sign Temperature resolution takes 100 ms typical and 112 ms maximum, while 11-bit plus sign takes 800
ms typical and 900 ms maximum. Fan tachometer readings take 20 ms typical, at 4400 rpm, and 200 ms max.
Note 12: The total fan count is based on 2 pulses per revolution of the fan tachometer output.
Note 13: Timing specifications are tested at the Serial Bus Input logic levels, VIN(0) = 0.3 x V+ for a falling edge and VIN(1) = 0.7 x V+ for a rising edge.
7
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Test Circuit
DS100040-6
FIGURE 3. Digital Output Load Test Circuitry
Fan Divisor/RST_OUT/OS Registers: Bits 0-5 of this register contain the divisor bits for FAN1 and FAN2 inputs. Bits
6-7 control the function of the RST_OUT/OS output.
Functional Description
1.0 GENERAL DESCRIPTION
The LM80 provides 7 analog inputs, a temperature sensor, a
Delta-Sigma ADC (Analog-to-Digital Converter), 2 fan speed
counters, WATCHDOG registers, and a variety of inputs and
outputs on a single chip. A two wire Serial Bus interface is
provided. The LM80 performs power supply, temperature,
fan control and fan monitoring for personal computers.
The LM80 continuously converts analog inputs to 8-bit digital
words with a 10 mV LSB (Least Significant Bit) weighting,
yielding input ranges of 0 to 2.56V. The Analog inputs are intended to be connected to the several power supplies
present in a a typical computer. Temperature can be converted to a 9-bit or 12-bit two’s complement word with resolutions of 0.5˚C LSB or 0.0625˚C LSB, respectively.
Fan inputs can be programmed to accept either fan failure
indicator or tachometer signals. Fan failure signals can be
programmed to be either active high or active low. Fan inputs
measure the period of tachometer pulses from the the fans,
providing a higher count for lower fan speeds. The fan inputs
are digital inputs with and acceptable range of 0 to V+ volts
and a transition level of approximately V+/2 volts. Full scale
fan counts are 255 (8-bit counter), which represent a
stopped or very slow fan. Nominal speed based on a count
of 153, are programmable from 1100 to 8800 RPM. Signal
conditioning circuitry is included to accommodate slow rise
and fall times.
The LM80 provides a number of internal registers, as detailed in Figure 4. These include:
Configuration Register:
Provides control and configuration.
Interrupt Status Registers:
Two registers to provide status of each WATCHDOG limit or Interrupt event.
OS Configuration/Temperature Resolution Register: The
configuration of the OS (Overtemperature Shutdown) is controlled by the lower 3 bits of this register. Bit 3 enables 12-bit
temperature conversions. Bits 4-7 reflect the lower four bits
of the temperature reading for a 12-bit resolution.
Value RAM: The monitoring results: temperature, voltages,
fan counts, and Fan Divisor/RST_OUT/OS Register limits
are all contained in the Value RAM. The Value RAM consists
of a total of 32 bytes. The first 10 bytes are all of the results,
the next 20 bytes are the Fan Divisor/RST_OUT/OS Register limits, and are located at 20h-3Fh, including two unused
bytes in the upper locations.
When the LM80 is started, it cycles through each measurement in sequence, and it continuously loops through the sequence approximately once every second. Each measured
value is compared to values stored in WATCHDOG, or Limit
registers. When the measured value violates the programmed limit the LM80 will set a corresponding Interrupt in
the Interrupt Status Registers. Two hardware Interrupt lines,
INT and RST_OUT/OS are available. INT is fully programmable with masking of each Interrupt source, and masking of
each output. RST_OUT/OS is dedicated to the temperature
reading WATCHDOG registers. In addition, the Fan Divisor
register has control bits to enable or disable the hardware Interrupts.
Additional digital inputs are provided for chaining of INT, outputs of multiple external LM75 temperature sensors via the
BTI (Board Temperature Interrupt) input, and a CI (Chassis
Intrusion) input. The Chassis Intrusion input is designed to
accept an active high signal from an external circuit that
latches when the case is removed from the computer.
Interrupt Mask Registers: Allows masking of individual
Interrupt sources, as well as separate masking for each of
both hardware Interrupt outputs.
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8
Functional Description
(Continued)
2.0 INTERFACE
DS100040-7
FIGURE 4. LM80 Register Structure
9
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Functional Description
(Continued)
2.1 Internal Registers of the LM80
TABLE 1. The internal registers and their corresponding internal LM80 address is as follows:
Register
LM80 Internal Hex
Address (This is the
data to be written to
the Address Register)
Power on
Value
Configuration Register
00h
0000 1000
Interrupt Status Register 1
01h
0000 0000
Interrupt Status Register 2
02h
0000 0000
Interrupt Mask Register 1
03h
0000 0000
Interrupt Mask Register 2
04h
0000 0000
Fan Divisor/RST_OUT/OS
Register
05h
0001 0100
OS/ Configuration and
Temperature Resolution
Register
06h
0000 0001
Value RAM
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20h-3Fh
10
Notes
FAN1 and FAN2 divisor = 2 (count of 153 =
4400 RPM)
Functional Description
(Continued)
2.2 Serial Bus Interface
DS100040-8
(a) Serial Bus Write to the Internal Address Register followed by the Data Byte
DS100040-9
(b) Serial Bus Write to the Internal Address Register Only
DS100040-10
(c) Serial Bus Read from a Register with the Internal Address Register Preset to Desired Location
FIGURE 5. Serial Bus Timing
2.
If the Internal Address Register value is unknown, write
to the LM80 with the Serial Bus Interface Address byte,
followed by the Internal Address Register byte. Then restart the Serial Communication with a Read consisting of
the Serial Bus Interface Address byte, followed by the
data byte read from the LM80.
The default power on Serial Bus address for the LM80 is:
0101(A2)(A1)(A0) binary, where A0-A2 reflect the state of
the pins defined by the same names.
All of these communications are depicted in the Serial Bus
Interface Timing Diagrams as shown in Figure 5.
The Serial Bus control lines consists of the SDA (serial data),
SCL (serial clock) and A0-A1 (address) pins. The LM80 can
only operate as a slave. The SCL line only controls the serial
interface, all other clock functions within LM80 such as the
ADC and fan counters are done with a separate asynchronous internal clock.
When using the Serial Bus Interface a write will always consist of the LM80 Serial Bus Interface Address byte, followed
by the Internal Address Register byte, then the data byte.
There are two cases for a read:
1. If the Internal Address Register is known to be at the desired Address, simply read the LM80 with the Serial Bus
Interface Address byte, followed by the data byte read
from the LM80.
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Functional Description
Bit 3 clears the INT output when taken high. The LM80 monitoring function will stop until bit 3 is taken low. The content of
the Interrupt (INT) Status Registers will not be affected.
(Continued)
3.0 USING THE LM80
Bit4, when taken high, will initiate a 10 ms RESET signal on
the RST_OUT/OS output (when this pin is in the RST mode).
3.1 Power On
When power is first applied, the LM80 performs a “power on
reset” on several of its registers. The power on condition of
registers is shown in Table 1. Registers whose power on values are not shown have power on conditions that are indeterminate (this includes the value RAM and WATCHDOG
limits). The ADC is inactive. In most applications, usually the
first action after power on would be to write WATCHDOG limits into the Value RAM.
When bit 5 is taken high the CI (Chassis Intrusion) pin is reset.
Bit 6 of the configuration register sets or clears the GPO output. This pin can be used in software power control by activating an external power control MOSFET.
3.4 Starting Conversions
3.4 STARTING CONVERSION The monitoring function
(Analog inputs, temperature, and fan speeds) in the LM80 is
started by writing to the Configuration Register and setting
INT_Clear (Bit 3), low, and Start (Bit 0), high. The LM80 then
performs a round-robin monitoring of all analog inputs, temperature, and fan speed inputs approximately once a second. If the temperature resolution is set to 12 bits one complete monitoring function will take approximately 2 seconds.
The sequence of items being monitored corresponds to locations in the Value RAM (except for the Temperature reading)
and is:
1. Temperature
2. IN0
3. IN1
4. IN2
3.2 Resets
Configuration Register INITIALIZATION accomplishes the
same function as power on reset. The Value RAM conversion results, and Value RAM WATCHDOG limits are not Reset and will be indeterminate immediately after power on. If
the Value RAM contains valid conversion results and/or
Value RAM WATCHDOG limits have been previously set,
they will not be affected by a Configuration Register INITIALIZATION. Power on reset, or Configuration Register INITIALIZATION, clear or initialize the following registers (the initialized values are shown in Table 1):
Configuration Register
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Mask Register 1
Interrupt Mask Register 2
Fan Divisor/RST_OUT/OS Register
OS Configuration/Temperature Resolution Register
Value Ram (Registers at Address 20h - 3Fh, which include:
Temperature reading, IN0-IN6 readings, FAN1 and FAN2
readings, and WATCHDOG limits)
Configuration Register INITIALIZATION is accomplished by
setting Bit 7 of the Configuration Register high. This Bit automatically clears after being set.
The LM80 can be reset to it’s “power on state” by taking
NTEST_IN/Reset_IN pin low for at least 50 ns.
5.
6.
7.
8. IN6
9. Fan 1
10. Fan 2
3.5 Reading Conversion Results
The conversion results are available in the Value RAM. Conversions can be read at any time and will provide the result
of the last conversion. Because the ADC stops, and starts a
new conversion whenever the conversion is read, reads of
any single value should not be done more often than once
every 120 ms. When reading all values with the temperature
resolution set to 9-bits, allow at least 1.5 seconds between
reading groups of values. Reading more frequently than
once every 1.5 seconds can also prevent complete updates
of Interrupt Status Registers and Interrupt Outputs. If the
temperature resolution is set to 12-bit, allow at least 2.0 seconds between reading groups of values.
A typical sequence of events upon power on of the LM80
would consist of:
1. Set WATCHDOG Limits
2. Set Interrupt Masks
3. Start the LM80 monitoring process
3.3 Using the Configuration Register
The Configuration Register provides all control over the
LM80. At power on, the ADC is stopped and INT_Clear is asserted, clearing the INT and RST_OUT/OS hardwire outputs. The Configuration Register starts and stops the LM80,
enables and disables INT outputs, clears and sets CI and
GPO I/O pins, initiates reset pulse on RST_OUT/OS pin, and
provides the Reset function described in Section 3.2.
Bit 0 of the Configuration Register controls the monitoring
loop of the LM80. Setting Bit 0 low stops the LM80 monitoring loop and puts the LM80 in shutdown mode, reducing
power consumption. Serial Bus communication is possible
with any register in the LM80 although activity on these lines
will increase shutdown current, up to as much as maximum
rated supply current, while the activity takes place. Taking Bit
0 high starts the monitoring loop, described in more detail
subsequently.
Bit 1 of the Configuration Register enables the INT Interrupt
hardwire output when this bit is taken high.
Bit 2 of the Configuration Register defines whether the INT
pin is open source or open drain.
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IN3
IN4
IN5
4.0 ANALOG INPUTS
The 8-bit ADC has a 10 mV LSB, yielding a 0V to 2.55V
(2.56 - 1LSB) input range. This is true for all analog inputs. In
PC monitoring applications these inputs would most often be
connected to power supplies. The 2.5, 3.3, ± 5 and ± 12 volt
inputs should be attenuated with external resistors to any desired value within the input range. Care should be taken not
to exceed the power supply voltage (V+) at any time.
12
Functional Description
5.0 LAYOUT AND GROUNDING
Analog inputs will provide best accuracy when referred to the
AGND pin or a supply with low noise. A separate,
low-impedance ground plane for analog ground, which provides a ground point for the voltage dividers and analog
components, will provide best performance but is not mandatory. Analog components such as voltage dividers should
be located physically as close as possible to the LM80.
(Continued)
A typical application, such as is shown in Figure 6, might select the input voltage divider to provide 1.9V at the analog inputs of the LM80. This is sufficiently high for good resolution
of the voltage, yet leaves headroom for upward excursions
from the supply of about 25%. To simplify the process of resistor selection, set the value of R2 first. Select a value for
R2 or R4 between 10 kΩ and 100 kΩ This is low enough to
avoid errors due to input leakage currents yet high enough to
both protect the inputs under overdrive conditions as well as
minimize loading of the source. Then select R1 or R3 to provide a 1.9V input as show in Figure 6.
For positive input voltages the equation for calculating R1 is
as follows:
R1 = [ (VS − VIN) / VIN] R2
The power supply bypass, the parallel combination of 10 µF
(electrolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors connected between pin 9 and ground, should also
be located as close as possible to the LM80.
For negative input voltages the equation for Calculating R3
is as follows:
R3 = [ (VS − VIN) / (VIN − 5V)] R4
The analog inputs have internal diodes that clamp inputs exceeding the power supply and ground. Exceeding any analog input has no detrimental effect on other channels. The input diodes will also clamp voltages appearing at the inputs of
an un-powered LM80. External resistors should be included
to limit input currents to the values given in the ABSOLUTE
MAXIMUM RATINGS for Input Current At Any Pin. Inputs
with the attenuator networks will usually meet these requirements. If it is possible for inputs without attenuators to be
turned on while LM80 is powered off, additional resistors of
about 10 kΩ should be added in series with the inputs to limit
the input current.
Voltage
Measurements
(VS)
R1 or
R3
R2 or
R4
Voltage
at
Analog Inputs
( ADC code 190)
+2.5V
23.7 kΩ
75 kΩ
+1.9V
+3.3V
22.1 kΩ
30 kΩ
+1.9V
+5.0V
24 kΩ
14.7 kΩ
+1.9V
+12V
160 kΩ
30.1 kΩ
+1.9V
−12V
160 kΩ
35.7 kΩ
+1.9V
−5V
36 kΩ
16.2 kΩ
+1.9V
DS100040-11
FIGURE 6. Input Examples. Resistor values shown in
table provide approximately 1.9V at the analog inputs.
13
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Functional Description
The Fan Inputs gate an internal 22.5 kHz oscillator for one
period of the Fan signal into an 8-bit counter (maximum
count = 255). The default divisor, located in the VID/Fan Divisor Register, is set to 2 (choices are 1, 2, 4, and 8) providing a nominal count of 153 for a 4400 rpm fan with two
pulses per revolution. Typical practice is to consider 70% of
normal RPM a fan failure, at which point the count will be
219.
(Continued)
6.0 FAN INPUTS
Inputs are provided for signals from fans equipped with tachometer outputs. These are logic-level inputs with an approximate threshold of V+/2. Signal conditioning in the LM80
accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 to
V+. In the event these inputs are supplied from fan outputs
which exceed 0 to V+, either resistive division or diode
clamping must be included to keep inputs within an acceptable range, as shown in Figure 7. R2 is selected so that it
does not develop excessive error voltage due to input leakage. R1 is selected based on R2 to provide a minimum input
of 2V and a maximum of V+. R1 should be as low as possible
to provide the maximum possible input up to V+ for best
noise immunity. Alternatively, use a shunt reference or zener
diode to clamp the input level.
Determine the fan count according to:
Note that Fan 1 and Fan 2 Divisors are programmable via
the Fan Divisor/RST_OUT/OS Register.
FAN1 and FAN2 inputs can also be programmed to be level
sensitive digital inputs.
Fans that provide only one pulse per revolution would require a divisor set twice as high as fans that provide two
pulses, thus maintaining a nominal fan count of 153. Therefore the divisor should be set to 4 for a fan that provides 1
pulse per revolution with a nominal RPM of 4400.
If fans can be powered while the power to the LM80 is off,
the LM80 inputs will provide diode clamping. Limit input current to the Input Current at Any Pin specification shown in the
ABSOLUTE MAXIMUM RATINGS section. In most cases,
open collector outputs with pull-up resistors inherently limit
this current. If this maximum current could be exceeded, either a larger pull up resistor should be used or resistors connected in series with the fan inputs.
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14
Functional Description
(Continued)
DS100040-12
(a) Fan with Tach Pull-Up to +5V
DS100040-13
(b) Fan with Tach Pull-Up to +12V, or Totem-Pole
Output and Resistor Attenuator
DS100040-14
(c) Fan with Tach Pull-Up to +12V and Diode Clamp
DS100040-15
(d) Fan with Strong Tach Pull-Up or Totem Pole Output
and Diode Clamp
FIGURE 7. Alternatives for Fan Inputs
Counts are based on 2 pulses per revolution tachometer outputs.
RPM
Time per Revolution
Counts for “Divide by 2”
Comments
(Default) in Decimal
4400
13.64 ms
153 counts
Typical RPM
3080
19.48 ms
219 counts
70% RPM
2640
22.73 ms
255 counts
60% RPM
(maximum counts)
Time per Revolution
Nominal
RPM
Time per Revolution
Divide by 1
8800
6.82 ms
153
6160
9.74 ms
Divide by 2
4400
13.64 ms
153
3080
19.48 ms
Divide by 4
2200
27.27 ms
153
1540
38.96 ms
Divide by 8
1100
54.54 ms
153
770
77.92 ms
Mode Select
Counts for the
70%
RPM
Given Speed in Decimal
15
for 70% RPM
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Functional Description
7.1 Temperature Data Format
Temperature data can be read from the Temperature, Thot,
Thot hyst, Tos and Tos hyst setpoint registers; and written to the
Thot, Thot hyst, Tos and Tos hyst setpoint registers. Thot set
point, Thot hyst set point, Tos set point and Tos hyst temperature data is represented by an 8-bit, two’s complement word
with an LSB (Least Significant Bit) equal to 1˚C:
(Continued)
7.0 TEMPERATURE MEASUREMENT SYSTEM
The LM80 bandgap type temperature sensor and ADC perform 9-bit or a 12-bit two’s-complement conversions of the
temperature. An 8-bit digital comparator is also incorporated
that compares the readings to the user-programmable Hot
and Overtemperature setpoints, and Hysteresis values.
Temperature
DS100040-20
(Non-Linear Scale for Clarity)
FIGURE 8. 9-bit Temperature-to-Digital Transfer
Function
DS100040-16
(Non-Linear Scale for Clarity)
FIGURE 9. 12-bit Temperature-to-Digital Transfer
Function
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16
Digital Output
Binary
Hex
+125˚C
0111 1101
7Dh
+25˚C
0001 1001
19h
+1.0˚C
0000 0001
01h
+0˚C
0000 0000
00h
−1.0˚C
1111 1111
FFh
−25˚C
1110 0111
E7h
−55˚C
1100 1001
C9h
Functional Description
7.2 Temperature Interrupts
There are four Value RAM WATCHDOG limits for the Temperature reading that affect the INT and OS outputs of the
LM80. They are: Hot Temperature Limit, Hot Temperature
Hysteresis Limit, OS Limit, OS Hysteresis Limit. There are
three interrupt modes of operation: “One-Time Interrupt”
mode, “Default Interrupt” mode, and “Comparator Mode”.
The OS output of the LM80 can be programmed for
“One-Time Interrupt” mode and “Comparator” mode. INT can
be programmed for “Default Interrupt” mode and “One-Time”
Interrupt.
(Continued)
By default Temperature Register data is represented by a
9-bit two’s complement digital word with the LSB having a
resolution of 0.5˚C:
Temperature
Digital Output
Binary
Hex
+125˚C
0 1111 1010
0 FAh
+25˚C
0 0011 0010
0 32h
+1.5˚C
0 0000 0011
0 03h
+0˚C
0 0000 0000
0 00h
−0.5˚C
1 1111 1111
1 FFh
−25˚C
1 1100 1110
1 CEh
−55˚C
1 1001 0010
1 92h
“Default Interrupt mode” operates in the following way: Exceeding Thot causes an Interrupt that will remain active indefinitely until reset by reading Interrupt Status Register 1 or
cleared by the INT_Clear bit in the Configuration register.
Once an Interrupt event has occurred by crossing Thot, then
reset, an Interrupt will occur again once the next temperature
conversion has completed. The interrupts will continue to occur in this manner until the temperature goes below Thot hyst,
at which time the Interrupt output will automatically clear.
“One-Time Interrupt” mode operates in the following way:
Exceeding Thot causes an Interrupt that will remain active indefinitely until reset by reading Interrupt Status Register 1 or
cleared by the INT_Clear bit in the Configuration register.
Once an Interrupt event has occurred by crossing Thot, then
reset, an Interrupt will not occur again until the temperature
goes below Thot hyst.
“Comparator” mode operates in the following way: Exceeding Tos causes the OS output to go Low (default). OS
will remain Low until the temperature goes below Tos. Once
the temperature goes below Tos, OS will go High.
Temperature Register data can also be represented by a
12-bit two’s complement digital word with a LSB of 0.0625˚C:
Temperature
Digital Output
Binary
Hex
+125˚C
0111 1100 0000
7 D0h
+25˚C
0001 1001 0000
1 90h
+1.0˚C
0000 0001 0000
0 10h
+0.0625˚C
0000 0000 0001
0 01h
0˚C
0000 0000 0000
00h
−0.0625˚C
1111 1111 1111
F FFh
−1.0˚C
1111 1111 0000
F F0h
−25˚C
1110 0111 0000
E 70h
−55˚C
1100 1001 0000
C 90h
The 8 MSBs of the Temperature reading can be found at
Value RAM address 28 h. The remainder of the Temperature
reading can be found in the OS Configuration/Temperature
Resolution Register bits 7-4. In 9-bit format bit 7 is the only
valid bit.
17
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Temperature Interrupt Response Diagram. This diagram does not reflect all the possible variations in the operation of
the OS and INT outputs nor the OS and Hot Temp bits. The interrupt outputs are cleared by reading the appropriate
Interrupt Status Register.
DS100040-17
Functional Description
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(Continued)
18
Functional Description
(Continued)
8.0 THE LM80 INTERRUPT STRUCTURE
DS100040-18
FIGURE 10. Interrupt Structure
•
Figure 10 depicts the Interrupt Structure of the LM80. The
LM80 can generate Interrupts as a result of each of its internal WATCHDOG registers on the analog, temperature, and
fan inputs.
8.1 INTERRUPT INPUTS
External Interrupts can come from the following sources.
While the label suggests a specific type or source of Interrupt, this label is not a restriction of its usage, and it could
come from any desired source:
•
BTI - This is an active low Interrupt intended to come
from the O.S. output of LM75 temperature sensors. The
LM75 O.S. output goes active when its temperature exceeds a programmed threshold. Up to 8 LM75’s can be
connected to a single Serial Bus bus with their O.S. output’s wire or’d to the BTI input of the LM80. If the temperature of any LM75 exceeds its programmed limit, it
drives BTI low. This generates an Interrupt to notify the
host of a possible overtemperature condition. Provides
an internal pull-up of 10 kΩ.
19
CI (Chassis Intrusion) - This is an active high interrupt
from any type of device that detects and captures chassis
intrusion violations. This could be accomplished mechanically, optically, or electrically, and circuitry external
to the LM80 is expected to latch the event. The design of
the LM80 allows this input to go high even with no power
applied to the LM80, and no clamping or other interference with the line will occur. This line can also be pulled
low for at least 10 ms by the LM80 to reset a typical
Chassis Intrusion circuit. Accomplish this reset by setting
Bit 5 of Configuration Register high. The bit in the Register is self-clearing.
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Functional Description
9.0 RST and GPO OUTPUTS
(Continued)
In PC applications the open drain GPO provides a gate drive
signal to an external P-channel MOSFET power switch. This
external MOSFET then would keep power turned on regardless of the state of front panel power switches when software
power control is used. In any given application this signal is
not limited to the function described by its label. For example, since the LM80 incorporates temperature sensing,
the GPO output could also be utilized to control power to a
cooling fan. Take GPO active low by setting Bit 6 in the Configuration Register low.
RST is intended to provide a master reset to devices connected to this line. The RST_OUT/OS Control bit in Fan
Divisor/RST_OUT/OS Register, Bit 7, must be set high to enable this function. Setting Bit 4 in the Configuration Register
high outputs a least 10 ms low on this line, at the end of
which Bit 4 in the Configuration Register automatically
clears. Again, the label for this pin is only its suggested use.
In applications where the RST capability is not needed it can
be used for any type of digital control that requires a 10 ms
active low open drain output.
• INT_IN - This active low Interrupt merely provides a
way to chain the INT (Interrupt) from other devices
through the LM80 to the processor.
8.2 INTERRUPT OUTPUTS
All Interrupts are indicated in the two Interrupt Status Registers.
INT output has two mask registers, and individual masks for
each Interrupt. As described in Section 3.3, this hardware Interrupt line can also be enabled/disabled in the Configuration
Register. The Configuration Register is also used to set the
mode of the INT Interrupt line.
OS is dedicated to the Temperature reading WATCHDOG. In
the “Fan Divisor/RST_OUT/OS Register” the OS enable bit
(Bit-6), must be set high and the RST enable bit (Bit -7) must
be set low to enable the OS function on the RST_OUT/OS
pin. OS pin has two modes of operation: “One-Time Interrupt” and “Comparator”. “One-Time Interrupt” mode is selected by taking bit-2 of the “OS Configuration/Temperature
Resolution Register” high. If bit-2 is taken low “Comparator”
mode is selected. Unlike the OS pin, the OS bit in “Interrupt
Status Register 2” functions in “Default Interrupt” and
“One-Time Interrupt” modes. The OS bit can be masked to
INT pin by taking bit-5 in the “Interrupt Mask Register 2” low.
A description of “Comparator”, “Default Interrupt” and
“One-Time Interrupt” modes can be found in Section 7.1.
10.0 NAND TREE TESTS
A NAND tree is provided in the LM80 for Automated Test
Equipment (ATE) board level connectivity testing. If the user
applies a logic zero to the NTEST_IN/Reset_IN input pin, the
device will be in the NAND tree test mode. A0/NTEST_OUT
will become the NAND tree output pin. To perform a NAND
tree test all pins included in the NAND tree should be driven
to 1. Beginning with IN0 and working clockwise around the
chip, each pin can be toggled and a resulting toggle can be
observed on A0/NTEST_OUT. The following pins are excluded from the NAND tree test: GNDA (analog ground),
GND (digital ground), V + (power supply), A0/NTEST_OUT,
NTEST_IN/Reset_IN and RST_OUT/OS. Allow for a typical
propagation delay of 500 ns.
8.3 INTERRUPT CLEARING
Reading an Interrupt Status Register will output the contents
of the Register, and reset the Register. A subsequent read
done before the analog “round-robin” monitoring loop is
complete will indicate a cleared Register. Allow at least 1.5
seconds to allow all Registers to be updated between reads.
In summary, the Interrupt Status Register clears upon being
read, and requires at least 1.5 seconds to be updated. When
the Interrupt Status Register clears, the hardwire interrupt
line will also clear until the Registers are updated by the
monitoring loop. The hardware Interrupt lines are cleared
with the INT_Clear bit, which is Bit 3 of the Configuration
Register, without affecting the contents of the Interrupt (INT)
Status Registers. When this bit is high, the LM80 monitoring
loop will stop. It will resume when the bit is low.
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20
Functional Description
Sanyo Denki America, Inc.
(Continued)
468 Amapola Ave.
Torrance, CA 90501
310 783-5400
11.0 FAN MANUFACTURERS
Manufacturers of cooling fans with tachometer outputs are
listed below:
NMB Tech
Model Number
9730 Independence Ave.
Chatsworth, California 91311
818 341-3355
109P06XXY601
818 341-8207
109R06XXY401
Frame Size
Airflow
CFM
2408NL
2.36 in sq. X 0.79 in
9-16
2.36 in sq. X 0.79 in
11-15
2.36 in sq. X 0.98 in
13-28
(60 mm sq. X 25 mm)
109P08XXY601
3.15 in sq. X 0.79 in
23-30
(80 mm sq. X 20 mm)
109R08XXY401
(60 mm sq. X 20 mm)
2.36 in sq. X 0.98 in
Airflow
CFM
(60 mm sq. X 20 mm)
Model Number
2410ML
Frame Size
3.15 in sq. X 0.98 in
21-42
(80 mm sq. X 25 mm)
14-25
(60 mm sq. X 25 mm)
3108NL
3.15 in sq. X 0.79 in
25-42
(80 mm sq. X 20 mm)
3110KL
3.15 in sq. X 0.98 in
25-40
(80 mm sq. X 25 mm)
Mechatronics Inc.
P.O. Box 20
Mercer Island, WA 98040
800 453-45698
Various sizes available with tach output option.
21
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Functional Description
(Continued)
12.0 REGISTERS AND RAM
12.1 Address Register
The main register is the ADDRESS Register. The bit designations are as follows:
Bit
7-0
Name
Read/
Write
Address
Pointer
Bit 7
Description
Read/Write
Bit 6
Address of RAM and Registers. See the tables below for detail.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A2
A1
A0
Address Pointer (Power On default 00h)
A7
A6
A5
A4
A3
12.2 Address Pointer Index (A7–A0)
Registers and RAM
A6–A0 in
Hex
Power On Value of Registers:
< 7:0 > in Binary
Configuration Register
00h
0000 1000
Interrupt Status Register 1
01h
0000 0000
Interrupt Status Register 2
02h
0000 0000
Interrupt Mask Register 1
03h
0000 0000
Interrupt Mask Register 2
04h
0000 0000
Fan Divisor/RST_OUT/OS
05h
0001 0100
OS
Configuration/Temperature
Resolution Register
06h
0000 0001
Value RAM
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20h–3Fh
22
Functional Description
(Continued)
12.3 Configuration Register — Address 00h
Power on default < 7:0 > = 00001000 binary
Bit
0
Name
Start
Read/
Write
Description
Read/Write
A one enables startup of monitoring operations, a zero puts the part in standby mode.
Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this
location after an interrupt has occurred unlike “INT_Clear” bit.At start up, limit checking
functions and scanning begin. Note, all limits should be set in the Value RAM before
setting this bit HIGH.
1
INT Enable
Read/Write
A one enables the INT Interrupt output.
2
INT polarity
select
Read/Write
A one selects an active high open source output while a zero selects an active low
open drain output.
3
INT_Clear
Read/Write
4
RESET
Read/Write
A one disables the INT and RST_OUT/OS outputs without affecting the contents of
Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing
of this bit.
A one outputs at least a 10 ms active low reset signal at RESET, if < 7 > = 1 and
< 6 > = 0 in the Fan Divisor/RST_OUT/OS Register. This bit is cleared once the pulse
has gone inactive.
5
Chassis Clear
Read/Write
6
GPO
Read/Write
A one in this bit drives a one on GPO (General Purpose Output) pin.
7
INITIALIZATION
Read/Write
A one restores power on default value to the Configuration Register, Interrupt Status
Registers, Interrupt Mask Registers, Fan Divisor/RST_OUT/OSRegister, and the OS
Configuration/Temperature Resolution Register. This bit clears itself since the power
on default is zero.
A one clears the CI (Chassis Intrusion) pin. This bit clears itself after the CI pins
cleared.
23
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Functional Description
(Continued)
12.4 Interrupt Status Register 1 — Address 01h
Power on default < 7:0 > = 0000 0000 binary
Bit
Name
Read/Write
Description
0
IN0
Read Only
A one indicates a High or Low limit has been exceeded.
1
IN1
Read Only
A one indicates a High or Low limit has been exceeded.
2
IN2
Read Only
A one indicates a High or Low limit has been exceeded.
3
IN3
Read Only
A one indicates a High or Low limit has been exceeded.
4
IN4
Read Only
A one indicates a High or Low limit has been exceeded.
5
IN5
Read Only
A one indicates a High or Low limit has been exceeded.
6
IN6
Read Only
A one indicates a High or Low limit has been exceeded.
7
INT_IN
Read Only
A zero indicates that a Low has been detected on the INT_IN.
12.5 Interrupt Status Register 2 — Address 02h
Power on default < 7:0 > = 0000 0000 binary
Bit
Name
0
Hot Temperature
Read Only
Read/Write
A one indicates a High or Low limit has been exceeded. Only “One-Time Interrupt”
and “Default Interrupt” modes are supported. The mode is set by bit-6 of the
Interrupt Mask Register 2.
Description
1
BTI
Read Only
A one indicates that an interrupt has occurred from the Board Temperature
Interrupt (BTI) input pin. BTI can be tied to the OS output of multiple LM75 chips.
2
FAN1
Read Only
A one indicates that a fan count limit has been exceeded.
3
FAN2
Read Only
A one indicates that a fan count limit has been exceeded.
4
CI (Chassis
Intrusion)
Read Only
A one indicates CI (Chassis Intrusion) has gone high.
5
OS bit
Read Only
A one indicates a High or a Low OS Temperature limit has been exceed. Only
comparator mode is supported. Only “One-Time Interrupt” and “Default Interrupt”
modes are supported. The mode is set by bit-7 of the Interrupt Mask Register 2.
6
Reserved
Read Only
7
Reserved
Read Only
12.6 Interrupt Mask Register 1 — Address 03h
Power on default < 7:0 > = 0000 0000 binary
Bit
Name
Read/
Write
Description
0
IN0
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
1
IN1
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
2
IN2
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
3
IN3
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
4
IN4
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
5
IN5
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
6
IN6
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
7
INT_IN
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
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24
Functional Description
(Continued)
12.7 Interrupt Mask Register 2 — Address 44h
Power on default < 7:0 > = 0000 0000 binary
Bit
Name
Read/
Write
Description
0
Hot Temperature
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
1
BTI
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
2
FAN1
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
3
FAN2
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
4
CI (Chassis
Intrusion)
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
5
OS bit
Read/Write
A one disables the corresponding interrupt status bit for INT interrupt.
6
Hot Temperature
Interrupt mode
select
Read/Write
A zero selects the default interrupt mode which gives the user an interrupt if the temperature goes above the hot limit. The interrupt will be cleared once the status register
is read, but it will again be generated when the next conversion has completed. It will
continue to do so until the temperature goes below the hysteresis limit.
A one selects the one time interrupt mode which only gives the user one interrupt when
it goes above the hot limit. The interrupt will be cleared once the status register is read.
Another interrupt will not be generated until the temperature goes below the hysteresis
limit. It will also be cleared if the status register is read. No more interrupts will be generated until the temperature goes above the hot limit again. The corresponding bit will
be cleared in the status register every time it is read but may not set again when the
next conversion is done. (See in Section 7.0)
7
OS bit Interrupt
mode select
Read/Write
A zero selects the default interrupt mode which gives the user an interrupt if the temperature goes above the hot limit. The interrupt will be cleared once the status register
is read, but it will again be generated when the next conversion has completed. It will
continue to do so until the temperature goes below the hysteresis limit.
A one selects the one time interrupt mode which only gives the user one interrupt when
it goes above the hot limit. The interrupt will be cleared once the status register is read.
Another interrupt will not be generated until the temperature goes below the hysteresis
limit. It will also be cleared if the status register is read. No more interrupts will be generated until the temperature goes above the hot limit again. The corresponding bit will
be cleared in the status register every time it is read but may not set again when the
next conversion is done. (See Section in Section 7.0)
25
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Functional Description
(Continued)
12.8 Fan Divisor Register/RST_OUT/OS — Address 05h
Power on – < 7:4 > is 0101, and < 3:0 > is mapped to VID < 3:0 >
Bit
Name
Read/Write
Description
0
FAN1 Mode
Select
Read/Write
A one selects the level sensitive input mode while a zero selects Fan count mode
for the FAN1 input pin.
1
FAN2 Mode
Select
Read/Write
A one selects the level sensitive input mode while a zero selects Fan count mode
for the FAN2 input pin.
2-3
FAN1 RPM
Control
Read/Write
FAN1 Speed Control.
< 3:2 >
< 3:2 >
< 3:2 >
< 3:2 >
= 00 - divide by 1;
= 01 - divide by 2;
= 10 - divide by 4;
= 11 - divide by 8.
If level sensitive input is selected: > 2 < = 1 selects and active-low input (An interrupt
will be generated if the FAN2 input is Low), > 2 < = 0 selects an active-high input (an
interrupt will be generated if the FAN2 input is High).
4-5
FAN2 RPM
Control
Read/Write
FAN2 Speed Control.
< 5:4 >
< 5:4 >
< 5:4 >
< 5:4 >
= 00 - divide by 1;
= 01 - divide by 2;
= 10 - divide by 4;
= 11 - divide by 8.
If level sensitive input is selected: < 2 > = 1 selects and active-low input (An interrupt
will be generated if the FAN2 input is Low), < 2 > = 0 selects an active-high input (an
interrupt will be generated if the FAN2 input is High).
6
OS pin enable
Read/Write
A one enables OS mode on the RST_OUT/OS output pin, while Bit 7 of this register
is set to zero. If bits 6 and 7 of this register are set to zero the RST_OUT/OS pin is
disabled.
7
RST enable
Read/Write
A one sets the RST_OUT/OS pin in the RST mode. In the RST mode, bit 7 of the
Fan Divisor/RST_OUT/OS Register has to be set to one. If bits 6 and 7 of this
register are set to zero the RST_OUT/OS pin is disabled.
12.9 OS Configuration/Temperature Resolution Register — Address 06h
Power on default Serial Bus address < 7:0 > = 0000 0001 binary
Bit
Name
Read/Write
Description
0
OS status
Read only
Status of the OS.This bit mirrors the state of the RST_OUT/OS pin when in the OS
mode.
1
OS Polarity
Read/Write
A zero selects OS to be active-low, while a one selects OS to be active high. OS is
an open-drain output.
2
OS mode select
Read/Write
A one selects the one time interrupt mode for OS, while a zero selects comparator
mode for OS. (See in Section 7.0)
3
Temperature
Resolution
Control
Read/Write
Temp [3:0]
Read/Write
A zero selects the default 8-bit plus sign resolution temperature conversions while a
one selects 11-bit plus sign resolution temperature conversions. 8-bit plus sign
conversions time is approximately 100 ms, while 11-bit plus sign conversion time is
approximately 2 seconds.
The lower nibble (4 LSBs) of the 11-bit plus sign temperature data. < 4 > = Temp
[0] (nibble LSB, 0.0625˚C), < 5 > = Temp [1], < 6 > = Temp [2], < 7 > = Temp 3
(nibble MSB, 0.5˚C). For 8-bit plus sign temperature resolution, < 7 > = Temp [0]
(LSB, 0.5˚C) while < 4:6 > are undefined.
4-7
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26
Functional Description
(Continued)
12.10 Value RAM — Address 20h–3Fh
Address A7–A0
Description
20h
IN0 reading
21h
IN1 reading
22h
IN2 reading
23h
IN3 reading
24h
IN4 reading
25h
IN5 reading
26h
IN6 reading
27h
Temperature reading
28h
FAN1 reading
Note: This location stores the number of counts of the internal clock per revolution.
29h
FAN2 reading
Note: This location stores the number of counts of the internal clock per revolution.
2Ah
IN0 High Limit
2Bh
IN0 Low Limit
2Ch
IN1 High Limit
2Dh
IN1 Low Limit
2Eh
IN2 High Limit
2Fh
IN2 Low Limit
30h
IN3 High Limit
31h
IN3 Low Limit
32h
IN4 High Limit
33h
IN4 Low Limit
34h
IN5 High Limit
35h
IN5 Low Limit
36h
IN6 High Limit
37h
IN6 Low Limit
38h
Hot Temperature Limit (High)
39h
Hot Temperature Hysteresis Limit (Low)
3Ah
OS Temperature Limit (High)
3Bh
OS Temperature Hysteresis Limit (Low)
3Ch
FAN1 Fan Count Limit
3Dh
FAN2 Fan Count Limit
Note: It is the number of counts of the internal clock for the Low Limit of the fan speed.
Note: It is the number of counts of the internal clock for the Low Limit of the fan speed.
3Eh-3Fh
Reserved
Note: Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits.
For voltage input high limits, the device is doing a greater than comparison. For low limits, however, it is doing a less than or equal to comparison.
27
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Typical Application
DS100040-19
FIGURE 11. In this PC application the LM80 monitors temperature, fan speed for 2 fans, and 7 power
supply voltages. It also monitors an optical chassis intrusion detector.
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28
inches (millimeters) unless otherwise noted
24-Lead Molded Plastic TSSOP
Order Number LM80CIMT-3, LM80CIMTX-3, LM80CIMTX-5 or LM80CIMT-5
NS Package Number MTC24B
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LM80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
Physical Dimensions
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