NSC LMC6494AEM Cmos rail-to-rail input and output operational amplifier Datasheet

LMC6492 Dual/LMC6494 Quad
CMOS Rail-to-Rail Input and Output Operational
Amplifier
General Description
Features
The LMC6492/LMC6494 amplifiers were specifically developed for single supply applications that operate from −40˚C
to +125˚C. This feature is well-suited for automotive systems
because of the wide temperature range. A unique design topology enables the LMC6492/LMC6494 common-mode voltage range to accommodate input signals beyond the rails.
This eliminates non-linear output errors due to input signals
exceeding a traditionally limited common-mode voltage
range. The LMC6492/LMC6494 signal range has a high
CMRR of 82 dB for excellent accuracy in non-inverting circuit
configurations.
The LMC6492/LMC6494 rail-to-rail input is complemented
by rail-to-rail output swing. This assures maximum dynamic
signal range which is particularly important in 5V systems.
Ultra-low input current of 150 fA and 120 dB open loop gain
provide high accuracy and direct interfacing with high impedance sources.
(Typical unless otherwise noted)
n Rail-to-Rail input common-mode voltage range,
guaranteed over temperature
n Rail-to-Rail output swing within 20 mV of supply rail,
100 kΩ load
n Operates from 5V to 15V supply
n Excellent CMRR and PSRR 82 dB
n Ultra low input current 150 fA
n High voltage gain (RL = 100 kΩ) 120 dB
n Low supply current ( @ VS = 5V) 500 µA/Amplifier
n Low offset voltage drift 1.0 µV/˚C
Applications
n
n
n
n
n
Automotive transducer amplifier
Pressure sensor
Oxygen sensor
Temperature sensor
Speed sensor
Connection Diagrams
8-Pin DIP/SO
14-Pin DIP/SO
DS012049-1
Top View
DS012049-2
Top View
© 1999 National Semiconductor Corporation
DS012049
www.national.com
LMC6492 Dual/LMC6494 Quad CMOS Rail-to-Rail Input and Output Operational Amplifier
October 1994
Ordering Information
Package
8-Pin Small Outline
Temperature Range
Extended −40˚C to +125˚C
LMC6492AEM
Transport
Media
NSC
Drawing
Rails
M08A
LMC6492BEM
LMC6492AEMX
Tape and Reel
LMC6492BEMX
8-Pin Molded DIP
LMC6492AEN
Rails
N08A
Rails
M14A
LMC6492BEN
14-Pin Small Outline
LMC6494AEM
LMC6494BEM
LMC6494AEMX
Tape and Reel
LMC6494BEMX
14-Pin Molded DIP
LMC6494AEN
Rails
LMC6494BEN
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2
N14A
Absolute Maximum Ratings (Note 1)
Junction Temperature (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance (Note 2)
Differential Input Voltage
Voltage at Input/Output Pin
Supply Voltage (V+ − V−)
Current at Input Pin
Current at Output Pin (Note 3)
Current at Power Supply Pin
Lead Temp. (Soldering, 10 sec.)
Storage Temperature Range
150˚C
Operating Conditions (Note 1)
Supply Voltage
Junction Temperature Range
LMC6492AE, LMC6492BE
LMC6494AE, LMC6494BE
Thermal Resistance (θJA)
N Package, 8-Pin Molded DIP
M Package, 8-Pin Surface Mount
N Package, 14-Pin Molded DIP
M Package, 14-Pin Surface Mount
2000V
± Supply Voltage
(V+) + 0.3V, (V−) − 0.3V
16V
± 5 mA
± 30 mA
40 mA
260˚C
−65˚C to +150˚C
2.5V ≤ V+ ≤ 15.5V
−40˚C ≤ TJ ≤ +125˚C
−40˚C ≤ TJ ≤ +125˚C
108˚C/W
171˚C/W
78˚C/W
118˚C/W
DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ. Boldface limits apply at the temperature extremes
Symbol
VOS
TCVOS
Parameter
Conditions
Input Offset Voltage
LMC6492AE
LMC6492BE
Typ
LMC6494AE
LMC6494BE
(Note 5)
Limit
Limit
(Note 6)
(Note 6)
3.0
6.0
mV
3.8
6.8
max
0.11
Input Offset Voltage
1.0
Units
µV/˚C
Average Drift
IB
Input Bias Current
(Note 11)
0.15
200
200
pA max
IOS
Input Offset Current
(Note 11)
0.075
100
100
pA max
RIN
Input Resistance
CIN
Common-Mode
> 10
Tera Ω
3
pF
Input Capacitance
CMRR
Common-Mode
Rejection Ratio
+PSRR
0V ≤ VCM ≤ 5V
82
82
0V ≤ V− ≤ −10V,
VO = 2.5V
82
Input Common-Mode
V+ = 5V and 15V
V− −0.3
Voltage Range
For CMRR ≥ 50 dB
Negative Power Supply
Rejection Ratio
VCM
82
5V ≤ V+ ≤ 15V,
VO = 2.5V
Positive Power Supply
Rejection Ratio
−PSRR
0V ≤ VCM ≤ 15V
V+ = 15V
V+ + 0.3
65
63
60
58
65
63
60
58
65
63
dB
60
58
min
65
63
dB
60
58
min
−0.25
−0.25
V
0
0
max
V+ + 0.25
V+ + 0.25
V
V+
min
V
AV
Large Signal Voltage Gain
dB
min
+
RL = 2 kΩ:
Sourcing
300
V/mV
(Note 7)
Sinking
40
min
3
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DC Electrical Characteristics
(Continued)
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ. Boldface limits apply at the temperature extremes
Symbol
VO
Parameter
Output Swing
Conditions
V+ = 5V
RL = 2 kΩ to V+/2
LMC6492AE
LMC6492BE
Typ
LMC6494AE
LMC6494BE
(Note 5)
Limit
Limit
(Note 6)
(Note 6)
4.9
0.1
V+ = 5V
RL = 600Ω to V+/2
4.7
0.3
V+ = 15V
RL = 2 kΩ to V+/2
14.7
0.16
V+ = 15V
RL = 600Ω to V+/2
14.1
0.5
ISC
ISC
IS
Output Short Circuit Current
Sourcing, VO = 0V
25
4.8
4.8
V
4.7
4.7
min
0.18
0.18
V
0.24
0.24
max
4.5
4.5
V
4.24
4.24
min
0.5
0.5
V
0.65
0.65
max
14.4
14.4
V
14.0
14.0
min
0.35
0.35
V
0.5
0.5
max
13.4
13.4
V
13.0
13.0
min
1.0
1.0
V
1.5
1.5
max
16
16
10
10
11
V+ = 5V
Sinking, VO = 5V
22
11
8
8
Output Short Circuit Current
Sourcing, VO = 0V
30
28
28
20
20
V+ = 15V
Sinking, VO = 5V
(Note 8)
30
LMC6492
V+ = +5V, VO = V+/2
1.0
LMC6492
V+ = +15V, VO = V+/2
1.3
LMC6494
V+ = +5V, VO = V+/2
2.0
LMC6494
V+ = +15V, VO = V+/2
2.6
Supply Current
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4
Units
mA
min
30
30
22
22
1.75
1.75
mA
2.1
2.1
max
1.95
1.95
mA
2.3
2.3
max
3.5
3.5
mA
4.2
4.2
max
3.9
3.9
mA
4.6
4.6
max
AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ. Boldface limits apply at the temperature extremes
Symbol
SR
Parameter
Slew Rate
Conditions
(Note 9)
LMC6492AE
LMC6492BE
Typ
LMC6494AE
LMC6494BE
(Note 5)
Limit
Limit
(Note 6)
(Note 6)
1.3
V+ = 15V
0.7
0.7
0.5
0.5
Units
Vµs min
GBW
Gain-Bandwidth Product
1.5
MHz
φm
Phase Margin
50
Deg
Gm
Gain Margin
15
dB
150
dB
Amp-to-Amp Isolation
en
in
Input-Referred
(Note 10)
F = 1 kHz
Voltage Noise
VCM = 1V
Input-Referred
F = 1 kHz
0.06
F = 1 kHz, AV = −2
RL = 10 kΩ, VO = −4.1 VPP
F = 10 kHz, AV = −2
0.01
RL = 10 kΩ, VO = 8.5 VPP
V+ = 10V
0.01
37
Current Noise
T.H.D.
Total Harmonic
Distortion
%
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Human body model, 1.5 kΩ in series with 100 pF.
Note 3: Applies to both single-supply and split-supply operation. Continuous short operation at elevated ambient temperature can result in exceeding the maximum
allowed junction temperature at 150˚C. Output currents in excess of ± 30 mA over long term may adversely affect reliability.
Note 4: The maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max)
− TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Note 5: Typical Values represent the most likely parametric norm.
Note 6: All limits are guaranteed by testing or statistical analysis.
Note 7: V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 3.5V ≤ VO ≤ 7.5V.
Note 8: Do not short circuit output to V+, when V+ is greater than 13V or reliability will be adversely affected.
Note 9: V+ = 15V. Connected as voltage follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
Note 10: Input referred, V+ = 15V and RL = 100 kΩ connected to 7.5V. Each amp excited in turn with 1 kHz to produce VO = 12 VPP.
Note 11: Guaranteed limits are dictated by tester limits and not device performance. Actual performance is reflected in the typical value.
Typical Performance Characteristics
VS = +15V, Single Supply, TA = 25˚C unless otherwise
specified
Supply Current vs
Supply Voltage
Input Current vs
Temperature
Sourcing Current vs
Output Voltage
DS012049-25
DS012049-26
5
DS012049-27
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Typical Performance Characteristics
VS = +15V, Single Supply, TA = 25˚C unless otherwise
specified (Continued)
Sourcing Current vs
Output Voltage
Sourcing Current vs
Output Voltage
DS012049-28
Sinking Current vs
Output Voltage
Sinking Current vs
Output Voltage
Input Voltage Noise
vs Frequency
DS012049-30
DS012049-29
DS012049-31
Output Voltage Swing vs
Supply Voltage
DS012049-32
Input Voltage Noise
vs Input Voltage
DS012049-34
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Sinking Current vs
Output Voltage
Input Voltage Noise
vs Input Voltage
DS012049-35
6
DS012049-33
DS012049-36
Typical Performance Characteristics
VS = +15V, Single Supply, TA = 25˚C unless otherwise
specified (Continued)
Input Voltage Noise
vs Input Voltage
Crosstalk Rejection
vs Frequency
DS012049-37
Positive PSRR
vs Frequency
Crosstalk Rejection
vs Frequency
DS012049-38
Negative PSRR
vs Frequency
CMRR vs
Frequency
DS012049-40
CMRR vs
Input Voltage
DS012049-39
DS012049-41
CMRR vs
Input Voltage
DS012049-42
CMRR vs
Input Voltage
DS012049-43
DS012049-44
7
DS012049-45
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Typical Performance Characteristics
VS = +15V, Single Supply, TA = 25˚C unless otherwise
specified (Continued)
∆VOS
vs CMR
∆VOS
vs CMR
Input Voltage vs
Output Voltage
DS012049-46
Input Voltage vs
Output Voltage
Open Loop
Frequency Response
DS012049-49
Open Loop Frequency
Response vs Temperature
Open Loop
Frequency Response
DS012049-50
Maximum Output Swing
vs Frequency
8
DS012049-51
Gain and Phase vs
Capacitive Load
DS012049-53
DS012049-52
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DS012049-48
DS012049-47
DS012049-54
Typical Performance Characteristics
VS = +15V, Single Supply, TA = 25˚C unless otherwise
specified (Continued)
Gain and Phase vs
Capacitive Load
Open Loop Output
Impedance vs Frequency
DS012049-55
Slew Rate vs
Supply Voltage
Open Loop Output
Impedance vs Frequency
DS012049-56
Non-Inverting Large
Signal Pulse Response
Non-Inverting Large
Signal Pulse Response
DS012049-59
DS012049-58
Non-Inverting Large
Signal Pulse Response
DS012049-57
Non-Inverting Small
Signal Pulse Response
DS012049-61
Non-Inverting Small
Signal Pulse Response
DS012049-62
9
DS012049-60
DS012049-63
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Typical Performance Characteristics
VS = +15V, Single Supply, TA = 25˚C unless otherwise
specified (Continued)
Non-Inverting Small
Signal Pulse Response
Inverting Large
Signal Pulse Response
DS012049-64
Inverting Large Signal
Pulse Response
Inverting Large Signal
Pulse Response
DS012049-65
Inverting Small Signal
Pulse Response
DS012049-67
Inverting Small Signal
Pulse Response
DS012049-66
Inverting Small Signal
Pulse Response
DS012049-68
Stability vs
Capacitive Load
DS012049-69
Stability vs
Capacitive Load
DS012049-70
DS012049-71
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DS012049-72
Typical Performance Characteristics
VS = +15V, Single Supply, TA = 25˚C unless otherwise
specified (Continued)
Stability vs
Capacitive Load
Stability vs
Capacitive Load
Stability vs
Capacitive Load
DS012049-73
DS012049-74
DS012049-75
Stability vs
Capacitive Load
DS012049-76
ceeding this absolute maximum rating, as in Figure 2, can
cause excessive current to flow in or out of the input pins
possibly affecting reliability.
Application Notes
Input Common-Mode Voltage Range
Unlike Bi-FET amplifier designs, the LMC6492/4 does not
exhibit phase inversion when an input voltage exceeds the
negative supply voltage. Figure 1 shows an input voltage exceeding both supplies with no resulting phase inversion on
the output.
DS012049-9
FIGURE 2. A ± 7.5V Input Signal Greatly
Exceeds the 5V Supply in Figure 3 Causing
No Phase Inversion Due to RI
Applications that exceed this rating must externally limit the
maximum input current to ± 5 mA with an input resistor (RI)
as shown in Figure 3.
DS012049-8
FIGURE 1. An Input Voltage Signal Exceeds the
LMC6492/4 Power Supply Voltages with
No Output Phase Inversion
The absolute maximum input voltage is 300 mV beyond either supply rail at room temperature. Voltages greatly ex11
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Application Notes
Capacitive Load Tolerance
All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor is
normally included in this integrator stage. The frequency location of the dominant pole is affected by the resistive load
on the amplifier. Capacitive load driving capability can be optimized by using an appropriate resistive load in parallel with
the capacitive load (see Typical Curves).
Direct capacitive loading will reduce the phase margin of
many op-amps. A pole in the feedback loop is created by the
combination of the op-amp’s output impedance and the capacitive load. This pole induces phase lag at the unity-gain
crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 5.
(Continued)
DS012049-10
FIGURE 3. RI Input Current Protection for
Voltages Exceeding the Supply Voltages
Rail-To-Rail Output
The approximate output resistance of the LMC6492/4 is
110Ω sourcing and 80Ω sinking at Vs = 5V. Using the calculated output resistance, maximum output voltage swing can
be esitmated as a function of load.
Compensating for Input Capacitance
It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the
LMC6492/4.
Although the LMC6492/4 is highly stable over a wide range
of operating conditions, certain precautions must be met to
achieve the desired pulse response when a large feedback
resistor is used. Large feedback resistors with even small
values of input capacitance, due to transducers, photodiodes, and circuit board parasitics, reduce phase margins.
When high input impedances are demanded, guarding of the
LMC6492/4 is suggested. Guarding input lines will not only
reduce leakage, but lowers stray input capacitance as well.
(See Printed-Circuit-Board Layout for High Impedance
Work).
The effect of input capacitance can be compensated for by
adding a capacitor, Cf, around the feedback resistors (as in
Figure 1 ) such that:
DS012049-12
FIGURE 5. LMC6492/4 Noninverting Amplifier,
Compensated to Handle Capacitive Loads
Printed-Circuit-Board Layout
for High-Impedance Work
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LMC6492/4, typically
150 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite
simple. First, the user must not ignore the surface leakage of
the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust
or contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC6492/4’s inputs and
the terminals of components connected to the op-amp’s inputs, as in Figure 6. To have a significant effect, guard rings
should be placed on both the top and bottom of the PC
board. This PC foil must then be connected to a voltage
which is at the same voltage as the amplifier inputs, since no
leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of
1012Ω, which is normally considered a very large resistance,
could leak 5 pA if the trace were a 5V bus adjacent to the pad
of the input.
or
R1 CIN ≤ R2 Cf
Since it is often difficult to know the exact value of CIN, Cf can
be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 and LMC662 for a
more detailed discussion on compensating for input
capacitance.
This would cause a 33 times degradation from the
LMC6492/4’s actual performance. If a guard ring is used and
held within 5 mV of the inputs, then the same resistance of
1011Ω will only cause 0.05 pA of leakage current. See Figure
7 for typical connections of guard rings for standard op-amp
configurations.
DS012049-11
FIGURE 4. Cancelling the Effect of Input Capacitance
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12
Application Notes
(Continued)
DS012049-13
FIGURE 6. Examples of Guard
Ring in PC Board Layout
DS012049-17
DS012049-14
(Input pins are lifted out of PC board and soldered directly to components.
All other pins connected to PC board).
Inverting Amplifier
FIGURE 8. Air Wiring
Application Circuits
DC Summing Amplifier (VIN ≥ 0VDC and VO ≥ VDC
DS012049-15
Non-Inverting Amplifier
DS012049-16
Follower
FIGURE 7. Typical Connections of Guard Rings
DS012049-18
The designer should be aware that when it is inappropriate
to lay out a PC board for the sake of just a few circuits, there
is another technique which is even better than a guard ring
on a PC board: Don’t insert the amplifier’s input pin into the
board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may
have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the
effort of using point-to-point up-in-the-air wiring. See Figure
8.
Where: V0 = V1 + V2 − V3 –
(V1 + V2 ≥ (V3 + V4) to keep
13
V4
V0 > 0VDC
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Application Circuits
(Continued)
Rail-to-Rail Single Supply Low Pass Filter
High Input Z, DC Differential Amplifier
DS012049-22
DS012049-19
This low-pass filter circuit can be used as an anti-aliasing filter with the same supply as the A/D converter. Filter designs
can also take advantage of the LMC6492/4 ultra-low input
current. The ultra-low input current yields negligible offset error even when large value resistors are used. This in turn allows the use of smaller valued capacitors which take less
board space and cost less.
For
(CMRR depends on this resistor ratio match)
As shown: VO = 2(V2 − V1)
Low Voltage Peak Detector with Rail-to-Rail Peak
Capture Range
Photo Voltaic-Cell Amplifier
DS012049-23
Dielectric absorption and leakage is minimized by using a
polystyrene or polypropylene hold capacitor. The droop rate
is primarily determined by the value of CH and diode leakage
current. Select low-leakage current diodes to minimize
drooping.
DS012049-20
Pressure Sensor
Instrumentation Amplifier
DS012049-24
Rf = Rx
Rf >> R1, R2, R3, and R4
DS012049-21
If R1 = R5, R3 = R6, and R4 = R7; then
In a manifold absolute pressure sensor application, a strain
gauge is mounted on the intake manifold in the engine unit.
Manifold pressure causes the sensing resistors, R1, R2, R3
∴AV ≈ 100 for circuit shown (R2 = 9.3k).
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14
Application Circuits
• Input common-model voltage range
• Frequency and transient response
• GBW dependence on loading conditions
• Quiescent and dynamic supply current
• Output swing dependence on loading conditions
and many other characteristics as listed on the macromodel
disk.
Contact your local National Semiconductor sales office to
obtain an operational amplifier spice model library disk.
(Continued)
and R4 to change. The resistors change in a way such that
R2 and R4 increase by the same amount R1 and R3 decrease. This causes a differential voltage between the input
of the amplifier. The gain of the amplifier is adjusted by Rf.
Spice Macromodel
A spice macromodel is available for the LMC6492/4. This
model includes accurate simulation of:
15
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Physical Dimensions
inches (millimeters) unless otherwise noted
8-Pin Small Outline Package
Order Number LMC6492AEM or LMC6492BEM
NS Package Number M08A
14-Pin Small Outline Package
Order Number LMC6494AEM or LMC6494BEM
NS Package Number M14A
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16
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
8-Lead (0.300" Wide) Molded Dual-In-Line Package
Order Number LMC6492AEN or LMC6492BEN
NS Package Number N08A
14-Lead Molded Dual-In-Line Package
Order Number LMC6494AEN or LMC6494BEN
NS Package Number N14A
17
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LMC6492 Dual/LMC6494 Quad CMOS Rail-to-Rail Input and Output Operational Amplifier
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