NSC LMS1487 5v low power rs-485 / rs-422 differential bus transceiver Datasheet

LMS1487
5V Low Power RS-485 / RS-422 Differential Bus
Transceiver
General Description
Features
The LMS1487 is a low power differential bus/line transceiver
designed for high speed bidirectional data communication on
multipoint bus transmission lines. It is designed for balanced
transmission lines. It meets ANSI Standards TIA/EIA
RS422-B, TIA/EIA RS485-A and ITU recommendation and
V.11 and X.27. The LMS1487 combines a TRI-STATE™
differential line driver and differential input receiver, both of
which operate from a single 5.0V power supply. The driver
and receiver have an active high and active low, respectively, that can be externally connected to function as a
direction control. The driver and receiver differential inputs
are internally connected to form differential input/output (I/O)
bus ports that are designed to offer minimum loading to bus
whenever the driver is disabled or when VCC = 0V. These
ports feature wide positive and negative common mode
voltage ranges, making the device suitable for multipoint
applications in noisy environments. The LMS1487 is available in a 8-Pin SOIC and 8-pin DIP packages. It is a drop-in
socket replacement to Maxim’s MAX1487
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Meet ANSI standard RS-485-A and RS-422-B
Data rate 2.5 Mbps
Single supply voltage operation, 5V
Wide input and output voltage range
Thermal shutdown protection
Short circuit protection
Low quiescent current 320µA
Allows up to 128 transceivers on the bus
Open circuit fail-safe for receiver
Extended operating temperature range −40˚C to 85˚C
Drop-in replacement to MAX1487
Available in 8-pin SOIC and 8-pin DIP package
Applications
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Low power RS-485 systems
Network hubs, bridges, and routers
Point of sales equipment (ATM, barcode scanners,…)
Local area networks (LAN)
Integrated service digital network (ISDN)
Industrial programmable logic controllers
High speed parallel and serial applications
Multipoint applications with noisy environment
Typical Application
20053001
A Typical multipoint application is shown in the above figure. Terminating resistors, RT, are typically required but only located at the two ends of the cable.
Pull up and pull down resistors maybe required at the end of the bus to provide fail-safe biasing. The biasing resistors provide a bias to the cable when all
drivers are in TRI-STATE, See National Application Note, AN-847 for further information.
© 2003 National Semiconductor Corporation
DS200530
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LMS1487 5V Low Power RS-485 / RS-422 Differential Bus Transceiver
April 2003
LMS1487
Connection Diagram
8-Pin SOIC / DIP
20053002
Top View
Truth Table
DRIVER SECTION
RE
DE
DI
A
X
H
H
H
L
X
H
L
L
H
X
L
X
Z
Z
B
RECEIVER SECTION
RE
DE
A-B
RO
L
L
≥ +0.2V
H
L
L
≤ −0.2V
L
H
X
X
Z
L
L
OPEN *
H
Note: * = Non Terminated, Open Input only
X = Irrelevant
Z = TRI-STATE
H = High level
L = Low level
Pin Descriptions
Pin # I/O
Name
Function
1
O
RO
Receiver Output: If A > B by 200 mV, RO will be high; If A < B by 200mV, RO will be low. RO
will be high also if the inputs (A and B) are open (non-terminated
2
I
RE
Receiver Output Enable: RO is enabled when RE is low; RO is in TRI-STATE when RE is high
3
I
DE
Driver Output Enable: The driver outputs (A and B) are enabled when DE is high; they are in
TRI-STATE when DE is low. Pins A and B also function as the receiver input pins (see below)
4
I
DI
Driver Input: A low on DI forces A low and B high while a high on DI forces A high and B low
when the driver is enabled
5
N/A
GND
Ground
6
I/O
A
Non-inverting Driver Output and Receiver Input pin. Driver Output levels conform to RS-485
signaling levels
7
I/O
B
Inverting Driver Output and Receiver Input pin. Driver Output levels conform to RS-485 signaling
levels
8
N/A
VCC
Power Supply: 4.75V ≤ VCC ≤ 5.25V
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Package
Part Number
LMS1487CM
8-Pin SOIC
LMS1487CMX
LMS1487IM
LMS1487IMX
8-Pin DIP
Package Marking
LMS1487CM
LMS1487IM
Transport Media
95 Units/Rail
2.5k Units Tape and Reel
95 Units/Rail
M08A
2.5k Units Tape and Reel
LMS1487CNA
LMS1487CNA
40 Units/Rail
LMS1487INA
LMS1487INA
40 Units/Rail
3
NSC Drawing
N08E
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LMS1487
Ordering Information
LMS1487
Absolute Maximum Ratings
ESD Rating (Note 4)
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, VCC (Note 2)
Input Voltage, VIN (DI, DE, or RE)
Operating Ratings
Min Nom Max
7V
Supply Voltage, VCC
−0.3V to VCC + 0.3V
Voltage Range at Any Bus Terminal
(AB)
Receiver Outputs
7kV
Voltage at any Bus Terminal
(Separately or Common Mode)
−7V to 12V
125˚C/W
88˚C/W
Junction Temperature (Note 3)
150˚C
Operating Free-Air Temperature
Range, TA
Commercial
0.8
V
Differential Input Voltage, VID
(Note 6)
± 12
V
Driver, IOH
Lead Temperature
260˚C
−42
mA
Driver, IOL
80
mA
Receiver, IOL
26
mA
Low-Level Output
Soldering Information
235˚C
−150 mA
Receiver, IOH
−65˚C to 150˚C
Infrared or Convection (20 sec.)
V
Low-Level Input Voltage, VIL
(Note 5)
−40˚C to 85˚C
Storage Temperature Range
V
V
High-Level Output
0˚C to 70˚C
Industrial
12
2
High-Level Input Voltage, VIH
(Note 5)
Package Thermal Impedance, θJA
DIP
5.0 5.25
−7
VIN or VIC
−0.3V to VCC + 0.3V
SOIC
4.75
Electrical Characteristics
Over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
5.25
V
Driver Section
| VOD1 |
Differential Output Voltage
R = ∞ (Figure 1)
| VOD2 |
Differential Output Voltage
R = 50Ω (Figure 1) ,RS-422
2.0
R = 27Ω (Figure 1) ,RS-485
1.5
V
5.0
∆VOD
Change in Magnitude of
Driver Differential Output
Voltage for Complementary
Output States
R = 27Ω or 50Ω (Figure 1) , (Note 7)
0.2
VOC
Common-Mode Output
Voltage
R = 27Ω or 50Ω (Figure 1)
3.0
∆VOC
Change in Magnitude of
R = 27Ω or 50Ω (Figure 1), (Note 7)
Driver Common-Mode Output
Voltage for Complementary
Output States
VIH
CMOS Inout Logic Threshold
High
DE, DI, RE
VIL
CMOS Input Logic Threshold
Low
DE, DI, RE
0.8
IIN1
Logic Input Current
DE, DI, RE
±2
µA
0.25
mA
0.2
2.0
V
V
V
V
V
Receiver Section
IIN2
Input Current (A, B)
VTH
Differential Input Threshold
Voltage
−7V ≤ VCM ≤ + 12V
Input Hysteresis Voltage
(VTH+ − VTH−)
VCM = 0
DE = 0V, VCC = 0V or 5.25V
VIN = 12V
VIN = − 7V
∆VTH
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−0.2
−0.2
+0.2
V
95
4
mV
(Continued)
Over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
VOH
CMOS High-level Output
Voltage
IOH = −4mA, VID = 200mV
VOL
CMOS Low-level
IOL = 4mA, VID = −200mV
IOZR
Tristate Output Leakage
Current
0.4V ≤ VO ≤ + 2.4V
RIN
Input Resistance
− 7V ≤ VCM≤+12V
Min
Typ
Max
3.5
Units
V
0.40
V
±1
µA
48
kΩ
Power Supply Current
ICC
Supply Current
IOSD1
Driver Short-circuit Output
Current
VO = high, −7V ≤ VCM ≤ + 12V
(Note 8)
35
250
mA
IOSD2
Driver Short-circuit Output
Current
VO = low, − 7V ≤VCM ≤ + 12V
(Note 8)
35
250
mA
IOSR
Receiver Short-circuit Output
Current
0 V ≤VO ≤ VCC
7
95
mA
10
35
60
nS
5
10
nS
8
40
nS
DE = VCC, RE = GND or VCC
DE = 0V, RE = GND or VCC
320
500
315
400
µA
Switching Characteristics
Driver
TPLH,
TPHL
Propagation Delay Input to
Output
RL = 54Ω, CL = 100pF
(Figure 3, Figure 7)
TSKEW
Driver Output Skew
RL = 54Ω, CL = 100 pF
(Figure 3, Figure 7)
TR,
TF
Driver Rise and Fall Time
RL = 54Ω, CL = 100 pF
(Figure 3, Figure 7)
TZH,
TZL
Driver Enable to Ouput Valid
Time
CL = 100 pF, RL = 500Ω
(Figure 4, Figure 8)
25
70
nS
THZ,
TLZ
Driver Output Disable Time
CL = 15 pF, RL = 500Ω (Figure 4,
Figure 8)
30
70
nS
TPLH,
TPHL
Propagation Delay Input to
Output
RL = 54Ω, CL = 100 pF
(Figure 5, Figure 7)
50
200
nS
TSKEW
Receiver Output Skew
RL = 54Ω, CL = 100 pF
(Figure 5, Figure 7)
5
TZH,
TZL
Receiver Enable Time
CL = 15 pF, RL = 1 kΩ
(Figure 6, Figure 10)
20
50
20
50
FMAX
Maximum Data Rate
3
Receiver
20
Receiver Disable Time
2.5
nS
nS
nS
Mbps
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics
Note 2: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
Note 3: The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD =
(TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Note 4: ESD rating based upon human body model, 100pF discharged through 1.5kΩ.
Note 5: Voltage limits apply to DI, DE, RE pins.
Note 6: Differential input/output bus voltage is measured at the non-inverting terminal A with respect to the inverting terminal B.
Note 7: |∆VOD| and |∆VOC| are changes in magnitude of VOD and VOC, respectively when the input changes from high to low levels.
Note 8: Peak current
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LMS1487
Electrical Characteristics
LMS1487
Typical Performance Characteristics
Output Current vs. Receiver Output Low Voltage
Output Current vs. Receiver Output High Voltage
20053014
20053013
Receiver Output High Voltage vs. Temperature
Receiver Output Low-Voltage vs. Temperature
20053016
20053015
Driver Output Current vs. Differential Output Voltage
Driver Differential Output Voltage vs. Temperature
20053018
20053017
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(Continued)
Output Current vs. Driver Output Low Voltage
Output Current vs. Driver Output High Voltage
20053019
20053020
Supply Current vs. Temperature
20053021
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LMS1487
Typical Performance Characteristics
LMS1487
Parameter Measuring Information
20053003
FIGURE 1. Test Circuit for VOD and VOC
20053004
FIGURE 2. Test Circuit for VOD3
20053005
FIGURE 3. Test Circuit for Driver Propagation Delay
20053006
FIGURE 4. Test Circuit for Driver Enable / Disable
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LMS1487
Parameter Measuring Information
(Continued)
20053007
FIGURE 5. Test Circuit for Receiver Propagation Delay
20053008
FIGURE 6. Test Circuit for Receiver Enable / Disable
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LMS1487
Switching Characteristics
20053011
20053009
FIGURE 9. Receiver Propagation Delay
FIGURE 7. Driver Propagation Delay, Rise / Fall Time
20053012
20053010
FIGURE 10. Receiver Enable / Disable Time
FIGURE 8. Driver Enable / Disable Time
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POWER LINE NOISE FILTERING
A factor to consider in designing power and ground is noise
filtering. A noise filtering circuit is designed to prevent noise
generated by the integrated circuit (IC) as well as noise
entering the IC from other devices. A common filtering
method is to place by-pass capacitors (Cbp) between the
power and ground lines.
Placing a by-pass capacitor (Cbp) with the correct value at
the proper location solves many power supply noise problems. Choosing the correct capacitor value is based upon
the desired noise filtering range. Since capacitors are not
20053022
FIGURE 11. Placement of by-pass Capacitors, Cbp
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LMS1487
ideal, they may act more like inductors or resistors over a
specific frequency range. Thus, many times two by-pass
capacitors may be used to filter a wider bandwidth of noise.
It is highly recommended to place a larger capacitor, such as
10µF, between the power supply pin and ground to filter out
low frequencies and a 0.1µF to filter out high frequencies.
By-pass capacitors must be mounted as close as possible to
the IC to be effective. Longs leads produce higher impedance at higher frequencies due to stray inductance. Thus,
this will reduce the by-pass capacitor’s effectiveness. Surface mounted chip capacitors are the best solution because
they have lower inductance.
Application Information
LMS1487
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Pin SOIC
NS Package Number M08A
8-Pin DIP
NS Package Number N08E
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LMS1487 5V Low Power RS-485 / RS-422 Differential Bus Transceiver
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
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whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
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Support Center
Email: [email protected]
Tel: 1-800-272-9959
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