MICROSS LS320_TO-92

LS320
BiFET Amplifier
Linear Systems High Input Impedance BiFET Amplifier
The LS320 is a high input impedance amplifier
produced using a BiFET process and packaged in
TO-92.
The TO-92 package is well suited for cost sensitive
applications and mass production.
(See Packaging Information).
LS320 Features:
ƒ
ƒ
High Input Impedance
High Transconductance
FEATURES HIGH INPUT IMPEDANCE rGs ≥ = 100GΩ HIGH TRANSCONDUCTANCE YFS = 30,000µS ABSOLUTE MAXIMUM RATINGS 1@ 25°C (unless otherwise noted) Maximum Temperatures Storage Temperature Operating Junction Temperature Maximum Power Dissipation Continuous Power Dissipation @ +125°C Maximum Currents Drain Current Maximum Voltages Drain to Source Gate to Source ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL CHARACTERISTICS MIN. VDS Drain to Source Voltage ‐20 VGS Collector to Source Voltage ‐12 gfs Common Source Forward 30000 Transconductance goss Common Source Output Conductance ‐‐ rGs Gate to Source Input Resistance 100 CISS Input Capacitance ‐‐ CRSS Reverse Transfer Capacitance ‐‐ en Noise Voltage ‐‐ TYP. ‐‐ ‐10 ‐‐ MAX. ‐‐ ‐7 ‐‐ UNITS V V µS 300 ‐‐ 8 1.5 25 ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ GΩ pA pF µV ‐65°C to +150°C ‐55°C to +125°C 200mW 2.3mW/°C ID = 25mA VDSO = 20V VGSS = 20V CONDITIONS IDS = 100µA, VGS = 0 IDS = 10mA, VGS = ‐10V23 IDS = 10mA, VGS = ‐10V, f =1kHz VGS = 0 to 20V, TJ to 125°C IDS = 100µA, VDS = ‐10V IDS = 10mA, VGS = ‐10V IDS = 10mA, VDS = 10V, BW = 50 to 15 kHz Click To Buy
Notes: 1. Absolute Maximum ratings are limiting values above which serviceability may be impaired
2. The gate to source voltage must never exceed 100V, t < 10ms 3. Additional screening available Micross Components Europe
Available Packages:
Functional Schematic
TO-92 (Bottom View)
LS320 in TO-92
LS320 in bare die.
Tel: +44 1603 788967
Email: [email protected]
Web: http://www.micross.com/distribution
Please contact Micross for full
package and die dimensions
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other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.