LSI LS7184 Quadrature clock converter Datasheet

LSI/CSI
UL
®
LS7183/LS7184
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
(631) 271-0400 FAX (631) 271-0405
A3800
August 2001
QUADRATURE CLOCK CONVERTER
1
V DD(+V)
2
VSS(-V)
3
A
4
1
V DD(+V)
2
VSS(-V)
3
A
4
LS7184
RBIAS
LS7183
INPUT/OUTPUT DESCRIPTION:
RBIAS (Pin 1)
Input for external component connection. A resistor connected
between this input and VSS adjusts the output clock pulse
width (Tow).
RBIAS
LSI
DESCRIPTION:
The LS7183 and LS7184 are monolithic CMOS silicon gate
quadrature clock converters. Quadrature clocks derived from
optical or magnetic encoders, when applied to the A and B
inputs of the LS7183/LS7184, are converted to strings of Up
Clocks and Down Clocks (LS7183) or to a Clock and an Up/
Down direction control (LS7184). These outputs can be interfaced directly with standard Up/Down counters for direction and position sensing of the encoder.
PIN ASSIGNMENT - TOP VIEW
LSI
FEATURES:
• x1, x2 and x4 resolution
• Programmable output pulse width (200ns to 140µs)
• Excellent regulation of output pulse width
• TTL and low voltage CMOS compatible I/Os
• +3V to +5.5V operation (VDD-VSS)
• LS7183, LS7184 (DIP)
LS7183-S, LS7184-S (SOIC) - See Figure 1
8
UPCK
7
DNCK
6
MODE
5
B
8
CLK
7
UP/DN
6
MODE
5
B
FIGURE 1
VDD (Pin 2)
Supply Voltage positive terminal.
VSS (Pin 3)
Supply Voltage negative terminal.
A, B (Pin 4, Pin 5)
Quadrature Clock inputs A and B. Directional output pulses are
generated from the A and B clocks according to Fig. 2. A and B
inputs have built-in immunity for noise signals less than 50ns
duration (Validation delay, TVD). The A and B inputs are inhibited during the occurrence of a directional output clock
(UPCK or DNCK), so that spurious clocks resulting from encoder dither are rejected.
MODE (Pin 6)
MODE is a 3-state input to select resolution x1, x2 or x4. The
input quadrature clock rate is multiplied by factors of 1, 2 and 4
in x1, x2 and x4 mode respectively in producing the output
UP/DN clocks (See Fig. 2). x1, x2 and x4 modes selected by
the MODE input logic levels are as follows:
Mode = 0
: x1 selected
Mode = 1
: x2 selected
Mode = Float : x4 selected
7183/84-071201-1
LS7183 - DNCK (Pin 7)
In LS7183, this is the DOWN Clock Output. This output
consists of low-going pulses generated when A input
lags the B input.
LS7184LV - UP/DN (Pin 7)
In LS7184, this is the count direction indication output.
When A input leads the B input, the UP/DN output goes
high indicating that the count direction is UP. When A
input lags the B input, UP/DN output goes low,
indicating that the count direction is DOWN.
LS7183 - UPCK (Pin 8)
In LS7083LV, this is the UP Clock output. This output
consists of low-going pulses generated when A input
leads the B input.
LS7184 - CLK (Pin 8)
In LS7184, this is the combined UP Clock and DOWN
Clock output. The count direction at any instant is
indicated by the UP/DN output (Pin 7).
NOTE: For the LS7184, the timing of CLK and UP/DN
requires that the counter interfacing with LS7184 counts
on the rising edge of the CLK pulses.
ABSOLUTE MAXIMUM RATINGS:
PARAMETER
DC Supply Voltage
Voltage at any input
Operating temperature
Storage temperature
SYMBOL
VDD - VSS
VIN
TA
TSTG
VALUE
7.0
VSS - .3 to VDD + .3
-20 to +85
-55 to +150
UNITS
V
V
°C
°C
DC ELECTRICAL CHARACTERISTICS:
(Unless otherwise specified VDD = 3V to 5V and TA = -20°C to 85°C)
PARAMETER
Supply Voltage
Supply current
SYMBOL
VDD
IDD
IDD
MIN
3.0
-
TYPE
30
110
MAX
5.5
45
150
UNITS
V
µA
µA
CONDITON
VDD = 3V
VDD = 5V
Vml
Vmh
Vmf
VDD -0.6
(VDD/2) - 0.5
VDD/2
0.6
(VDD/2) + 0.5
V
V
V
-
Logic 0 input current
Iml
Iml
-
3.0
12.0
5.0
16.0
µA
µA
VDD = 3V
VDD = 5V
Logic 1 input current
Imh
Imh
-
-3.0
-12.0
-5.0
-16.0
µA
µA
VDD = 3V
VDD = 5V
VABl
VABh
IABlk
0.7VDD
-
0
0.3VDD
10
V
V
nA
-
RB
5k
-
10M
ohm
-
Sink current
Iol
Iol
-1.2
-2.5
-1.8
-3.5
-
mA
mA
Vo = 0.5V, VDD = 3V
Vo = 0.5V, VDD = 5V
Source current
Ioh
Ioh
1.2
2.5
1.8
3.5
-
mA
mA
Vo = 2.5V, VDD = 3V
Vo = 4.5V, VDD = 5V
SYMBOL
TOW
MIN
190
TYPE
-
MAX
-
UNITS
ns
TVD
TVD
-
25
50
50
100
ns
ns
VDD = 5V
VDD = 3V
Phase Delay
TPS
TVD +TOW
-
Infinite
s
-
Pulse Width
TPW
2TPS
-
Infinite
s
-
Frequency
fA,B
-
-
1/(2TPW)
Hz
-
Inupt to Output Delay
TDS
TDS
-
200
110
270
150
ns
ns
VDD = 3V
VDD = 5V
MODE input:
Logic 0
Logic 1
Logic float
A,B inputs:
Logic 0
Logic 1
Input current
RBIAS input:
External resistor
All outputs:
TRANSIENT CHARACTERISTICS
(TA = -20°C to 85°C)
PARAMETER
Output Clock Pulse Width
A,B inputs:
Validation Delay
7183/84-070601-2
CONDITON
See Fig. 2
FORWARD
A
REVERSE
TPW
TPS
TPS
4
1
B
TDS
UPCLK
(7183LV)
2
4
2
TOW
DNCLK
(7183LV)
CLK
(7184LV)
2
4
1
4
2
2
4
1
4
2
2
4
1
4
2
UP/DN
(7184LV)
NOTE: Output clocks labelled 1, 2 and 4 have the following interpretations.
1: Generated in x1, x2 and x4 modes
2: Generated in x2 and x4 modes only
4: Generated in x4 mode only
FIGURE 2. LS7183, LS7184 INPUT/OUTPUT TIMING
A
4
DIRECTION
FILTER
INHIBIT
LOGIC
B
MUX
AND
BUFFER
8 UPCK or CLK
FILTER
5
7
RBIAS
1
CURRENT
MIRROR
DNCK or UP/DN
PULSE
V DD
1M
MODE
MODE
DECODE
6
1M
V DD
2
V SS
3
FIGURE 3. LS7183, LS7184 BLOCK DIAGRAM
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
7183/84-071201-3
RBIAS vs Tow
10000
9000
8000
7000
Tow,ns
6000
5000
4000
3000
2000
1000
0
5
10
20
51
100
220
430
750
R, kohm
Figure 4. Bias resistance vs pulse width. R in kΩ.
RBIAS vs Tow
160
140
Tow, us
120
100
80
60
40
20
0
1
2
3
5.1
6.8
8.2
10
R, Mohm
Figure 5. Bias resistance vs pulse width. R in MΩ.
SPDT (On - Off - On)
+V
+V
+V
6
16
2
V DD
V DD
MODE
8
A CLOCK
E N C O D E R B CLOCK
4
5
A CLOCK
7
DNCK
1
RB
V DD
MODE
CK-UP
LS7183
B
16
2
6
5
UPCK
A
+V
10K
4
B CLOCK
5
Vss
1
Vss
3
4516
7
B
RB
10
UP/DN
RBIAS
Vss
8
CK
LS7184
UP/DN
RBIAS
15
CLK
A
EN C OD ER
CK-DN
8
4
40193
V DD
Vss
3
8
FIGURE 6A. TYPICAL APPLICATION FOR LS7183 IN x4 MODE
FIGURE 6B. TYPICAL APPLICATION FOR LS7184 WITH MODE SELECTION
7183/84-082301-4
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