Micross LS842 Linear systems ultra low leakage low drift monolithic dual jfet Datasheet

LS842
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET
The LS842 is a high-performance monolithic dual
JFET featuring extremely low noise, tight offset voltage
and low drift over temperature specifications, and is
targeted for use in a wide range of precision
instrumentation applications. The LS842 features a 25mV offset and 40-µV/°C drift.
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
(See Packaging Information).
LS842 Applications:
ƒ
ƒ
ƒ
ƒ
Wideband Differential Amps
High-Speed,Temp-Compensated SingleEnded Input Amps
High-Speed Comparators
Impedance Converters and vibrations
detectors.
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN.
BVGSS
Breakdown Voltage
60
BVGGO
Gate‐To‐Gate Breakdown
60
TRANSCONDUCTANCE
YfSS
Full Conduction
1000
YfS
Typical Operation
500
|YFS1‐2 / Y FS|
Mismatch
‐‐
DRAIN CURRENT
IDSS
Full Conduction
0.5
|IDSS1‐2 / IDSS|
Mismatch at Full Conduction
‐‐
GATE VOLTAGE
VGS(off) or Vp
Pinchoff voltage
1
VGS(on)
Operating Range
0.5
GATE CURRENT
‐IGmax.
Operating
‐‐
‐IGmax.
High Temperature
‐‐
‐IGmax.
Reduced VDG
‐‐
‐IGSSmax.
At Full Conduction
‐‐
OUTPUT CONDUCTANCE
YOSS
Full Conduction
‐‐
YOS
Operating
‐‐
|YOS1‐2|
Differential
‐‐
COMMON MODE REJECTION
CMR
‐20 log | V GS1‐2/ V DS|
‐‐
‐20 log | V GS1‐2/ V DS|
‐‐
NOISE
NF
Figure
‐‐
en
Voltage
‐‐
‐‐
CAPACITANCE
CISS
Input
‐‐
CRSS
Reverse Transfer
‐‐
CDD
Drain‐to‐Drain
‐‐
FEATURES
LOW DRIFT
| V GS1‐2 / T| ≤40µV/°C
LOW LEAKAGE
IG = 10pA TYP.
LOW NOISE
en = 8nV/√Hz TYP.
LOW OFFSET VOLTAGE
| V GS1‐2| ≤25mV
ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted)
Maximum Temperatures
Storage Temperature
‐65°C to +150°C
Operating Junction Temperature
+150°C
Maximum Voltage and Current for Each Transistor – Note 1
‐VGSS
Gate Voltage to Drain or Source
60V
‐VDSO
Drain to Source Voltage
60V
‐IG(f)
Gate Forward Current
50mA
Maximum Power Dissipation
Device Dissipation @ Free Air – Total
400mW @ +125°C
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
CHARACTERISTICS VALUE UNITS CONDITIONS
| V GS1‐2 / T| max.
DRIFT VS.
40
µV/°C
VDG=20V, ID=200µA
TEMPERATURE
TA=‐55°C to +125°C
| V GS1‐2 | max.
OFFSET VOLTAGE
25
mV
VDG=20V, ID=200µA
TYP.
60
‐‐
MAX.
‐‐
‐‐
UNITS
V
V
CONDITIONS
VDS = 0
ID=1nA
I G= 1nA
ID= 0
I S= 0
‐‐
‐‐
0.6
4000
1000
3
µmho
µmho
%
VDG= 20V
VDG= 20V
2
1
5
5
mA
%
VDG= 20V
VGS= 0V
2
‐‐
4.5
4
V
V
VDS= 20V
VDS=20V
ID= 1nA
ID=200µA
10
‐‐
5
‐‐
50
50
‐‐
100
pA
nA
pA
pA
‐‐
0.1
0.01
10
1
0.1
µmho
µmho
µmho
100
75
‐‐
‐‐
dB
‐‐
‐‐
‐‐
0.5
10
15
10
dB
nV/√Hz
5
‐‐
pF
VGS= 0V f = 1kHz
ID= 200µA
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Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
4
1.2
0.1
VDG= 20V ID= 200µA
TA= +125°C
VDG = 10V ID= 200µA
VDG= 20V , VDS =0
VDG= 20V
VDG= 20V
VGS= 0V
ID= 200µA
∆VDS = 10 to 20V
ID=200µA
∆VDS = 5 to 10V
ID=200µA
VDS= 20V VGS= 0V
RG= 10MΩ
f= 100Hz
NBW= 6Hz
VDS=20V ID=200µA f=1KHz NBW=1Hz
VDS=20V ID=200µA f=10Hz NBW=1Hz
VDS= 20V, ID=200µA
PDIP & SOIC (Top View)
Available Packages:
LS842 / LS842 in PDIP & SOIC
LS842 / LS842 available as bare die
Please contact Micross for full package and die dimensions
Tel: +44 1603 788967
Email: [email protected]
Web: http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
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