LINER LT3837 Isolated no-opto synchronous flyback controller Datasheet

LT3837
Isolated No-Opto
Synchronous Flyback Controller
FEATURES
DESCRIPTION
n
The LT®3837 is an isolated switching regulator controller
designed for medium power flyback topologies. A typical
application is 10W to 60W with the part powered from a
DC supply.
n
n
n
n
n
n
n
n
Senses Output Voltage Directly from Primary Side
Winding—No Optoisolator Required
Synchronous Driver for High Efficiency
Supply Voltage Range 4.5V to 20V
Accurate Regulation Without User Trims
Programmable Switching Frequency from
50kHz to 250kHz
Synchronizable
Load Compensation
Undervoltage Lockout
Available in a Thermally Enhanced 16-Lead
TSSOP Package
The LT3837 is a current mode controller that regulates an
output voltage based on sensing the secondary voltage
via a transformer winding during flyback. This allows for
tight output regulation without the use of an optoisolator,
improving dynamic response and reliability. Synchronous
rectification increases converter efficiency and improves
output cross regulation in multiple output converters.
The LT3837 operates in forced continuous conduction
mode which improves cross regulation in multiple winding
applications. Switching frequency is user programmable
and can be externally synchronized. The part also has load
compensation, undervoltage lockout and soft-start circuitry.
APPLICATIONS
n
n
n
Isolated Medium Power (10W to 60W) Supplies
Instrumentation Power Supplies
Isolated Medical Supplies
The LT3837 is available in a thermally enhanced 16-pin
TSSOP package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6498466, 5841643.
TYPICAL APPLICATION
Efficiency vs Load Current
90
9V –18V to 3.3V at 10A Isolated Converter
18VIN
9VIN
88
22.1k
10μF
BAS16
100nH OUTPUT 3.3V/10A
2N3906
22μF
FB
2.2nF
86.6k
VCC
•
20k
OSC
3.3nF
FMMT618
150k
Si7852DP
PG
tON
ENDLY
SENSE
0.1μF
RCMP
FMMT718
SENSE–
SG
CCMP
GND
330Ω
5
7
8
6
LOAD CURRENT (A)
9
10
3837 TA01b
3.50
3.40
8mΩ
PGDLY
4
3.60
+
12k
1.37k
3
Regulation vs Load Current
1μF
Si7336ADP
SFST
100k
2
10Ω
15k
LT3837
47pF
76
2.2nF
0.1μF
•
OUTPUT (V)
1nF
78
B0540W
VC
3k
84
82
80
220μF
•
10Ω
UVLO
47μF s 3
EFFICIENCY (%)
86
VIN
15Ω
•
9VIN
3.30
18VIN
3.20
10k
BAT54
3.10
3837 TA01
3.00
2
3
4
5
7
8
6
LOAD CURRENT (A)
9
10
3837 TA01c
3837fa
1
LT3837
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
VCC to GND ................................................ –0.3V to 22V
UVLO, SYNC Pin Voltage ............................–0.3V to VCC
SENSE–, SENSE+ Pin Voltage ...................... –0.5V, +0.5V
FB Pin Current........................................................±2mA
VC Pin Current........................................................±1mA
Operating Junction Temperature Range
(Notes 2, 3) .......................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
SG
1
16 PG
VCC
2
15 PGDLY
tON
3
14 RCMP
ENDLY
4
SYNC
5
12 SENSE+
SFST
6
11 SENSE–
OSC
7
10 UVLO
FB
8
9
13 CCMP
17
VC
FE PACKAGE
16-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 40°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 17) IS GND,MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3837EFE#PBF
LT3837EFE#TRPBF
3837EFE
16-Lead Plastic TSSOP
–40°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LLT3837EFE
LT3837EFE#TR
3837EFE
16-Lead Plastic TSSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 14V; PG, SG Open; VC = 1.4V, VSENSE = 0, RCMP = 1k, RTON = 90k,
RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
VCC Operating Range
l
4.5
4
VCC Supply Current (ICC) (Note 5)
VC = Open
l
VCC Shutdown Current
VC = Open, VUVLO = OV
l
20
V
6.4
10
mA
50
150
μA
1.237
1.251
V
Feedback Amplifier
l
Feedback Regulation Voltage (VFB)
Feedback Pin Input Bias Current
RCMP Open
Feedback Amplifier Transconductance
ΔIC = ±10μA
Feedback Amplifier Source or Sink Current
Feedback Amplifier Clamp Voltage
VFB = 0.9
VFB = 1.4
Reference Voltage/Current Line Regulation
12V ≤ VIN ≤ 18V
1.220
200
nA
l
700
1000
1400
l
25
55
90
2.56
0.84
l
0.005
μmho
μA
V
V
0.05
%V
3837fa
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LT3837
ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 14V; PG, SG Open; VC = 1.4V, VSENSE = 0, RCMP = 1k, RTON = 90k,
RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified.
PARAMETER
CONDITIONS
Feedback Amplifier Voltage Gain
VC = 1V to 2V
MIN
TYP
MAX
UNITS
Soft-Start Charging Current
VSFST = 1.5V
16
20
Soft-Start Discharge Current
VSFST = 1.5V, VUVLO = 0V
0.7
1.3
mA
Control Pin Threshold (VC)
Duty Cycle = Min
1.0
V
1400
V/V
25
μA
Gate Outputs
l
l
PG, SG Output High Level
PG, SG Output Low Level
6.6
l
7.4
0.01
8.0
0.05
V
V
1.6
2.3
V
PG, SG Output Shutdown Strength
VUVLO = 0V; IPG, ISG = 20mA
PG Rise Time
CPG = 1nF
11
ns
SG Rise Time
CSG = 1nF
15
ns
PG, SG Fall Time
CPG, CSG = 1nF
10
ns
Current Amplifier
Switch Current Limit at Maximum VC
l
VSENSE +
88
ΔVSENSE/ΔVC
Sense Voltage Overcurrent Fault Voltage
98
110
mV
0.07
VSENSE +, VSFST < 1V
V/V
206
230
mV
100
110
kHz
200
pF
Timing
Switching Frequency (fOSC)
COSC = 100pF
Oscillator Capacitor Value (COSC)
(Note 6)
l
84
33
Minimum Switch On Time (tON(MIN))
200
ns
Flyback Enable Delay Time (tED)
265
ns
200
ns
PG Turn-On Delay Time (tPGDLY)
Maximum Switch Duty Cycle
l
SYNC Pin Threshold
l
85
88
1.53
SYNC Pin Input Resistance
%
2.1
V
40
kΩ
Load Compensation
Load Comp to VSENSE Offset Voltage
VRCMP with VSENSE+ = 0
0.8
mV
Feedback Pin Load Compensation Current
VSENSE+ = 20mV
20
μA
UVLO Function
l
UVLO Pin Threshold (VUVLO)
UVLO Pin Bias Current
VUVLO = 1.2V
VUVLO = 1.3V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
1.215
1.240
1.265
V
–0.25
–4.50
0.1
–3.4
0.25
–2.50
μA
μA
Note 3: The LT3837E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 4: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
TJ = TA + (PD • 40°C/W)
Note 5: Supply current does not include gate charge current to the
MOSFETs. See Applications Information.
Note 6: Component value range guaranteed by design.
3837fa
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LT3837
TYPICAL PERFORMANCE CHARACTERISTICS
VCC Shutdown Current
vs Temperature
10
110
VCC CURRENT (μA)
70
106
8
VCC = 14V
IVCC (mA)
60
108
DYNAMIC CURRENT CPG
CSG = 1nF, fOSC = 100kHz
9
SENSE VOLTAGE (mV)
VUVLO = 0
80
SENSE Voltage vs Temperature
VCC Current vs Temperature
90
50
40
7
6
STATIC PART CURRENT
30
5
20
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
VCC = 14V
3
50
–50 –25
25
75
0
TEMPERATURE (°C)
125
3837 G02
96
100
90
–50
125
200
195
190
185
100
–25
50
25
0
75
TEMPERATURE (°C)
3837 G04
VFB vs Temperature
1.240
COSC = 100pF
1.239
106
1.238
104
1.237
102
1.236
1.235
100
98
1.234
96
1.233
94
1.232
92
1.231
90
–50
125
–25
50
25
0
75
TEMPERATURE (°C)
3837 G05
100
125
1.230
–50
–25
50
25
0
75
TEMPERATURE (°C)
3837 G07
Feedback Amplifier Output
Current vs VFB
VFB Reset vs Temperature
300
125
100
3837 G06
Feedback Pin Input Bias
vs Temperature
125
100
VFB (V)
205
fOSC (kHz)
VSENSE+ – VSENSE– (mV)
108
210
50
75
25
TEMPERATURE (°C)
98
92
110
SENSE = VSENSE
–
215 WITH VSENSE = 0V
0
100
Oscillator Frequency
vs Temperature
+
180
–50 –25
102
3837 G03
SENSE Fault Voltage
vs Temperature
220
104
94
4
10
FB = 1.1V
SENSE = VSENSE+
WITH VSENSE– = 0V
1.04
70
1.03
50
250
1.02
150
100
50
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3837 G08
25°C
–40°C
30
1.01
IVC (μA)
200
VFB RESET (V)
FEEDBACK PIN INPUT BIAS (nA)
125°C
1.00
0.99
10
–10
0.98
–30
0.97
–50
0.96
–50 –25
75
50
25
TEMPERATURE (°C)
0
100
125
3837 G09
–70
0.9
1
1.1
1.2
VFB (V)
1.3
1.4
1.5
3837 G10
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LT3837
TYPICAL PERFORMANCE CHARACTERISTICS
Feedback Amplifier Source and
Sink Current vs Temperature
1600
1550
1050
1500
gm (μmho)
IVC (μA)
1650
SINK
CURRENT
VFB = 1.4V
60
1700
1100
SOURCE CURRENT
VFB = 1.1V
65
Feedback Amplifier Voltage Gain
vs Temperature
55
AV (V/V)
70
Feedback Amplifier gm
vs Temperature
1000
1450
1400
1350
1300
50
1250
950
45
1200
1150
40
–50
–25
50
25
75
0
TEMPERATURE (°C)
100
900
–50
125
–25
75
0
25
50
TEMPERATURE (°C)
100
3837 G11
125
UVLO Shutdown Threshold
vs Temperature
3.7
0.90
0.85
3.6
1.245
100
3837 G13
IUVLO Hysteresis vs Temperature
1.250
0.80
3.5
1.235
1.230
VCC = 14V
0.75
VUVLO (μA)
IUVLO (μA)
1.240
UVLO (V)
75
50
25
TEMPERATURE (°C)
0
3837 G12
UVLO vs Temperature
3.4
3.3
0.70
0.65
0.60
0.55
3.2
0.50
1.225
3.1
1.220
–50 –25
3.0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
0.45
50
25
75
0
TEMPERATURE (°C)
100
3837 G14
125
0.40
–50 –25
80
23
70
22
60
21
50
Minimum On-Time
vs Temperature
21.5
TA = 25°C
ICC = 10mA
21.0
20.5
FALL TIME
40
20.0
30
19
125
VCC (V)
TIME (ns)
24
100
3837 G15a
PG, SG Rise and Fall Times
vs Load Capacitance
20
50
25
75
0
TEMPERATURE (°C)
3837 G15
Soft-Start Charge Current
vs Temperature
SFST CHARGE CURRENT (μA)
1100
–50 –25
125
RISE TIME
18
20
17
10
19.5
16
–50 –25
0
75
50
25
TEMPERATURE (°C)
0
100
125
3837 G16
0
1
2
3 4 5 6 7
CAPACITANCE (nF)
8
9
10
3837 G17
19.0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
3837 G18
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LT3837
TYPICAL PERFORMANCE CHARACTERISTICS
Enable Delay Time vs Temperature
PG Delay Time vs Temperature
260
300
MINIMUM ENABLE TIME (ns)
250
RPGDLY = 27.4k
tPG (ns)
200
150
100
RPGDLY = 16.7k
240
220
200
180
160
50
0
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
RENDLY = 90k
90 110
3837 G20
140
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3837 G21
PIN FUNCTIONS
SG (Pin 1): Synchronous gate drive output. This pin provides an output signal for a secondary-side synchronous
switch. Large dynamic currents may flow during voltage
transitions. See the Applications Information for details.
VCC (Pin 2): Supply voltage pin. Bypass this pin to ground
with a 4.7μF capacitor or more.
tON (Pin 3): Pin for external programming resistor to set
the minimum time that the primary switch is on for each
cycle. Minimum turn-on facilitates the isolated feedback
method. See Applications Information for details.
ENDLY (Pin 4): Pin for external programming resistor to
set enable delay time. The enable delay time disables the
feedback amplifier for a fixed time after the turn-off of the
primary-side MOSFET. This allows the leakage inductance
voltage spike to be ignored for flyback voltage sensing.
See Applications Information for details.
SYNC (Pin 5): Pin for synchronizing the internal oscillator with an external clock. The positive edge on a pulse
causes the oscillator to discharge causing PG to go low
(off) and SG high (on). The sync threshold is typically 1.4V.
See Applications Information for details. Tie to ground if
unused.
SFST (Pin 6): This pin, in conjunction with a capacitor to
ground, controls the ramp-up of peak primary current as
sensed through the sense resistor. This is used to control
converter inrush current at start-up. The VC pin voltage
cannot exceed the SFST pin voltage, so as SFST increases,
the maximum voltage on VC increases commensurately,
allowing higher peak currents. Total VC ramp time is approximately 70ms per μF of capacitance. Leave pin open
if not using the soft-start function.
OSC (Pin 7): This pin in conjunction with an external
capacitor defines the controller oscillator frequency. The
frequency is approximately 100kHz • 100/COSC(pF).
FB (Pin 8): Pin for the feedback node for the power supply feedback amplifier. Feedback is sensed via a transformer winding and enabled during the flyback period.
This pin also sinks additional current to compensate for
load current variation as set by the RCMP pin. Keep the
Thevenin equivalent resistance of the feedback divider
at roughly 3k.
VC (Pin 9): Pin used for frequency compensation for the
switcher control loop. It is the output of the feedback
amplifier and the input to the current comparator. Switcher
frequency compensation components are normally placed
on this pin to ground. The voltage on this pin is proportional to the peak primary switch current. The feedback
amplifier output is enabled during the synchronous switch
on time.
3837fa
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LT3837
PIN FUNCTIONS
UVLO (Pin 10): A resistive divider from VIN to this pin sets
an undervoltage lockout based upon VIN level (not VCC).
When the UVLO pin is below its threshold, the gate drives
are disabled, but the part draws its normal quiescent current
from VCC. The VCC undervoltage lockout supersedes this
function so VCC must be great enough to start the part.
CCMP (Pin 13): Pin for external filter capacitor for the
optional load compensation function. Load compensation
reduces the effects of parasitic resistances in the feedback
sensing path. A 0.1μF ceramic capacitor suffices for most
applications. Short this pin to GND in less demanding applications that don’t require load compensation.
The bias current on this pin has hysteresis such that the
bias current is sourced when the UVLO threshold is exceeded. This introduces a hysteresis at the pin equivalent
to the bias current change times the impedance of the
upper divider resistor. The user can control the amount of
hysteresis by adjusting the impedance of the divider. See
the Applications Information for details. Tie the UVLO pin
to VCC if you are not using this function.
RCMP (Pin 14): Pin for optional external load compensation
resistor. Use of this pin allows for nominal compensation
of parasitic resistances in the feedback sensing path. In
less demanding applications, this resistor is not needed
and this pin can be left open. See Applications Information for details.
SENSE– (Pin 11), SENSE+ (Pin 12): These pins are used to
measure primary side switch current through an external
sense resistor. Peak primary side current is used in the
converter control loop. Make Kelvin connections to the
sense resistor to reduce noise problems. SENSE– connects to the ground side. At maximum current (VC at its
maximum voltage) it has a 98mV threshold. The signal is
blanked (ignored) during the minimum turn-on time.
PGDLY (Pin 15): Pin for external programming resistor to
set delay from synchronous gate turn-off to primary gate
turn-on. See Applications Information for details.
PG (Pin 16): Gate drive pin for the primary side MOSFET
Switch. Large dynamic currents flow during voltage transitions. See the Applications Information for details.
GND (Exposed Pad, Pin 17): This is the ground connection for both signal ground and gate driver grounds. This
GND should be connected to the PCB ground plane for
electrical contact and rated thermal performance. Careful
attention must be paid to ground layout. See Applications
Information for details.
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LT3837
BLOCK DIAGRAM
CLAMPS
VCC
0.7
+
1.25V
VC
+
S
Q
R
Q
9
COLLAPSE DETECT
–
–
UVLO
+
CURRENT
COMPARATOR
TSD
SFST
1V
6
OVERCURRENT
FAULT
–
10
8
ERROR AMP
–
INTERNAL
REGULATOR
+
UVLO
–
3V
DISABLE
+
–
1.3
–
1.25V
REFERENCE
(VFB)
0.8V
FB
+
2
SENSE–
11
–
CURRENT
SENSE AMP
+
+
CURRENT TRIP
SENSE+
SLOPE COMPENSATION
7
5
3
15
4
OSC
OSCILLATOR
RCMPF
50k
CCMP
ENABLE
SET
+
SYNC
ENDLY
13
–
LOAD
COMPENSATION
tON
PGDLY
12
LOGIC
BLOCK
RCMP
TO FB
14
VCC
PGATE
GATE DRIVE
PG
16
SGATE
+
–
3V
VCC
GATE DRIVE
SG
GND
1
17
3837 BD
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LT3837
FLYBACK FEEDBACK AMPLIFIER
T1
VFLBK
FLYBACK
LT3837 FEEDBACK AMP
R1
8
FB
•
–
1V
VFB
1.25V
R2
VCC
9
+
CVC
VIN
•
PRIMARY
SECONDARY
+
•
COUT
ISOLATED
OUTPUT
MP
–
COLLAPSE
DETECT
MS
R
ENABLE
S
Q
3837 FFA
TIMING DIAGRAM
VIN
VFLBK
PRIMARY SIDE
MOSFET DRAIN
VOLTAGE
VIN
0.8 • VFLBK
PG VOLTAGE
SG VOLTAGE
3825 TD
tON
MIN ENABLE
ENABLE
DELAY
PG DELAY
FEEDBACK
AMPLIFIER
ENABLED
3837fa
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LT3837
OPERATION
The LT3837 is a current mode switcher controller IC
designed specifically for use in an isolated flyback topology
employing synchronous rectification. The LT3837 operation
is similar to traditional current mode switchers. The major
difference is that output voltage feedback is derived via
sensing the output voltage through the transformer. This
precludes the need of an optoisolator in isolated designs
greatly improving dynamic response and reliability. The
LT3837 has a unique feedback amplifier that samples a
transformer winding voltage during the flyback period and
uses that voltage to control output voltage.
The internal blocks are similar to many current mode
controllers. The differences lie in the flyback feedback
amplifier and load compensation circuitry. The logic block
also contains circuitry to control the special dynamic
requirements of flyback control.
See Application Note 19 for more information on the basics
of current mode switcher/controllers and isolated flyback
converters.
Feedback Amplifier—Pseudo DC Theory
For the following discussion refer to the simplified
Flyback Feedback Amplifier diagram. When the primary side
MOSFET switch MP turns off, its drain voltage rises above
the VIN rail. Flyback occurs when the primary MOSFET is
off and the synchronous secondary MOSFET is on. During flyback the voltage on nondriven transformer pins is
determined by the secondary voltage. The amplitude of this
flyback pulse as seen on the third winding is given as:
VFLBK =
(
VOUT + ISEC • ESR + RDS(ON)
)
N SF
RDS(ON) = on resistance of the synchronous MOSFET MS
ISEC = transformer secondary current
ESR = impedance of secondary circuit capacitor, winding
and traces
amplifier then compares the voltage to the internal bandgap
reference. The feedback amp is actually a transconductance
amplifier whose output is connected to VC only during a
period in the flyback time. An external capacitor on the VC
pin integrates the net feedback amp current to provide the
control voltage to set the current mode trip point.
The regulation voltage at the FB pin is nearly equal to the
bandgap reference VFB because of the high gain in the
overall loop. The relationship between VFLBK and VFB is
expressed as:
VFLBK =
R1+ R2
• VFB
R2
Combining this with the previous VFLBK expression yields
an expression for VOUT in terms of the internal reference,
programming resistors and secondary resistances:
(
⎛ R1+ R2
⎞
VOUT = ⎜
• VFB • NSF ⎟ – ISEC • ESR + RDS(ON)
⎝ R2
⎠
Rearranging yields the equation for R1.
(
)
)
⎤
⎡ V + I • ESR + R
OUT SEC
DS(ON)
R1= R2 • ⎢
– 1⎥
⎥
⎢
(NSF )( VFB )
⎦
⎣
The effect of nonzero secondary output impedance is discussed in further detail; see Load Compensation Theory.
The practical aspects of applying this equation for VOUT
are found in the Applications Information.
Feedback Amplifier Dynamic Theory
So far, this has been a pseudo-DC treatment of flyback
feedback amplifier operation. But the flyback signal is a
pulse, not a DC level. Provision must be made to enable
the flyback amplifier only when the flyback pulse is present.
This is accomplished by the “Enable” line in the diagram.
Timing signals are then required to enable and disable the
flyback amplifier. There are several timing signals which
are required for proper LT3837 operation. Please refer to
the Timing Diagram.
NSF = transformer effective secondary-to-feedback winding
turns ratio (i.e., NS/NFLBK)
The flyback voltage is then scaled by an external resistive
divider R1/R2 and presented at the FB pin. The feedback
3837fa
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LT3837
OPERATION
Minimum Output Switch On-Time (tON(MIN))
The LT3837 affects output voltage regulation via flyback
pulse action. If the output switch is not turned on, there
is no flyback pulse and output voltage information is
not available. This causes irregular loop response and
start-up/latch-up problems. The solution is to require the
primary switch to be on for an absolute minimum time
per each oscillator cycle. If the output load is less than
that developed under these conditions, forced continuous
operation normally occurs. See Applications Information
for further details.
Enable Delay (ENDLY)
The flyback pulse appears when the primary side switch
shuts off. However, it takes a finite time until the transformer primary side voltage waveform represents the
output voltage. This is partly due to rise time on the primary side MOSFET drain node but, more importantly, is
due to transformer leakage inductance. The latter causes
a voltage spike on the primary side, not directly related
to output voltage. Some time is also required for internal
settling of the feedback amplifier circuitry. In order to
maintain immunity to these phenomena, a fixed delay is
introduced between the switch turn-off command and the
enabling of the feedback amplifier. This is termed “enable
delay.” In certain cases where the leakage spike is not
sufficiently settled by the end of the enable delay period,
regulation error may result. See Applications Information
for further details.
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
voltage (FB referred) to a fixed reference, nominally 80%
of VFB. When the flyback waveform drops below this level,
the feedback amplifier is disabled.
Minimum Enable Time
The feedback amplifier, once enabled, stays enabled for
a fixed minimum time period termed “minimum enable
time.” This prevents lockup, especially when the output
voltage is abnormally low; e.g., during start-up. The mini-
mum enable time period ensures that the VC node is able
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. This time is internally set.
Effects of Variable Enable Period
The feedback amplifier is enabled during only a portion of
the cycle time. This can vary from the fixed minimum enable
time described to a maximum of roughly the “off” switch
time minus the enable delay time. Certain parameters of
flyback amp behavior are directly affected by the variable
enable period. These include effective transconductance
and VC node slew rate.
Load Compensation Theory
The LT3837 uses the flyback pulse to obtain information
about the isolated output voltage. An error source is
caused by transformer secondary current flow through the
synchronous MOSFET RDS(ON) and real life nonzero impedances of the transformer secondary and output capacitor.
This was represented previously by the expression “ISEC
• (ESR + RDS(ON)).” However, it is generally more useful
to convert this expression to effective output impedance.
Because the secondary current only flows during the off
portion of the duty cycle (DC), the effective output impedance equals the lumped secondary impedance divided by
OFF time DC.
Since the OFF time duty cycle is equal to 1 – DC then:
RS(OUT) =
ESR + RDS(ON)
1– DC
where:
RS(OUT) = effective supply output impedance
DC = duty cycle
RDS(ON) and ESR are as defined previously
This impedance error may be judged acceptable in less
critical applications, or if the output load current remains
relatively constant. In these cases the external FB resistive
divider is adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error is minimized by the use of the load compensation
function.
3837fa
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LT3837
OPERATION
VFLBK
R1
IIN = K1• IOUT
•
FB
Q1 Q2
8
VFB
VIN
R2
Average primary side current is expressed in terms of
output current as follows:
T1
LOAD
COMP I
•
•
MP
+
Q3
A1
–
14 RCMP
where :
V
K1= OUT
VIN • Eff
So the effective change in VOUT target is:
RCMPF
+
50k SENSE
12
13 CCMP
ΔVOUT = K1• ΔIOUT •
RSENSE
3837 F01
RSENSE
• R1• NSF
RCMP
thus :
R
ΔVOUT
= K1• SENSE • R1• NSF
RCMP
ΔIOUT
where:
Figure 1. Load Compensation Diagram
Figure 1 shows the block diagram of the load compensation function. Switch current is converted to voltage by the
external sense resistor, averaged and lowpass filtered by
the internal 50k resistor RCMPF and the external capacitor
on CCMP. This voltage is then impressed across the external RCMP resistor by op amp A1 and transistor Q3. This
produces a current at the collector of Q3 that is subtracted
from the FB node. This action effectively increases the
voltage required at the top of the R1/R2 feedback divider
to achieve equilibrium.
The average primary side switch current increases to
maintain output voltage regulation as output loading
increases. The increase in average current increases
the RCMP resistor current which affects a corresponding
increase in sensed output voltage, compensating for the
IR drops.
K1 = dimensionless variable related to VIN, VOUT and
efficiency as explained above
RSENSE = external sense resistor
Nominal output impedance cancellation is obtained by
equating this expression with RS(OUT):
K1 •
ESR + RDS(ON)
RSENSE
• R1• NSF =
RCMP
1– DC
Solving for RCMP gives:
RCMP = K1•
RSENSE • (1– DC)
• R1• NSF
ESR + RDS(ON)
The practical aspects of applying this equation to determine
an appropriate value for the RCMP resistor are found in the
Applications Information.
Assuming a relatively fixed power supply efficiency, Eff,
power balance gives:
POUT = Eff • PIN
VOUT • IOUT = Eff • VIN • IIN
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LT3837
APPLICATIONS INFORMATION
Primary Winding Feedback
The previous work was developed using a separate winding for voltage feedback. It is possible to use the primary
winding as the feedback winding as well. This can simplify
the design of the transformer.
Likewise the load compensation equation needs to be
changed to use NSP instead of NSF so:
RCMP = K1•
When using the primary winding the feedback voltage
will be added to the VIN voltage so:
VFLYBK =
(
VOUT + IOUT • ESR + RDS(ON)
VFLYBK
R1
)
VIN
PRIMARY
NSP
where NSP is the transformer effective secondary to
primary winding turns ratio. Use the circuit of Figure 2
to get more accurate output regulation. In this case the
regulation equations becomes:
R1=
RSENSE • (1– DC)
• R1• NSF
ESR + RDS(ON)
(
)
COUT
• SECONDARY
LT3837
FB
MP
MS
PG
R2
⎤
R2 ⎡⎢ VOUT + IOUT • ESR + RDS(ON)
•
− VBE ⎥
VFB ⎢
NSP
⎥
⎣
⎦
where VBE is the base emitter drop of the PNP (approximately 0.7V).
•
3837 F10
Figure 2
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LT3837
APPLICATIONS INFORMATION
Transformer Design
Transformer design/specification is the most critical part
of a successful application of the LT3837. The following
sections provide basic information about designing the
transformer and potential tradeoffs.
If you need help, the LTC Applications group is available to
assist in the choice and/or design of the transformer.
Turns Ratios
The design of the transformer starts with determining
duty cycle (DC). DC impacts the current and voltage stress
on the power switches, input and output capacitor RMS
currents and transformer utilization (size vs power).
The ideal turns ratio is:
V
1– DC
NIDEAL = OUT •
VIN
DC
Avoid extreme duty cycles as they, in general, increase
current stresses. A reasonable target for duty cycle is 50%
at nominal input voltage.
For instance, if we wanted a 9V to 3.3V converter at 50%
DC then:
3.3 1– 0.5
1
NIDEAL =
•
=
9
0.5
2.72
In general, better performance is obtained with a lower
turns ratio. A DC of 52% yields a 1:3 ratio.
Note the use of the external feedback resistive divider
ratio to set output voltage provides the user additional
freedom in selecting a suitable transformer turns ratio.
Turns ratios that are the simple ratios of small integers;
e.g., 1:1, 2:1, 3:2 help facilitate transformer construction
and improve performance.
When building a supply with multiple outputs derived
through a multiple winding transformer, lower duty cycle
can improve cross regulation by keeping the synchronous
rectifier on longer, and thus, keep secondary windings
coupled longer.
For a multiple output transformer, the turns ratio between
output windings is critical and affects the accuracy of the
voltages. The ratio between two output voltages is set with
the formula VOUT2 = VOUT1 • N21 where N21 is the turns
ratio of between the two windings. Also keep the secondary
MOSFET RDS(ON) small to improve cross regulation.
Leakage Inductance
Transformer leakage inductance (on either the primary or
secondary) causes a spike after the primary side switch
turn-off. This is increasingly prominent at higher load
currents, where more stored energy is dissipated. Higher
flyback voltage may break down the MOSFET switch if it
has too low a BVDSS rating.
One solution to reducing this spike is to use a snubber
circuit to suppress the voltage excursion. However, suppressing the voltage extends the flyback pulse width. If
the flyback pulse extends beyond the enable delay time,
output voltage regulation is affected. The feedback system
has a deliberately limited input range, roughly ±50mV referred to the FB node. This rejects higher voltage leakage
spikes because once a leakage spike is several volts in
amplitude, a further increase in amplitude has little effect
on the feedback system.
So it is advisable to arrange the snubber circuit to clamp
at as high a voltage as possible, observing MOSFET
breakdown, such that leakage spike duration is as short
as possible. Application Note 19 provides a good reference
on snubber design.
As a rough guide, total leakage inductances of several percent (of mutual inductance) or less may require a snubber,
but exhibit little to no regulation error due to leakage spike
behavior. Inductances from several percent up to perhaps
ten percent cause increasing regulation error.
Avoid double digit percentage leakage inductances as there
is a potential for abrupt loss of control at high load current.
This curious condition potentially occurs when the leakage
spike becomes such a large portion of the flyback waveform
that the processing circuitry is fooled into thinking that the
leakage spike itself is the real flyback signal!
3837fa
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LT3837
APPLICATIONS INFORMATION
It then reverts to a potentially stable state whereby the
top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This typically reduces the output voltage
abruptly to a fraction, roughly one-third to two-thirds of
its correct value.
Once load current is reduced sufficiently, the system snaps
back to normal operation. When using transformers with
considerable leakage inductance, exercise this worst-case
check for potential bistability:
1. Operate the prototype supply at maximum expected
load current.
2. Temporarily short-circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
low value, the system has a problem. This is usually evident
by simultaneously viewing the primary side MOSFET drain
voltage to observe firsthand the leakage spike behavior.
A final note—the susceptibility of the system to bistable
behavior is somewhat a function of the load current/voltage characteristics. A load with resistive—i.e., I = V/R
behavior—is the most apt to be bistable. Capacitive loads
that exhibit I = V2/R behavior are less susceptible.
Secondary Leakage Inductance
Leakage inductance on the secondary forms an inductive
divider on the transformer secondary, reducing the size
of the feedback flyback pulse. This increases the output
voltage target by a similar percentage.
Note that unlike leakage spike behavior, this phenomenon
is independent of load. Since the secondary leakage inductance is a constant percentage of mutual inductance
(within manufacturing variations), the solution is to adjust
the feedback resistive divider ratio to compensate.
Winding Resistance Effects
Primary or secondary winding resistance acts to reduce
overall efficiency (POUT/PIN). Secondary winding resistance
increases effective output impedance degrading load regulation. Load compensation can mitigate this to some extent
but a good design keeps parasitic resistances low.
Bifilar Winding
A bifilar or similar winding is a good way to minimize
troublesome leakage inductances. Bifilar windings also
improve coupling coefficients and thus improve cross
regulation in multiple winding transformers. However,
tight coupling usually increases primary-to-secondary
capacitance and limits the primary-to-secondary breakdown voltage, so it isn’t always practical.
Primary Inductance
The transformer primary inductance, LP, is selected based
on the peak-to-peak ripple current ratio (X) in the transformer relative to its maximum value. As a general rule,
keep X in the range of 50% to 70% ripple current (i.e., X =
0.5 to 0.7). Higher values of ripple will increase conduction
losses, while lower values will require larger cores.
Ripple current and percentage ripple is largest at minimum
duty cycle; in other words, at the highest input voltage.
LP is calculated from:
LP
2
2
VIN(MAX ) • DCMIN ) ( VIN(MAX ) • DCMIN ) • Eff
(
=
=
fOSC • XMAX • PIN
fOSC • XMAX • POUT
where:
fOSC is the OSC frequency
DCMIN is the DC at maximum input voltage
XMAX is ripple current ratio at maximum input voltage
Continuing with the 9V to 3.3V example, let us assume a
10A output, 9V to 18V input power with 88% efficiency.
Using X = 0.7, and fOSC = 200kHz:
3.3 • 10 A
= 37.5W
88%
1
1
=
= 35.5%
DCMIN =
N • VIN(MAX )
1 18
1+ •
1+
3 3.3
VOUT
PIN =
LP =
(18V • 0.355)2
200kHz • 0.7 • 37.5W
= 7.8μH
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LT3837
APPLICATIONS INFORMATION
Optimization might show that a more efficient solution
is obtained at higher peak current but lower inductance
and the associated winding series resistance. A simple
spreadsheet program is useful for looking at tradeoffs.
Transformer Core Selection
Once LP is known, the type of transformer is selected.
High efficiency converters use ferrite cores to minimize
core loss. Actual core loss is independent of core size for
a fixed inductance, but decreases as inductance increases.
Since increased inductance is accomplished through
more turns of wire, copper losses increase. Thus transformer design balances core and copper losses. Remember that increased winding resistance will degrade cross
regulation and increase the amount of load compensation required.
The main design goals for core selection are reducing
copper losses and preventing saturation. Ferrite core material saturates hard, rapidly reducing inductance when the
peak design current is exceeded. This results in an abrupt
increase in inductor ripple current and, consequently, output voltage ripple. Do not allow the core to saturate! The
maximum peak primary current occurs at minimum VIN:
PIN
IPK =
VIN(MIN) • DCMAX
⎛ X ⎞
• ⎜ 1+ MIN ⎟
⎝
2 ⎠
1+
XMIN
1
=
N • VIN(MIN)
VOUT
1
= 52.4%
1 9
1+ •
3 3.3
2
VIN(MIN) • DCMAX )
(
=
=
fOSC • LP • PIN
(9 • 0.52)2
200kHz • 7.8μH • 37.5W
= 0.380
Using the example numbers leads to:
IPK =
One advantage that the flyback topology offers is that additional output voltages can be obtained simply by adding
windings. Designing a transformer for such a situation is
beyond the scope of this document. For multiple windings,
realize that the flyback winding signal is a combination of
activity on all the secondary windings. Thus load regulation
is affected by each windings load. Take care to minimize
cross regulation effects.
Setting Feedback Resistive Divider
Use the equation developed in the Operation section for
the feedback divider.
It is recommended that the Thevenin impedance of the
resistors on the FB Pin is roughly 3k for bias current
cancellation and other reasons.
For the example using primary winding sensing if
ESR = 0.002 and RDS(ON) = 0.004 then:
R1=
(
)
⎤
3k ⎡⎛ 3.3 + 10 • ( 0.002 + 0.004 ⎞
⎥ = 22.75k
• ⎢⎜
–
0
.
7
⎟
1.237 ⎢⎝
1 / 3)
(
⎥⎦
⎠
⎣
So, choose 22.1k.
Current Sense Resistor Considerations
now :
DCMAX =
Multiple Outputs
37.5W ⎛ 0.380 ⎞
• 1+
= 9.47 A
9 V • 0.524 ⎜⎝
2 ⎟⎠
The external current sense resistor is used to control peak
primary switch current, which controls a number of key
converter characteristics including maximum power and
external component ratings. Use a noninductive current
sense resistor (no wire-wound resistors). Mounting the
resistor directly above an unbroken ground plane connected with wide and short traces keeps stray resistance
and inductance low.
The dual sense pins allow for a fully Kelvined connection.
Make sure that SENSE+ and SENSE– are isolated and connect close to the sense resistor to preserve this.
Peak current occurs at 98mV of sense voltage VSENSE. So
the nominal sense resistor is VSENSE/IPK. For example, a
peak switch current of 10A requires a nominal sense resistor
of 0.010Ω. Note that the instantaneous peak power in the
sense resistor is 1W, and that it is rated accordingly. The
use of parallel resistors can help achieve low resistance,
low parasitic inductance and increased power capability.
3837fa
16
LT3837
APPLICATIONS INFORMATION
Size RSENSE using worst-case conditions, minimum LP,
VSENSE and maximum VIN. Continuing the example, let us
assume that our worst-case conditions yield an IPK 10%
above nominal so IPK = 10.41A . If there is a 5% tolerance
on RSENSE and minimum VSENSE = 80mV, then RSENSE •
105% = 88mV/10.41A and nominal RSENSE = 8.05mΩ.
Round to the nearest available lower value 8.0mΩ.
Selecting the Load Compensation Resistor
The expression for RCMP was derived in the Operation
section for primary winding sensing as:
RCMP = K1•
RSENSE • (1– DC)
• R1 • NSP = RS(OUT)
ESR + RDS(ON)
Continuing the example:
⎛ V
⎞
3.3
K1= ⎜ OUT ⎟ =
= 0.417
⎝ VIN • Eff ⎠ 9 ( 88%)
If ESR = 0.002Ω and RDS(ON) = 0.004Ω
8.0mΩ • (1– 0.52)
• 22.1kΩ • 0.33
RCMP = 0.417 •
0.002Ω + 0.004Ω
= 1.93kΩ
3. Calculate a value for the K1 constant based on VIN, VOUT
and the measured (differential) efficiency.
4. Compute:
RCMP = K1•
RSENSE
• R1• NSP orNSF
RS(OUT)
5. Verify this result by connecting a resistor of this value
from the RCMP pin to ground.
6. Disconnect the ground short to CCMP and connect the
requisite 0.1μF filter capacitor to ground. Measure the
output impedance RS(OUT) = ΔVOUT/ΔIOUT with the
new compensation in place. RS(OUT) should have
decreased significantly. Fine tuning is accomplished
experimentally by slightly altering RCMP. A revised
estimate for RCMP is:
⎛ RS(OUT)CMP ⎞
R′CMP = RCMP • ⎜ 1+
⎟
RS(OUT) ⎠
⎝
where R′CMP is the new value for the load compensation
resistor, RS(OUT)CMP is the output impedance with RCMP
in place and RS(OUT) is the output impedance with no load
compensation (from step 2).
This value for RCMP is a good starting point, but empirical methods are required for producing the best results.
This is because several of the required input variables are
difficult to estimate precisely. For instance, the ESR term
above includes that of the transformer secondary, but its
effective ESR value depends on high frequency behavior,
not simply DC winding resistance. Similarly, K1 appears
as a simple ratio of VIN to VOUT times (differential) efficiency, but theoretically estimating efficiency is not a
simple calculation.
Setting Frequency
The suggested empirical method is as follows:
You can synchronize the oscillator frequency to an external
frequency. This is done with a signal on the SYNC pin. Set
the LT3837 frequency 10% slower than the desired external
frequency using the OSC pin capacitor, then use a pulse on
the SYNC pin of amplitude greater than 2V and with the
desired period. The rising edge of the SYNC signal initiates
an OSC capacitor discharge forcing primary MOSFET off
(PG voltage goes low). If the oscillator frequency is much
different from the sync frequency, problems may occur
1. Build a prototype of the desired supply including the
actual secondary components.
2. Temporarily ground the CCMP pin to disable the load
compensation function. Measure output voltage while
sweeping output current over the expected range.
Approximate the voltage variation as a straight line,
ΔVOUT/ΔIOUT = RS(OUT).
The switching frequency of the LT3837 is set by an
external capacitor connected between the OSC pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz. Figure 3 shows the nominal relationship between
external capacitance and switching frequency. Place the
capacitor as close as possible to the IC and minimize OSC
trace length and area to minimize stray capacitance and
potential noise pickup.
3837fa
17
LT3837
APPLICATIONS INFORMATION
300
with slope compensation and system stability. Keep the
sync pulse width greater than 500ns.
200
There are three internal “one-shot” times that are programmed by external application resistors: minimum
on-time, enable delay time and primary MOSFET turn-on
delay. These are all part of the isolated flyback control
technique, and their functions are previously outlined in
the Theory of Operation section.
The following information should help in selecting and/or
optimizing these timing values.
fOSC (kHz)
Selecting Timing Resistors
100
50
30
100
COSCAP (pF)
200
3837 F02
Figure 3. fOSC vs OSC Capacitor Values
Minimum On-Time (tON(MIN))
Enable Delay Time (ENDLY)
Minimum on-time is the programmable period during
which current limit is blanked (ignored) after the turn
on of the primary side switch. This improves regulator
performance by eliminating false tripping on the leading
edge spike in the switch, especially at light loads. This
spike is due to both the gate/source charging current and
the discharge of drain capacitance. The isolated flyback
sensing requires a pulse to sense the output. Minimum
on-time ensures that there is always a signal to close the
feedback loop. The LT3837 does not employ cycle skipping
at light loads. Therefore, minimum on-time along with
synchronous rectification sets the switch over in forced
continuous mode operation.
Enable delay time provides a programmable delay between
turn-off of the primary gate drive node and the subsequent
enabling of the feedback amplifier. As discussed earlier, this
delay allows the feedback amplifier to ignore the leakage
inductance voltage spike on the primary side.
The tON(MIN) resistor is set with the following equation:
R tON(MIN) (kΩ) =
Keep RtON(MIN)
is 160k.
tON(MIN)(ns) – 104
1.063
greater than 70k. A good starting value
The worst-case leakage spike pulse width is at maximum
load conditions. So set the enable delay time at these
conditions.
While the typical applications for this part use forced
continuous operation, it is conceivable that a secondaryside controller might cause discontinuous operation at
light loads. Under such conditions the amount of energy
stored in the transformer is small. The flyback waveform
becomes “lazy” and some time elapses before it indicates
the actual secondary output voltage. The enable delay time
should be made long enough to ignore the “irrelevant”
portion of the flyback waveform at light load.
Even though the LT3837 has a robust gate drive, the gate
transition-time slows with very large MOSFETs. Increase
delay time is as required when using such MOSFETs.
The enable delay resistor is set with the following
equation:
tENDLY (ns) – 30
2.616
greater than 40k. A good starting point
RENDLY (kΩ) =
Keep RENDLY
is 56k.
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LT3837
APPLICATIONS INFORMATION
Primary Gate Delay Time (PGDLY)
UVLO Pin Function
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of
the primary side MOSFET. Correct setting eliminates
overlap between the primary side switch and secondary
side synchronous switch(es) and the subsequent current
spike in the transformer. This spike will cause additional
component stress and a loss in regulator efficiency.
The UVLO pin provides a user programming undervoltage
lockout. This is usually used to provide undervoltage
lockout based on VIN. The gate drivers are disabled when
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The primary gate delay resistor is set with the following
equation:
RPGDLY (kΩ) =
tPGDLY (ns) + 47
9.01
A good starting point is 27k.
The bias current on this pin depends on the pin voltage and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
dropping the voltage on UVLO. In this manner, hysteresis
is produced.
Soft-Start Functions
The LT3837 contains an optional soft-start function that is
enabled by connecting an external capacitor between the
SFST pin and ground. Internal circuitry prevents the control
voltage at the VC pin from exceeding that on the SFST pin.
There is an initial pull-up circuit to quickly bring the SFST
voltage to approximately 0.8V. From there it charges to
approximately 2.8V with a 20μA current source.
The SFST node is then discharged to 0.8V when a fault
occurs. A fault is VCC too low (undervoltage lockout),
current sense voltage greater than 200mV or the IC’s
thermal (overtemperature) shutdown is tripped. When
SFST discharges, the VC node voltage is also pulled low
to below the minimum current voltage. Once discharged,
the SFST recharges up again.
In this manner, switch currents are reduced and the stresses
in the converter are reduced during fault conditions.
The time it takes to fully charge soft-start is:
C
• 1.4V
t SS = SFST
= 70ms • CSFST (μF)
20μA
VIN
IUVLO
IUVLO
VIN
RA1
VIN
RA2
RA
RA
UVLO
RB
LT3837
RB
UVLO
CUVLO
UVLO
RB
LT3837
3837 F03
(3a) UV Turning ON
(3b) UV Turning OFF
(3c) UV Filtering
Figure 4
Referring to Figure 4, the voltage hysteresis at VIN is
equal to the change in bias current times RA. The design
procedure is to select the desired VIN referred voltage
hysteresis, VUVHYS. Then:
RA =
VUVHYS
IUVLO
where:
IUVLO = IUVLOL – IUVLOH is approximately 3.4μA
RB is then selected with the desired turn-on voltage:
RB =
RA
⎛ VIN(ON) ⎞
– 1⎟
⎜ V
⎝ UVLO ⎠
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LT3837
APPLICATIONS INFORMATION
If we wanted a VIN-referred trip point of 8.4V, with 0.3V
of hysteresis (on at 8.4V, off at 8.1V):
0.3V
= 88.2k, use 86.6k
3.4μA
86.6k
= 14.99k, use 15k
RB =
⎛ 8.4V
⎞
⎜⎝ 1.24V – 1⎟⎠
RA =
Even with good board layout, board noise may cause
problems with UVLO. You can filter the divider but keep
large capacitance off the UVLO node because it will slow
the hysteresis produced from the change in bias current.
Figure 4c shows an alternate method of filtering by splitting the RA resistor with the capacitor. The split should
put more of the resistance on the UVLO side.
Control Loop Compensation
Loop frequency compensation is performed by connecting a capacitor network from the output of the feedback
amplifier (VC pin) to ground as shown in Figure 5. Because of the sampling behavior of the feedback amplifier,
compensation is different from traditional current mode
switcher controllers. Normally only CVC is required. RVC
can be used to add a “zero” but the phase margin improvement traditionally offered by this extra resistor is usually
already accomplished by the nonzero secondary circuit
impedance. CVC2 can be used to add an additional high
frequency pole and is usually sized at 0.1 times CVC.
VC
9
CVC2
RVC
CVC
3825 F05
Figure 5. VC Compensation Network
In further contrast to traditional current mode switchers,
VC pin ripple is generally not an issue with the LT3837.
The dynamic nature of the clamped feedback amplifier
forms an effective track/hold type response, whereby the
VC voltage changes during the flyback pulse, but is then
“held” during the subsequent “switch on” portion of the
next cycle. This action naturally holds the VC voltage stable
during the current comparator sense action (current mode
switching).
AN19 provides a method for empirically tweaking frequency
compensation. Basically, it involves introducing a load
current step and monitoring the response.
Slope Compensation
This part incorporates current slope compensation. Slope
compensation is required to ensure current loop stability
when the DC is greater than 50%. In some switcher controllers, slope compensation reduces the maximum peak
current at higher duty cycles. The LT3837 eliminates this
need by having circuitry that compensates for the slope
compensation so that maximum current sense voltage is
constant across all duty cycles.
Minimum Load Considerations
At light loads, the LT3837 derived regulator goes into
forced continuous conduction mode. The primary side
switch always turns on for a short time as set by the
tON(MIN) resistor. If this produces more power than the
load requires, power will flow back into the primary during
the “off” period when the synchronization switch is on.
This does not produce any inherently adverse problems,
though light load efficiency is reduced.
Maximum Load Considerations
The current mode control uses the VC node voltage and
amplified sense resistor voltage as inputs to the current
comparator. When the amplified sense voltage exceeds the
VC node voltage, the primary side switch is turned off.
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
VC reaches its 2.56V clamp. At clamp, the primary side
MOSFET will turn off at the rated 98mV VSENSE level. This
repeats on the next cycle.
It is possible for the peak primary switch currents as
referred across RSENSE to exceed the max 98mV rating
because of the minimum switch on time blanking. If the
voltage on VSENSE reaches 206mV after the minimum
turn-on time, the SFST capacitor is discharged, which also
discharges the VC capacitor. This then reduces the peak
current on the next cycle and will reduce overall stress in
the primary switch.
3837fa
20
LT3837
APPLICATIONS INFORMATION
Short-Circuit Conditions
Loss of current limit is possible under certain conditions
such as an output short circuit. If the duty cycle exhibited by the minimum on-time is greater than the ratio of
secondary winding voltage (referred-to-primary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cycle-by-cycle to some
higher level. Expressed mathematically, the requirement
to maintain short-circuit control is:
DCMIN = tON(MIN) • fOSC <
(
ISC • RSEC + RDS(ON)
)
VIN • NSP
where:
tON(MIN) = primary side switch minimum on-time
The transformer secondary current flows through the impedances of the winding resistance, synchronous MOSFET
RDS(ON) and output capacitor ESR. The DC equivalent
current for these errors is higher than the load current
because conduction occurs only during the converter’s
“off” time. So divide the load current by (1 – DC).
If the output load current is relatively constant, the feedback
resistive divider is used to compensate for these losses.
Otherwise, use the LT3837 load compensation circuitry
(see Load Compensation).
If multiple output windings are used, the flyback winding
will have a signal that represents an amalgamation of all
these windings impedances. Take care that you examine
worst-case loading conditions when tweaking the voltages.
ISC = short-circuit output current
Other variables as previously defined.
Power MOSFET Selection
Trouble is typically encountered only in applications with a
relatively high product of input voltage times secondaryto-primary turns ratio and/or a relatively long minimum
switch on time. Additionally, several real world effects such
as transformer leakage inductance, AC winding losses, and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
design evaluates the switcher for short-circuit protection
and adds any additional circuitry to prevent destruction.
The power MOSFETs are selected primarily on the criteria
of “on” resistance RDS(ON), input capacitance, drain-tosource breakdown voltage (BVDSS), maximum gate voltage
(VGS) and maximum drain current (ID(MAX)).
Output Voltage Error Sources
The LT3837’s feedback sensing introduces additional
sources of errors. The following is a summary list.
The internal bandgap voltage reference sets the reference
voltage for the feedback amplifier. The specifications detail
its variation.
For the primary-side power MOSFET, the peak current
is:
IOUT
⎛ X ⎞
• ⎜ 1+ MIN ⎟
IPK =
1– DCMAX ⎝
2 ⎠
where X is peak-to-peak current ratio as defined earlier.
For each secondary-side power MOSFET, the peak current is:
IPK =
IOUT
⎛ X ⎞
• ⎜ 1+ MIN ⎟
1– DCMAX ⎝
2 ⎠
Select a primary-side power MOSFET with a BVDSS greater
than:
The external feedback resistive divider ratio proportional
directly affects regulated voltage. Use 1% components.
Leakage inductance on the transformer secondary reduces
the effective secondary-to-feedback winding turns ratio
(NS/NF) from its ideal value. This increases the output voltage target by a similar percentage. Since secondary leakage
inductance is constant from part to part (with a tolerance)
adjust the feedback resistor ratio to compensate.
BVDSS ≥ IPK
VOUT(MAX )
LLKG
+ VIN(MAX ) +
CP
NSP
3837fa
21
LT3837
APPLICATIONS INFORMATION
where NSP reflects the turns ratio of that secondary-to-primary winding. LLKG is the primary-side leakage inductance
and CP is the primary-side capacitance (mostly from the
COSS of the primary-side power MOSFET). A snubber
may be added to reduce the leakage inductance spike as
discussed earlier.
For each secondary-side power MOSFET, the BVDSS should
be greater than:
BVDSS ≥ VOUT + VIN(MAX) • NSP
Choose the primary side MOSFET RDS(ON) at the nominal
gate drive voltage (7.5V). The secondary side MOSFET
gate drive voltage depends on the gate drive method.
Primary side power MOSFET RMS current is given by:
IRMSPRI =
IOUT
1– DCMAX
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET may operate at high VDS, a
transition power loss term is included for accuracy. CMILLER
is the most critical parameter in determining the transition
loss, but is not directly specified on the data sheets.
CMILLER is calculated from the gate charge curve included
on most MOSFET data sheets (Figure 6).
b
QA
QB
GATE CHARGE (QG)
3825 F06
Figure 6. Gate Charge Curve
The flat portion of the curve is the result of the Miller
(gate-to-drain) capacitance as the drain voltage drops.
The Miller capacitance is computed as:
CMILLER =
VIN(MAX ) •
PIN(MAX )
DCIN
• RDR •
CMILLER
•f
VGATE(MAX ) – VTH OSC
where:
RDR is the gate driver resistance approximately 10Ω
(1 + δ) is generally given for a MOSFET in the form of a
normalized RDS(ON) vs temperature curve. If you don’t
have a curve, use δ = 0.005/°C as an estimate.
The secondary-side power MOSFETs typically operate
at substantially lower VDS, so you can neglect transition
losses. The dissipation is calculated using:
PD(SEC) = IRMS(SEC)2 • RDS(ON)(1 + δ)
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
TJ = TA + PD • θJA
where TA is the ambient temperature and θJA is the MOSFET
junction to ambient thermal resistance.
Once you have TJ, iterate your calculations recomputing
δ, power dissipations until convergence.
MILLER EFFECT
a
PDPRI = IRMS(PRI)2 • RDS(ON) (1+ δ ) +
fOSC is the operating frequency.
VIN(MIN) DCMAX
VGS
With CMILLER determined, calculate the primary-side power
MOSFET power dissipation:
VTH is the MOSFET gate threshold voltage
PIN
For each secondary-side power MOSFET RMS current is
given by:
IRMSSEC =
The curve is done for a given VDS. The Miller capacitance
for different VDS voltages are estimated by multiplying the
computed CMILLER by the ratio of the application VDS to
the curve specified VDS.
Gate Drive Node Consideration
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves efficiency
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
QB – Q A
VDS
3837fa
22
LT3837
APPLICATIONS INFORMATION
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and efficiency.
The LT3837 gate drives will clamp the max gate voltage
to roughly 7.5V, so you can safely use MOSFETs with max
VGS of 10V or larger.
Synchronous Gate Drive
There are several different ways to drive the synchronous
gate MOSFET. Full converter isolation requires the synchronous gate drive to be isolated. This is usually accomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary as shown in the
application on the front page of this data sheet.
However, other schemes are possible. There are gate
drivers and secondary side synchronous controllers available that provide the buffer function as well as additional
features.
In a flyback converter, the input and output current flows
in pulses, placing severe demands on the input and output
filter capacitors. The input and output filter capacitors
are selected based on RMS current ratings and ripple
voltage.
Select an input capacitor with a ripple current rating
greater than:
PIN
VIN(MIN)
1– DCMAX
DCMAX
Continuing the example:
37.5W 1– 52.4%
= 3.97 A
9V
52.4%
Input capacitor series resistance (ESR) and inductance
(ESL) need to be small as they affect electromagnetic
interference suppression. In some instances, high ESR can
also produce stability problems because flyback converters
exhibit a negative input resistance characteristic. Refer to
Application Note 19 for more information.
IRMS =
IRMS = IOUT
DCMAX
1– DCMAX
Continuing the example::
52.4%
= 10.5A
1– 52.4%
This is calculated for each output in a multiple winding
application.
IRMS = 10 A
ESR and ESL along with bulk capacitance directly affect
the output voltage ripple. The waveforms for a typical
flyback converter are illustrated in Figure 7.
IPRI
PRIMARY
CURRENT
SECONDARY
CURRENT
Capacitor Selection
IRMS =
The output capacitor is sized to handle the ripple current
and to ensure acceptable output voltage ripple. The output
capacitor should have an RMS current rating greater than:
IPRI
N
RINGING
DUE TO ESL
$VCOUT
OUTPUT VOLTAGE
RIPPLE WAVEFORM
$VESR
3825 F07
Figure 7. Typical Flyback Converter Waveforms
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
starting point for the capacitor values. For the purpose
of simplicity we will choose 2% for the maximum output
ripple, divided equally between the ESR step and the
charging/discharging ΔV. This percentage ripple changes,
depending on the requirements of the application. You
can modify the following equations.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor is determined by:
ESRCOUT ≤ 1% •
VOUT • (1– DCMAX )
IOUT
3837fa
23
LT3837
APPLICATIONS INFORMATION
The other 1% is due to the bulk C component, so use:
COUT ≥
IOUT
1% • VOUT • fOSC
In many applications the output capacitor is created from
multiple capacitors to achieve desired voltage ripple, reliability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisfies the required bulk C.
Continuing our example, the output capacitor needs:
3.3V • (1– 52.4%)
= 1.6mΩ
10 A
10 A
= 1515μF
COUT ≥
1% • 3.3 • 200kHz
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
ESRCOUT ≤ 1% •
Most capacitor ripple current ratings are based on 2000
hour life. This makes it advisable to derate the capacitor
or to choose a capacitor rated at a higher temperature
than required.
One way to reduce cost and improve output ripple is to
use a simple LC filter. Figure 8 shows an example of the
filter.
C1
47μF
s3
IC Thermal Considerations
Take care to ensure that the LT3837 junction temperature
does not exceed 125°C. Power is computed from the average supply current, the sum of quiescent supply current
(ICC in the specifications) plus gate drive currents.
The primary gate drive current is computed as:
fOSC • QG
where QG is the total gate charge at max VGS (obtained from
the gate charge curve) and f is the switching frequency.
Since the synchronous driver is usually driving a capacitive
load, the power dissipation is:
fOSC • CS • VSGMAX
where CS is the SG capacitive load and VSGMAX is the SG
pin max voltage.
So total IC dissipation is computed as:
L1
0.1μH
FROM
SECONDARY
WINDING
Circuit simulation is a way to optimize output capacitance
and filters, just make sure to include the component
parasitics. LTC SwitcherCAD™ is a terrific free circuit
simulation tool that is available at www.linear.com. Final
optimization of output ripple must be done on a dedicated
PC board. Parasitic inductance due to poor layout can
significantly impact ripple. Refer to the PC Board Layout
section for more details.
VOUT
COUT
470μF
COUT2
1μF
PD(TOTAL) = VCC • (ICC + f •(QGPRI + CS • VSGMAX))
RLOAD
VCC is the worst-case LT3837 supply voltage.
3837 F08
Figure 8
The design of the filter is beyond the scope of this data
sheet. However, as a starting point, use these general
guide lines. Start with a COUT 1/4 the size of the nonfilter
solution. Make C1 1/4 of COUT to make the second filter
pole independent of COUT. The smaller C1 may be best
implemented with multiple ceramic capacitors. Make L1
smaller than the output inductance of the transformer. In
general, a 0.1μH filter inductor is sufficient. Add a small
ceramic capacitor (COUT2) for high frequency noise on VOUT.
For those interested in more details refer to “Second-Stage
LC Filter Design,” Ridley, Switching Power Magazine, July
2000, p8-10.
Junction temperature is computed as:
TJ = TA + PD • θJA
where:
TA is the ambient temperature
θJA is the FE16 package junction-to-ambient thermal
impedance (40°C/W).
SwitcherCAD is a trademark of Linear Technology Corporation.
3837fa
24
LT3837
APPLICATIONS INFORMATION
PC Board Layout Considerations
In order to minimize switching noise and improve output
load regulation, connect the GND pin of the LT3837 directly
to the ground terminal of the VCC decoupling capacitor,
the bottom terminal of the current sense resistor, the
ground terminal of the input capacitor, and the ground
plane (multiple vias). Place the VCC capacitor immediately
adjacent to the VCC and GND pins on the IC package. This
capacitor carries high di/dt MOSFET gate drive currents.
Use a low ESR ceramic capacitor.
Take care in PCB layout to keep the traces that conduct high
switching currents short, wide and with minimal overall
loop area. These are typically the traces associated with
the switches. This reduces the parasitic inductance and
also minimizes magnetic field radiation. Figure 9 outlines
the critical paths.
Keep electric field radiation low by minimizing the length
and area of traces (keep stray capacitances low). The drain
of the primary side MOSFET is the worst offender in this
category. Always use a ground plane under the switcher
circuitry to prevent coupling between PCB planes.
Check that the maximum BVDSS ratings of the MOSFETs
are not exceeded due to inductive ringing. This is done by
viewing the MOSFET node voltages with an oscilloscope. If
it is breaking down either choose a higher voltage device,
add a snubber or specify an avalanche-rated MOSFET.
Place the small-signal components away from high frequency switching nodes. This allows the use of a pseudoKelvin connection for the signal ground, where high di/dt
gate driver currents flow out of the IC ground pin in one
direction (to the bottom plate of the VCC decoupling
capacitor) and small-signal currents flow in the other
direction.
Keep the trace from the feedback divider tap to the FB
short to preclude inadvertent pickup.
For applications with multiple switching power converters
connected to the same input supply, make sure that the
input filter capacitor for the LTC3837 is not shared with
other converters. AC input current from another converter
could cause substantial input voltage ripple and this could
interfere with the LT3837 operation. A few inches of PC
trace or wire (L ≅ 100nH) between the CIN of the LT3837
and the actual source VIN is sufficient to prevent current
sharing problems.
T1
VCC
•
VIN
CVCC
•
GATE
TURN-ON
•
LT3825 VCC
PG
GND
MP
CVIN
GATE
TURN-OFF
OUT
RSENSE
VCC
COUT
CR
LT3825 VCC
T2
SG
•
GND
Q4
GATE
TURN-ON
MS
•
GATE
Q3
TURN-OFF
3837 F09
Figure 9. High Current Paths
3837fa
25
LT3837
TYPICAL APPLICATION
9V – 36V to 3.3V at 10A Isolated Converter
1/2
VIN
9V TO
36V
FP2S-100-R
0.1μH
T1 7/8/9
VOUT
3.3V AT 10A
•
470pF
39Ω
10k
MMBT3904
10μF
20Ω
47μF s 3
3/4
• 10/11/12
220μF
6TPE220MI
BAS70
6
0.1μF
7.5V
1nF
B0540W 10Ω
T1
•
100k
1%
29.4k
1%
5
VCC
FB
12k
4.7Ω
Si7336ADP
PG SENSE+
8mΩ
100k
GND SFST CCMP
0.1μF
20k
47pF
2.2nF
3.3nF
150k
1.37k
1%
15Ω
3307
VC
OSC
1μF
SG
SENSE–
LT3837
PGDLY
tON SYNC RCMP ENDLY
3.01k
1%
SG
SG
UVLO
17.4k
1%
Si4896DY
1nF
0.1μF
•
PA0184
•
BAT54
10k
3837 TA05
T1: EFD20-3F3 (LP = 5μH)
PIN 5 TO 6, 7T OF 32AWG
PIN 2 TO 4, 6T OF 4 s 25AWG
TAPE
PIN 10/11/12 TO 7/8/9, 2T OF 7MIL CU FOIL
PIN 1 TO 3, 6T OF 4 s 25AWG
3837fa
26
LT3837
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BC
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
3.58
(.141)
16 1514 13 12 1110
6.60 ±0.10
9
2.94
(.116)
4.50 ±0.10
6.40
2.94
(.252)
(.116)
BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.25
REF
1.10
(.0433)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE16 (BC) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3837fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3837
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT3825
Isolated Synchronous Flyback Controller with Wide Input
Supply Range
Suitable for Telecom or Offline Input Voltage
LT1424-5
Isolated Flyback Switching Regulator
5V Output Voltage, No Optoisolator Required
LT1424-9
Isolated Flyback Switching Regulator
9V Output Voltage, Regulation Maintained Under Light Loads
LT1425
Isolated Flyback Switching Regulator
No Third Winding or Optoisolator Required
LTC1698
Isolated Secondary Synchronous Rectifier Controller
Isolated Power Supplies, Contains Voltage Merging, Optocoupler Driver,
Primary Synchronization Circuit
LT1725
General Purpose High Power Isolated Flyback Controller
Suitable for Telecom or Offline Input Voltage
LT1737
High Power Isolated Flyback Controller
Powered from a DC Supply Voltage
LTC1871
Wide Input Range Current Mode No RSENSE™ Controller
50kHz to 1MHz, Boost, Flyback and SEPIC Topology
LTC3710
Secondary Side Synchronous Post Regulator
Generates a Regulated Auxiliary Output in Isolated DC/DC Converters.
Dual N-Channel MOSFET Synchronous Drivers
LT3781/LT1698
36V to 72V Input Isolated DC/DC Converter Chipset
Synchronous Operation: Overvoltage/Undervoltage Protection, 10W to
100W Power Supply, 1/2 to 1/4 Brick Footprint
LTC3803
SOT-23 Flyback Controller
Adjustable Slope Compensation, Internal Soft-Start, 200kHz
LTC3806
Synchronous Flyback DC/DC Controller
Medium Power Multiple Outputs, 250kHz Soft-Start
No RSENSE is a trademark of Linear Technology Corporation.
3837fa
28
Linear Technology Corporation
LT 0108 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
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