LINER LT4250L Negative 48v hot swap controller Datasheet

LT4250L/LT4250H
Negative 48V
Hot Swap Controller
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FEATURES
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DESCRIPTIO
Allows Safe Board Insertion and Removal
from a Live – 48V Backplane
Circuit Breaker Immunity to Voltage Steps and
Current Spikes
Programmable Inrush and
Short-Circuit Current Limits
Pin Compatible with LT1640L/LT1640H
Operates from –20V to – 80V
Programmable Overvoltage Protection
Programmable Undervoltage Lockout
Power Good Control Output
Bell-Core Compatible ON/OFF Threshold
The LT®4250L/LT4250H are 8-pin, negative 48V Hot SwapTM
controllers that allow a board to be safely inserted and
removed from a live backplane. Inrush current is limited to
a programmable value by controlling the gate voltage of an
external N-channel pass transistor. The pass transistor is
turned off if the input voltage is less than the programmable undervoltage threshold or greater than the overvoltage threshold. A programmable current limit protects
the system against shorts. After a 500µs timeout the
current limit activates the electronic circuit breaker. The
PWRGD (LT4250L) or PWRGD (LT4250H) signal can be
used to directly enable a power module. The LT4250L is
designed for modules with a low enable input and the
LT4250H for modules with a high enable input.
Central Office Switching
– 48V Distributed Power Systems
Negative Power Supply Control
The LT4250L/LT4250H are available in 8-pin PDIP and SO
packages.
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APPLICATIO S
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, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
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TYPICAL APPLICATIO
–48V RTN
(SHORT PIN)
–48V RTN
UV =
38.5V
UV
RELEASE
AT 43V
OV =
71V
R4†
549k
1%
3
R5†
6.49k
1%
R6†
10k
1%
Voltage Step On Input Supply
8
VDD
2
UV
LT4250L
PWRGD
GATE
DRAIN
OV
VEE
SENSE
4
5
6
VEE AND
DRAIN
20V/DIV
7
R3†
1k, 5%
*
–48V
INPUT 1
1
0.1µF
10V
R1†
0.02Ω
5%
C1†
470nF
25V
R2
10Ω
5%
* DIODES INC. SMAT70A
†
THESE COMPONENTS ARE APPLICATION
SPECIFIC AND MUST BE SELECTED BASED
UPON OPERATING CONDITIONS AND DESIRED
PERFORMANCE. SEE APPLICATIONS
INFORMATION.
C3
0.1µF
100V
+
ID (Q1)
5A/DIV
2
Q1
IRF530
–48V
INPUT 2
C2†
15nF
100V
C4
100µF
100V
ON/OFF
1
9
VOUT+
VIN+
8
+
SENSE
7
TRIM
– 6
SENSE
4
5
VOUT–
VIN–
LUCENT
JW050A1-E
5V
+
500µs/DIV
C5
100µF
16V
4250 TA01
4250lhf
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LT4250L/LT4250H
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ABSOLUTE MAXIMUM RATINGS
(Note 1), All Voltages Referred to VEE
Supply Voltage (VDD – VEE) .................... – 0.3V to 100V
PWRGD, PWRGD Pins ........................... – 0.3V to 100V
SENSE, GATE Pins .................................... – 0.3V to 20V
UV, OV Pins .............................................. – 0.3V to 60V
DRAIN Pin .................................................. –2V to 100V
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range
LT4250LC/LT4250HC ............................. 0°C to 70°C
LT4250LI/LT4250HI .......................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
PWRGD 1
8
VDD
OV 2
7
DRAIN
UV 3
6
GATE
VEE 4
5
SENSE
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 120°C/W (N8)
TJMAX = 125°C, θJA = 150°C/W (S8)
LT4250LCN8
LT4250LCS8
LT4250LIN8
LT4250LIS8
ORDER PART
NUMBER
TOP VIEW
PWRGD 1
8
VDD
OV 2
7
DRAIN
UV 3
6
GATE
VEE 4
5
SENSE
S8 PART MARKING
N8 PACKAGE
8-LEAD PDIP
4250L
4250LI
S8 PACKAGE
8-LEAD PLASTIC SO
LT4250HCN8
LT4250HCS8
LT4250HIN8
LT4250HIS8
S8 PART MARKING
TJMAX = 125°C, θJA = 120°C/W (N8)
TJMAX = 125°C, θJA = 150°C/W (S8)
4250H
4250HI
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC
VDD
Supply Voltage Operating Range
IDD
Supply Current
VUVL
Undervoltage Lockout
VCL
Current Limit Trip Voltage
VCL = (VSENSE – VEE)
●
40
50
60
mV
IPU
GATE Pin Pull-Up Current
Gate Drive On, VGATE = VEE
●
– 30
– 45
– 60
µA
IPD
GATE Pin Pull-Down Current
Gate Drive OFF
24
50
70
mA
ISENSE
SENSE Pin Current
VSENSE = 50mV
∆VGATE
External Gate Drive
(VGATE – VEE), 20V ≤ VDD ≤ 80V
●
10
13.5
18
V
VUVH
UV Pin High Threshold Voltage
UV Increasing
●
1.240
1.255
1.270
V
VUVL
UV Pin Low Threshold Voltage
UV Decreasing
●
1.105
1.125
1.145
VUVHY
UV Pin Hysteresis
IINUV
UV Pin Input Current
VOVH
VOVL
●
UV = 3V, OV = VEE, SENSE = VEE
20
●
1.6
●
15.4
80
V
5
mA
V
µA
– 20
130
VUV = VEE
●
OV Pin High Threshold Voltage
OV Increasing
●
OV Pin Low Threshold Voltage
OV Decreasing
●
V
mV
– 0.02
– 0.5
µA
1.235
1.255
1.275
V
1.210
1.235
1.255
V
4250lhf
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LT4250L/LT4250H
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted.
SYMBOL
PARAMETER
VOVHY
OV Pin Hysteresis
CONDITIONS
MIN
IINOV
OV Pin Input Current
VOV = VEE
VDL
DRAIN Low Threshold
VDRAIN – VEE, DRAIN Decreasing
VGH
GATE High Threshold
∆VGATE – VGATE Decreasing
IDRAIN
Drain Input Bias Current
VDRAIN = 48V
●
VOL
PWRGD Output Low Voltage
PWRGD (LT4250L), (VDRAIN – VEE) < VDL
IOUT = 1mA
IOUT = 5mA
PWRGD Output Low Voltage
(PWRGD – DRAIN)
TYP
MAX
UNITS
20
●
1.1
mV
– 0 .03
– 0.5
µA
1.6
2.3
V
1.3
V
80
500
µA
●
●
0.48
1.2
0.8
3.0
V
V
PWRGD (LT4250H), VDRAIN = 5V
IOUT = 1mA
●
0.75
1.0
V
Output Leakage
PWRGD (LT4250L), VDRAIN = 48V, VPWRGD = 80V
PWRGD (LT4250H), VDRAIN = 0V, VPWRGD = 80V
●
●
0.05
0.05
10
10
µA
µA
tPHLOV
OV High to GATE Low
Figures 1a, 2
1.7
µs
tPHLUV
UV Low to GATE Low
Figures 1a, 3
1.5
µs
tPLHOV
OV Low to GATE High
Figures 1a, 2
5.5
µs
tPLHUV
UV High to GATE High
Figures 1a, 3
6.5
µs
tPHLSENSE
SENSE High to Gate Low
Figures 1a, 4a
1
tPHLCB
Current Limit to GATE Low
Figures 1b, 4b
500
µs
tPHLDL
DRAIN Low to PWRGD Low
(LT4250L) Figures 1a, 5a
DRAIN Low to (PWRGD – DRAIN) High (LT4250H) Figures 1a, 5a
1
1
µs
µs
tPHLGH
GATE High to PWRGD Low
GATE High to (PWRGD – DRAIN) High
1.5
1.5
µs
µs
IOH
10
AC
(LT4250L) Figures 1a, 5b
(LT4250H) Figures 1a, 5b
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
µs
3
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to VEE unless otherwise
specified.
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
Supply Current vs Temperature
1.8
TA = 25°C
1.4
1.3
1.2
13
GATE VOLTAGE (V)
1.5
TA = 25°C
14
1.5
1.6
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
15
VDD = 48V
1.7
1.4
1.3
1.2
12
11
10
9
8
1.1
1.1
0
Gate Voltage vs Supply Voltage
1.6
7
0
20
40
80
60
SUPPLY VOLTAGE (V)
100
1640 G01
1.0
– 50
– 25
0
25
50
TEMPERATURE (°C)
75
100
1640 G02
6
0
20
80
60
40
SUPPLY VOLTAGE (V)
100
1640 G03
4250lhf
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LT4250L/LT4250H
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TYPICAL PERFOR A CE CHARACTERISTICS
Gate Pull-Up Current
vs Temperature
Current Limit Trip Voltage
vs Temperature
Gate Voltage vs Temperature
15.0
55
48
54
47
TRIP VOLTAGE (mV)
GATE VOLTAGE (V)
14.5
14.0
13.5
13.0
12.5
GATE PULL-UP CURRENT (µA)
VDD = 48V
53
52
51
50
49
12.0
– 50
– 25
25
50
0
TEMPERATURE (°C)
75
– 25
50
0
25
TEMPERATURE (°C)
75
1640 G04
42
52
49
46
43
75
100
– 25
0
25
50
TEMPERATURE (°C)
75
PWRGD Output Impedance
vs Temperature (LT4250H)
8
VDRAIN – VEE > 2.4V
IOUT = 1mA
7
0.4
0.3
0.2
0.1
0
– 50
100
1640 G06
OUTPUT IMPEDANCE (kΩ)
PWRGD OUTPUT LOW VOLTAGE (V)
GATE PULL-DOWN CURRENT (mA)
43
40
– 50
100
0.5
VGATE = 2V
0
50
25
TEMPERATURE (°C)
44
PWRGD Output Low Voltage
vs Temperature (LT4250L)
55
– 25
45
1640 G05
Gate Pull-Down Current
vs Temperature
40
– 50
46
41
48
– 50
100
VGATE = 0V
6
5
4
3
– 25
25
50
0
TEMPERATURE (°C)
1640 G07
75
100
1640 G08
2
– 50
– 25
0
25
50
TEMPERATURE (°C)
75
100
1640 G09
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PIN FUNCTIONS
PWRGD/PWRGD (Pin 1): Power Good Output Pin. This pin
will latch a power good indication when VDRAIN is within VDL
of VEE and VGATE is within VGH of ∆VGATE. This pin can be
connected directly to the enable pin of a power module.
When the DRAIN pin of the LT4250L is above VEE by more
than VDL or VGATE is more than VGH from ∆VGATE, the
PWRGD pin will be high impedance, allowing the pull-up
current of the module’s enable pin to pull the pin high and
turn the module off. When VDRAIN drops below VDL and
VGATE rises above VGH, the PWRGD pin sinks current to
VEE, pulling the enable pin low and turning on the module.
This condition is latched until the GATE pin is turned off via
the UV, OV, UVLO or the electronic circuit breaker.
When the DRAIN pin of the LT4250H is above VEE by more
than VDL or VGATE is more than VGH from ∆VGATE, the
PWRGD pin will sink current to the DRAIN pin which pulls
the module’s enable pin low, forcing it off. When VDRAIN
drops below VDL and VGATE rises above VGH, the PWRGD
sink current is turned off, allowing the module’s pull-up
current to pull the enable pin high and turn on the module.
This condition is latched until the GATE pin is turned off via
the UV, OV, UVLO or the electronic circuit breaker.
4250lhf
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LT4250L/LT4250H
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PIN FUNCTIONS
OV (Pin 2): Analog Overvoltage Input. When OV is pulled
above the 1.255V threshold, an overvoltage condition is
detected and the GATE pin will be immediately pulled low.
The GATE pin will remain low until OV drops below the
1.235V threshold.
If the current limit value is set to twice the normal
operating current, only 25mV is dropped across the
sense resistor during normal operation. To disable the
current limit feature, VEE and SENSE can be shorted
together.
UV (Pin 3): Analog Undervoltage Input. When UV is
pulled below the 1.125V threshold, an undervoltage
condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until UV
rises above the 1.255 threshold.
GATE (Pin 6): Gate Drive Output for the External
N-Channel MOSFET. The GATE pin will go high when the
following start-up conditions are met: the UV pin is high,
the OV pin is low, (VSENSE – VEE) < 50mV and the VDD pin
is greater than VUVLOH. The GATE pin is pulled high by a
45µA current source and pulled low with a 50mA current
source. During current limit the GATE pin is pulled low
using a 100mA current source.
The UV pin is also used to reset the electronic circuit
breaker. If the UV pin is cycled low and high following the
trip of the circuit breaker, the circuit breaker is reset and
a normal power-up sequence will occur. The response
time for this pin is 1.5µs. Add an external capacitor to this
pin for additional filtering.
DRAIN (Pin 7): Analog Drain Sense Input. Connect this
pin to the drain of the external N-channel MOSFET and the
V – pin of the power module. When the DRAIN pin is
below VDL, the PWRGD/PWRGD pin will latch to indicate
the switch is on.
VEE (Pin 4): Negative Supply Voltage Input. Connect to
the lower potential of the power supply.
VDD (Pin 8): Positive Supply Voltage Input. Connect this
pin to the higher potential of the power supply inputs and
the V + pin of the power module. An undervoltage lockout
circuit disables the chip until the VDD pin is greater than
the 16V VUVLOH threshold.
SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense
resistor placed in the supply path between VEE and
SENSE, the overcurrent condition will pull down the
GATE pin and regulate the voltage across the resistor to
be 50mV. If the overcurrent condition exists for more
than 500µs the electronic circuit breaker will trip and turn
off the external MOSFET.
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BLOCK DIAGRA
VDD
–
UV
UVLO
+
VCC AND
REFERENCE
GENERATOR
VCC
REF
OUTPUT
DRIVE
REF
–
OV
+
PWRGD/PWRGD
LOGIC
50mV
–+
–
+
500µs
DELAY
GATE
DRIVER
+
+
–
–
VDL
+
–
+–
VGH
∆VGATE
VEE
4250 BD
VEE SENSE
GATE
DRAIN
4250lhf
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LT4250L/LT4250H
R
5k
V+
5V
PWRGD/PWRGD VDD
OV
VOV
+
–
DRAIN
UV
48V
OV
VDRAIN
LT4250L/LT4250H
+
–
DRAIN
20V
48V
LT4250L/LT4250H
10k
10Ω
GATE
UV
VUV
VEE
+
–
PWRGD/PWRGD VDD
0.1µF
VUV
SENSE
IRF530
GATE
SENSE
VEE
VSENSE
10Ω
1640 F01a
Figure 1a. Test Circuit 1
4250 F01b
Figure 1b. Test Circuit 2
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TIMING DIAGRAMS
2V
1.255V
OV
2V
1.235V
1.125V
UV
0V
1.255V
0V
tPHLOV
GATE
tPLHOV
1V
1V
tPHLUV
GATE
tPLHUV
1V
4250 F02
Figure 2. OV to GATE Timing
1V
4250 F03
Figure 3. UV to GATE Timing
100mV
60mV
SENSE
UV
VEE
tPHLCB
tPHLSENSE
GATE
GATE
1V
1V
1V
4250 F04b
4250 F04a
Figure 4b. Active Current Limit Timeout
Figure 4a. SENSE to GATE Timing
1.4V
∆VGATE – VGATE = 0
DRAIN
1.4V
GATE
VEE
tPHLGH
tPHLDL
PWRGD
PWRGD
DRAIN
1V
1V
VEE
VEE
1.4V
∆VGATE – VGATE = 0
GATE
1.4V
VEE
tPHLGH
tPHLDL
PWRGD
VPWRGD – VDRAIN = 0V
PWRGD
1V
4250 F05a
Figure 5a. DRAIN to PWRGD/PWRGD Timing
VPWRGD – VDRAIN = 0
1V
4250 F05b
Figure 5b. GATE to PWRGD/PWRGD Timing
4250lhf
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LT4250L/LT4250H
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APPLICATIONS INFORMATION
Hot Circuit Insertion
where CL is the total load capacitance = C3 + C4 + module
input capacitance.
When circuit boards are inserted into a live – 48V backplane,
the bypass capacitors at the input of the board’s power
module or switching power supply can draw huge transient currents as they charge up. The transient currents
can cause permanent damage to the board’s components
and cause glitches on the system power supply.
Capacitor C1 and resistor R3 prevent Q1 from momentarily turning on when the power pins first make contact.
Without C1 and R3, capacitor C2 would pull the gate of Q1
up to a voltage roughly equal to VEE • C2/CGS(Q1) before the
LT4250 could power up and actively pull the gate low. By
placing capacitor C1 in parallel with the gate capacitance
of Q1 and isolating them from C2 using resistor R3 the
problem is solved. The value of C1 is given by:
The LT4250 is designed to turn on a board’s supply
voltage in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The chip
also provides undervoltage, overvoltage and overcurrent
protection while keeping the power module off until its
input voltage is stable and within tolerance.
V
− VTH 
C1 =  INMAX
 • C 2 + C GD
VTH


(
C1≅ 35 • C2 for VINMAX = 72V
Power Supply Ramping
where VTH is the MOSFET’s minimum gate threshold and
VINMAX is the maximum operating input voltage.
The input to the power module on a board is controlled by
placing an external N-channel pass transistor (Q1) in the
power path (Figure 6a, all waveforms are with respect to
the VEE pin of the LT4250). R1 provides current fault
detection and R2 prevents high frequency oscillations.
Resistors R4, R5 and R6 provide undervoltage and overvoltage sensing. By ramping the gate of Q1 up at a slow
rate, the inrush current charging load capacitors C3 and
C4 can be limited to a safe value when the board makes
connection.
R3 should not exceed a value that produces an
R3 • C2 time-constant of 150µs. A 1k value for R3 will
ensure this for C2 values up to 150nF.
The waveforms are shown in Figure 6b. When the power
pins make contact, they bounce several times. While the
contacts are bouncing, the LT4250 senses an undervoltage
condition and the GATE is immediately pulled low when
the power pins are disconnected.
Resistor R3 and capacitor C2 act as a feedback network to
accurately control the inrush current. The C2 capacitor can
be calculated with the following equation:
Once the power pins stop bouncing, the GATE pin starts to
ramp up. When Q1 turns on, the GATE voltage is held
constant by the feedback network of R3 and C2. When the
DRAIN voltage has finished ramping, the GATE pin then
ramps to its final value.
C2 = (45µA • CL)/IINRUSH
–48V RTN
(SHORT PIN)
–48V RTN
R4
549k
1%
UV = 38.5V
OV = 71V
R5
6.49k
1%
R6
10k
1%
C3
0.1µF
100V
8
VDD
3
UV
2
LT4250H
PWRGD
GATE
DRAIN
1
C4 +
100µF
100V
VIN+ VOUT+
SENSE
4
*
R1
0.02Ω
5%
3
– 48V
* DIODES INC. SMAT70A
5
6
C1
470nF
25V
R3
1k, 5%
R2
10Ω
5%
4
VIN– VOUT–
7
C2
15nF
100V
4250 F06a
1
2
Q1
IRF530
Figure 6a. Inrush Control Circuitry
5V
+
GATE IN
MODULE
TURN-ON
MODULE
TURN-ON
INRUSH
CURRENT
500mA/DIV
VICOR
VI-J30-CY
OV
VEE
)
C5
100µF
16V
GATE –VEE
10V/DIV
DRAIN
50V/DIV
VEE
50V/DIV
CONTACT
BOUNCE
BOUNCE
25ms/DIV
4250 F06b
Figure 6b. Inrush Control Waveforms
4250lhf
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LT4250L/LT4250H
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APPLICATIONS INFORMATION
Current Limit/Electronic Circuit Breaker
The LT4250 features a current limit function that protects
against short circuits or excessive supply currents. If the
current limit is active for more than 500µs the electronic
circuit breaker will trip. By placing a sense resistor
between the VEE and SENSE pin, the current limit will be
activated whenever the voltage across the sense resistor
is greater than 50mV.
Note that the current limit threshold should be set sufficiently high to account for the sum of the load current and
the inrush current. The maximum value of the inrush
current is given by:
 40mV 
IINRUSH ≤ 0.8 • 
 – ILOAD,
 RSENSE 
where the 0.8 factor is used as a worst case margin
combined with the minimum trip voltage (40mV).
In the case of a short circuit, the current limit circuitry
activates and immediately pulls the GATE low, servos the
SENSE voltage to 50mV, and starts a 500µs timer. The
MOSFET current is limited to 50mV/RSENSE (see Figure 7).
If the short circuit persists for more than 500µs, the circuit
breaker trips and pulls the GATE pin low, shutting off the
MOSFET. The circuit breaker is reset by pulling UV low, or
by cycling power to the part. If the short circuit clears
before the 500µs timing interval the current limit will
deactivate and release the GATE.
DRAIN
50V/DIV
GATE
10V/DIV
The LT4250 guards against voltage steps on the input
supply. A positive voltage step (increasing in magnitude)
on the input supply causes an inrush current that is
proportional to the voltage slew rate I = CL • ∆V/∆T. If the
inrush exceeds 50mV/RSENSE, the current limit will activate as shown in Figure 8. The GATE pin pulls low, limiting
the current to 50mV/RSENSE. At this level the MOSFET
drain will not follow the source as the input voltage rapidly
changes, but instead remains at the voltage stored on the
load capacitance. The load capacitance begins to charge
at a current of 50mV/RSENSE, but not for long. As the load
capacitance charges, C2 pushes back on the gate and
limits the MOSFET current in a manner identical to the
initial start-up condition which is less than the short circuit
limiting value of 50mV/RSENSE. Thus the circuit breaker
does not trip. To ensure correct operation under input
voltage step conditions, RSENSE must be chosen to provide a current limit value greater than the sum of the load
current and the dynamic current in the load capacitance.
For C2 values less than 10nF a positive voltage step on the
input supply can result in the Q1 turning off momentarily
which can shut down the output. By adding an additional
resistor and diode, Q1 remains on during the voltage step.
This is shown as D1 and R7 in Figure 9. The purpose of D1
is to shunt current around R7 when the power pins first
make contact and allow C1 to hold the GATE low. The value
of R7 should be sized to generate an R7 • C1 time constant
of 33µs.
Under some conditions, a short circuit at the output can
cause the input supply to dip below the UV threshold. The
LT4250 turns off once and then turns on until the electronic circuit breaker is tripped. This can be minimized by
adding a deglitching delay to the UV pin with a capacitor
from UV to VEE. This capacitor forms an RC time constant
with the resistors at UV, allowing the input supply to
recover before the UV pin resets the circuit breaker.
ID (Q1)
5A/DIV
1ms/DIV
Figure 7. Short-Circuit Protection Waveforms
4250lhf
8
LT4250L/LT4250H
U
U
W
U
APPLICATIONS INFORMATION
A circuit that automatically resets the circuit breaker after
a current fault is shown in Figure 10. Transistors Q2 and
Q3 along with R7, R8, C4 and D1 form a programmable
one-shot circuit. Before a short occurs, the GATE pin is
pulled high and Q3 is turned on, pulling node 2 to VEE.
Resistor R8 turns off Q2. When a short occurs, the GATE
pin is pulled low and Q3 turns off. Node 2 starts to charge
C4 and Q2 turns on, pulling the UV pin low and resetting
the circuit breaker. As soon as C4 is fully charged, R8 turns
off Q2, UV goes high and the GATE starts to ramp up. Q3
turns back on and quickly pulls node 2 back to VEE. Diode
D1 clamps node 3 one diode drop below VEE. The duty
cycle is set to 10% to prevent Q1 from overheating.
–48V RTN
(SHORT PIN)
–48V RTN
8
R4
549k
1%
R5
6.49k
1%
VEE AND
DRAIN
20V/DIV
UV
LT4250H
2
1
+
SENSE
VEE
4
GATE
5
R1
0.02Ω
5%
3
500µs/DIV
– 48V
1
DRAIN
R3
1k
5%
6
R7
220Ω
5%
*
D1
BAT85
R2
10Ω
5%
C4
22µF
100V
7
C2
3.3nF
100V
C1
150nF
25V
4
2
Q1
IRF530
* DIODES INC. SMAT70A
Figure 8. Voltage Step on
Input Supply Waveforms
PWRGD
OV
R6
10k
1%
ID (Q1)
5A/DIV
C3
0.1µF
100V
VDD
3
4250 F09
Figure 9. Circuit for Input Steps with Small C2 (<10nF)
–48V RTN
(SHORT PIN)
–48V RTN
R7
1M
5%
2
R6
549k
1%
R4
549k
1%
C4
1µF
100V
Q2
2N2222
8
VDD
3
UV
LT4250L
2
R9
10k
1%
R5
16.5k
1%
OV
VEE
SENSE
4
3
D1
1N4148
R8
510k
5%
– 48V
1
* DIODES INC. SMAT70A
DRAIN
6
C1
470nF
25V
R1
0.02Ω
5%
3
GATE
5
Q3
ZVN3310
*
PWRGD
4
2
Q1
IRF530
+
C3
100µF
100V
7
R3
1k, 5%
R2
10Ω
5%
1
C2
15nF
100V
4250 F10a
NODE 2
50V/DIV
GATE
2V/DIV
1s/DIV
Figure 10. Automatic Restart After Current Fault
4250lhf
9
LT4250L/LT4250H
U
U
W
U
APPLICATIONS INFORMATION
Undervoltage and Overvoltage Detection
internal transistor Q3 is turned off and I1 and Q2 clamp the
PWRGD pin one SAT drop (≈ 0.3V) above the DRAIN pin.
Transistor Q2 sinks the module’s pull-up current and the
module turns off.
The UV (Pin 3) and OV (Pin 2) pins can be used to detect
undervoltage and overvoltage conditions at the power
supply input. The UV and OV pins are internally connected
to analog comparators with 130mV and 20mV of hysteresis respectively. When the UV pin falls below its threshold
or the OV pin rises above its threshold, the GATE pin is
immediately pulled low. The GATE pin will be held low until
UV is high and OV is low.
When the DRAIN voltage drops below VDL and the GATE
voltage is high, Q3 will turn on, shorting the bottom of I1
to DRAIN and turning Q2 off. The pull-up current in the
module pulls the PWRGD pin high and enables the
module.
The undervoltage and overvoltage trip voltages can be
programmed using a three resistor divider as shown in
Figure 11. With R4 = 549k, R5 = 6.49k and R6 = 10K, the
undervoltage threshold is set to 38.5V (with a 43V release
from undervoltage) and the overvoltage threshold is set to
71V. The resistor divider will also gain up the hysteresis
at the UV pin and OV pin to 4.5V and 1.2V at the input
respectively.
When the DRAIN voltage of the LT4250L is high with
respect to VEE or the GATE voltage is low, the internal pulldown transistor Q2 is off and the PWRGD pin is in a high
impedance state (Figure␣ 13). The PWRGD pin will be
pulled high by the module’s internal pull-up current source,
turning the module off. When the DRAIN voltage drops
below VDL and the GATE voltage is high, Q2 will turn on and
the PWRGD pin will pull low, enabling the module.
The PWRGD signal can also be used to turn on an LED or
optoisolator to indicate that the power is good as shown
in Figure 14.
PWRGD/PWRGD Output
The PWRGD/PWRGD output can be used to directly enable a power module when the input voltage to the module
is within tolerance. The LT4250L has a PWRGD output for
modules with an active low enable input, and the LT4250H
has a PWRGD output for modules with an active high
enable input.
Gate Pin Voltage Regulation
When the supply voltage to the chip is more than 20V, the
GATE pin voltage is regulated at 13.5V above VEE. The gate
voltage will be no greater than 18V for supply voltages up
to 80V.
When the DRAIN voltage of the LT4250H is high with
respect to VEE (Figure 12) or the GATE voltage is low, the
ACTIVE HIGH
ENABLE MODULE
–48V RTN
(SHORT PIN)
8
–48V RTN
VOV = 1.255
(
(
R4 + R5+ R6
R5 + R6
R4 + R5+ R6
R6
)
)
R4
3
VDD
3
2
LT4250L/LT4250H
R5
2
R6
R5
UV
R6
OV
GATE
UV
– VGH
+
OV
+
–
PWRGD 1
I1
+
+
Q3
+
VDL
DRAIN 7
SENSE
5
GATE
6
*
C1
4250 F11
3
R2
R3
C2
4
R1
4250 F12
* DIODES INC. SMAT70A
Figure 11. Undervoltage and Overvoltage Sensing
–
VIN– VOUT
VEE
–
4
– 48V
ON/OFF
C3
Q2
–
∆VGATE VEE
VEE
4
– 48V
VDD
LT4250H
R4
8
VUV = 1.255
VIN+ VOUT+
–48V RTN
–48V RTN
(SHORT PIN)
1
2
Q1
Figure 12. Active High Enable Module
4250lhf
10
LT4250L/LT4250H
U
W
U U
APPLICATIO S I FOR ATIO
ACTIVE LOW
ENABLE MODULE
–48V RTN
(SHORT PIN)
VIN+ VOUT+
–48V RTN
8
VDD
LT4250L
R4
3
GATE
2
OV
–
+
+
+
–
R6
∆VGATE
VDL
VEE
C3
VEE
–
ON/OFF
VIN
–
R5
6.49k
1%
7
DRAIN
PWRGD
8
3
2
UV
C1
R2
R3
3
4
C2
4
R1
1
– 48V
2
4250 F13
Q1
PWRGD
GATE
DRAIN
SENSE
VEE
3
– 48V
* DIODES INC. SMAT70A
LT4250L
1
OV
5
R1
0.02Ω
5%
1
* DIODES INC. SMAT70A
R3
1k, 5%
6
R2
10Ω
5%
C1
470nF
25V
*
*
R7
51k
5%
VDD
R6
10k
1%
–
VOUT
GATE
6
SENSE
5
4
Q2
R4
549k
1%
+
–
VGH
1
+
UV
R5
PWRGD
–48V RTN
(SHORT PIN)
–48V RTN
MOC207
7
C3 +
100µF
100V
C2
15nF
100V
4
Q1
IRF530
2
4250 F14
Figure 14. Using PWRGD to Drive an Optoisolator
Figure 13. Active Low Enable Module
U
PACKAGE DESCRIPTIO
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
(
0.400*
(10.160)
MAX
0.130 ± 0.005
(3.302 ± 0.127)
+0.035
0.325 –0.015
+0.889
8.255
–0.381
)
8
7
6
5
1
2
3
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.100
(2.54)
BSC
0.125
(3.175) 0.020
MIN
(0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
N8 1098
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.053 – 0.069
(1.346 – 1.752)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
8
7
6
5
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
SO8 1298
1
2
3
4
4250lhf
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT4250L/LT4250H
U
TYPICAL APPLICATION
Using an EMI Filter Module
using the Lucent FLTR100V10 filter module is shown in
Figure 15. When using a filter, an optoisolator is required
to prevent common mode transients from destroying the
PWRGD and ON/OFF pins.
Many applications place an EMI filter module in the power
path to prevent switching noise of the module from being
injected back onto the power supply. A typical application
–48V RTN
(SHORT PIN)
–48V RTN
R7
51k
5%
8
VDD
R4
549k
1%
R5
6.49k
1%
PWRGD
3
DRAIN
UV
1
7
LT4250L
2
R6
10k
1%
OV
GATE
VEE
VIN+
C2
15nF
100V
5
4
R1
0.02Ω
5%
3
1
C1
470nF
25V
R2
10Ω
5%
1N4003
1
2
VOUT+
C3
LUCENT
0.1µF
FLTR100V10
100V
VIN– VOUT–
R3
1k
5%
SENSE
*
– 48V
6
LUCENT
JW050A1-E
MOC207
C4
0.1µF
100V
+
C5
100µF
100V
C6
0.1µF
100V
4
CASE
VIN+
VOUT+
SENSE +
TRIM
ON/OFF
SENSE –
VIN–
VOUT
–
9
5V
8
7
+
C7
100µF
16V
6
5
CASE
3
4250 F15
4
2
* DIODES INC. SMAT70A
Q1
IRF530
Figure 15. Typical Application Using a Filter Module
RELATED PARTS
PART NUMBER
®
LTC 1421
DESCRIPTION
COMMENTS
Dual Hot Swap Controller with Additional –12V Control
Operates from 3V to 12V
LTC1422
Hot Swap Controller in SO-8
System Reset Output with Programmable Delay
LT1640AH/LT1640AL
–48V Hot Swap Controller in SO-8
LT4250 is a Pin-Compatible Upgrade to LT1640
LT1641-1/LT1641-2
+48V Hot Swap Controller in SO-8
Foldback Current Limit, 9V to 80V, Auto-Retry/Latch-Off
LTC1642
Fault Protected Hot Swap Controller
Operates Up to 16.5V, Protected to 33V
LTC1643
PCI Hot Swap Controller
3.3V, 5V, 12V, – 12V Supplies for PCI Bus
LTC1645
Dual Hot Swap Controller
Operates from 1.2V to 12V, Power Sequencing
LTC1646
Dual CompactPCI Hot Swap Controller
3.3V, 5V Supplies with Precharge and Local PCI Reset Logic
LTC1647
Dual Hot Swap Controller
Dual ON Pins for Supplies from 3V to 15V
LTC4211
Hot Swap Controller with Multifunction Current Control
2.5V to 16.5V Supplies, Active Inrush Current Limiting
LTC4251
–48 Hot Swap Controller in SOT-23
Active Current Limiting, Fast Comparator
for Catastrophic Faults
LTC4252
–48 Hot Swap Controller in MSOP
Active Current Limiting, Fast Comparator for Catastrophic
Faults, Separate UV/0V Pins, Power-Good Output
4250lhf
12
Linear Technology Corporation
LT/TP 0402 2K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 2001
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