Lyontek LT6164DL-15T 8k x 8 bit high speed cmos sram Datasheet

®
LY6164
8K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.4
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Description
Issue Date
Aug.3.2005
Initial Issue
Mar.26.2008
Revised STSOP Package Outline Dimension
Apr.17.2009
Revised Test Condition of ISB1/IDR
Revised VTERM to VT1 and VT2
Revised FEATURES & ORDERING INFORMATION
Lead free and green package available to Green package available
Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS
Added packing type in ORDERING INFORMATION
May.7.2010
Revised PACKAGE OUTLINE DIMENSION in page 10
Aug.25.2010
Revised ORDERING INFORMATION in page 11
Revised PACKAGE OUTLINE DIMENSION in page 9
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
®
LY6164
8K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.4
FEATURES
GENERAL DESCRIPTION
„ Fast access time : 8/10/12/15ns
„ Low power consumption:
Operating current : 110/100/90/80mA (TYP.)
Standby current : 1mA (TYP.)
„ Single 5V power supply
„ All inputs and outputs TTL compatible
„ Fully static operation
„ Tri-state output
„ Data retention voltage : 2.0V (MIN.)
„ Green package available
„ Package : 28-pin 300 mil SOJ
28-pin 300 mil Skinny P-DIP
28-pin 8mm x 13.4mm STSOP
The LY6164 is a 65,536-bit high speed CMOS static
random access memory organized as 8,192 words
by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
The LY6164 is well designed for high speed system
applications, and particularly well suited for battery
back-up nonvolatile memory application.
The LY6164 operates from a single power supply
of 5V and all inputs and outputs are fully TTL
compatible
PRODUCT FAMILY
Product
Family
LY6164
LY6164(E)
LY6164(I)
Operating
Temperature
0 ~ 70℃
-20 ~ 80℃
-40 ~ 85℃
Vcc Range
Speed
4.5 ~ 5.5V
4.5 ~ 5.5V
4.5 ~ 5.5V
8/10/12/15ns
8/10/12/15ns
8/10/12/15ns
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Vcc
Vss
A0-A12
DECODER
DQ0-DQ7
I/O DATA
CIRCUIT
CE#
CE2
WE#
OE#
CONTROL
CIRCUIT
Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
1mA
110/100/90/80mA
1mA
110/100/90/80mA
1mA
110/100/90/80mA
8Kx8
MEMORY ARRAY
SYMBOL
DESCRIPTION
A0 - A12
Address Inputs
DQ0 – DQ7
Data Inputs/Outputs
CE#, CE2
Chip Enable Inputs
WE#
Write Enable Input
OE#
Output Enable Input
VCC
Power Supply
VSS
Ground
NC
No Connection
COLUMN I/O
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
®
LY6164
8K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.4
PIN CONFIGURATION
1
28
Vcc
2
27
WE#
A7
3
26
CE2
A6
4
25
A8
A5
5
24
A9
A4
6
A3
7
A2
8
A1
9
LY6164
NC
A12
23
A11
22
OE#
21
A10
20
CE#
A0
10
19
DQ7
DQ0
11
18
DQ6
DQ1
12
17
DQ5
DQ2
13
16
DQ4
Vss
14
15
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
OE#
A11
A9
A8
CE2
WE#
Vcc
NC
A12
A7
A6
A5
A4
A3
LY6164
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
STSOP
Skinny PDIP/SOJ
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
SYMBOL
VT1
VT2
Operating Temperature
TA
Storage Temperature
Power Dissipation
DC Output Current
TSTG
PD
IOUT
RATING
-0.5 to 6.5
-0.5 to VCC+0.5
0 to 70(C grade)
-20 to 80(E grade)
-40 to 85(I grade)
-65 to 150
1
50
UNIT
V
V
℃
℃
W
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
H
X
L
L
L
CE2
X
L
H
H
H
OE#
X
X
H
L
X
WE#
X
X
H
H
L
I/O OPERATION
High-Z
High-Z
High-Z
DOUT
DIN
H = VIH, L = VIL, X = Don't care.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
SUPPLY CURRENT
ISB1
ISB1
ICC
ICC
ICC
®
LY6164
8K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.4
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
PARAMETER
Supply Voltage
VCC
*1
Input High Voltage
VIH
*2
Input Low Voltage
VIL
VCC ≧ VIN ≧ VSS
Input Leakage Current
ILI
Output Leakage
VCC ≧ VOUT ≧ VSS,
ILO
Current
Output Disabled
Output High Voltage
VOH IOH = -1mA
Output Low Voltage
VOL IOL = 2mA
Average Operating
Power supply Current
ICC
Standby Power
Supply Current
ISB1
MIN.
4.5
2.4
- 0.5
-1
-8
Cycle time = Min.
CE# = VIL and CE2 = VIH, -10
-12
II/O = 0mA
Other pins at VIH or VIL -15
CE# ≧VCC-0.2V or CE2≦0.2V
Other pins at 0.2V or VCC-0.2V
TYP.
5.0
-
*4
MAX.
5.5
VCC+0.5
0.8
1
UNIT
V
V
V
µA
-1
-
1
µA
2.4
-
110
100
90
80
0.4
190
180
160
140
V
V
mA
mA
mA
mA
-
1
5
mA
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN.
-
MAX
6
8
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
UNIT
pF
pF
®
LY6164
8K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.4
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
SYM.
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
SYM.
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
tOW*
tWHZ*
LY6164-8
LY6164-10 LY6164-12 LY6164-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
8
10
12
15
ns
8
10
12
15
ns
8
10
12
15
ns
4
5
6
7
ns
2
2
3
4
ns
0
0
0
0
ns
4
5
6
7
ns
4
5
6
7
ns
3
3
3
3
ns
LY6164-8
LY6164-10 LY6164-12 LY6164-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
8
10
12
15
ns
6.5
8
10
12
ns
6.5
8
10
12
ns
0
0
0
0
ns
6.5
8
9
10
ns
0
0
0
0
ns
5
6
7
8
ns
0
0
0
0
ns
1.5
2
3
4
ns
5
6
7
8
ns
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
®
LY6164
8K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.4
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
Dout
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
CE2
OE#
tOE
tOH
tOHZ
tCHZ
tOLZ
tCLZ
Dout
High-Z
Data Valid
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
®
LY6164
8K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.4
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
CE2
tAS
tWP
tWR
WE#
tWHZ
Dout
TOW
High-Z
(4)
tDW
Din
(4)
tDH
Data Valid
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
tAS
tWR
tCW
CE2
tWP
WE#
tWHZ
Dout
High-Z
(4)
tDW
Din
tDH
Data Valid
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6
®
LY6164
8K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.4
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
VCC for Data Retention
VDR
Data Retention Current
IDR
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
tCDR
TEST CONDITION
CE# ≧ VCC - 0.2V
or CE2 ≦ 0.2V
VCC = 2.0V
CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V
Others at 0.2V or VCC-0.2V
See Data Retention
Waveforms (below)
tR
MIN.
TYP.
MAX.
UNIT
2.0
-
5.5
V
-
0.6
3
mA
0
-
-
ns
tRC*
-
-
ns
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR ≧ 2.0V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE#
VIH
tR
CE# ≧ Vcc-0.2V
VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR ≧ 2.0V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE2
tR
CE2 ≦ 0.2V
VIL
VIL
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
®
LY6164
Rev. 1.4
8K X 8 BIT HIGH SPEED CMOS SRAM
PACKAGE OUTLINE DIMENSION
28 pin 300 mil PDIP Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
®
LY6164
8K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.4
28-pin 300 mil SOJ Package Outline Dimension
28
15
1
14
A2
CL
X
XX
UNIT
SYM.
A
A1
A2
B
B1
c
D
E
E1
e
L
S
Y
INCH(REF)
MM(BASE)
0.140(MAX)
0.025(MIN)
0.100±0.015
0.018±0.004
0.028±0.004
0.010±0.004
0.710±0.020
0.337±0.010
0.300±0.005
0.050±0.006
0.087±0.010
0.045(MAX)
0.004(MAX)
3.556(MAX)
0.635(MIN)
2.540±0.381
0.457±0.102
0.711±0.102
0.254±0.102
18.03±0.508
8.560±0.254
7.620±0.127
1.270±0.152
2.210±0.254
1.143(MAX)
0.102(MAX)
Note : 1.S/E/D dimension is not including mold flash.
2.The end flash in package lengthwise is not more than 10 mils each side.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
®
LY6164
8K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.4
28 pin 8x13.4mm STSOP Package Outline Dimension
HD
cL
12° (2x)
28
14
15
12° (2x)
b
E
e
1
"A"
y
Seating Plane
D
12° (2X)
14
15
0.254
A
A2
c
GAUGE PLANE
A1
0
SEATING PLANE
12° (2X)
L
1
28
SYMBOLS
A
A1
A2
b
c
HD
D
E
e
L
L1
Y
Θ
"A" DATAIL VIEW
DIMENSIONS IN MILLIMETERS
MIN
NOM
MAX
1.00
1.10
1.20
0.05
0.15
0.91
1.00
1.05
0.17
0.22
0.27
0.07
0.15
0.23
13.20
13.40
13.60
11.60
11.80
12.00
7.80
8.00
8.20
0.55
0.30
0.50
0.70
0.675
0.00
0.076
0°
3°
5°
DIMENSIONS IN INCHES
MIN
NOM
MAX
0.040
0.043
0.047
0.002
0.006
0.036
0.039
0.041
0.007
0.009
0.011
0.003
0.006
0.009
0.520
0.528
0.535
0.457
0.465
0.472
0.307
0.315
0.323
0.0216
0.012
0.020
0.028
0.027
0.000
0.003
0°
3°
5°
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
L1
®
LY6164
Rev. 1.4
8K X 8 BIT HIGH SPEED CMOS SRAM
ORDERING INFORMATION
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11
®
LY6164
Rev. 1.4
8K X 8 BIT HIGH SPEED CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
12
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