LINER LTC1604ACG High speed, 16-bit, 333ksps sampling a/d converter with shutdown Datasheet

LTC1604
High Speed, 16-Bit, 333ksps
Sampling A/D Converter
with Shutdown
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DESCRIPTION
FEATURES
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The LTC®1604 is a 333ksps, 16-bit sampling A/D converter that draws only 220mW from ±5V supplies. This
high performance device includes a high dynamic range
sample-and-hold, a precision reference and a high speed
parallel output. Two digitally selectable power shutdown
modes provide power savings for low power systems.
A Complete, 333ksps 16-Bit ADC
90dB S/(N+D) and –100dB THD (Typ)
Power Dissipation: 220mW (Typ)
No Pipeline Delay
No Missing Codes over Temperature
Nap (7mW) and Sleep (10µW) Shutdown Modes
Operates with Internal 15ppm/°C Reference
or External Reference
True Differential Inputs Reject Common Mode Noise
5MHz Full Power Bandwidth
±2.5V Bipolar Input Range
36-Pin SSOP Package
The LTC1604’s full-scale input range is ± 2.5V. Outstanding AC performance includes 90dB S/(N+D) and – 100dB
THD at a sample rate of 333ksps.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 15MHz
bandwidth. The 68dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
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APPLICATIONS
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Telecommunications
Digital Signal Processing
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectrum Analysis
Imaging Systems
The ADC has µP compatible,16-bit parallel output port.
There is no pipeline delay in conversion results. A separate
convert start input and a data ready signal (BUSY) ease
connections to FlFOs, DSPs and microprocessors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
2.2µF
10µF
10Ω
+
3
VREF
5V 10µF
+
36
AVDD
5V
35
9
AVDD
10µF
LTC1604 4096 Point FFT
+
10
DVDD
0
DGND
SHDN 33
+
7.5k
4.375V
1.75X
2.5V
REF
CS 32
µP
CONTROL
LINES
CONVST 31
RD 30
BUSY 27
47µF
OVDD 29
+
1 AIN+
DIFFERENTIAL
ANALOG INPUT
± 2.5V
2 AIN–
+
–
OGND 28
16-BIT
SAMPLING
ADC
AGND
5
AGND
6
OUTPUT
BUFFERS
B15 TO B0
AGND
7
–60
–80
–100
–140
0
1604 TA01
34
–40
–120
16-BIT
PARALLEL
BUS
11 TO 26
AGND VSS
8
D15 TO D0
5V OR
3V
10µF
AMPLITUDE (dB)
4 REFCOMP
CONTROL
LOGIC
AND
TIMING
fSAMPLE = 333kHz
fIN = 100kHz
SINAD = 89dB
THD = –96dB
–20
20
40
60 80 100 120 140 160
FREQUENCY (kHz)
1604 TA02
+
10µF
–5V
1
LTC1604
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
AVDD = DVDD = OVDD = VDD (Notes 1, 2)
ORDER
PART NUMBER
TOP VIEW
Supply Voltage (VDD) ................................................ 6V
Negative Supply Voltage (VSS)................................ – 6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Analog Input Voltage
(Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V)
VREF Voltage (Note 4) ................. – 0.3V to (VDD + 0.3V)
REFCOMP Voltage (Note 4) ......... – 0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 4) ....................– 0.3V to 10V
Digital Output Voltage .................. – 0.3V to (VDD + 0.3V)
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1604C............................................... 0°C to 70°C
LTC1604I ............................................ – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
AIN+
1
AIN–
2
36 AVDD
35 AVDD
VREF
3
34 VSS
REFCOMP
4
33 SHDN
AGND
5
32 CS
AGND
6
31 CONV
AGND
7
30 RD
AGND
8
29 OVDD
DVDD
9
28 OGND
DGND 10
27 BUSY
D15 (MSB) 11
26 D0
D14 12
25 D1
D13 13
24 D2
D12 14
23 D3
D11 15
22 D4
D10 16
21 D5
D9 17
20 D6
D8 18
LTC1604CG
LTC1604IG
LTC1604ACG
LTC1604AIG
19 D7
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/W
Consult factory for Military grade parts.
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CO VERTER CHARACTERISTICS
PARAMETER
With Internal Reference (Notes 5, 6)
CONDITIONS
MIN
Resolution (No Missing Codes)
15
●
Integral Linearity Error
(Note 7)
Transition Noise
(Note 8)
Offset Error
(Note 9)
Offset Tempco
(Note 9)
Full-Scale Error
Internal Reference
External Reference
Full-Scale Tempco
IOUT(Reference) = 0, Internal Reference
LTC1604
TYP
MAX
16
±1
●
MIN
16
±4
16
±0.5
0.7
±2
0.5
0.5
%
ppm/°C
±0.125 ±0.25
±0.25
±15
LSB
LSB
±0.05 ±0.125
± 0.125 ± 0.25
±0.25
UNITS
Bits
0.7
± 0.05 ± 0.125
●
LTC1604A
TYP
MAX
±15
%
%
ppm/°C
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A ALOG I PUT
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 2)
4.75 ≤ VDD ≤ 5.25V, – 5.25 ≤ VSS ≤ – 4.75V,
VSS ≤ (AIN–, AIN+) ≤ AVDD
IIN
Analog Input Leakage Current
CS = High
CIN
Analog Input Capacitance
Between Conversions
During Conversions
tACQ
tAP
tjitter
Sample-and-Hold Acquisition Delay Time Jitter
CMRR
2
MIN
TYP
MAX
±2.5
V
±1
●
UNITS
µA
43
5
pF
pF
Sample-and-Hold Acquisition Time
380
ns
Sample-and-Hold Acquisition Delay Time
– 1.5
ns
Analog Input Common Mode Rejection Ratio
–
– 2.5V < (AIN = AIN
+) < 2.5V
5
psRMS
68
dB
LTC1604
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DY A IC ACCURACY
(Note 5)
SYMBOL PARAMETER
CONDITIONS
S/N
5kHz Input Signal
100kHz Input Signal
Signal-to-Noise Ratio
S/(N + D) Signal-to-(Noise + Distortion) Ratio
MIN
●
LTC1604
TYP MAX
90
90
LTC1604A
MIN TYP MAX
87
UNITS
90
90
dB
dB
90
89
dB
dB
5kHz Input Signal
100kHz Input Signal (Note 10)
●
90
89
Total Harmonic Distortion
Up to 5th Harmonic
5kHz Input Signal
100kHz Input Signal
●
–100
– 94
SFDR
Spurious Free Dynamic Range
100kHz Input Signal
96
96
dB
IMD
Intermodulation Distortion
fIN1 = 29.37kHz, fIN2 = 32.446kHz
– 88
– 88
dB
5
5
MHz
350
350
kHz
THD
Full Power Bandwidth
Full Linear Bandwidth (S/(N + D) ≥ 84dB
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I TER AL REFERE CE CHARACTERISTICS
84
– 100
– 94 – 88
dB
dB
(Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VREF Output Voltage
IOUT = 0
2.475
2.500
2.515
V
VREF Output Tempco
IOUT = 0
±15
ppm/°C
VREF Line Regulation
4.75 ≤ VDD ≤ 5.25V
– 5.25V ≤ VSS ≤ – 4.75V
0.01
0.01
LSB/V
LSB/V
7.5
kΩ
VREF Output Resistance
0 ≤ IOUT ≤ 1mA
REFCOMP Output Voltage
IOUT = 0
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DIGITAL I PUTS A D DIGITAL OUTPUTS
4.375
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.75V
●
IIN
Digital Input Current
VIN = 0V to VDD
●
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
V
MIN
VDD = 4.75V, IOUT = – 10µA
VDD = 4.75V, IOUT = – 400µA
●
VDD = 4.75V, IOUT = 160µA
VDD = 4.75V, IOUT = 1.6mA
●
TYP
MAX
2.4
UNITS
V
0.8
V
±1 0
µA
5
pF
4.5
V
V
4.0
0.05
0.10
0.4
V
V
IOZ
Hi-Z Output Leakage D15 to D0
VOUT = 0V to VDD, CS High
●
±10
µA
COZ
Hi-Z Output Capacitance D15 to D0
CS High (Note 11)
●
15
pF
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
3
LTC1604
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POWER REQUIRE E TS
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNITS
VDD
Positive Supply Voltage
(Notes 12, 13)
4.75
5.25
V
VSS
Negative Supply Voltage
(Note 12)
– 4.75
– 5.25
V
IDD
Positive Supply Current
Nap Mode
Sleep Mode
CS = RD = 0V
CS = 0V, SHDN = 0V
CS = 5V, SHDN = 0V
●
18
1.5
1
30
2.4
100
mA
mA
µA
ISS
Negative Supply Current
Nap Mode
Sleep Mode
CS = RD = 0V
CS = 0V, SHDN = 0V
CS = 5V, SHDN = 0V
●
26
1
1
40
100
100
mA
µA
µA
PD
Power Dissipation
Nap Mode
Sleep Mode
CS = RD = 0V
CS = 0V, SHDN = 0V
CS = 5V, SHDN = 0V
●
220
7.5
0.01
350
12
1
mW
mW
mW
TYP
MAX
UNITS
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TI I G CHARACTERISTICS
TYP
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
fSMPL(MAX)
Maximum Sampling Frequency
tCONV
Conversion Time
tACQ
Acquisition Time
tACQ+CONV
Throughput Time (Acquisition + Conversion)
t1
CS to RD Setup Time
(Notes 11, 12)
●
0
ns
t2
CS↓ to CONVST↓ Setup Time
(Notes 11, 12)
●
10
ns
t3
SHDN↓ to CS↑ Setup Time
(Notes 11, 12)
●
10
ns
t4
SHDN↑ to CONVST↓ Wake-Up Time
CS = Low (Note 12)
t5
CONVST Low Time
(Note 12)
●
40
t6
CONVST to BUSY Delay
CL = 25pF
(Note 11)
MIN
●
333
●
1.5
kHz
2.8
µs
●
480
ns
●
3
µs
2.45
400
ns
36
80
●
t7
ns
Data Ready Before BUSY↑
60
ns
ns
●
32
ns
ns
t8
Delay Between Conversions
(Note 12)
●
200
ns
t9
Wait Time RD↓ After BUSY↑
(Note 12)
●
–5
ns
t10
Data Access Time After RD↓
CL = 25pF
40
50
60
ns
ns
45
60
75
ns
ns
50
60
70
75
ns
ns
ns
●
CL = 100pF
●
t11
Bus Relinquish Time
LTC1604C
LTC1604I
●
●
t12
RD Low Time
(Note 12)
●
t10
t13
CONVST High Time
(Note 12)
●
40
t14
Aperture Delay of Sample-and-Hold
4
ns
ns
2
ns
LTC1604
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TI I G CHARACTERISTICS
(Note 5)
The ● denotes specifications that apply over the full operating temperature
range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
and AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.
Note 4: When these pin voltages are taken below VSS, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = – 5V, fSMPL = 333kHz, and t r = t f = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specification apply for a singleended AIN+ input with AIN– grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Typical RMS noise at the code transitions. See Figure 17 for
histogram.
Note 9: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111.
Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion
is measured at 100kHz. These results are used to calculate Signal-to-Nosie
Plus Distortion (SINAD).
Note 11: Guaranteed by design, not subject to test.
Note 12: Recommended operating conditions.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best performance ensure that CONVST returns high either within 250ns
after conversion start or after BUSY rises.
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TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs
Output Code
2.0
1.0
100
1.5
0.8
90
0.6
80
0.4
70
DNL (LSB)
0.5
0.0
–0.5
–1.0
–1.5
–2.0
–32768
0.2
SINAD (dB)
1.0
INL (LSB)
S/(N + D) vs Input Frequency
and Amplitude
Differential Nonlinearity vs
Output Code
0.0
–0.2
–16384
0
16384
32767
40
30
20
–0.8
10
0
–16384
CODE
0
16384
32767
VIN = –40dB
50
–0.6
–32768
VIN = –20dB
60
–0.4
–1.0
VIN = 0dB
1k
10k
100k
FREQUENCY (Hz)
CODE
1604 G11
1M
1604 G01
1604 G10
Signal-to-Noise Ratio vs
Input Frequency
SIGNAL-TO-NOISE RATIO (dB)
90
80
70
60
50
40
30
20
10
10k
100k
FREQUENCY (Hz)
1M
1604 G03
0
0
–10
–20
–30
–40
–50
–60
–70
–80
THD
3RD
–90
–100
–110
1k
2ND
10k
100k
INPUT FREQUENCY (Hz)
1M
1604 G04
SPURIOUS-FREE DYNAMIC RANGE (dB)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
100
0
1k
Spurious-Free Dynamic Range
vs Input Frequency
Distortion vs Input Frequency
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
1604 G05
5
LTC1604
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TYPICAL PERFORMANCE CHARACTERISTICS
0
–20
–40
–60
–80
–100
–20
–40
–60
–80
AVDD
–100
–120
–140
–120
0
20
40
60 80 100 120 140 160
FREQUENCY (kHz)
80
fSAMPLE = 333kHz
VRIPPLE = 10mV
COMMON MODE REJECTION (dB)
fSAMPLE = 333kHz
fIN1 = 29.3kHz
fIN2 = 32.4kHz
AMPLITUDE OF POWER SUPPLY
FEEDTHROUGH (dB)
0
AMPLITUDE (dB)
Input Common Mode Rejection
vs Input Frequency
Power Supply Feedthrough vs
Ripple Frequency
Intermodulaton Distortion
V SS
70
60
50
40
30
20
10
0
1k
10k
100k
INPUT FREQUENCY (Hz)
1604 G06
1M
1k
10k
100k
INPUT FREQUENCY (Hz)
1604 G07
1M
1604G09
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PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input. The ADC converts the
difference voltage between AIN+ and AIN– with a differential range of ±2.5V. AIN+ has a ±2.5V input range when
AIN– is grounded.
AIN– (Pin 2): Negative Analog Input. Can be grounded, tied
to a DC voltage or driven differentially with AIN+ .
VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with
2.2µF tantalum in parallel with 0.1µF ceramic.
REFCOMP (Pin 4): 4.375 Reference Compensation Pin.
Bypass to AGND with 47µF tantalum in parallel with 0.1µF
ceramic.
AGND (Pins 5 to 8): Analog Grounds. Tie to analog ground
plane.
DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGND
with 10µF tantalum in parallel with 0.1µF ceramic.
DGND (Pin 10): Digital Ground for Internal Logic. Tie to
analog ground plane.
D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15
is the Most Significant Bit.
BUSY (Pin 27): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data is
valid on the rising edge of BUSY.
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OGND (Pin 28): Digital Ground for Output Drivers.
OVDD (Pin 29): Digital Power Supply for Output Drivers.
Bypass to OGND with 10µF tantalum in parallel with 0.1µF
ceramic.
RD (Pin 30): Read Input. A logic low enables the output
drivers when CS is low.
CONVST (Pin 31): Conversion Start Signal. This active
low signal starts a conversion on its falling edge when CS
is low.
CS (Pin 32): The Chip Select Input. Must be low for the
ADC to recognize CONVST and RD inputs.
SHDN (Pin 33): Power Shutdown. Drive this pin low with
CS low for nap mode. Drive this pin low with CS high for
sleep mode.
VSS (Pin 34): – 5V Negative Supply. Bypass to AGND with
10µF tantalum in parallel with 0.1µF ceramic.
AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic.
AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic and
connect this pin to Pin 35 with a 10Ω resistor.
LTC1604
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FU CTIO AL BLOCK DIAGRA
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10µF
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2.2µF
10Ω
+
3
VREF
5V 10µF
5V
+
36
35
AVDD
9
AVDD
10µF
+
10
DVDD
DGND
SHDN 33
4 REFCOMP
+
7.5k
4.375V
1.75X
CS 32
CONTROL
LOGIC
AND
TIMING
2.5V
REF
µP
CONTROL
LINES
CONVST 31
RD 30
BUSY 27
47µF
OVDD 29
+
1 AIN+
DIFFERENTIAL
ANALOG INPUT
± 2.5V
+
2 AIN–
–
OGND 28
16-BIT
SAMPLING
ADC
AGND
AGND
5
OUTPUT
BUFFERS
B15 TO B0
AGND
7
6
D15 TO D0
16-BIT
PARALLEL
BUS
11 TO 26
AGND VSS
8
5V OR
3V
10µF
1604 TA01
34
+
10µF
–5V
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
1k
DN
1k
DN
1k
CL
(A) Hi-Z TO VOH AND VOL TO VOH
DN
DN
1k
CL
(B) Hi-Z TO VOL AND VOH TO VOL
1604 TC01
(A) VOH TO Hi-Z
CL
CL
(B) VOL TO Hi-Z
1604 TC02
7
LTC1604
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APPLICATIONS INFORMATION
CONVERSION DETAILS
The LTC1604 uses a successive approximation algorithm
and internal sample-and-hold circuit to convert an analog
signal to a 16-bit parallel output. The ADC is complete with
a sample-and-hold, a precision reference and an internal
clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) resets. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
(LSB). Referring to Figure 1, the AIN+ and AIN– inputs are
acquired during the acquire phase and the comparator
offset is nulled by the zeroing switches. In this acquire
phase, a duration of 480ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the CSMPL capacitors to ground,
transferring the differential analog input charge onto the
ZEROING SWITCHES
CSMPL
HOLD
SAMPLE
HOLD
HOLD
+CDAC
+
–CDAC
COMP
Internal Clock
The A/D converter has an internal clock that runs the A/D
conversion. The internal clock is factory trimmed to achieve
a typical conversion time of 2.45µs and a maximum
conversion time of 2.8µs over the full temperature range.
No external adjustments are required. The guaranteed
maximum acquisition time is 480ns. In addition, a throughput time (acquisition + conversion) of 3µs and a minimum
sampling rate of 333ksps are guaranteed.
–
+VDAC
Power Shutdown
–VDAC
16
SAR
OUTPUT
LATCHES
•
•
•
D15
D0
1604 F01
Figure 1. Simplified Block Diagram
8
The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a conversion.
The LTC1604 operates on ±5V supplies, which makes the
device easy to interface to 5V digital systems. This device
can also talk to 3V digital systems: the digital input pins
(SHDN, CS, CONVST and RD) of the LTC1604 recognize
3V or 5V inputs. The LTC1604 has a dedicated output
supply pin (OVDD) that controls the output swings of the
digital output pins (D0 to D15, BUSY) and allows the part
to talk to either 3V or 5V digital systems. The output is
two’s complement binary.
SAMPLE
HOLD
AIN–
DIGITAL INTERFACE
3V Input/Output Compatible
CSMPL
AIN+
summing junctions. This input charge is successively
compared with the binary-weighted charges supplied by
the differential capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion, the
differential DAC output balances the AIN+ and AIN– input
charges. The SAR contents (a 16-bit data word) which
represent the difference of AIN+ and AIN– are loaded into
the 16-bit output latches.
The LTC1604 provides two power shutdown modes, Nap
and Sleep, to save power during inactive periods. The Nap
mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up time
from Nap to active is 200ns. In Sleep mode all bias
LTC1604
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APPLICATIONS INFORMATION
currents are shut down and only leakage current remains
(about 1µA). Wake-up time from Sleep mode is much
slower since the reference circuit must power up and
settle. Sleep mode wake-up time is dependent on the value
of the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 160ms with the recommended 47µF
capacitor.
SHDN
t3
CS
1604 F02a
Figure 2a. Nap Mode to Sleep Mode Timing
Shutdown is controlled by Pin 33 (SHDN). The ADC is in
shutdown when SHDN is low. The shutdown mode is
selected with Pin 32 (CS). When SHDN is low, CS low
selects nap and CS high selects sleep.
SHDN
t4
CONVST
1604 F02b
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A falling edge
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY is
low during a conversion.
Figure 2b. SHDN to CONVST Wake-Up Timing
CS
t2
CONVST
t1
We recommend using a narrow logic low or narrow logic
high CONVST pulse to start a conversion as shown in
Figures 5 and 6. A narrow low or high CONVST pulse
prevents the rising edge of the CONVST pulse from upsetting the critical bit decisions during the conversion time.
Figure 4 shows the change of the differential nonlinearity
error versus the low time of the CONVST pulse. As shown,
if CONVST returns high early in the conversion (e.g.,
CONVST low time <500ns), accuracy is unaffected. Similarly, if CONVST returns high after the conversion is over
(e.g., CONVST low time >tCONV), accuracy is unaffected.
For best results, keep t 5 less than 500ns or greater than
tCONV.
RD
1604 F03
Figure 3. CS top CONVST Setup Timing
CHANGE IN DNL (LSB)
4
3
2
tCONV
tACQ
1
0
0
400
800
1200
1600
2000
2400
2800
CONVST LOW TIME, t5 (ns)
1604 F04
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
CONVST Pulse Returns High Early in the Conversion or After
the End of Conversion
Figures 5 through 9 show several different modes of
operation. In modes 1a and 1b (Figures 5 and 6), CS and
RD are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 7) CS is tied low. The falling edge of
CONVST signal starts the conversion. Data outputs are in
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t CONV
CS = RD = 0
t5
CONVST
t6
t8
BUSY
t7
DATA
DATA (N + 1)
D15 TO D0
DATA N
D15 TO D0
DATA (N – 1)
D15 TO D0
1604 F05
Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
tCONV
CS = RD = 0
t8
t5
t13
CONVST
t6
t6
BUSY
t7
DATA (N – 1)
D15 TO D0
DATA
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
1604 F06
Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t13
tCONV
t5
CS = 0
t8
CONVST
t6
BUSY
t 11
t9
t 12
RD
t 10
DATA
DATA N
D15 TO D0
1604 F07
Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD
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t8
t CONV
CS = 0
RD = CONVST
t6
t 11
BUSY
t 10
t7
DATA (N – 1)
D5 TO D0
DATA
DATA N
D15 TO D0
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
1604 F08
Figure 8. Mode 2. Slow Memory Mode Timing
t CONV
CS = 0
t8
RD = CONVST
t6
t 11
BUSY
t 10
DATA
DATA N
D15 TO D0
DATA (N – 1)
D15 TO D0
1604 F09
Figure 9. ROM Mode Timing
three-state until read by the MPU with the RD signal. Mode
2 can be used for operation with a shared data bus.
In slow memory and ROM modes (Figures 8 and 9) CS is
tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the combined CONVST-RD signal. Conversions are started by the
MPU or DSP (no external sample clock is needed).
In slow memory mode the processor applies a logic low to
RD (= CONVST), starting the conversion. BUSY goes low,
forcing the processor into a wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results
appear on the data outputs; BUSY goes high, releasing the
processor and the processor takes RD (= CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD (= CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
DIFFERENTIAL ANALOG INPUTS
Driving the Analog Inputs
The differential analog inputs of the LTC1604 are easy to
drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN – input is grounded). The AIN+ and
AIN – inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be
reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1604
inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 10). For
minimum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
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ACQUISITION TIME (µs)
10
LT ® 1007: Low Noise Precision Amplifier. 2.7mA supply
current, ±5V to ±15V supplies, gain bandwidth product
8MHz, DC applications.
1
0.1
LT1097: Low Cost, Low Power Precision Amplifier. 300µA
supply current, ±5V to ±15V supplies, gain bandwidth
product 0.7MHz, DC applications.
0.01
LT1227: 140MHz Video Current Feedback Amplifier. 10mA
supply current, ±5V to ±15V supplies, low noise and low
distortion.
1
10
100
1k
SOURCE RESISTANCE (Ω)
10k
1604 F10
LT1360: 37MHz Voltage Feedback Amplifier. 3.8mA supply current, ±5V to ±15V supplies, good AC/DC specs.
Figure 10. tACQ vs Source Resistance
LT1363: 50MHz Voltage Feedback Amplifier. 6.3mA supply current, good AC/DC specs.
starts (settling time must be 200ns for full throughput
rate).
LT1364/LT1365: Dual and Quad 50MHz Voltage Feedback
Amplifiers. 6.3mA supply current per amplifier, good AC/
DC specs.
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
low output impedance (< 100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a
gain of +1 and has a unity-gain bandwidth of 50MHz, then
the output impedance at 50MHz should be less than
100Ω. The second requirement is that the closed-loop
bandwidth must be greater than 15MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.
The best choice for an op amp to drive the LTC1604 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifications are most critical and time domain applications
where DC accuracy and settling time are most critical.
The following list is a summary of the op amps that are
suitable for driving the LTC1604. More detailed information is available in the Linear Technology databooks, the
LinearViewTM CD-ROM and on our web site at:
www.linear-tech. com.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1604 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 15MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 11 shows a 3000pF
capacitor from AIN+ to ground and a 100Ω source resistor
to limit the input bandwidth to 530kHz. The 3000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors can
also generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
LinearView is a trademark of Linear Technology Corporation.
12
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100Ω
ANALOG INPUT
3000pF
1
AIN+
2.500V
2
R1
7.5k
3 VREF
–
BANDGAP
REFERENCE
AIN
LTC1604
3
4
VREF
4.375V
4 REFCOMP
REFERENCE
AMP
REFCOMP
R2
12k
47µF
47µF
5
AGND
1604 F11
R3
16k
5 AGND
LTC1604
1604 F12a
Figure 11. RC Input Filter
Figure 12a. LTC1604 Reference Circuit
Input Range
The ±2.5V input range of the LTC1604 is optimized for low
noise and low distortion. Most op amps also perform well
over this same range, allowing direct coupling to the
analog inputs and eliminating the need for special translation circuitry.
5V
ANALOG
INPUT
VIN
LT1019A-2.5
VOUT
1
AIN+
2
AIN–
3
LTC1604
4
Some applications may require other input ranges. The
LTC1604 differential inputs and reference circuitry can
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
Internal Reference
The LTC1604 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmed to 2.500V. It is connected internally to a reference
amplifier and is available at VREF (Pin 3) (see Figure 12a).
A 7.5k resistor is in series with the output so that it can be
easily overdriven by an external reference or other
circuitry (see Figure 12b). The reference amplifier gains
the voltage at the VREF pin by 1.75 to create the required
internal reference voltage. This provides buffering
between the VREF pin and the high speed capacitive DAC.
The reference amplifier compensation pin (REFCOMP, Pin
4) must be bypassed with a capacitor to ground. The
reference amplifier is stable with capacitors of 22µF or
greater. For the best noise performance a 47µF ceramic or
47µF tantalum in parallel with a 0.1µF ceramic is recommended.
VREF
+
10µF
0.1µF
5
REFCOMP
AGND
1604 F12b
Figure 12b. Using the LT1019-2.5 as an External Reference
The VREF pin can be driven with a DAC or other means
shown in Figure 13. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1604 reference amplifier will limit
the bandwidth and settling time of this circuit. A settling
time of 20ms should be allowed for after a reference
adjustment.
Differential Inputs
The LTC1604 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of AIN+ – AIN– independent of the
common mode voltage (see Figure 15a). The common
mode rejection holds up to extremely high frequencies
(see Figure 14a). The only requirement is that both inputs
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1
ANALOG INPUT
2V TO 2.7V
DIFFERENTIAL
2
AIN+
ANALOG INPUT
–
AIN
0V TO
5V
±2.5V
+
LTC1604
LTC1450
2V TO 2.7V
3
4
1
AIN+
2
AIN–
3
VREF
–
VREF
LTC1604
4
REFCOMP
REFCOMP
10µF
47µF
5
5
AGND
AGND
1604 F13
80
Full-Scale and Offset Adjustment
70
Figure 15a shows the ideal input/output characteristics
for the LTC1604. The code transitions occur midway
between successive integer LSB values (i.e., – FS +
0.5LSB, – FS + 1.5LSB, – FS + 2.5LSB,... FS – 1.5LSB,
FS – 0.5LSB). The output is two’s complement binary with
1LSB = FS – (– FS)/65536 = 5V/65536 = 76.3µV.
60
50
40
30
20
10
0
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
1604 G14a
Figure 14a. CMRR vs Input Frequency
can not exceed the AVDD or VSS power supply voltages.
Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode
voltage, however, the bipolar zero error (BZE) will vary.
The change in BZE is typically less than 0.1% of the
common mode voltage. Dynamic performance is also
affected by the common mode voltage. THD will degrade
as the inputs approach either power supply rail, from 96dB
with a common mode of 0V to 86dB with a common mode
of 2.5V or – 2.5V.
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 14b shows a circuit that
converts a 0V to 5V analog input signal with only an
additional buffer that is not in the signal path.
14
Figure 14b. Selectable 0V to 5V or ±2.5V Input Range
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 15b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the AIN– input. For zero offset error apply
011...111
011...110
OUTPUT CODE
COMMON MODE REJECTION (dB)
Figure 13. Driving VREF with a DAC
1604 F14b
000...001
000...000
111...111
111...110
100...001
100...000
– (FS – 1LSB)
FS – 1LSB
INPUT VOLTAGE (AIN+ – AIN– )
1604 F15a
Figure 15a. LTC1604 Transfer Characteristics
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–5V
ANALOG
INPUT
R3
24k
R8
50k
1
AIN+
2
AIN–
R4
100Ω
3
R5 R7
47k 50k
R6
24k
+
47µF
4
LTC1604
VREF
REFCOMP
0.1µF
5
AGND
1604 F15b
Figure 15b. Offset and Full-Scale Adjust Circuit
– 38µV (i.e., – 0.5LSB) at AIN+ and adjust the offset at the
AIN– input until the output code flickers between 0000
0000 0000 0000 and 1111 1111 1111 1111. For full-scale
adjustment, an input voltage of 2.499886V (FS/2 – 1.5LSBs)
is applied to AIN+ and R2 is adjusted until the output code
flickers between 0111 1111 1111 1110 and 0111 1111
1111 1111.
BOARD LAYOUT AND GROUNDING
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1604, a printed circuit board
with ground plane is required. Layout should ensure that
digital and analog signal lines are separated as much as
possible. Particular care should be taken not to run any
digital track alongside an analog signal track or underneath the ADC.The analog input should be screened by
AGND.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 to Pin 8 (AGNDs), Pin 10 (ADC’s DGND) and all other
analog grounds should be connected to this single analog
ground point. The REFCOMP bypass capacitor and the
DVDD bypass capacitor should also be connected to this
analog ground plane. No other digital grounds should be
connected to this analog ground plane. Low impedance
analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil
width for these tracks should be as wide as possible. In
applications where the ADC data outputs and control
signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate the ADC data bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC1604 has differential inputs to minimize noise
coupling. Common mode noise on the AIN+ and AIN– leads
will be rejected by the input CMRR. The AIN– input can be
used as a ground sense for the AIN+ input; the LTC1604
will hold and convert the difference voltage between AIN+
and AIN– . The leads to AIN+ (Pin 1) and AIN– (Pin 2) should
be kept as short as possible. In applications where this is
not possible, the AIN+ and AIN– traces should be run side
by side to equalize coupling.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10µF or 47µF
bypass capacitors should be used at the VDD and REFCOMP
pins as shown in Figure 16 and in the Typical Application
on the first page of this data sheet. Surface mount ceramic
capacitors such as Murata GRM235Y5V106Z016 provide
excellent bypassing in a small board space. Alternatively,
10µF tantalum capacitors in parallel with 0.1µF ceramic
capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short
and should be made as wide as possible.
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1
ANALOG
INPUT
CIRCUITRY
AIN+
AIN–
+
–
2
DIGITAL
SYSTEM
LTC1604
VREF REFCOMP AGND
3
4
2.2µF
47µF
5 TO 8
VSS
AVDD
AVDD
DVDD
DGND OVDD OGND
34
36
35
9
10µF
10µF
10µF
10µF
10
29
28
10µF
1604 F16
Figure 16. Power Supply Grounding Practice
2500
DC PERFORMANCE
COUNT
2000
1500
1000
500
0
–5 –4 –3 –2 –1 0 1
CODE
2
3
4
5
1604 F17
Figure 17. Histogram for 4096 Conversions
0
fSAMPLE = 333kHz
fIN = 4.959kHz
SINAD = 90.2dB
THD = –103.2dB
–20
AMPLITUDE (dB)
The noise of an ADC can be evaluated in two ways: signalto-noise raio (SNR) in frequency domain and histogram in
time domain. The LTC1604 excels in both. Figure 18a
demonstrates that the LTC1604 has an SNR of over 90dB
in frequency domain. The noise in the time domain histogram is the transition noise associated with a high resolution ADC which can be measured with a fixed DC signal
applied to the input of the ADC. The resulting output codes
are collected over a large number of conversions. The
shape of the distribution of codes will give an indication of
the magnitude of the transition noise. In Figure 17 the
distribution of output codes is shown for a DC input that
has been digitized 4096 times. The distribution is Gaussian
and the RMS code transition noise is about 0.66LSB. This
corresponds to a noise level of 90.9dB relative to full scale.
Adding to that the theoretical 98dB of quantization error
for 16-bit ADC, the resultant corresponds to an SNR level
of 90.1dB which correlates very well to the frequency
domain measurements in DYNAMIC PERFORMANCE
section.
–40
–60
–80
–100
DYNAMIC PERFORMANCE
The LTC1604 has excellent high speed sampling capability. Fast fourier transform (FFT) test techniques are used
to test the ADC’s frequency response, distortions and
noise at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figures 18a and 18b
show typical LTC1604 FFT plots.
16
–120
–140
0
20
40
60 80 100 120 140 160
FREQUENCY (kHz)
1604 F18a
Figure 18a. This FFT of the LTC1604’s Conversion of a
Full-Scale 5kHz Sine Wave Shows Outstanding Response
with a Very Low Noise Floor When Sampling at 333ksps
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Signal-to-Noise Ratio
–40
AMPLITUDE (dB)
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 18a shows a typical spectral content
with a 333kHz sampling rate and a 5kHz input. The
dynamic performance is excellent for input frequencies up
to and beyond the Nyquist limit of 167kHz.
fSAMPLE = 333kHz
fIN = 97.152kHz
SINAD = 89dB
THD = –96dB
–20
–60
–80
–100
–120
–140
0
20
40
60
80 100 120 140 160
FREQUENCY (kHz)
Effective Number of Bits
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
1604 F18b
Figure 18b. Even with Inputs at 100kHz, the LTC1604’s
Dynamic Linearity Remains Robust
Total Harmonic Distortion
V22 + V32 + V42 + ...Vn2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs Input Frequency is
shown in Figure 20. The LTC1604 has good distortion
performance up to the Nyquist frequency and beyond.
THD = 20Log
15
92
14
86
13
80
12
74
11
68
10
62
9
56
50
1M
8
1k
10k
100k
FREQUENCY (Hz)
1604 F19
Figure 19. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
98
SINAD (dB)
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 333kHz the LTC1604 maintains above 14 bits up to
the Nyquist input frequency of 167kHz (refer to Figure 19).
EFFECTIVE BITS
N = [S/(N + D) – 1.76]/6.02
16
0
–10
–20
–30
–40
–50
–60
–70
–80
THD
3RD
–90
–100
–110
1k
2ND
10k
100k
INPUT FREQUENCY (Hz)
1M
1604 G04
Figure 20. Distortion vs Input Frequency
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Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
0
fSAMPLE = 333kHz
fIN1 = 29.3kHz
fIN2 = 32.4kHz
–20
AMPLITUDE (dB)
(
)
IMD fa ± fb = 20Log
Amplitude at (fa ± fb)
Amplitude at fa
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
–40
–60
–80
–100
–120
–140
0
20
40
60 80 100 120 140 160
FREQUENCY (kHz)
1604 G06
Figure 21. Intermodulation Distortion Plot
18
etc. For example, the 2nd order IMD terms include
(fa – fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products
can be expressed by the following formula:
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 84dB (13.66 effective bits).
The LTC1604 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with
frequencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
G Package
36-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.499 – 0.509*
(12.67 – 12.93)
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
0.301 – 0.311
(7.65 – 7.90)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0° – 8°
0.005 – 0.009
(0.13 – 0.22)
0.022 – 0.037
(0.55 – 0.95)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.0256
(0.65)
BSC
0.010 – 0.015
(0.25 – 0.38)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
0.002 – 0.008
(0.05 – 0.21)
G36 SSOP 1196
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TYPICAL APPLICATION
Using the LTC1604 and Two LTC1391s as an 8-Channel Differential 16-Bit ADC System
5V
1
2
3
4
5
6
7
CH7 +
8
CH0
V+
D
CH1
CH2
DOUT
CH4
DIN
CH5
CS
CH6
CLK
CH7
GND
16
VREF
2
3
4
5
6
7
CH7
–
8
V+
CH1
D
CH2
V–
CH3
DOUT
CH4
DIN
CH5
CS
CH6
CLK
CH7
GND
AVDD
10
9
DVDD
AVDD
DGND
SHDN 33
–5V
1µF
+
13
4 REFCOMP
12
+
4.375V
47µF
11
7.5k
1.75X
2.5V
REF
1 AIN
15
+
OGND 28
+
–
16-BIT
SAMPLING
ADC
OUTPUT
BUFFERS
B15 TO B0
AGND
AGND
AGND
5
6
7
34
+
+
12
CS
10
1604 TA03
10µF
–5V
DIN
11
11 TO 26
AGND VSS
8
5V OR
3V
10µF
16-BIT
PARALLEL
BUS
D15 TO D0
–5V
14
RD 30
3000pF
1µF
µP
CONTROL
LINES
+
2 AIN–
16
CS 32
CONVST 31
OVDD 29
LTC1604
9
13
CONTROL
LOGIC
AND
TIMING
BUSY 27
10
LTC1391
CH0
+
35
15
5V
1
5V 10µF
+
36
3000pF
CH0 –
5V 10µF
10Ω
3
1µF
14
V–
CH3
10µF
+
+
LTC1391
CH0+
2.2µF
CLK
µP
CONTROL
LINES
9
RELATED PARTS
SAMPLING ADCs
PART NUMBER
DESCRIPTION
COMMENTS
LTC1410
12-Bit, 1.25Msps, ±5V ADC
71.5dB SINAD at Nyquist, 150mW Dissipation
LTC1415
12-Bit, 1.25Msps, Single 5V ADC
55mW Power Dissipation, 72dB SINAD
LTC1418
14-Bit, 200ksps, Single 5V ADC
15mW, Serial/Para llel ±10V
LTC1419
Low Power 14-Bit, 800ksps ADC
True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
LTC1605
16-Bit, 100ksps, Single 5V ADC
±10V Inputs, 55mW, Byte or Parallel I/O
PART NUMBER
DESCRIPTION
COMMENTS
LTC1595
16-Bit Serial Multiplying IOUT DAC in SO-8
±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
LTC1596
16-Bit Serial Multiplying IOUT DAC
±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade
LTC1597
16-Bit Parallel, Multiplying DAC
±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors
LTC1650
16-Bit Serial VOUT DAC
Low Power, Low Gritch, 4-Quadrant Multiplication
20
Linear Technology Corporation
DACs
1604fa LT/TP 1098 REV A 2K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1998
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