LINER LTC2228 12-bit, 65/40/25msps low power 3v adc Datasheet

LTC2228/LTC2227/LTC2226
12-Bit, 65/40/25Msps
Low Power 3V ADCs
FEATURES
DESCRIPTION
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The LTC®2228/LTC2227/LTC2226 are 12-bit 65Msps/
40Msps/25Msps, low power 3V A/D converters designed
for digitizing high frequency, wide dynamic range signals.
The LTC2228/LTC2227/LTC2226 are perfect for demanding imaging and communications applications with AC
performance that includes 71.3dB SNR and 90dB SFDR
for signals at the Nyquist frequency.
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Sample Rate: 65Msps/40Msps/25Msps
Single 3V Supply (2.7V to 3.4V)
Low Power: 205mW/120mW/75mW
71.3dB SNR
90dB SFDR
No Missing Codes
Flexible Input: 1VP-P to 2VP-P Range
575MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Pin Compatible Family
125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit)
105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit)
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)
32-Pin (5mm × 5mm) QFN Package
DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high performance
at full speed for a wide range of clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIONS
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Wireless and Wired Broadband Communication
Imaging Systems
Ultrasound
Spectral Analysis
Portable Instrumentation
TYPICAL APPLICATION
REFH
REFL
LTC2228: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
72
FLEXIBLE
REFERENCE
OVDD
ANALOG
INPUT
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
D11
•
•
•
D0
OUTPUT
DRIVERS
OGND
CLOCK/DUTY
CYCLE
CONTROL
70
69
68
222876 TA01
CLK
SNR (dBFS)
71
+
0
100
150
50
INPUT FREQUENCY (MHz)
200
2228 G09
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1
LTC2228/LTC2227/LTC2226
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
OVDD = VDD (Notes 1, 2)
D9
D10
D11
OF
MODE
SENSE
VCM
TOP VIEW
VDD
Supply Voltage (VDD) ..................................................4V
Digital Output Ground Voltage (OGND) ........ –0.3V to 1V
Analog Input Voltage (Note 3) .......–0.3V to (VDD + 0.3V)
Digital Input Voltage......................–0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation .............................................1500mW
Operating Temperature Range
LTC2228C, LTC2227C, LTC2226C............. 0°C to 70°C
LTC2228I, LTC2227I, LTC2226I ............ –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
32 31 30 29 28 27 26 25
AIN+ 1
24 D8
AIN– 2
23 D7
REFH 3
22 D6
REFH 4
21 OVDD
33
REFL 5
20 OGND
REFL 6
19 D5
VDD 7
18 D4
GND 8
17 D3
D2
D1
D0
NC
NC
OE
CLK
SHDN
9 10 11 12 13 14 15 16
UH PACKAGE
32-LEAD (5mm s 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2228CUH#PBF
LTC2228CUH#TRPBF
2228
32-Lead (5mm × 5mm) Plastic QFN
0°C to 70°C
LTC2228IUH#PBF
LTC2228IUH#TRPBF
2228
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
LTC2227CUH#PBF
LTC2227CUH#TRPBF
2227
32-Lead (5mm × 5mm) Plastic QFN
0°C to 70°C
LTC2227IUH#PBF
LTC2227IUH#TRPBF
2227
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
LTC2226CUH#PBF
LTC2226CUH#TRPBF
2226
32-Lead (5mm × 5mm) Plastic QFN
0°C to 70°C
LTC2226IUH#PBF
LTC2226IUH#TRPBF
2226
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2228CUH
LTC2228CUH#TR
2228
32-Lead (5mm × 5mm) Plastic QFN
0°C to 70°C
LTC2228IUH
LTC2228IUH#TR
2228
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
LTC2227CUH
LTC2227CUH#TR
2227
32-Lead (5mm × 5mm) Plastic QFN
0°C to 70°C
LTC2227IUH
LTC2227IUH#TR
2227
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
LTC2226CUH
LTC2226CUH#TR
2226
32-Lead (5mm × 5mm) Plastic QFN
0°C to 70°C
LTC2226IUH
LTC2226IUH#TR
2226
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2228/LTC2227/LTC2226
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
Resolution
(No Missing Codes)
l
12
LTC2228
TYP
MAX
MIN
LTC2227
TYP
MAX
12
MIN
LTC2226
TYP
MAX
UNITS
12
Bits
Integral
Linearity Error
Differential Analog Input (Note 5)
l
–1.1
±0.3
1.1
–1
±0.3
1
–1
±0.3
1
LSB
Differential
Linearity Error
Differential Analog Input
l
–0.8
±0.15
0.8
–0.7
±0.15
0.7
–0.7
±0.15
0.7
LSB
Offset Error
(Note 6)
l
–12
±2
12
–12
±2
12
–12
±2
12
mV
Gain Error
External Reference
l
–2.5
±0.5
2.5
–2.5
±0.5
2.5
–2.5
±0.5
2.5
Offset Drift
Full-Scale Drift
Internal Reference
External Reference
Transition Noise
SENSE = 1V
%FS
±10
±10
±10
μV/°C
±30
±30
±30
ppm/°C
±5
±5
±5
ppm/°C
0.25
0.25
0.25
LSBRMS
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (AIN+ – AIN–)
2.7V < VDD < 3.4V (Note 7)
l
MIN
TYP
MAX
UNITS
VIN,CM
Analog Input Common Mode (AIN+ + AIN–)/2
Differential Input (Note 7)
Single-Ended Input (Note 7)
l
l
1
0.5
IIN
Analog Input Leakage Current
0V < AIN+, AIN– < VDD
l
ISENSE
SENSE Input Leakage
0V < SENSE < 1V
IMODE
MODE Pin Leakage
tAP
Sample-and-Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Time Jitter
0.2
psRMS
CMRR
Analog Input Common Mode Rejection Ratio
80
dB
575
MHz
±0.5V to ±1V
1.5
1.5
V
1.9
2
V
V
–1
1
μA
l
–3
3
μA
l
–3
3
μA
0
Full Power Bandwidth
Figure 8 Test Circuit
ns
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER
CONDITIONS
SNR
5MHz Input
12.5MHz Input
20MHz Input
30MHz Input
70MHz Input
140MHz Input
5MHz Input
12.5MHz Input
20MHz Input
30MHz Input
70MHz Input
140MHz Input
SFDR
Signal-to-Noise Ratio
Spurious Free
Dynamic Range
2nd or 3rd
Harmonic
MIN
LTC2228
TYP
MAX
MIN
71.3
LTC2227
TYP
MAX
71.4
l
l
l
70.1
70
71.3
71.3
71
90
l
75
90
85
80
70.2
71.4
71.2
76
70.9
70.6
90
90
71.1
70.7
90
76
LTC2226
TYP
MAX
71.3
l
l
MIN
90
85
80
85
80
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
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LTC2228/LTC2227/LTC2226
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER
CONDITIONS
SFDR
5MHz Input
12.5MHz Input
20MHz Input
30MHz Input
70MHz Input
140MHz Input
5MHz Input
12.5MHz Input
20MHz Input
30MHz Input
70MHz Input
140MHz Input
fIN1 = 28.2MHz,
fIN2 = 26.8MHz
S/(N+D)
IMD
Spurious Free
Dynamic Range
4th Harmonic
or Higher
Signal-to-Noise
Plus Distortion
Ratio
Intermodulation
Distortion
MIN
LTC2228
TYP
MAX
MIN
LTC2227
TYP
MAX
95
95
l
l
l
82
82
95
95
90
71.3
l
82
95
95
69.8
95
90
71.4
71.2
95
90
71.4
69.7
69.6
71.2
71.1
69.9
90
LTC2226
TYP
MAX
71.2
70.9
69.9
90
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
95
l
l
MIN
70.8
69.8
90
INTERNAL REFERENCE CHARACTERISTICS (Note 4)
PARAMETER
VCM Output Voltage
VCM Output Tempco
VCM Line Regulation
VCM Output Resistance
CONDITIONS
IOUT = 0
MIN
1.475
TYP
1.500
±25
3
4
2.7V < VDD < 3.4V
–1mA < IOUT < 1mA
MAX
1.525
UNITS
V
ppm/°C
mV/V
Ω
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
LOGIC INPUTS (CLK, OE, SHDN)
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
Input Current
IIN
Input Capacitance
CIN
LOGIC OUTPUTS
OVDD = 3V
Hi-Z Output Capacitance
COZ
Output Source Current
ISOURCE
Output Sink Current
ISINK
High Level Output Voltage
VOH
VOL
Low Level Output Voltage
OVDD = 2.5V
High Level Output Voltage
VOH
Low Level Output Voltage
VOL
OVDD = 1.8V
High Level Output Voltage
VOH
Low Level Output Voltage
VOL
CONDITIONS
VDD = 3V
VDD = 3V
VIN = 0V to VDD
(Note 7)
OE = High (Note 7)
VOUT = 0V
VOUT = 3V
IO = –10μA
IO = –200μA
IO = 10μA
IO = 1.6mA
MIN
l
TYP
2
l
3
3
50
50
2.995
2.99
0.005
0.09
pF
mA
mA
V
V
V
V
l
0.8
10
–10
2.7
UNITS
V
V
μA
pF
l
l
MAX
0.4
IO = –200μA
IO = 1.6mA
2.49
0.09
V
V
IO = –200μA
IO = 1.6mA
1.79
0.09
V
V
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LTC2228/LTC2227/LTC2226
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER
CONDITIONS
MIN
LTC2228
TYP
MAX
LTC2227
TYP
MAX
MIN
MIN
LTC2226
TYP
MAX
UNITS
VDD
Analog Supply Voltage (Note 9)
l
2.7
3
3.4
2.7
3
3.4
2.7
3
3.4
V
OVDD
Output Supply Voltage (Note 9)
l
0.5
3
3.6
0.5
3
3.6
0.5
3
3.6
V
IVDD
Supply Current
l
68.3
80
40
48
25
30
mA
PDISS
Power Dissipation
l
205
240
120
144
75
90
PSHDN
Shutdown Power
SHDN = H, OE = H,
No CLK
2
2
2
mW
PNAP
Nap Mode Power
SHDN = H, OE = L,
No CLK
15
15
15
mW
mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
fS
Sampling Frequency
(Note 9)
l
1
tL
CLK Low Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
l
l
7.3
5
tH
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
l
l
7.3
5
tAP
Sample-and-Hold
Aperture Delay
tD
CLK to DATA Delay
CL = 5pF (Note 7)
l
Data Access Time
After OE↓
CL = 5pF (Note 7)
BUS Relinquish Time
(Note 7)
LTC2228
TYP
MAX
MIN
65
1
7.7
7.7
500
500
11.8
5
7.7
7.7
500
500
11.8
5
0
1.4
5.4
l
4.3
l
3.3
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 65MHz (LTC2228), 40MHz (LTC2227), or
25MHz (LTC2226), input range = 2VP-P with differential drive, unless
otherwise noted.
5
MIN
40
1
12.5
500
500
18.9
5
12.5
12.5
500
500
18.9
5
0
2.7
Pipeline
Latency
LTC2227
TYP
MAX
1.4
UNITS
25
MHz
20
20
500
500
ns
ns
20
20
500
500
ns
ns
0
2.7
5.4
10
4.3
8.5
3.3
5
LTC2226
TYP
MAX
1.4
ns
2.7
5.4
ns
10
4.3
10
ns
8.5
3.3
8.5
5
ns
Cycles
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 65MHz (LTC2228), 40MHz (LTC2227), or
25MHz (LTC2226), input range = 1VP-P with differential drive.
Note 9: Recommend operating conditions.
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LTC2228/LTC2227/LTC2226
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2228: Typical INL, 2V Range,
65Msps
0
1.00
0.75
0.50
0.50
0.25
0
–0.25
–0.50
–10
–20
–30
AMPLITUDE (dB)
0.75
DNL ERROR (LSB)
INL ERROR (LSB)
1.00
0.25
0
–0.25
–0.75
–1.00
–1.00
1024
0
2048
CODE
3072
4096
–50
–60
–70
–80
–100
–110
–120
0
1024
2048
CODE
3072
2228 G01
4096
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dB)
0
–10
AMPLITUDE (dB)
0
–10
–60
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
5
10
15
20
25
FREQUENCY (MHz)
30
0
5
0
5
10
15
20
25
FREQUENCY (MHz)
2228 G05
LTC2228: 8192 Point 2-Tone FFT,
fIN = 28.2MHz and 26.8MHz,
–1dB, 2V Range, 65Msps
LTC2228: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
70000
0
30
2228 G06
LTC2228: Grounded Input
Histogram, 65Msps
72
–10
61496
60000
–20
–30
71
COUNT
–50
–60
–70
–80
SNR (dBFS)
50000
–40
40000
30000
20000
–90
–100
70
69
10000
–110
–120
–120
30
10
15
20
25
FREQUENCY (MHz)
2228 G04
30
–40
–90
0
10
15
20
25
FREQUENCY (MHz)
2228 G03
0
–50
5
LTC2228: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
65Msps
–10
–40
0
2228 G02
LTC2228: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
65Msps
LTC2228: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
65Msps
AMPLITUDE (dB)
–40
–90
–0.50
–0.75
AMPLITUDE (dB)
LTC2228: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
65Msps
LTC2228: Typical DNL, 2V Range,
65Msps
2123
0
5
10
15
20
25
FREQUENCY (MHz)
30
2228 G07
1910
0
2042
2043
CODE
2044
2228 G08
68
0
100
150
50
INPUT FREQUENCY (MHz)
200
2228 G09
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LTC2228/LTC2227/LTC2226
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2228: SNR and SFDR vs Sample
Rate, 2V Range,fIN = 5MHz, –1dB
LTC2228: SFDR vs Input Frequency,
–1dB, 2V Range, 65Msps
100
LTC2228: SNR and SFDR vs Clock
Duty Cycle, 65Msps
110
100
95
95
85
80
75
SFDR
90
80
SNR
SFDR: DCS ON
SFDR: DCS OFF
90
85
80
75
SNR: DCS ON
70
70
70
65
50
100
150
INPUT FREQUENCY (MHz)
200
60
20
0
60
80
40
SAMPLE RATE (Msps)
65
100
2228 G10
SNR: DCS OFF
30
35
45 50 55 60
CLOCK DUTY CYCLE (%)
40
2228 G11
65
70
2228 G12
LTC2228: SFDR vs Input Level,
fIN = 30MHz, 2V Range, 65Msps
LTC2228: SNR vs Input Level,
fIN = 30MHz, 2V Range, 65Msps
120
80
dBFS
110
70
dBFS
100
60
50
SFDR (dBc AND dBFS)
SNR (dBc AND dBFS)
dBc
40
30
20
90
80
dBc
70
60
90dBc SFDR
REFERENCE LINE
50
40
10
30
0
–60
–50
–40
–30
–20
INPUT LEVEL (dBFS)
–10
20
–60
0
–50
–40
–30
–20
INPUT LEVEL (dBFS)
2228 G13
80
6
75
5
70
4
2V RANGE
65
1V RANGE
3
60
2
55
1
0
10
20 30 40 50 60
SAMPLE RATE (Msps)
70
0
LTC2228: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
LTC2228: IVDD vs Sample Rate,
5mHz Sine Wave Input, –1dB
50
–10
2228 G14
IOVDD (mA)
0
IVDD (mA)
SFDR (dBFS)
90
SNR AND SFDR (dBFS)
SNR AND SFDR (dBFS)
100
80
2228 G15
0
0
10
20 30 40 50 60
SAMPLE RATE (Msps)
70
80
2228 G16
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LTC2228/LTC2227/LTC2226
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2227: Typical INL, 2V Range,
40Msps
0
1.00
0.75
0.50
0.50
0.25
0
–0.25
–0.50
–10
–20
–30
AMPLITUDE (dB)
0.75
DNL ERROR (LSB)
INL ERROR (LSB)
1.00
0.25
0
–0.25
–0.50
–0.75
–0.75
–1.00
–1.00
0
1024
2048
CODE
3072
–50
–60
–70
–80
–90
–110
1024
2048
CODE
3072
2227 G01
–120
4096
0
–10
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dB)
0
–10
–60
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
5
10
15
FREQUENCY (MHz)
20
0
5
10
15
FREQUENCY (MHz)
2227 G04
0
5
10
15
FREQUENCY (MHz)
0
20
2227 G06
LTC2227: Grounded Input
Histogram, 40Msps
LTC2227: SNR vs Input Frequency,
–1dB, 2V Range, 40Msps
72
70000
–10
61538
60000
–20
–30
71
COUNT
–50
–60
–70
–80
SNR (dBFS)
50000
–40
40000
30000
20000
–90
–100
70
69
10000
–110
–120
–120
20
2227 G05
LTC2227: 8192 Point 2-Tone FFT,
fIN = 21.6MHz and 23.6MHz,
–1dB, 2V Range, 40Msps
20
–40
–90
0
10
15
FREQUENCY (MHz)
2227 G03
0
–50
5
LTC2227: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
40Msps
–10
–40
0
2227 G02
LTC2227: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
40Msps
AMPLITUDE (dB)
AMPLITUDE (dB)
–40
–100
0
4096
LTC2228: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
40Msps
AMPLITUDE (dB)
LTC2227: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
40Msps
LTC2227: Typical DNL, 2V Range,
40Msps
2558
1424
0
0
5
10
15
FREQUENCY (MHz)
20
2227 G07
68
2050
2051
CODE
2052
2227 G08
0
100
150
50
INPUT FREQUENCY (MHz)
200
2227 G09
222876fb
8
LTC2228/LTC2227/LTC2226
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2227: SFDR vs Input Frequency,
–1dB, 2V Range, 40Msps
LTC2227: SNR and SFDR vs Sample
Rate, 2V Range,fIN = 5MHz, –1dB
110
100
80
dBFS
95
85
80
75
SNR (dBc AND dBFS)
SNR AND SFDR (dBFS)
90
70
SFDR
100
SFDR (dBFS)
LTC2227: SNR vs Input Level,
fIN = 5MHz, 2V Range, 40Msps
90
80
SNR
60
50
dBc
40
30
20
70
70
10
65
0
–60
60
0
50
100
0
200
150
INPUT FREQUENCY (MHz)
20
40
60
SAMPLE RATE (Msps)
80
–50
–40
–30
–20
INPUT LEVEL (dBFS)
–10
2227 G12
2227 G11
2227 G10
LTC2227: SFDR vs Input Level,
fIN = 5MHz, 2V Range, 40Msps
LTC2227: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
LTC2227: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
120
0
50
4
45
3
110
dBFS
80
dBc
70
60
90dBc SFDR
REFERENCE LINE
50
2V RANGE
IOVDD (mA)
90
IVDD (mA)
SNR (dBc AND dBFS)
100
40
1V RANGE
35
2
1
40
30
20
–60
30
–50
–40
–30
–20
–10
0
0
10
20
30
40
50
SAMPLE RATE (Msps)
INPUT LEVEL (dBFS)
2227 G13
0
0
10
20
30
40
50
SAMPLE RATE (Msps)
2227 G14
2227 G15
222876fb
9
LTC2228/LTC2227/LTC2226
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2226: Typical INL, 2V Range,
25Msps
0
1.00
0.75
0.50
0.50
0.25
0
–0.25
–0.50
–10
–20
–30
AMPLITUDE (dB)
0.75
DNL ERROR (LSB)
INL ERROR (LSB)
1.00
0.25
0
–0.25
–0.75
–1.00
–1.00
1024
0
2048
CODE
3072
4096
–50
–60
–70
–80
–90
–100
–110
1024
0
2048
CODE
3072
2226 G01
–120
4096
0
–10
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dB)
0
–10
AMPLITUDE (dB)
0
–60
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
2
4
6
8
FREQUENCY (MHz)
10
12
0
2
4
6
8
FREQUENCY (MHz)
2226 G04
12
10
–120
0
2
4
6
8
FREQUENCY (MHz)
10
2226 G05
LTC2226: 8192 Point 2-Tone FFT,
fIN = 10.9MHz and 13.8MHz,
–1dB, 2V Range, 25Msps
12
2226 G06
LTC2226: Grounded Input
Histogram, 25Msps
0
12
10
–40
–90
0
4
6
8
FREQUENCY (MHz)
LTC2226: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
25Msps
–10
–50
2
2226 G03
LTC2226: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
25Msps
–40
0
2226 G02
LTC2226: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
25Msps
AMPLITUDE (dB)
–40
–0.50
–0.75
LTC2226: SNR vs Input Frequency,
–1dB, 2V Range, 25Msps
72
70000
61758
–10
60000
–20
71
–30
–50
–60
–70
SNR (dBFS)
50000
–40
COUNT
AMPLITUDE (dB)
LTC2226: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
25Msps
LTC2226: Typical DNL, 2V Range,
25Msps
40000
30000
70
–80
20000
–90
–100
10000
–110
–120
69
2155
0
2
4
6
8
FREQUENCY (MHz)
10
12
2226 G07
10
0
1607
68
2048
2049
CODE
2050
2226 G08
0
100
150
50
INPUT FREQUENCY (MHz)
200
2226 G09
222876fb
LTC2228/LTC2227/LTC2226
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2226: SFDR vs Input Frequency,
–1dB, 2V Range, 25Msps
LTC2226: SNR and SFDR vs Sample
Rate, 2V Range,fIN = 5MHz, –1dB
100
LTC2226: SNR vs Input Level,
fIN = 5MHz, 2V Range, 25Msps
110
80
dBFS
95
SFDR (dBFS)
85
80
75
SNR (dBc AND dBFS)
SNR AND SFDR (dBFS)
100
90
70
SFDR
90
80
SNR
50
dBc
40
30
20
70
70
10
65
50
100
60
200
150
INPUT FREQUENCY (MHz)
0
10
0
30
40
20
SAMPLE RATE (Msps)
2226 G10
0
–60
50
–50
–40
–30
–20
INPUT LEVEL (dBFS)
–10
LTC2226: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
LTC2226: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
35
120
0
2227 G12
2226 G11
LTC2226: SFDR vs Input Level,
fIN = 5MHz, 2V Range, 25Msps
3
dBFS
110
100
30
90
2V RANGE
dBc
70
60
90dBc SFDR
REFERENCE LINE
50
2
IOVDD (mA)
80
IVDD (mA)
SFDR (dBc AND dBFS)
60
25
1V RANGE
1
20
40
30
20
–60
15
–50
–40
–30
–20
INPUT LEVEL (dBFS)
–10
0
2226 G13
0
5
10
15
20
25
SAMPLE RATE (Msps)
30
35
2226 G14
0
0
5
10 15
25
20
SAMPLE RATE (Msps)
30
35
2226 G15
222876fb
11
LTC2228/LTC2227/LTC2226
PIN FUNCTIONS
AIN+ (Pin 1): Positive Differential Analog Input.
NC (Pins 12, 13): Do Not Connect These Pins.
AIN– (Pin 2): Negative Differential Analog Input.
D0-D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26,
27): Digital Outputs. D11 is the MSB.
REFH (Pins 3, 4): ADC High Reference. Short together and
bypass to Pins 5, 6 with a 0.1μF ceramic chip capacitor as
close to the pin as possible. Also bypass to Pins 5, 6 with
an additional 2.2μF ceramic chip capacitor and to ground
with a 1μF ceramic chip capacitor.
REFL (Pins 5, 6): ADC Low Reference. Short together and
bypass to Pins 3, 4 with a 0.1μF ceramic chip capacitor as
close to the pin as possible. Also bypass to Pins 3, 4 with
an additional 2.2μF ceramic chip capacitor and to ground
with a 1μF ceramic chip capacitor.
VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1μF
ceramic chip capacitors.
GND (Pin 8): ADC Power Ground.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting
SHDN to GND and OE to GND results in normal operation
with the outputs enabled. Connecting SHDN to GND and
OE to VDD results in normal operation with the outputs at
high impedance. Connecting SHDN to VDD and OE to GND
results in nap mode with the outputs at high impedance.
Connecting SHDN to VDD and OE to VDD results in sleep
mode with the outputs at high impedance.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin
function.
OGND (Pin 20): Output Driver Ground.
OVDD (Pin 21): Positive Supply for the Output Drivers.
Bypass to ground with 0.1μF ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 VDD selects offset binary output format
and turns the clock duty cycle stabilizer on. 2/3 VDD selects
2’s complement output format and turns the clock duty
cycle stabilizer on. VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 30): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
VCM (Pin 31): 1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2μF ceramic chip capacitor.
Exposed Pad (Pin 33): ADC Power Ground. The Exposed
Pad on the bottom of the package needs to be soldered
to ground.
222876fb
12
LTC2228/LTC2227/LTC2226
FUNCTIONAL BLOCK DIAGRAM
AIN+
AIN–
VCM
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
1.5V
REFERENCE
SIXTH PIPELINED
ADC STAGE
SHIFT REGISTER
AND CORRECTION
2.2μF
RANGE
SELECT
REFH
SENSE
REFL
INTERNAL CLOCK SIGNALS
OVDD
REF
BUF
OF
D11
CLOCK/DUTY
CYCLE
CONTROL
DIFF
REF
AMP
CONTROL
LOGIC
OUTPUT
DRIVERS
•
•
•
D0
REFH
0.1μF
222876 F01
REFL
OGND
CLK
M0DE
SHDN
OE
2.2μF
1μF
1μF
Figure 1. Functional Block Diagram
222876fb
13
LTC2228/LTC2227/LTC2226
TIMING DIAGRAM
Timing Diagram
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
N+5
N+1
tL
CLK
tD
D0-D11, OF
N–5
N–4
N–3
N–2
N–1
N
222876 TD01
222876fb
14
LTC2228/LTC2227/LTC2226
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other
frequency components at the ADC output. The output is
band limited to frequencies above DC to below half the
sampling frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1)
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second
through nth harmonics. The THD calculated in this data
sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa ± nfb, where m and n = 0,
1, 2, 3, etc. The 3rd order intermodulation products are
2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of
either input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding
the input signal and DC. This value is expressed in decibels
relative to the RMS value of a full-scale input signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced
by 3dB for a full-scale input signal.
Aperture Delay Time
The time from when CLK reaches mid-supply to the instant that the input signal is held by the sample-and-hold
circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
222876fb
15
LTC2228/LTC2227/LTC2226
APPLICATIONS INFORMATION
CONVERTER OPERATION
SAMPLE/HOLD OPERATION AND INPUT DRIVE
As shown in Figure 1, the LTC2228/LTC2227/LTC2226
is a CMOS pipelined multi-step converter. The converter
has six pipelined ADC stages; a sampled analog input will
result in a digitized value five cycles later (see the Timing
Diagram section). For optimal AC performance the analog
inputs should be driven differentially. For cost sensitive
applications, the analog inputs can be driven single-ended
with slightly worse harmonic distortion. The CLK input is
single-ended. The LTC2228/LTC2227/LTC2226 has two
phases of operation, determined by the state of the CLK
input pin.
Sample/Hold Operation
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the Block Diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the
first stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back to
acquiring the analog input. When CLK goes back high, the
second stage produces its residue which is acquired by the
third stage. An identical process is repeated for the third,
fourth and fifth stages, resulting in a fifth stage residue
that is sent to the sixth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
Figure 2 shows an equivalent circuit for the LTC2228/
LTC2227/LTC2226 CMOS differential sample-and-hold.
The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors
shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage. When
CLK transitions from low to high, the sampled input voltage
is held on the sampling capacitors. During the hold phase
when CLK is high, the sampling capacitors are disconnected
from the input and the held voltage is passed to the ADC
core for processing. As CLK transitions from high to low,
the inputs are reconnected to the sampling capacitors to
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional to
the change in voltage between samples will be seen at this
time. If the change between the last sample and the new
sample is small, the charging glitch seen at the input will
be small. If the input change is large, such as the change
seen with input frequencies near Nyquist, then a larger
charging glitch will be seen.
LTC2228/27/26
VDD
AIN+
CSAMPLE
4pF
15Ω
CPARASITIC
1pF
VDD
AIN–
CSAMPLE
4pF
15Ω
CPARASITIC
1pF
VDD
CLK
222876 F02
Figure 2. Equivalent Input Circuit
222876fb
16
LTC2228/LTC2227/LTC2226
APPLICATIONS INFORMATION
however, this is not always possible and the incomplete
settling may degrade the SFDR. The sampling glitch has
been designed to be as linear as possible to minimize the
effects of incomplete settling.
Single-Ended Input
For cost-sensitive applications, the analog inputs can be
driven single ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to 1.5V or VCM.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Common Mode Bias
For optimal performance the analog inputs should be driven
differentially. Each input should swing ±0.5V for the 2V
range or ±0.25V for the 1V range, around a common mode
voltage of 1.5V. The VCM output pin (Pin 31) may be used
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with a 2.2μF or greater capacitor.
Input Drive Circuits
Figure 3 shows the LTC2228/LTC2227/LTC2226 being
driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM,
setting the ADC input signal at its optimum DC level.
Terminating on the transformer secondary is desirable,
as this provides a common mode path for charging
glitches caused by the sample and hold. Figure 3 shows
a 1:1 turns ratio transformer. Other turns ratios can be
used if the source impedance seen by the ADC does not
exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response.
Most small RF transformers have poor performance at
frequencies below 1MHz.
Input Drive Impedance
As with all high performance, high speed ADCs, the dynamic performance of the LTC2228/LTC2227/LTC2226 can
be influenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and input
reactance can influence SFDR. At the falling edge of CLK,
the sample-and-hold circuit will connect the 4pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when CLK rises, holding the
sampled input on the sampling capacitor. Ideally the input
circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE);
Figure 4 demonstrates the use of a differential amplifier to
convert a single-ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of most op amps will limit the SFDR at high
input frequencies.
VCM
2.2μF
0.1μF
ANALOG
INPUT
T1
1:1
25Ω
25Ω
AIN+
LTC2228/27/26
0.1μF
12pF
25Ω
25Ω
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
222876 F03
Figure 3. Single-Ended to Differential Conversion Using a Transformer
222876fb
17
LTC2228/LTC2227/LTC2226
APPLICATIONS INFORMATION
VCM
HIGH SPEED
DIFFERENTIAL
25Ω
AMPLIFIER
ANALOG
INPUT
+
2.2μF
AIN+
2.2μF
0.1μF
LTC2228/27/26
LTC2228/27/26
25Ω
25Ω
0.1μF
T1
12pF
–
0.1μF
AIN–
AIN+
12Ω
ANALOG
INPUT
+
CM
–
VCM
8pF
25Ω
AIN–
12Ω
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
222876 F04
222876 F06
Figure 4. Differential Drive with an Amplifier
Figure 5 shows a single-ended input circuit. The impedance
seen by the analog inputs should be matched. This circuit
is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input.
Figure 6. Recommended Front-End Circuit for
Input Frequencies Between 70MHz and 170MHz
VCM
2.2μF
0.1μF
AIN+
ANALOG
INPUT
25Ω
LTC2228/27/26
0.1μF
T1
0.1μF
25Ω
AIN–
VCM
1k
0.1μF
ANALOG
INPUT
1k
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2.2μF
AIN+
25Ω
LTC2228/27/26
Figure 7. Recommended Front-End Circuit for
Input Frequencies Between 170MHz and 300MHz
12pF
25Ω
222876 F07
AIN–
0.1μF
VCM
222876 F05
2.2μF
0.1μF
Figure 5. Single-Ended Drive
6.8nH
ANALOG
INPUT
25Ω
For input frequencies above 70MHz, the input circuits of
Figure 6, 7 and 8 are recommended. The balun transformer
gives better high frequency response than a flux coupled
center tapped transformer. The coupling capacitors allow
the analog inputs to be DC biased at 1.5V. In Figure 8, the
series inductors are impedance matching elements that
maximize the ADC bandwidth.
AIN+
LTC2228/27/26
0.1μF
T1
0.1μF
25Ω
6.8nH
AIN–
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
222876 F08
Figure 8. Recommended Front-End Circuit for
Input Frequencies Above 300MHz
222876fb
18
LTC2228/LTC2227/LTC2226
TYPICAL APPLICATIONS
Reference Operation
Figure 9 shows the LTC2228/LTC2227/LTC2226 reference circuitry consisting of a 1.5V bandgap reference,
a difference amplifier and switching and control circuit.
The internal voltage reference can be configured for two
pin selectable input ranges of 2V (±1V differential) or 1V
(±0.5V differential). Tying the SENSE pin to VDD selects
the 2V range; tying the SENSE pin to VCM selects the 1V
range.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required
for the 1.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
The difference amplifier generates the high and low
reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9.
Other voltage ranges in-between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to
SENSE. It is not recommended to drive the SENSE pin
with a logic device. The SENSE pin should be tied to the
appropriate level as close to the converter as possible. If
the SENSE pin is driven externally, it should be bypassed
to ground as close to the device as possible with a 1μF
ceramic capacitor.
LTC2228/27/26
4Ω
VCM
1.5V
1.5V BANDGAP
REFERENCE
2.2μF
1V
0.5V
RANGE
DETECT
AND
CONTROL
TIE TO VDD FOR 2V RANGE;
TIE TO VCM FOR 1V RANGE;
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V
SENSE
BUFFER
INTERNAL ADC
HIGH REFERENCE
1μF
REFH
2.2μF
0.1μF
DIFF AMP
1μF
REFL
INTERNAL ADC
LOW REFERENCE
222876 F09
Figure 9. Equivalent Reference Circuit
1.5V
VCM
2.2μF
12k
0.75V
12k
SENSE
LTC2228/27/26
1μF
222876 F10
Figure 10. 1.5V Range ADC
222876fb
19
LTC2228/LTC2227/LTC2226
APPLICATIONS INFORMATION
Input Range
The input range can be set based on the application.
The 2V input range will provide the best signal-to-noise
performance while maintaining excellent SFDR. The 1V
input range will have better SFDR performance, but the
SNR will degrade by 3.8dB. See the Typical Performance
Characteristics section.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or
TTL level signal. A sinusoidal clock can also be used
along with a low jitter squaring circuit before the CLK pin
(Figure 11).
The noise performance of the LTC2228/LTC2227/LTC2226
can depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
result in additional aperture jitter that will be RMS summed
with the inherent ADC aperture jitter.
The nature of the received signals also has a large bearing on how much SNR degradation will be experienced.
For high crest factor signals such as WCDMA or OFDM,
where the nominal power level must be at least 6dB to
8dB below full scale, the use of these translators will have
a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed
to ground through a capacitor close to the ADC if the
differential signals originate on a different plane. The
use of a capacitor at the input may result in peaking, and
depending on transmission line length may require a 10Ω
to 20Ω series resistor to act as both a lowpass filter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for reflections.
In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude
as possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
to phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz will
degrade the SNR compared to the transformer solution.
4.7μF
FERRITE
BEAD
0.1μF
CLK
100Ω
LTC2238/
LTC2237/
LTC2236
223876 F12
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 12. CLK Drive Using an LVDS or PECL-to-CMOS Converter
CLEAN
SUPPLY
4.7μF
CLEAN
SUPPLY
FERRITE
BEAD
ETC1-1T
1k
5pF-30pF
0.1μF
CLK
SINUSOIDAL
CLOCK INPUT
50Ω
1k
CLK
0.1μF
NC7SVU04
LTC2228/
LTC2227/
LTC2226
DIFFERENTIAL
CLOCK
INPUT
223876 F13
0.1μF
222876 F11
Figure 11. Single-Ended CLK Drive
LTC2238/
LTC2237/
LTC2236
FERRITE
BEAD
VCM
Figure 13. LVDS or PECL CLK Drive Using a Transformer
222876fb
20
LTC2228/LTC2227/LTC2226
APPLICATIONS INFORMATION
Maximum and Minimum Conversion Rates
DIGITAL OUTPUTS
The maximum conversion rate for the LTC2228/LTC2227/
LTC2226 is 65Msps (LTC2228), 40Msps (LTC2227), and
25Msps (LTC2226). For the ADC to operate properly, the
CLK signal should have a 50% (±5%) duty cycle. Each
half cycle must have at least 7.3ns (LTC2228), 11.8ns
(LTC2227), and 18.9ns (LTC2226) for the ADC internal circuitry to have enough settling time for proper operation.
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overflow bit.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 40% to 60% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2228/LTC2227/LTC2226 sample
rate is determined by droop of the sample-and-hold circuits.
The pipelined architecture of this ADC relies on storing
analog signals on small-valued capacitors. Junction leakage will discharge the capacitors. The specified minimum
operating frequency for the LTC2228/LTC2227/LTC2226
is 1Msps.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
OF
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
>+1.000000V
+0.999512V
+0.999024V
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
0
0
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.999512V
–1.000000V
<–1.000000V
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
1000 0000 0001
1000 0000 0000
1000 0000 0000
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
LTC2228/27/26
OVDD
VDD
0.5V
TO 3.6V
VDD
0.1μF
OVDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
OE
OGND
222876 F14
Figure 14. Digital Output Buffer
222876fb
21
LTC2228/LTC2227/LTC2226
APPLICATIONS INFORMATION
digital outputs of the LTC2228/LTC2227/LTC2226 should
drive a minimal capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to allow
the outputs to be enabled and disabled during full speed
operation. The output Hi-Z state is intended for use during
long periods of inactivity.
Sleep and Nap Modes
Data Format
Using the MODE pin, the LTC2228/LTC2227/LTC2226
parallel digital output can be selected for offset binary
or 2’s complement format. Connecting MODE to GND or
1/3VDD selects offset binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 2 shows the logic
states for the MODE pin.
Table 2. MODE Pin Function
MODE PIN
OUTPUT FORMAT
CLOCK DUTY
CYCLE STABILIZER
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overflow Bit
When OF outputs a logic high the converter is either overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
For example if the converter is driving a DSP powered
by a 1.8V supply, then OVDD should be tied to that same
1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND
up to 1V and must be less than OVDD. The logic outputs
will swing between OGND and OVDD.
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors
have to recharge and stabilize. Connecting SHDN to VDD
and OE to GND results in nap mode, which typically dissipates 15mW. In nap mode, the on-chip reference circuit
is kept on, so that recovery from nap mode is faster than
that from sleep mode, typically taking 100 clock cycles. In
both sleep and nap modes, all digital outputs are disabled
and enter the Hi-Z state.
Grounding and Bypassing
The LTC2228/LTC2227/LTC2226 require a printed circuit
board with a clean, unbroken ground plane. A multilayer
board with an internal ground plane is recommended.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much
as possible. In particular, care should be taken not to
run any digital track alongside an analog signal track or
underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of
particular importance is the 0.1μF capacitor between REFH
and REFL. This capacitor should be placed as close to the
device as possible (1.5mm or less). A size 0402 ceramic
capacitor is recommended. The large 2.2μF capacitor between REFH and REFL can be somewhat further away. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
222876fb
22
LTC2228/LTC2227/LTC2226
TYPICAL APPLICATIONS
The LTC2228/LTC2227/LTC2226 differential inputs should
run parallel and close to each other. The input traces should
be as short as possible to minimize capacitance and to
minimize noise pickup.
Heat Transfer
Most of the heat generated by the LTC2228/LTC2227/
LTC2226 is transferred from the die through the bottomside Exposed Pad and package leads onto the printed
circuit board. For good electrical and thermal performance,
the exposed pad should be soldered to a large grounded
pad on the PC board. It is critical that all ground pins are
connected to a ground plane of sufficient area.
Clock Sources for Undersampling
Undersampling raises the bar on the clock source and the
higher the input frequency, the greater the sensitivity to
clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a 3V canned oscillator from vendors such as Saronix
or Vectron can be placed close to the ADC and simply
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
may occur even over a fraction of an inch is advisable.
You must not allow the clock to overshoot the supplies or
performance will suffer. Do not filter the clock signal with
a narrow band filter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
the filter and the ADC. If you are sensitive to close-in phase
noise, the power supply for oscillators and any buffers
must be very stable, or propagation delay variation with
supply will translate into phase noise. Even though these
clock sources may be regarded as digital devices, do not
operate them on a digital supply. If your clock is also used
to drive digital devices such as an FPGA, you should locate
the oscillator, and any clock fan-out devices close to the
ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination
at the source to prevent high frequency noise from the
FPGA disturbing the substrate of the clock fan-out device.
If you use an FPGA as a programmable divider, you must
re-time the signal using the original oscillator, and the retiming flip-flop as well as the oscillator should be close to
the ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated in
the waveguides that exist between the layers of multilayer
PCBs. The differential pairs must be close together, and
distanced from other signals. The differential pair should
be guarded on both sides with copper distanced at least
3x the distance between the traces, and grounded with
vias no more than 1/4 inch apart.
222876fb
23
24
J3
CLOCK
INPUT
VCM
VDD
R9
1k
R7
1k
NC7SVU04
VCM
VDD
4
2
EXT REF
5
6
3
1
JP3 SENSE
4
•
C19
0.1μF
R10
33Ω
VDD
GND
VDD
R16
1k
R15
1k
1/3VDD
2/3VDD
VDD
6
4
2
GND
C15
2.2μF
VDD
7 GND 8
5
3
1
C8
0.1μF
29
30
31
32
11
10
9
8
7
6
5
4
3
2
1
C20
0.1μF
C2
12pF
C11
0.1μF
VDD
JP4 MODE
JP2
OE
C7
2.2μF
R6
24.9Ω
R4
24.9Ω
C4
0.1μF
R14
1k
VDD
R2
24.9Ω
R3
24.9Ω
C14
0.1μF VCM
VDD
VDD
C9
1μF
C6
1μF
JP1
SHDN
R5
50Ω
•3
2
T1
ETC1-1T
5
1
C13
0.1μF
C3
0.1μF VCM
C1
0.1μF
C10
0.1μF
C5
4.7μF
6.3V
NC7SVU04
R1
OPT
E1
EXT REF
R8
49.9Ω
C12
0.1μF
VDD
L1
BEAD
J1
ANALOG
INPUT
D0
REFH
C26
10μF
6.3V
33
R18
100k
R17
105k
OGND
MODE
GND
OVDD
OF
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
SENSE
VCM
VDD
OE
SHDN
CLK
GND
VDD
REFL
REFL
D1
NC
AIN–
REFH
NC
AIN+
LTC2228/LTC2227/
LTC2226
VCC
LT1763
C16
0.1μF
VCC
VCC
OE1
47
I0
46
I1
44
I2
43
I3
41
I4
40
I5
38
I6
37
I7
36
I8
35
I9
33
I10
32
I11
30
I12
29
I13
27
I14
26
I15
VDD
C28
1μF
VCC
GND
OE2
1
24
7
4
10
18
15
21
31
28
E3
GND
C18
0.1μF
C25
4.7μF E4
PWR
GND
E2
VDD
3V
1
A0
2
A1
3
A2
4
A3
SDA
SCL
WP
VCC
5
6
8
7
C17 0.1μF
24LC025
RN4A 33Ω
RN4B 33Ω
RN4C 33Ω
RN4D 33Ω
RN3A 33Ω
RN3B 33Ω
RN3C 33Ω
RN3D 33Ω
RN2A 33Ω
RN2B 33Ω
RN2C 33Ω
RN2D 33Ω
RN1A 33Ω
RN1B 33Ω
RN1C 33Ω
RN1D 33Ω
VCC
VDD
2
O0
3
O1
5
O2
6
O3
8
O4
9
O5
11
O6
12
O7
13
O8
14
O9
16
O10
17
O11
19
O12
20
O13
22
O14
23
O15
VCC
48
GND
VCC
LE1
GND
GND
GND
GND
GND
GND
74VCX16373MTD
LE2
25
42
39
45
34
NC7SV86P5X
1
8
IN
OUT
2
7
ADJ GND
3
6
GND GND
4
5
BYP SHDN
VCC
C27
0.01μF
20
21
28
27
26
25
24
23
22
19
18
17
16
15
14
13
12
VCC
C21
0.1μF
R11
10k
R12
10k
C22
0.1μF
VCC
R13
10k
C23
0.1μF
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
40
38
222876 TA02
C24
0.1μF
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
3201S-40G1
39
39
37
37
35
35
33
33
31
31
29
29
27
27
25
25
23
23
21
21
19
19
17
17
15
15
13
13
11
11
9
9
7
7
5
5
3
3
1
1
LTC2228/LTC2227/LTC2226
APPLICATIONS INFORMATION
222876fb
LTC2228/LTC2227/LTC2226
APPLICATIONS INFORMATION
Silkscreen Top
Topside
Inner Layer 2 GND
222876fb
25
LTC2228/LTC2227/LTC2226
APPLICATIONS INFORMATION
Inner Layer 3 Power
Bottomside
Silkscreen Bottom
222876fb
26
LTC2228/LTC2227/LTC2226
PACKAGE DESCRIPTION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 p0.05
5.50 p0.05
4.10 p0.05
3.45 p 0.05
3.50 REF
(4 SIDES)
3.45 p 0.05
PACKAGE OUTLINE
0.25 p 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 p 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75 p 0.05
R = 0.05
TYP
0.00 – 0.05
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 s 45o CHAMFER
R = 0.115
TYP
31 32
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.50 REF
(4-SIDES)
3.45 p 0.10
3.45 p 0.10
(UH32) QFN 0406 REV D
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 p 0.05
0.50 BSC
222876fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2228/LTC2227/LTC2226
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1748
14-Bit, 80Msps, 5V ADC
76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
LTC1750
14-Bit, 80Msps, 5V Wideband ADC
Up to 500MHz IF Undersampling, 90dB SFDR
LT1993-2
High Speed Differential Op Amp
800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
LT1994
Low Noise, Low Distortion Fully Differential
Input/Output Amplifier/Driver
Low Distortion: –94dBc at 1MHz
LTC2202
16-Bit, 10Msps, 3V ADC, Lowest Power
150mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2208
16-Bit, 130Msps, 3V ADC, LVDS Outputs
1250mW, 78dB SNR, 100dB SFDR, 64-Pin QFN
LTC2220-1
12-Bit, 185Msps, 3V ADC, LVDS Outputs
910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
LTC2224
12-Bit, 135Msps, 3V ADC, High IF Sampling
630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
LTC2225
12-Bit, 10Msps, 3V ADC, Lowest Power
60mW, 71.3dB SNR, 90dB SFDR, 32-Pin QFN
LTC2226
12-Bit, 25Msps, 3V ADC, Lowest Power
75mW, 71.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2227
12-Bit, 40Msps, 3V ADC, Lowest Power
120mW, 71.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2228
12-Bit, 65Msps, 3V ADC, Lowest Power
205mW, 71.3dB SNR, 90dB SFDR, 32-Pin QFN
LTC2229
12-Bit, 80Msps, 3V ADC, Lowest Power
211mW, 70.6dB SNR, 90dB SFDR, 32-Pin QFN
LTC2236
10-Bit, 25Msps, 3V ADC, Lowest Power
75mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
LTC2237
10-Bit, 40Msps, 3V ADC, Lowest Power
120mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
LTC2238
10-Bit, 65Msps, 3V ADC, Lowest Power
205mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
LTC2239
10-Bit, 80Msps, 3V ADC, Lowest Power
211mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2245
14-Bit, 10Msps, 3V ADC, Lowest Power
60mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2246
14-Bit, 25Msps, 3V ADC, Lowest Power
75mW, 74.5dB SNR, 90dB SFDR, 32-Pin QFN
LTC2247
14-Bit, 40Msps, 3V ADC, Lowest Power
120mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2248
14-Bit, 65Msps, 3V ADC, Lowest Power
205mW, 74.3dB SNR, 90dB SFDR, 32-Pin QFN
LTC2249
14-Bit, 80Msps, 3V ADC, Lowest Power
222mW, 73dB SNR, 90dB SFDR, 32-Pin QFN
LTC2250
10-Bit, 105Msps, 3V ADC, Lowest Power
320mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2251
10-Bit, 125Msps, 3V ADC, Lowest Power
395mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2252
12-Bit, 105Msps, 3V ADC, Lowest Power
320mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN
LTC2253
12-Bit, 125Msps, 3V ADC, Lowest Power
395mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN
LTC2254
14-Bit, 105Msps, 3V ADC, Lowest Power
320mW, 72.4dB SNR, 88dB SFDR, 32-Pin QFN
LTC2255
14-Bit, 125Msps, 3V ADC, Lowest Power
395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
LTC2284
14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
LT5512
DC-3GHz High Signal Level Downconverting Mixer
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514
Ultralow Distortion IF Amplifier/ADC Driver
with Digitally Controlled Gain
450MHz to 1dB BW, 47dB OIP3, Digital Gain Control
10.5dB to 33dB in 1.5dB/Step
LT5515
1.5GHz to 2.5GHz Direct Conversion
High IIP3: 20dBm at 1.9GHz, Quadrature Demodulator Integrated
LO Quadrature Generator
LT5516
800MHz to 1.5GHz Direct Conversion
High IIP3: 21.5dBm at 900MHz, Quadrature Demodulator
Integrated LO Quadrature Generator
LT5517
40MHz to 900MHz Direct Conversion
High IIP3: 21dBm at 800MHz, Quadrature Demodulator
Integrated LO Quadrature Generator
LT5522
600MHz to 2.7GHz High Linearity Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz. NF = 12.5dB,
50W Single-Ended RF and LO Ports
222876fb
28 Linear Technology Corporation
LT 0608 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
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