LINER LTC2655BIGN-L16PBF Quad iâ²c 16-/12-bit rail-to-rail dacs with 10ppm/â°c max reference Datasheet

LTC2655
Quad I2C 16-/12-Bit
Rail-to-Rail DACs with
10ppm/°C Max Reference
DESCRIPTION
FEATURES
n
n
n
n
n
n
n
n
n
n
The LTC®2655 is a family of Quad I2C 16-/12-Bit Rail-toRail DACs with integrated 10ppm/°C max reference. The
DACs have built-in high performance, rail-to-rail, output
buffers and are guaranteed monotonic. The LTC2655-L
has a full-scale output of 2.5V with the integrated reference and operates from a single 2.7V to 5.5V supply.
The LTC2655-H has a full-scale output of 4.096V with
the integrated reference and operates from a 4.5V to
5.5V supply. Each DAC can also operate with an external
reference, which sets the full-scale output to 2 times the
external reference voltage.
Integrated Reference 10ppm/°C Max
Maximum INL Error: ±4LSB at 16 Bits
Guaranteed Monotonic Over Temperature
Selectable Internal or External Reference
2.7V to 5.5V Supply Range (LTC2655-L)
Integrated Reference Buffers
Ultralow Crosstalk Between DACs (<1nV•s)
Power-On-Reset to Zero-Scale/Mid-Scale
Asynchronous DAC Update Pin
Tiny 20-Lead 4mm × 4mm QFN and
16-Lead Narrow SSOP packages
The parts use the 2-wire I2C compatible serial interface.
The LTC2655 operates in both the standard mode (maximum clock rate of 100kHz) and the fast mode (maximum
clock rate of 400kHz). The LTC2655 incorporates a
power-on reset circuit that is controlled by the PORSEL
pin. If PORSEL is tied to GND the DACs power-on reset to
zero-scale. If PORSEL is tied to VCC, the DACs power-on
reset to mid-scale.
APPLICATIONS
n
n
n
n
n
Mobile Communications
Process Control and Industrial Automation
Instrumentation
Automatic Test Equipment
Automotive
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5396245, 6891433 and 7671770.
BLOCK DIAGRAM
REFCOMP
REFIN/OUT
INTERNAL REFERENCE
INL Curve
GND
4
VCC
CA1
32-BIT SHIFT REGISTER
CA2
SCL
DAC D
2
VOUTD
INL (LSB)
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
CA0
DAC B
REGISTER
VOUTB
DAC A
REGISTER
VOUTA
VCC = 5V
3
REFLO
1
0
–1
DAC C
VOUTC
–2
–3
POWER-ON
RESET
PORSEL
SDA
–4
128
16384
32768
CODE
49152
65535
2655 TA01b
2-WIRE INTERFACE
LDAC
2655 BD
2655f
1
LTC2655
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) ................................... –0.3V to 6V
SCL, SDA, LDAC, REFLO .............................. –0.3V to 6V
VOUTA to VOUTD ................–0.3V to Min (VCC + 0.3V, 6V)
REFIN/OUT, REFCOMP .....–0.3V to Min (VCC + 0.3V, 6V)
PORSEL, CA0, CA1, CA2 ..–0.3V to Min (VCC + 0.3V, 6V)
Operating Temperature Range
LTC2655C ................................................ 0°C to 70°C
LTC2655I .............................................–40°C to 85°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range ......................–65 to 150°C
Lead Temperature, GN Only (Soldering, 10 sec).... 300°C
PIN CONFIGURATION
15 VCC
3
14 VOUTD
VOUTB
4
13 VOUTC
REFIN/OUT
5
12 PORSEL
LDAC
6
11 CA0
CA2
7
10 CA1
SCL
8
9
SDA
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 110°C/W
DNC
DNC
15 DNC
VOUTA 1
14 VOUTD
REFCOMP 2
21
GND
VOUTB 3
REFIN/OUT 4
13 VOUTC
12 PORSEL
LDAC 5
11 CA0
6
7
8
9 10
CA1
2
SDA
VOUTA
REFCOMP
20 19 18 17 16
SCL
16 GND
DNC
1
CA2
REFLO
VCC
TOP VIEW
GND
REFLO
TOP VIEW
UF PACKAGE
20-LEAD (4mm s 4mm) PLASTIC QFN
TJMAX = 150°C, θJA = 37°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
2655f
2
LTC2655
ORDER INFORMATION
LTC2655 B
C
UF
–L
16
#TR
PBF
LEAD FREE DESIGNATOR
TAPE AND REEL
TR = Tape and Reel
RESOLUTION
16 = 16-Bit
12 = 12-Bit
FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE
L = 2.5V
H = 4.096V
PACKAGE TYPE
UF = 20-Lead (4mm × 4mm) Plastic QFN
GN = 16-Lead Narrow SSOP
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
ELECTRICAL GRADE (OPTIONAL)
B = ±4LSB Maximum INL (16-Bit)
PRODUCT PART NUMBER
Consult LTC Marketing for information on non-standard lead based finish parts. Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2655f
3
LTC2655
PRODUCT SELECTION GUIDE
TEMPERATURE
RANGE
MAXIMUM
INL
16-Lead Narrow SSOP
0°C to 70°C
±4
16-Lead Narrow SSOP
–40°C to 85°C
±4
20-Lead (4mm × 4mm) Plastic QFN
0°C to 70°C
±4
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
±4
16-Lead Narrow SSOP
0°C to 70°C
±4
655H16
16-Lead Narrow SSOP
–40°C to 85°C
±4
LTC2655BCUF-H16#TRPBF
55H16
20-Lead (4mm × 4mm) Plastic QFN
0°C to 70°C
±4
LTC2655BIUF-H16#TRPBF
55H16
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
±4
LTC2655CGN-L12#TRPBF
655L12
16-Lead Narrow SSOP
0°C to 70°C
±1
LEAD FREE FINISH
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
LTC2655BCGN-L16#PBF
LTC2655BCGN-L16#TRPBF
655L16
LTC2655BIGN-L16#PBF
LTC2655BIGN-L16#TRPBF
655L16
LTC2655BCUF-L16#PBF
LTC2655BCUF-L16#TRPBF
55L16
LTC2655BIUF-L16#PBF
LTC2655BIUF-L16#TRPBF
55L16
LTC2655BCGN-H16#PBF
LTC2655BCGN-H16#TRPBF 655H16
LTC2655BIGN-H16#PBF
LTC2655BIGN-H16#TRPBF
LTC2655BCUF-H16#PBF
LTC2655BIUF-H16#PBF
LTC2655CGN-L12#PBF
LTC2655IGN-L12#PBF
LTC2655IGN-L12#TRPBF
655L12
16-Lead Narrow SSOP
–40°C to 85°C
±1
LTC2655CUF-L12#PBF
LTC2655CUF-L12#TRPBF
55L12
20-Lead (4mm × 4mm) Plastic QFN
0°C to 70°C
±1
LTC2655IUF-L12#PBF
LTC2655IUF-L12#TRPBF
55L12
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
±1
LTC2655CGN-H12#PBF
LTC2655CGN-H12#TRPBF
655H12
16-Lead Narrow SSOP
0°C to 70°C
±1
LTC2655IGN-H12#PBF
LTC2655IGN-H12#TRPBF
655H12
16-Lead Narrow SSOP
–40°C to 85°C
±1
LTC2655CUF-H12#PBF
LTC2655CUF-H12#TRPBF
55H12
20-Lead (4mm × 4mm) Plastic QFN
0°C to 70°C
±1
LTC2655IUF-H12#PBF
LTC2655IUF-H12#TRPBF
55H12
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
±1
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2655f
4
LTC2655
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2655B-L16/ LTC2655-L12 (Internal Reference=1.25V)
LTC2655-12
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
LTC2655B-16
MAX
MIN
TYP
MAX
UNITS
DC Performance
Resolution
l
12
12
16
Bits
Monotonicity
(Note 3)
l
DNL
Differential Nonlinearity
(Note 3)
l
±0.1
±0.5
±0.3
±1
LSB
INL
Integral Nonlinearity (Note 3)
VCC = 5.5V, VREF = 2.5V
l
±0.5
±1
±2
±4
LSB
Load Regulation
VCC = 5V ±10%, Internal Reference,
Mid-Scale, –15mA ≤ IOUT ≤ 15mA
l
0.04
0.125
0.6
2
LSB/mA
VCC = 3V ±10%, Internal Reference,
Mid-Scale, –7.5mA ≤ IOUT ≤ 5mA
l
0.06
0.25
1
4
LSB/mA
Zero-Scale Error
l
1
3
1
3
mV
Offset Error
l
±1
±2
±1
±2
ZSE
VOS
VREF = 1.25V (Note 4)
VOS Temperature Coefficient
GE
Bits
5
l
Gain Error
Gain Temperature Coefficient
±0.02
5
±0.1
±0.02
1
SYMBOL
PARAMETER
CONDITIONS
VOUT
DAC Output Span
Internal Reference
External Reference = VEXTREF
PSR
Power Supply Rejection
VCC ±10%
ROUT
DC Output Impedance
VCC = 5V ±10%, Internal Reference, Mid-Scale,
–15mA ≤ IOUT ≤ 15mA
VCC = 3V ±10%, Internal Reference, Mid-Scale,
–7.5mA ≤ IOUT ≤ 7.5mA
ISC
16
±0.1
1
MIN
TYP
mV
μV/°C
%FSR
ppm/°C
MAX
0 to 2.5
0 to 2•VEXTREF
UNITS
V
V
–80
dB
l
0.04
0.15
Ω
l
0.04
0.15
Ω
DC Crosstalk (Note 5)
Due to Full-Scale Output Change
Due to Load Current Change
Due to Powering Down (per Channel)
±1.5
±2
±1
μV
μV/mA
μV
Short-Circuit Output Current (Note 6)
VCC = 5.5V VEXTREF = 2.8V
Code: Zero-Scale; Forcing Output to VCC
Code: Full-Scale; Forcing Output to GND
l
l
20
20
65
65
mA
mA
VCC = 2.7V VEXTREF = 1.4V
Code: Zero-Scale; Forcing Output to VCC
Code: Full-Scale; Forcing Output to GND
l
l
10
10
45
45
mA
mA
2655f
5
LTC2655
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2655B-L16/LTC2655-L12 (Internal Reference = 1.25V)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.248
1.25
1.252
V
±2
±10
Reference
Reference Output Voltage
Reference Temperature Coefficient
(Note 7)
Reference Line Regulation
VCC ±10%
Reference Short-Circuit Current
VCC = 5.5V, Forcing REFIN/OUT to GND
l
3
5
REFCOMP Pin Short-Circuit Current
VCC = 5.5V, Forcing REFCOMP to GND
l
65
200
Reference Load Regulation
VCC = 3V±10% or 5V±10%, IOUT = 100μA Sourcing
40
mV/mA
Reference Output Voltage Noise Density
CREFCOMP = CREFIN/OUT = 0.1μF, at f = 1kHz
30
nV/√Hz
Reference Input Range
External Reference Mode (Note 14)
l
0.5
l
Reference Input Current
Reference Input Capacitance
–80
0.001
(Note 9)
ppm/°C
dB
mA
μA
VCC /2
V
1
μA
20
pF
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
l
ICC
Supply Current (Note 8)
VCC = 5V, Internal Reference On
VCC = 5V, Internal Reference Off
VCC = 3V, Internal Reference On
VCC = 3V, Internal Reference Off
l
l
l
l
ISD
Supply Current in Shutdown Mode (Note 8) VCC = 5V
VIL
Low Level Input Voltage (SDA and SCL)
VIH
High Level Input Voltage (SDA and SCL)
VIL(LDAC)
Low Level Input Voltage (LDAC)
2.7
5.5
V
2.5
2
2.2
1.7
mA
mA
mA
mA
l
3
μA
l
0.3VCC
V
1.7
1.3
1.6
1.2
Digital I/O
VIH(LDAC)
High Level Input Voltage (LDAC)
l
0.7VCC
V
VCC = 4.5V to 5.5V
l
0.8
V
VCC = 2.7V to 4.5V
l
0.6
V
VCC = 3.6V to 5.5V
l
2.4
V
VCC = 2.7V to 3.6V
l
2
V
VIL(CA)
Low Level Input Voltage (CA0 to CA2)
See Test Circuit 1
l
VIH(CA)
High Level Input Voltage (CA0 to CA2)
See Test Circuit 1
l
RINH
Resistance from CAn (n = 0,1,2)
to VCC to Set CAn = VCC
See Test Circuit 2
l
10
kΩ
RINL
Resistance from CAn (n = 0,1,2)
to GND to Set CAn = GND
See Test Circuit 2
l
10
kΩ
RINF
Resistance from CAn (n = 0,1,2)
to VCC or GND to Set Can = FLOAT
See Test Circuit 2
l
2
VOL
Low Level Output Voltage
Sink Current =3mA
l
0
0.4
V
tOF
Output Fall Time
VO = VIH(MIN) to VO = VIL(MAX),
CB = 10pF to 400pF (Note 13)
20+0.1CB
250
ns
tSP
Pulse Width of Spikes Suppressed by Input
Filter
0
50
ns
IIN
Input Leakage
0.1VCC ≤ VIN ≤ 0.9VCC
l
1
μA
CIN
I/O Pin Capacitance
(Note 9)
l
10
pF
CB
Capacitance Load for Each Bus Line
l
400
pF
CCAn
External Capacitive Load on Address Pins
CA0, CA1 and CA2
l
10
pF
l
0.15VCC
0.85VCC
V
V
MΩ
2655f
6
LTC2655
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2655B-H16/LTC2655-H12 (Internal Reference = 2.048V)
LTC2655-12
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
LTC2655B-16
MAX
MIN
TYP
MAX
UNITS
DC Performance
Resolution
DNL
INL
l
12
12
16
Monotonicity
(Note 3)
l
Differential Nonlinearity
(Note 3)
l
±0.1
Integral Nonlinearity (Note 3)
VCC = 5.5V, VREF = 2.5V
l
±0.5
Load Regulation
VCC = 5V ±10%, Internal Reference,
Mid-Scale, –15mA ≤ IOUT ≤ 15mA
l
0.04
ZSE
Zero-Scale Error
VOS
Offset Error
VREF = 2.048V (Note 4)
16
±0.3
±1
±1
±2
±4
LSB
0.125
0.6
2
LSB/mA
1
3
1
3
mV
±1
±2
±1
±2
mV
l
±0.02
±0.1
±0.02
5
Gain Error
LSB
l
Gain Temperature Coefficient
5
1
SYMBOL
PARAMETER
CONDITIONS
VOUT
DAC Output Span
Internal Reference
External Reference = VEXTREF
PSR
Power Supply Rejection
VCC ±10%
ROUT
DC Output Impedance
VCC = 5V ±10%, Internal Reference, Mid-Scale,
–15mA ≤ IOUT ≤ 15mA
DC Crosstalk
Due to Full Scale Output Change
Due to Load Current Change
Due to Powering Down (per Channel)
Short-Circuit Output Current (Note 4)
VCC = 5.5V VEXTREF = 2.8V
Code: Zero-Scale; Forcing Output to VCC
Code: Full-Scale; Forcing Output to GND
ISC
Bits
±0.5
l
VOS Temperature Coefficient
GE
Bits
μV/°C
±0.1
1
MIN
l
TYP
ppm/°C
MAX
V
V
–80
dB
0.04
20
20
UNITS
0 to 4.096
0 to 2•VEXTREF
0.15
±1.5
±2
±1
l
l
%FSR
Ω
μV
μV/mA
μV
65
65
mA
mA
2655f
7
LTC2655
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2655B-H16/LTC2655-H12 (Internal Reference = 2.048V)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
2.044
UNITS
Reference
Reference Output Voltage
2.048
2.052
Reference Temperature Coefficient
(Note 7)
±2
±10
Reference Line Regulation
VCC ±10%
–80
Reference Short-Circuit Current
VCC = 5.5V, Forcing REFIN/OUT to GND
l
3
5
mA
REFCOMP Pin Short-Circuit Current
VCC = 5.5V, Forcing REFCOMP to GND
l
65
200
μA
Reference Load Regulation
VCC = 5V±10%, IOUT = 100μA Sourcing
40
mV/mA
Reference Output Voltage Noise Density
CREFCOMP = CREFIN/OUT = 0.1μF, at f = 1kHz
35
nV/√Hz
Reference Input Range
External Reference Mode (Note 14)
0.5
l
0.001
(Note 9)
l
20
Reference Input Current
Reference Input Capacitance
l
V
ppm/°C
dB
VCC /2
V
1
μA
pF
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
l
ICC
Supply Current (Note 8)
VCC = 5V, Internal Reference On
VCC = 5V, Internal Reference Off
l
l
ISD
Supply Current in Shutdown Mode (Note 8)
VCC = 5V
l
4.5
1.9
1.5
5.5
V
2.5
2
mA
mA
3
μA
0.3VCC
V
Digital I/O
VIL
Low Level Input Voltage (SDA and SCL)
l
VIH
High Level Input Voltage (SDA and SCL)
l
VIL(LDAC)
Low Level Input Voltage (LDAC)
VCC = 4.5V to 5.5V
l
VIH(LDAC)
High Level Input Voltage (LDAC)
VCC = 4.5V to 5.5V
l
VIL(CA)
Low Level Input Voltage (CA0 to CA2)
See Test Circuit 1
l
0.7VCC
V
0.8
2.4
V
V
0.15VCC
V
VIH(CA)
High Level Input Voltage (CA0 to CA2)
See Test Circuit 1
l
RINH
Resistance from CAn (n = 0,1,2)
to VCC to Set CAn = VCC
See Test Circuit 2
l
10
kΩ
RINL
Resistance from CAn (n = 0,1,2)
to GND to Set CAn = GND
See Test Circuit 2
l
10
kΩ
RINF
Resistance from CAn (n = 0,1,2)
to VCC or GND to Set CAn = FLOAT
See Test Circuit 2
l
VOL
Low Level Output Voltage
Sink Current = 3mA
l
0
0.4
V
tOF
Output Fall Time
VO = VIH(MIN) to VO = VIL(MAX),
CB = 10pF to 400pF (Note 13)
l
20+0.1CB
250
ns
tSP
Pulse Width of Spikes Suppressed by Input
Filter
l
0
50
ns
IIN
Input Leakage
0.1VCC ≤ VIN ≤ 0.9VCC
l
1
μA
CIN
I/O Pin Capacitance
(Note 9)
l
10
pF
CB
Capacitance Load for Each Bus Line
l
400
pF
CCAn
External Capacitive Load on Address Pins
CA0, CA1 and CA2
l
10
pF
0.85VCC
V
2
MΩ
2655f
8
LTC2655
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V (LTC2655B-L16/LTC2655-L12), VCC = 4.5V to 5.5V
(LTC2655B-H16, LTC2655-H12), VOUT unloaded unless otherwise specified.
LTC2655B-L16/LTC2655-L12/LTC2655B-H16/LTC2655-H12
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC Performance
ts
Settling Time ( Note 10)
±0.024%(±1LSB at 12 Bits)
±0.0015%(±1LSB at 16 Bits)
3.9
9.1
μs
μs
Settling Time for 1LSB Step
±0.024%(±1LSB at 12 Bits)
±0.0015%(±1LSB at 16 Bits)
2.4
4.5
μs
μs
1.8
V/μs
Voltage Output Slew Rate
Capacitive Load Driving
Glitch Impulse (Note 11)
1000
At Mid-Scale Transition, -L Option
4
At Mid-Scale Transition, -H Option
DAC to DAC Crosstalk (Note 12)
CREFCOMP = CREFIN/OUT = 0.22μF
Multiplying Bandwidth
en
pF
nV•s
7
nV•s
0.5
nV•s
150
kHz
Output Voltage Noise Density
At f = 1kHz
At f = 10kHz
85
80
nV/√Hz
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz, Internal Reference (-L Options)
0.1Hz to 10Hz, Internal Reference (-H Options)
0.1Hz to 200KHz, Internal Reference (-L Options)
0.1Hz to 200KHz, Internal Reference (-H Options)
8
12
400
450
μVP-P
μVP-P
μVP-P
μVP-P
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V (LTC2655B-L16/LTC2655-L12), VCC = 4.5V to 5.5V (LTC2655B-H16,
LTC2655-H12), VOUT unloaded unless otherwise specified.
LTC2655B-L16/LTC2655-L12/LTC2655B-H16/LTC2655-H12 (see Figure 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSCL
SCL Clock Frequency
l
0
tHD(STA)
Hold Time (Repeated) Start Condition
l
400
kHz
0.6
μs
tLOW
Low Period of the SCL Clock Pin
l
1.3
μs
tHIGH
High Period of the SCL Clock Pin
l
0.6
μs
tSU(STA)
Set-Up Time for a Repeated Start Program
l
0.6
μs
tHD(DAT)
Data Hold Time
l
0
0.9
μs
tSU(DAT)
Data Set-Up Time
l
100
tr
Rise Time of Both SDA and SCL Signals
(Note 13)
l
20+0.1CB
300
ns
tf
Fall Time of Both SDA and SCL Signals
(Note 13)
l
20+0.1CB
300
ns
ns
tSU(STO)
Set-Up Time for Stop Condition
l
0.6
μs
tBUF
Bus Free Time Between a Stop and Start Condition
l
1.3
μs
t1
Falling edge of the 9th Clock of the 3rd Input Byte
to LDAC High or Low Transition
l
400
ns
t2
LDAC Low Pulse Width
l
20
ns
2655f
9
LTC2655
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to GND.
Note 3: Linearity and monotonicity are defined from code kL to code 2N–1,
where N is the resolution and kL is the lower end code for which no output
limiting occurs. For VREF = 2.5V and N = 16, kL = 128 and linearity is
defined from code 128 to code 65535. For VREF = 2.5V and N = 12, kL =8
and linearity is defined from code 8 to code 4095.
Note 4: Inferred from measurement at code 128 (LTC2655-16), or code 8
(LTC2655-12).
Note 5: DC Crosstalk is measured with VCC = 5V and using internal
reference, with the measured DAC at mid-scale.
Note 6: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
Note 7: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range. Maximum
temperature coefficient is guaranteed for C-grade only.
Note 8: Digital inputs at 0V or VCC.
Note 9: Guaranteed by design and not production tested.
Note 10: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 200pF to GND.
Note 11: VCC = 5V (-H Options) or VCC = 3V (-L Options), internal
reference mode. DAC is stepped ±1 LSB between half-scale and
half-scale – 1. Load is 2kΩ n parallel with 200pF to GND.
Note 12: DAC to DAC Crosstalk is the glitch that appears at the output
of one DAC due to a full scale change at the output of another DAC. It is
measured with VCC = 5V and using internal reference, with the measured
DAC at mid-scale.
Note 13: CB = Capacitance of one bus line in pF.
Note 14: Gain error specification may be degraded for reference input
voltages less than 1V. See Gain Error vs Reference Input Curve in the
Typical Performance Characteristics section.
2655f
10
LTC2655
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted.
LTC2655-L16
Integral Nonlinearity (INL)
4
Differential Nonlinearity (DNL)
1.0
VCC = 3V
VCC = 3V
3
0.5
1
DNL (LSB)
INL (LSB)
2
0
–1
–2
0
–0.5
–3
–4
128
16384
32768
CODE
–1.0
128
65535
49152
16384
32768
CODE
49152
2655 G01
4
2655 G02
REFIN/OUT Output Voltage
vs Temperature
DNL vs Temperature
INL vs Temperature
1.0
VCC = 3V
1.253
VCC = 3V
3
1.252
1.251
0
–1
DNL(POS)
VREF (V)
1
–2
VCC = 3V
0.5
INL(POS)
DNL (LSB)
INL (LSB)
2
65535
0
DNL(NEG)
1.250
1.249
INL(NEG)
–0.5
1.248
–3
–4
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
–1.0
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
2655 G04
2655 G03
Settling to ±1LSB Rising
SCL
3V/DIV
1.247
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
2655 G05
Settling to ±1LSB Falling
9TH CLOCK OF
3RD DATA BYTE
VOUT
200μV/DIV
1/4 SCALE TO
3/4 SCALE STEP
VCC = 3V, VFS = 2.50V
VOUT
250μV/DIV
7.3μs
3/4 SCALE TO
1/4 SCALE STEP
VCC = 3V, VFS = 2.50V
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
7.8μs
SCL
3V/DIV
9TH CLOCK OF
3RD DATA BYTE
2655 G06
2μs/DIV
2655 G07
2μs/DIV
2655f
11
LTC2655
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted.
LTC2655-H16
Integral Nonlinearity (INL)
4
Differential Nonlinearity (DNL)
1.0
VCC = 5V
VCC = 5V
3
0.5
1
DNL (LSB)
INL (LSB)
2
0
–1
–2
0
–0.5
–3
–4
128
16384
32768
CODE
–1.0
128
65535
49152
16384
32768
CODE
49152
2655 G08
INL vs Temperature
4
2655 G09
Reference Output Voltage
vs Temperature
DNL vs Temperature
1.0
VCC = 3V
2.054
VCC = 3V
3
0.5
2.050
0
–1
DNL(POS)
VREF (V)
1
–2
VCC = 5V
2.052
INL(POS)
DNL (LSB)
INL (LSB)
2
65535
0
DNL(NEG)
2.048
2.046
–0.5
INL(NEG)
2.044
–3
–4
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
–1.0
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
2655 G11
2655 G10
Settling to ±1LSB Rising
SCL
5V/DIV
2.042
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
2655 G12
Settling to ±1LSB Falling
9TH CLOCK OF
3RD DATA BYTE
1/4 SCALE TO
3/4 SCALE STEP
VCC = 5V, VFS = 4.096V
RL = 2k, CL = 200pF
VOUT
250μV/DIV
3/4 SCALE TO
1/4 SCALE STEP
VCC = 5V, VFS = 4.096V
RL = 2k, CL = 200pF
7.9μs
VOUT
250μV/DIV
5.5μs
SCL
5V/DIV
9TH CLOCK OF
3RD DATA BYTE
2655 G14
2655 G13
2μs/DIV
2μs/DIV
2655f
12
LTC2655
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted.
LTC2655-12
1.0
VCC = 5V
VREF = 2.048V
DNL (LSB)
INL (LSB)
VCC = 3V
VREF = 1.25V
SCL
3V/DIV
0.5
0.5
0
4.0μs
0
VOUT
1mV/DIV
–0.5
–0.5
–1.0
Settling to ±1LSB Falling
Differential Nonlinearity (INL)
Integral Nonlinearity (INL)
1.0
–1.0
8
1024
2048
CODE
3072
4095
3/4 TO 1/4 SCALE STEP
VCC = 3V, VFS = 2.5V
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
8
1024
2048
CODE
3072
2655 G17
4095
2μs/DIV
2655 G16
2655 G15
LTC2655
Load Regulation
Headroom at Rails
vs Output Current
Current Limiting
10
5.0
0.20
INTERNAL REF
8 CODE = MID-SCALE
INTERNAL REF
0.15 CODE = MID-SCALE
4.5 5V (LTC2655-H) SOURCING
6
4.0
0.10
0
–2
3.5
0.05
VOUT (V)
2
ΔVOUT (V)
$VOUT (mV)
4
0
–0.05
–4
2.5
2.0
1.5
–0.10
–6
VCC = 5V (LTC2655-H)
–8
VCC = 3V (LTC2655-L)
–10
–50 –40 –30 –20 –10 0 10 20 30 40 50
IOUT (mA)
2655 G18
VCC = 5V (LTC2655-H)
VCC = 3V (LTC2655-L)
–0.20
–50 –40 –30 –20 –10 0 10 20 30 40 50
IOUT (mA)
0.5 3V (LTC2655-L) SINKING
0
Zero-Scale Error vs Temperature
2
2655 G21
4 5 6
IOUT (mA)
7
8
9
10
LTC2655-16
32
2.0
1.5
1.0
16
0
–16
–32
0.5
–3
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3
48
GAIN ERROR (LSB)
ZERO-SCALE ERROR (mV)
–2
2
Gain Error vs Temperature
64
2.5
–1
1
2655 G20
3.0
0
0
2655 G19
Offset Error vs Temperature
1
5V (LTC2655-H) SINKING
1.0
–0.15
3
OFFSET ERROR (mV)
3V (LTC2655-L) SOURCING
3.0
–48
0
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
2655 G22
–64
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
2655 G23
2655f
13
LTC2655
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted.
LTC2655
Gain Error vs Reference Input
Offset Error vs Reference Input
LTC2655-16
48 VCC = 5.5V
GAIN ERROR OF 4 CHANNELS
1.0
32
0.5
0
–0.5
350
300
0
–16
–32
–1.5
–48
50
1
1.5
2
REFERENCE VOLTAGE (V)
4.5
5.5
5
ICC Shutdown vs Temperature
VCC = 5V
(LTC2655-H)
2.0
VCC = 3V
(LTC2655-L)
2.5
2.0
1.5
1.6
2
3
LOGIC VOLTAGE (V)
4
5
LTC2655-H
VCC = 5V, CODE = MS
INTERNAL REFERENCE
LTC2655-L
VCC = 3V, CODE = MS
INTERNAL REFERENCE
1.0
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
ICC SHUTDOWN (μA)
SUPPLY CURRENT (mA)
ICC (mA)
4
VCC (V)
4
2.2
3
LTC2655-H
VCC = 5V
2
1
LTC2655-L
VCC = 3V
0
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
2655 G29
2655 G28
2655 G27
Multiplying Bandwidth
Large-Signal Response
8
Mid-Scale Glitch Impulse
VCC = 5V, VREF = 2.048V
ZERO-SCALE TO FULL-SCALE
6
SCL
5V/DIV
4
AMPLITUDE (dB)
3.5
5
3.0
SWEEP SCL AND SDA
BETWEEN
2.4 0V AND VCC
3
2655 G26
Supply Current vs Temperature
Supply Current vs Logic Voltage
1
0
2.5
2.5
2655 G25
2.6
0
200
100
2655 G24
1.8
250
150
–64
0.5
2.5
1
1.5
2
REFERENCE VOLTAGE (V)
400
16
–1.0
–2
0.5
450
ICC (nA)
GAIN ERROR (LSB)
OFFSET ERROR (mV)
VCC = 5V
1.5 OFFSET ERROR OF 4 CHANNELS
1.4
ICC Shutdown vs VCC
64
2.0
9TH CLOCK OF
3RD DATA BYTE
2
0
VOUT
5mV/DIV
VOUT
1V/DIV
–2
LTC2655-H16, VCC = 5V
7nV-s TYP
–4
–6
–10
–12
LTC2655-L16, VCC = 3V
4nV-s TYP
VS = 5V
VREF(DC) = 2V
VREF(AC) = 0.2VP-P
CODE = FULL-SCALE
–8
1k
10k
100k
FREQUENCY (Hz)
1M
2655 G32
2655 G31
2μs/DIV
2μs/DIV
2655 G30
2655f
14
LTC2655
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted.
LTC2655
DAC to DAC Crosstalk (Dynamic)
ONE DAC
SWITCH 0-FS
1V/DIV
Power-On Reset Glitch
VCC
2V/DIV
ZERO-SCALE
VOUT
10mV/DIV
VOUT
0.5mV/DIV
LTC2655-L16, VCC = 5V, 0.4nV•s TYP
CREFCOMP = CREFOUT = 0.22μF
2655 G34
2655 G33
200μs/DIV
2μs/DIV
Power-On Reset to Mid-Scale
Noise Voltage vs Frequency
400
NOISE VOLTAGE (nV/√Hz)
LTC2655-L
VCC
2V/DIV
VOUT
1V/DIV
2655 G35
300
VCC = 5V
CODE = MID-SCALE
INTERNAL REF
CREFCOMP = CREFOUT = 0.1μF
200
LTC2655-H
100
0
1ms/DIV
LTC2655-L
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
2655 G36
DAC Output 0.1Hz to
10Hz Voltage Noise
Reference 0.1Hz to
10Hz Voltage Noise
VREFOUT = 2.048V
CREFCOMP = CREFOUT = 0.1μF
VCC = 5V, LTC2655-H
CODE = MID-SCALE
INTERNAL REF
CREFCOMP = CREFOUT = 0.1μF
2μV/DIV
5μV/DIV
2655 G38
2655 G37
1s/DIV
1s/DIV
2655f
15
LTC2655
PIN FUNCTIONS
(GN/UF)
REFLO (Pin 1/Pin 20): Reference Low. The voltage at this
pin sets the zero-scale voltage of all DACs. This pin should
be tied to GND.
VOUTA to VOUTD (Pins 2,4,13,14/Pins 1, 3, 13, 14): DAC
Analog Voltage Outputs. The output range is 0V to 2 times
the voltage at the REFIN/OUT pin.
REFCOMP (Pin 3/Pin 2): Internal Reference Compensation.
For low noise and reference stability, tie 0.1μF capacitor
to GND. Connect to GND to use an external reference at
start-up. Command 0111b must still be issued to turn off
internal reference.
REFIN/OUT (Pin 5/Pin 4): This pin acts as the internal
reference output in internal reference mode and acts as
the reference input pin in external reference mode. When
acting as an output the nominal voltage at this pin is
1.25V for -L options and 2.048V for -H options. For low
noise and reference stability tie a capacitor from this pin
to GND. Capacitor value must be ≤ CREFCOMP. In external
reference mode, the allowable reference input voltage
range is 0.5V to VCC /2.
LDAC (Pin 6/Pin 5): Asynchronous DAC Update. A falling edge on this input after four bytes have been written
into the part, immediately updates the DAC register with
the contents of the input register. A low on this input
without a complete 32-bit (four bytes including the slave
address) data write transfer to the part does not update
the DAC output. Software power-down is disabled when
LDAC is low.
SCL (Pin 8/Pin 7): Serial Clock Input. Data is shifted
into the SDA pin at the rising edges of the clock. This
high impedance pin requires a pull-up resistor or current
source to VCC.
SDA (Pin 9/Pin 9): Serial Data Bidirectional. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This is
a high impedance pin while data is shifted in. It is an opendrain N-channel output during acknowledgement. This pin
requires a pull-up resistor or current source to VCC.
CA1 (Pin 10/Pin 10): Chip Address Bit 1. Tie this pin to
VCC, GND or leave it floating to select an I2C slave address
for the part (Table 2).
CA0 (Pin 11/Pin 11): Chip Address Bit 0. Tie this pin to
VCC, GND or leave it floating to select an I2C slave address
for the part (Table 2).
PORSEL (Pin 12/Pin 12): Power-On-Reset Select. If tied
to GND, the part resets to zero-scale at power-up, if tied
to VCC, the part resets to mid-scale.
VCC (Pin 15/Pin 18): Supply Voltage Input. For -L options,
2.7V ≤ VCC ≤ 5.5V, and for -H options, 4.5V ≤ VCC ≤ 5.5V.
Bypass to ground with a 0.1μF capacitor placed as close
to pin as possible.
GND (Pin 16/Pin 19, Exposed Pad Pin 21): Ground. Must
be soldered to PCB Ground.
DNC (NA/Pins 8, 15, 16, 17): Do not connect these
pins.
CA2 (Pin 7/Pin 6): Chip Address Bit 2. Tie this pin to VCC,
GND or leave it floating to select an I2C slave address for
the part (Table 2).
2655f
16
LTC2655
BLOCK DIAGRAM
REFCOMP
REFIN/OUT
INTERNAL REFERENCE
GND
VCC
REGISTER
REGISTER
REGISTER
DAC B
REGISTER
REGISTER
CA0
DAC D
REGISTER
VOUTB
DAC A
REGISTER
VOUTA
REGISTER
REFLO
DAC C
CA1
32-BIT SHIFT REGISTER
CA2
SCL
POWER-ON
RESET
VOUTD
VOUTC
PORSEL
SDA
2-WIRE INTERFACE
LDAC
2655 BD
2655f
17
LTC2655
TEST CIRCUITS
Test Circuit 1
100Ω
CAn
VIH(CAn)/VIL(CAn)
2655 TC01
Test Circuit 2
VDD
RINH/RINL/RINF
2655 TC02
GND
TIMING DIAGRAM
SDA
tf
tLOW
tSU(DAT)
tr
tf
tHD(STA)
tSP
tr
tBUF
SCL
S
tHD(STA)
tHD(DAT)
tHIGH
tSU(STA)
S
tSU(STO)
P
S
2655 F01
ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS
9TH CLOCK
OF 3RD
DATA BYTE
SCL
t1
LDAC
Figure 1
2655f
18
LTC2655
OPERATION
The LTC2655 is a family of quad voltage output DACs in
20-lead 4mm × 4mm QFN and in 16-lead narrow SSOP
packages. Each DAC can operate rail-to-rail in external
reference mode, or with its full-scale voltage set by an
integrated reference. Four combinations of accuracy (16-bit
and 12-bit), and full-scale voltage (2.5V or 4.096V) are
available. The LTC2655 is controlled using a 2-wire I2C
compatible interface.
Power-On Reset
The LTC2655-L/LTC2655-H clear the output to zero-scale
if PORSEL pin is tied to GND, when power is first applied,
making system initialization consistent and repeatable. For
some applications, downstream circuits are active during
DAC power-up, and may be sensitive to nonzero outputs
from the DAC during this time. The LTC2655 contains
circuitry to reduce the power-on glitch. The analog outputs
typically rise less than 10mV above zero-scale during power
on if the power supply is ramped to 5V in 1ms or more.
In general, the glitch amplitude decreases as the power
supply ramp time is increased. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Alternatively, if PORSEL pin is tied to VCC, The LTC2655-L/
LTC2655-H set the output to mid-scale when power is
first applied.
Power Supply Sequencing and Start-Up
For the LTC2655 family of parts, the internal reference is
powered up at start-up by default. If an external reference
is to be used, REFCOMP (Pin 3/Pin 2, GN/UF) must be
hardwired to GND. This configuration allows the use of an
external reference at start-up and converts the REFIN/OUT
pin to an input. However, the internal reference will still be
ON and draw supply current. In order to use an external
reference, command 0111b should be used to turn the
internal reference off (see Table 1).
The voltage at REFIN/OUT (Pin 5/Pin 4, GN/UF) should be
kept within the range – 0.3V ≤ REFIN/OUT ≤ VCC + 0.3V
(see the Absolute Maximum Ratings section). Particular
care should be taken to observe these limits during power
supply turn-on and turn-off sequences, when the voltage
at VCC (Pin 15/Pin 18, GN/UF) is in transition.
Transfer Function
The digital-to-analog transfer function is
VOUT(IDEAL) = 2 • k/2N [VREF – REFLO] + REFLO
where k is the decimal equivalent of the binary DAC input
code, N is the resolution, and VREF is the voltage at the
REFIN/OUT Pin. The resulting DAC output span is 0V to
2•VREF, as it is necessary to tie REFLO to GND. VREF is
nominally 1.25V for LTC2655-L and 2.048V for LTC2655-H,
in internal reference mode.
Table 1
COMMAND*
C3 C2 C1 C0
0
0
0
0 Write to Input Register n
0
0
0
1 Update (Power-Up) DAC Register n
0
0
1
0 Write to Input Register n, Update (Power-Up) All
0
0
1
1 Write to and Update (Power-Up) n
0
1
0
0 Power-Down n
0
1
0
1 Power-Down Chip (All DAC’s and Reference)
0
1
1
0 Select Internal Reference (Power-Up Reference)
0
1
1
1 Select External Reference (Power-Down Reference)
1
1
1
1 No Operation
ADDRESS (n)*
A3 A2 A1 A0
0
0
0
0 DAC A
0
0
0
1 DAC B
0
0
1
0 DAC C
0
0
1
1 DAC D
1
1
1
1 All DACs
* Command and address codes not shown are reserved and should not
be used.
Serial Interface
The LTC2655 communicates with a host using the standard 2-wire I2C interface. The Timing Diagram (Figure 1)
shows the timing relationship of the signals on the bus.
The two bus lines, SDA and SCL, must be high when the
bus is not in use. External pull-up resistors or current
sources are required on these lines. The value of these
pull-up resistors is dependent on the power supply and
can be obtained from the I2C specifications. For an I2C
bus operating in the fast mode, an active pull-up will be
2655f
19
LTC2655
OPERATION
necessary if the bus capacitance is greater than 200pF.
The LTC2655 is a receive-only (slave) device. The master
can write to the LTC2655. The LTC2655 does not respond
to a read command from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be high.
A bus master signals the beginning of a communication
to a slave device by transmitting a START condition (see
Figure 1). A START condition is generated by transitioning
SDA from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a STOP
condition. A STOP condition is generated by transitioning
SDA from low to high while SCL is high. The bus is then
free for communication with another I2C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
bus line during the Acknowledge clock pulse so that it
remains a stable LOW during the HIGH period of this clock
pulse. The LTC2655 responds to a write by a master in
this manner. The LTC2655 does not acknowledge a read
(retains SDA HIGH during the period of the Acknowledge
clock pulse).
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set
to any one of three states: VCC , GND or float. This results
in 27 selectable addresses for the part. The slave address
assignments are shown in Table 2.
In addition to the address selected by the address pins,
the parts also respond to a global address. This address
allows a common write to all LTC2655 parts to be accomplished with one 3-byte write transaction on the I2C bus.
The global address is a 7-bit on-chip hardwired address
and is not selectable by CA0, CA1 and CA2. The addresses
corresponding to the states of CA0, CA1 and CA2 and
the global address are shown in Table 2. The maximum
capacitive load allowed on the address pins (CA0, CA1
and CA2) is 10pF, as these pins are driven during address
detection to determine if they are floating.
Table 2. Slave Address Map
CA2
CA1
CA0
A6
A5
A4
A3
A2
A1
A0
GND
GND
GND
0
0
1
0
0
0
0
GND
GND
FLOAT
0
0
1
0
0
0
1
GND
GND
VCC
0
0
1
0
0
1
0
GND
FLOAT
GND
0
0
1
0
0
1
1
GND
FLOAT
FLOAT
0
1
0
0
0
0
0
GND
FLOAT
VCC
0
1
0
0
0
0
1
GND
VCC
GND
0
1
0
0
0
1
0
GND
VCC
FLOAT
0
1
0
0
0
1
1
GND
VCC
VCC
0
1
1
0
0
0
0
FLOAT
GND
GND
0
1
1
0
0
0
1
FLOAT
GND
FLOAT
0
1
1
0
0
1
0
FLOAT
GND
VCC
0
1
1
0
0
1
1
FLOAT
FLOAT
GND
1
0
0
0
0
0
0
FLOAT
FLOAT
FLOAT
1
0
0
0
0
0
1
FLOAT
FLOAT
VCC
1
0
0
0
0
1
0
FLOAT
VCC
GND
1
0
0
0
0
1
1
FLOAT
VCC
FLOAT
1
0
1
0
0
0
0
FLOAT
VCC
VCC
1
0
1
0
0
0
1
VCC
GND
GND
1
0
1
0
0
1
0
VCC
GND
FLOAT
1
0
1
0
0
1
1
VCC
GND
VCC
1
1
0
0
0
0
0
VCC
FLOAT
GND
1
1
0
0
0
0
1
VCC
FLOAT
FLOAT
1
1
0
0
0
1
0
VCC
FLOAT
VCC
1
1
0
0
0
1
1
VCC
VCC
GND
1
1
1
0
0
0
0
VCC
VCC
FLOAT
1
1
1
0
0
0
1
VCC
VCC
VCC
GLOBAL ADDRESS
1
1
1
0
0
1
0
1
1
1
0
0
1
1
2655f
20
LTC2655
OPERATION
Write Word Protocol
Power-Down Mode
The master initiates communication with the LTC2655
with a START condition and a 7-bit slave address followed
by the Write bit (W) = 0. The LTC2655 acknowledges by
pulling the SDA pin low at the 9th clock if the 7-bit slave
address matches the address of the part (set by CA0, CA1
and CA2) or the global address. The master then transmits
three bytes of write data. The LTC2655 acknowledges each
byte of data by pulling the SDA line low at the 9th clock of
each data byte transmission. After receiving three complete bytes of data, the LTC2655 executes the command
specified in the 24-bit input word. If more than three data
bytes are transmitted after a valid 7-bit slave address, the
LTC2655 does not acknowledge the extra bytes of data
(SDA is high during the 9th clock). The first byte of the
input word consists of the 4-bit command followed by
the 4-bit address. The next two bytes consist of the 16-bit
data word. The 16-bit data word consists of the 16-bit, or
12-bit input code, MSB to LSB, followed by 0 or 4 don’t
care bits (LTC2655-16 and LTC2655-12 respectively). A
typical LTC2655 write transaction is shown in Figure 2.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register into
the input register. In an update operation, the data word
is copied from the input register to the DAC register and
converted to an analog voltage at the DAC output. The
update operation also powers up the DAC if it had been in
power-down mode. The data path and registers are shown
in the Block Diagram.
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than four outputs are needed. When in power-down, the
buffer amplifiers, bias circuits and integrated reference
circuits are disabled, and draw essentially zero current.
The DAC outputs are put into a high-impedance state, and
the output pins are passively pulled to ground through
individual 80k resistors. Input- and DAC-register contents
are not disturbed during power-down.
Any channel or combination of channels can be put into
power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The integrated
reference is automatically powered down when external
reference mode is selected using command 0111b. In addition, all the DAC channels and the integrated reference
together can be put into power-down mode using the
Power-Down Chip command 0101b. For all power-down
commands the 16-bit data word is ignored, but still required
in order to complete a full communication cycle.
Normal operation resumes by executing any command
which includes a DAC update, in software as shown in
Table 1 or using the asynchronous LDAC pin. The selected
DAC is powered up as its voltage output is updated. When
a DAC which is in a powered-down state is powered up and
updated, normal settling is delayed. If less than four DACs
are in a powered-down state prior to the update command,
the power-up delay time is approximately 12μs. If on the
other hand, all four DACs and the integrated reference
are powered down, then the main bias generation circuit
block has been automatically shut down in addition to the
individual DAC amplifiers and the integrated reference.
2655f
21
LTC2655
OPERATION
In this case, the power-up delay time is approximately
14μs. The power-up of the integrated reference depends
on the command that powered it down. If the reference is
powered down using the Select External Reference command (0111b), then it can only be powered back up by
sending the Select Internal Reference command (0110b).
However if the reference was powered down by sending
the Power-Down Chip command (0101b), then in addition
to the Select Internal Reference command (0110b), any
command that powers up the DACs will also power-up
the integrated reference.
Reference Modes
For applications where an accurate external reference is
not available, the LTC2655 has a user-selectable, integrated reference. The LTC2655-L has a 1.25V reference
that provides a full-scale output of 2.5V. The LTC2655-H
has a 2.048V reference that provides a full-scale output
of 4.096V. Both references exhibit a typical temperature
drift of 2ppm/°C. Internal reference mode can be selected
by using command 0110b, and is the power-on default. A
buffer is needed if the internal reference is required to drive
external circuitry. For reference stability and low noise, it
is recommended that a 0.1μF capacitor be tied between
REFCOMP and GND. In this configuration, the internal
reference can drive up to 0.1μF capacitive load without any
stability problems. In order to ensure stable operation, the
capacitive load on the REFIN/OUT pin should not exceed
the capacitive load on the REFCOMP pin.
The DAC can also operate in external reference mode using
command 0111b. In this mode, the REFIN/OUT pin acts
as an input that sets the DAC’s reference voltage. This
input is high impedance and does not load the external
reference source. The acceptable voltage range at this
pin is 0.5V ≤ REFIN/OUT ≤ VCC /2. The resulting full-scale
output voltage is 2•VREFIN/OUT. For using external reference at start-up, see the Power Supply Sequencing and
Start-Up Sections.
Integrated Reference Buffers
Each of the four DACs in LTC2655 has its own integrated
high performance reference buffer. The buffers have very
high input impedance and do not load the reference voltage source. These buffers shield the reference voltage
from glitches caused by DAC switching and thus minimize
DAC-to-DAC dynamic crosstalk. By tying 0.22μF capacitors
between REFCOMP and GND, and also between REFIN/OUT
and GND, the crosstalk can be reduced to less than 1nV•s.
See the curve DAC-to-DAC Crosstalk (Dynamic) in the
Typical Performance Characteristics section.
Voltage Outputs
Each of the four rail-to-rail amplifiers contained in LTC2655
has guaranteed load regulation when sourcing or sinking
up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifiers’ DC output
impedance is 0.040Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30Ω • 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The amplifiers are stable driving capacitive loads of up
to 1000pF.
2655f
22
LTC2655
OPERATION
Board Layout
Rail-to-Rail Output Considerations
The excellent load regulation and DC crosstalk performance
of these devices is achieved in part by keeping signal and
power grounds separate.
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown in
Figure 3b. Similarly, limiting can occur in external reference mode near full scale when the REFIN/OUT pin is at
VCC/2. If VREFIN/OUT = VCC /2 and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits
at VCC as shown in Figure 3c. No full-scale limiting can
occur if VREFIN/OUT ≤ (VCC – FSE)/2.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground. The REFLO pin should be connected to system
star ground. Resistance from the REFLO pin to system
star ground should be as low as possible.
2655f
23
24
2
1
SCL
VOUT
SA5
SA6
SA5
3
SA4
4
SA3
SA3
5
SA2
SA2
6
SA1
SA1
SLAVE ADDRESS
SA4
7
SA0
SA0
8
WR
1
C3
2
C2
C2
3
C1
C1
4
C0
C0
5
A3
A3
COMMAND
6
A2
A2
7
A1
A1
8
A0
A0
9
ACK
1
D15
2
D14
3
D13
4
5
D11
MS DATA
D12
6
D10
7
D9
8
D8
9
ACK
1
D7
2
D6
Figure 2. Typical LTC2655 Input Waveform—Programming DAC Output for Full-Scale
9
ACK
C3
3
D5
4
5
D3
LS DATA
D4
6
D2
7
D1
8
D0
9
ACK
2655 F02
ZERO-SCALE
VOLTAGE
FULL-SCALE
VOLTAGE
STOP
OPERATION
SDA
START
SA6
LTC2655
2655f
LTC2655
OPERATION
POSITIVE
FSE
VREF = VCC
VREF = VCC
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
(c)
OUTPUT
VOLTAGE
0
65, 535
(a)
0V
NEGATIVE
OFFSET
32, 768
INPUT CODE
INPUT CODE
(b)
2655 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function,
(b) Effect of Negative Offset for Codes Near Zero-Scale, (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
2655f
25
LTC2655
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2655f
26
LTC2655
PACKAGE DESCRIPTION
UF Package
20-Lead (4mm × 4mm) Plastic QFN
(Reference LTC DWG # 05-08-1710 Rev A)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.00 REF
2.45 ± 0.05
2.45 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
0.75 ± 0.05
R = 0.05
TYP
R = 0.115
TYP
19 20
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
4.00 ± 0.10
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 × 45°
CHAMFER
BOTTOM VIEW—EXPOSED PAD
1
2.00 REF
2.45 ± 0.10
2
2.45 ± 0.10
(UF20) QFN 01-07 REV A
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2655f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2655
TYPICAL APPLICATION
±5V Bipolar Output DAC
+5V
C2
0.1μF
3
C1 +5V
0.1μF
C3
0.1μF
+
5
1
+12V
LTC6240IS5
4
–
7
2
LT1991
8
5
TO
MICROCONTROLLER
7
9
11
10
6
18
2
4
LDAC VCC REFCOMP REFIN/OUT
SCL
SDA
CA0
LTC2655IUF-L16*
CA1
CA2
GND GND REFLO
PORSEL
19
21
20
12
17
16
DNC DNC
VOUTA
VOUTB
VOUTC
VOUTD
9
1
10
3
50k
450k
150k
4pF
M9
M3
450k
M1
13
1
14
2
DNC DNC
8
VCC
15
3
5V
–
+
6 VOUT
±5V
450k
450k
P1
4pF
150k
P3
50k
VEE
REF
P9
2655 TA02
4
*PIN NUMBERS SHOWN ARE FOR THE QFN PACKAGE.
5
–12V
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC2609/LTC2619/ Quad 16-/14-/12-Bit I2C VOUT DACs
LTC2629
250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with
Separate VREF Pins for Each DAC, SSOP-16 Package
LTC2605/LTC2615/ Octal 16-/14-/12-Bit I2C VOUT DACs
LTC2625
250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,
SSOP-16 Package
LTC2607/LTC2617/ Dual 16-/14-/12-Bit I2C VOUT DACs
LTC2627
260μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,
3mm × 4mm DFN-12 Package
LTC2606/LTC2616/ Single 16-/14-/12-Bit I2C VOUT DACs
LTC2626
270μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,
3mm × 3mm DFN-10 Package
LTC2654
Quad 16-/12-Bit SPI VOUT DACs with 10ppm/°C (Max)
Reference
±4LSB INL, ±1LSB DNL, 4mm × 4mm QFN-20, Narrow SSOP-16
Packages
LTC2656/LTC2657
Octal 16-/12-Bit SPI/I2C VOUT DACs with 10ppm/°C (Max)
Reference
±4LSB INL, ±1LSB DNL, 4mm × 5mm QFN-20, TSSOP-20 Packages
LTC2634/LTC2635
Quad 12-/10-/8-Bit SPI/I2C VOUT DACs with 10ppm/°C
(Typ) Reference
125μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,
3mm × 3mm QFN-16 and MSOP-10 Packages
LTC2636/LTC2637
Octal 12-/10-/8-Bit SPI/I2C VOUT DACs with 10ppm/°C
(Typ) Reference
125μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,
4mm × 3mm DFN-14 and MSOP-16 Packages
LTC2630/LTC2631
Single 12-/10-/8-Bit SPI/I2C VOUT DACs with Bidirectional
10ppm/°C (Typ) Reference
180μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,
6-Lead SC70 Package (LTC2630), 8-Lead TSOT-23 (LTC2631)
LTC2641/LTC2642
Single 16-/14-/12-Bit SPI VOUT DACs with ±1LSB INL, DNL ±1LSB (Max) INL, DNL, 120μA, 3mm × 3mm DFN and MSOP Packages
LTC1669
10-Bit I2C Interface VOUT Micropower DAC
60μA, ±0.75 LSB DNL, Rail-to-Rail, 5-Lead SOT-23 and
MSOP-8 Packages
LTC6240
Single 18MHz, CMOS Op Amp
Low Noise, Rail-to-Rail
LT1991
Precision Gain Selectable Difference Amplifier
100μA Micropower, Pin Selectable Gain = –13 to 14
2655f
28 Linear Technology Corporation
LT 0710 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010
Similar pages