LTC2664 Quad 16-Bit/12-Bit ±10V VOUT SoftSpan DACs with 10ppm/°C Max Reference Description Features Precision Reference 10ppm/°C Max nn Independently Programmable Output Ranges: 0V to 5V, 0V to 10V, ±2.5V, ±5V, ±10V nn Full 16-Bit/12-Bit Resolution at All Ranges nn Maximum INL Error: ±4LSB at 16 Bits nn A/B Toggle via Software or Dedicated Pin nn Analog Multiplexer with Auxiliary Inputs nn Guaranteed Monotonic Over Temperature nn Internal or External Reference nn Outputs Drive ±10mA Guaranteed nn 1.8V to 5V SPI Serial interface nn 32-Lead (5mm × 5mm) QFN Package The LTC®2664 is a family of four-channel, 16-/12-bit ±10V digital-to-analog converters with integrated precision references. They are guaranteed monotonic and have built-in rail-to-rail output buffers. These SoftSpan™ DACs offer five output ranges up to ±10V. The range of each channel is independently programmable, or the part can be hardware-configured for operation in a fixed range. nn The integrated 2.5V reference is buffered separately to each channel; an external reference can be used for additional range options. The LTC2664 also includes A/B toggle capability via a dedicated pin or software toggle command. The SPI/Microwire-compatible 3-wire serial interface operates on logic levels as low as 1.71V at clock rates up to 50MHz. Applications Optical Networking Instrumentation nn Data Acquisition nn Automatic Test Equipment nn Process Control and Industrial Automation nn L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6891433, 5859606, 5936245, 7671770. nn Block Diagram RGSTR A REGISTER 28 VCC 4 24 CLR 3 7 V+ 8 V– 23 MUXIN3 22 VOUT3 SPAN DAC 3 SPAN SPAN SPAN DAC 0 VREF MUX RGSTR B MUX RGSTR B REGISTER VREF MUXIN0 2 VOUT0 3 RGSTR A OVRTMP 30 GND 11, 29 REFLO 10, 27 Integral Nonlinearity (LTC2664-16) 25 REF INTERNAL REFERENCE ±10V RANGE 2 INL (LSB) REFCOMP 26 1 0 –1 –2 VREF –4 SPAN DAC 2 SPAN RGSTR B MUX CS/LD 13 SCK 14 SDI 16 SDO 15 MUXOUT 9 CONTROL LOGIC 21 VOUT2 20 MUXIN2 16384 32768 CODE 49152 65535 2664 TA01b 12 LDAC 31 MSP0 POWER-ON RESET 32 MSP1 1 MONITOR MUX 0 17 TGP DECODE 32-BIT SHIFT REGISTER –3 REGISTER RGSTR A RGSTR A SPAN MUXIN1 5 DAC 1 SPAN VOUT1 4 MUX RGSTR B REGISTER VREF TOGGLE SELECT REGISTER MSP2 18 IOVCC 2664 BD For more information www.linear.com/LTC2664 2664fa 1 LTC2664 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) 2 REF REFCOMP REFLO VCC GND OVRTMP MSP0 MSP1 TOP VIEW 32 31 30 29 28 27 26 25 24 CLR MSP2 1 MUXIN0 2 23 MUXIN3 VOUT0 3 22 VOUT3 VOUT1 4 21 VOUT2 33 MUXIN1 5 20 MUXIN2 DNC 6 19 DNC V+ 7 18 IOVCC V– 8 17 TGP SDI SDO SCK CS/LD LDAC GND REFLO 9 10 11 12 13 14 15 16 MUXOUT Analog Supply Voltage (VCC)........................ –0.3V to 6V Digital I/O Voltage (IOVCC)............................ –0.3V to 6V REFLO........................................................ –0.3V to 0.3V V +............................................................ –0.3V to 16.5V V –.............................................................–16.5V to 0.3V CS/LD, SCK, SDI, LDAC, CLR, TGP............... –0.3V to 6V MSP0, MSP1, MSP2.........–0.3V to Min (VCC + 0.3V, 6V) VOUT0 to VOUT3, MUXIN0 to MUXIN3, MUXOUT................ V – – 0.3V to V + + 0.3V (Max ±16.5V) REF, REFCOMP.................–0.3V to Min (VCC + 0.3V, 6V) SDO.............................. –0.3V to Min (IOVCC + 0.3V, 6V) OVRTMP........................................................ –0.3V to 6V Operating Temperature Range LTC2664C................................................. 0°C to 70°C LTC2664I..............................................–40°C to 85°C LTC2664H........................................... –40°C to 125°C Maximum Junction Temperature........................... 150°C Storage Temperature Range................... –65°C to 150°C UH PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN TJMAX = 150°C, θJA = 44°C/W EXPOSED PAD IS V–, MUST BE SOLDERED TO PCB 2664fa For more information www.linear.com/LTC2664 LTC2664 Order Information LTC2664 C UH 16 http://www.linear.com/product/LTC2664#orderinfo #TR PBF LEAD FREE DESIGNATOR PBF = Lead Free TAPE AND REEL TR = 2500-Piece Tape and Reel RESOLUTION 16 = 16-Bit 12 = 12-Bit PACKAGE TYPE UH = 32-Lead QFN TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) H = Automotive Temperature Range (–40°C to 125°C) PRODUCT PART NUMBER For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Product Selection Guide LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2664CUH-16#PBF LTC2664CUH-16#TRPBF 266416 32-Lead (5mm × 5mm) QFN 0°C to 70°C LTC2664IUH-16#PBF LTC2664IUH-16#TRPBF 266416 32-Lead (5mm × 5mm) QFN –40°C to 85°C LTC2664HUH-16#PBF LTC2664HUH-16#TRPBF 266416 32-Lead (5mm × 5mm) QFN –40°C to 125°C LTC2664CUH-12#PBF LTC2664CUH-12#TRPBF 266412 32-Lead (5mm × 5mm) QFN 0°C to 70°C LTC2664IUH-12#PBF LTC2664IUH-12#TRPBF 266412 32-Lead (5mm × 5mm) QFN –40°C to 85°C LTC2664HUH-12#PBF LTC2664HUH-12#TRPBF 266412 32-Lead (5mm × 5mm) QFN –40°C to 125°C *Temperature grades are identified by a label on the shipping container. 2664fa For more information www.linear.com/LTC2664 3 LTC2664 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, IOVCC = 5V, V+ = 15V, V – = –15V, VREF = 2.5V, VOUT unloaded unless otherwise specified. LTC2664-16/LTC2664-12 LTC2664-12 SYMBOL PARAMETER CONDITIONS MIN TYP LTC2664-16 MAX MIN TYP MAX UNITS DC Performance l 12 16 Bits All Ranges (Note 3) l 12 16 Bits Resolution Monotonicity DNL Differential Nonlinearity All Ranges (Note 3) l ±0.05 ±0.5 ±0.35 ±1 LSB INL Integral Nonlinearity All Ranges (Note 3) V+/V – = ±15V l ±0.2 ±1 ±2.2 ±4 LSB l l ±0.2 ±0.2 ±1 ±1 ±2.2 ±2.2 ±4 ±5 LSB LSB l l ±1 ±2 ±2 ±4 ±1 ±2 ±2 ±4 mV mV 6 2 V – = GND (Note 3) C-Grade, I-Grade H-Grade VOS Unipolar Offset Error 0V to 5V Range 0V to 10V Range VOS Temperature Coefficient All Unipolar Ranges ZSE Single-Supply Zero-Scale Error All Unipolar Ranges, V – = GND l BZE Bipolar Zero Error All Bipolar Ranges l BZE Temperature Coefficient All Bipolar Ranges Gain Error All Ranges, External Reference GE 1 ±0.02 ±0.08 Power Supply Rejection All Ranges SYMBOL PARAMETER VOUT ROUT ISC Output Voltage Swing CONDITIONS To V– (Unloaded, V– = GND) To V+ (Unloaded, V+ = 5V) To V– (–10mA ≤ IOUT ≤ 10mA) To V+ (–10mA ≤ IOUT ≤ 10mA) 1 ±0.02 ±0.08 VCC = 5V, ±10% V+/V– = ±15V, ±5% mV %FSR ppm/°C ±0.02 ±0.08 %FSR 2 2 ppm/°C 0.1 0.001 1 0.01 LSB/V LSB/V MIN TYP V – + 0.004 V + – 0.004 l l ppm/°C 6 ±0.02 ±0.08 1 l Gain Temperature Coefficient PSR 1 2 V + – 1.4 MAX V – + 1.4 UNITS V V V V Load Regulation –10mA ≤ IOUT ≤ 10mA (Note 4) l 78 150 µV/mA DC Output Impedance –10mA ≤ IOUT ≤ 10mA (Note 4) l 0.078 0.15 Ω DC Crosstalk (Note 5) 0V to 5V Range Due to Full-Scale Output Change Due to Load Current Change Due to Powering Down (per Channel) V+/V – Short-Circuit Output Current (Note 6) VCC = 5.5V, V+/V – = ±15.75V, VREF = 2.5V, ±10V Output Range Code: Zero-Scale; Forcing Output to GND Code: Full-Scale; Forcing Output to GND ±1 ±2 ±4 l l 16 –40 µV µV/mA µV 42 –14.5 mA mA 2.5 2.505 V ±10 Reference Reference Output Voltage 4 2.495 Reference Temperature Coefficient (Note 7) ±2 Reference Line Regulation VCC ±10% 50 ppm/°C µV/V Reference Short-Circuit Current VCC = 5.5V, Forcing Output to GND 2.6 mA REFCOMP Pin Short-Circuit Current VCC = 5.5V, Forcing Output to GND 65 µA 2664fa For more information www.linear.com/LTC2664 LTC2664 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, IOVCC = 5V, V+ = 15V, V – = –15V, VREF = 2.5V, VOUT unloaded unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Load Regulation VCC = 5V ± 10%, IOUT = 100µA Sourcing 140 mV/mA Reference Output Voltage Noise Density CREFCOMP = CREF = 0.1µF, at f = 10kHz 32 nV/√Hz Reference Input Range External Reference Mode (Note 8) l Reference Input Current External Reference l 0.001 l 40 Reference Input Capacitance (Note 9) 0.5 VCC – 1.75 V 1 µA pF Power Supply VCC Analog Supply Voltage l 4.5 5.5 V V+ Analog Positive Supply l 4.5 15.75 V V– Analog Negative Supply l –15.75 –4.5 V V IOVCC Digital I/O Supply Voltage VCC + 0.3 V I(VCC) Supply Current VCC VCC = 5V, Unipolar Ranges (Note 10) VCC = 5V, Bipolar Ranges (Note 10) l l 1.6 2.7 2.1 3.2 mA mA IS Supply Current V+/V – Unipolar Ranges (Code = 0) Bipolar Ranges (Note 11) l l 1.3 2.3 1.8 2.7 mA mA I(IOVCC) Supply Current IOVCC (Note 12) IOVCC = 5V l 0.02 1 µA V – Not Tied to GND V – Tied to GND l 0 1.71 VCC Shutdown Supply Current IOVCC = VCC = 5V, V+/V – = ±15V l 1 10 µA V+ Shutdown Supply Current IOVCC = VCC = 5V, V+/V – = ±15V l 35 70 µA V – Shutdown Supply Current = 5V, V+/V – = ±15V l IOVCC = VCC –60 –27 µA 2.2 kΩ Analog Mux Analog Mux DC Output Impedance Analog Mux Leakage Current Analog Mux Disabled (High Impedance) l Analog Mux Output Voltage Range Analog Mux Selected to DAC Channel l Analog Mux Continuous Current (Note 9) 0.02 V– 1 µA V+ – 1.4 V ±1 l mA Temperature Monitor Initial Voltage T = 25°C Temperature Coefficient 1.4 V –3.7 mV/°C AC Performance tSET SR en Settling Time (Notes 9, 13) 0V to 5V or ±2.5V Span, ±5V Step ±0.024% (±1LSB at 12 Bits) ±0.0015% (±1LSB at 16 Bits) 4.5 9 µs µs Settling Time (Notes 9, 13) 0V to 10V or ±5V Span, ±10V Step ±0.024% (±1LSB at 12 Bits) ±0.0015% (±1LSB at 16 Bits) 8 9.5 µs µs Settling Time (Notes 9, 13) ±10V Span, ±20V Step ±0.024% (±1LSB at 12 Bits) ±0.0015% (±1LSB at 16 Bits) 15.5 20 µs µs Voltage Output Slew Rate 5 1000 V/µs Capacitive Load Driving No Oscillation Glitch Impulse (Note 14) At Mid-Scale Transition, 0V to 5V Range DAC-to-DAC Crosstalk (Note 15) Due to Full-Scale Output Change 3.5 nV • s Output Voltage Noise 0V to 5V Output Span, Internal Reference Density at f = 1kHz Density at f = 10kHz 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, Internal Reference 90 80 1.7 55 nV/√Hz nV/√Hz µVRMS µVRMS 7 pF nV • s 2664fa For more information www.linear.com/LTC2664 5 LTC2664 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, IOVCC = 5V, V+ = 15V, V – = –15V, VREF = 2.5V, VOUT unloaded unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital I/O VCC = 4.5V to 5.5V, IOVCC = 1.71V to VCC VOH Digital Output High Voltage SDO Pin. Load Current = –100µA l IOVCC – 0.2 V VOL Digital Output Low Voltage SDO Pin. Load Current = 100µA OVRTMP Pin. Load Current = 100µA l l 0.2 0.2 V V IOZ Digital Hi-Z Output Leakage SDO Pin Leakage Current (CS/LD High) OVRTMP Pin Leakage Current (Not Asserted) l l ±1 1 µA µA ILK Digital Input Leakage VIN = GND to IOVCC l ±1 µA CIN Digital Input Capacitance (Note 9) l 8 pF IOVCC = 2.7V to VCC VIH Digital Input High Voltage l VIL Digital Input Low Voltage l 0.8 • IOVCC V 0.5 V IOVCC = 1.71V to 2.7V VIH Digital Input High Voltage l VIL Digital Input Low Voltage l 0.8 • IOVCC V 0.3 V Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Digital input low and high voltages are 0V and IOVCC, respectively. LTC2664-16/LTC2664-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC = 4.5V to 5.5V, IOVCC = 2.7V to VCC t1 SDI Valid to SCK Setup l 6 ns t2 SDI Valid to SCK Hold l 6 ns t3 SCK HIGH Time l 9 ns t4 SCK LOW Time l 9 ns t5 CS/LD Pulse Width l 10 ns t6 LSB SCK High to CS/LD High l 7 ns t7 CS/LD Low to SCK High l 7 ns t8 SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF IOVCC = 4.5V to VCC IOVCC = 2.7V to 4.5V 20 30 l l ns ns t9 CLR Pulse Width l 20 ns t10 CS/LD High to SCK Positive Edge l 7 ns t12 LDAC Pulse Width l 15 ns t13 CS/LD High to LDAC High or Low Transition l 15 ns SCK Frequency 50% Duty Cycle 50 l MHz t14 TGP High Time (Note 9) l 1 µs t15 TGP Low Time (Note 9) l 1 µs 6 2664fa For more information www.linear.com/LTC2664 LTC2664 Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Digital input low and high voltages are 0V and IOVCC, respectively. LTC2664-16/LTC2664-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC = 4.5V to 5.5V, IOVCC = 1.71V to 2.7V t1 SDI Valid to SCK Setup l 7 ns t2 SDI Valid to SCK Hold l 7 ns t3 SCK HIGH Time l 30 ns t4 SCK LOW Time l 30 ns t5 CS/LD Pulse Width l 15 ns t6 LSB SCK High to CS/LD High l 7 ns t7 CS/LD Low to SCK High l 7 t8 SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF ns 60 l ns t9 CLR Pulse Width l 30 ns t10 CS/LD High to SCK Positive Edge l 7 ns t12 LDAC Pulse Width l 15 ns t13 CS/LD High to LDAC High or Low Transition l 15 SCK Frequency 50% Duty Cycle ns 15 l MHz t14 TGP High Time (Note 9) l 1 µs t15 TGP Low Time (Note 9) l 1 µs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND Note 3: For V – = GND, linearity is defined from code kL to code 2N – 1, where N is the resolution and kL is the lower end code for which no output limiting occurs. For VREF = 2.5V and N = 16, kL = 128 and linearity is defined from code 128 to code 65,535. For VREF = 2.5V and N = 12, kL = 8 and linearity is defined from code 8 to code 4095. Note 4: 4.5V ≤ V+ ≤ 16.5V; –16.5V ≤ V – ≤ –4.5V or V – = GND. VOUT is at least 1.4V below V+ and 1.4V above V –. Note 5: DC crosstalk is measured with VCC = 5V, using the internal reference. The conditions of one DAC channel are changed as specified, and the output of an adjacent channel (at mid-scale) is measured before and after the change. Note 6: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 7: Temperature coefficient is calculated by first computing the ratio of the maximum change in output voltage to the nominal output voltage. The ratio is then divided by the specified temperature range. Note 8: Gain-error and bipolar zero error specifications may be degraded for reference input voltages less than 1.25V. See the Gain Error vs Reference Input and Bipolar Zero vs Reference Input curves in the Typical Performance Characteristics section. Note 9: Guaranteed by design and not production tested. Note 10: Internal reference. Note 11: I(V+) measured in ±10V span; outputs unloaded; all channels at full scale. I(V–) measured in ±10V span; outputs unloaded; all channels at negative full scale. Each DAC amplifier is internally loaded by a 40kΩ feedback network, so supply currents increase as output voltages diverge from 0V. Note 12: Digital inputs at 0V or IOVCC. Note 13: Internal reference. Load is 2k in parallel with 100pF to GND. Note 14: VCC = 5V, 0V to 5V range, internal reference. DAC is stepped ±1LSB between half-scale and half-scale – 1LSB. Load is 2k in parallel with 200pF to GND. Note 15: DAC-to-DAC crosstalk is the glitch that appears at the output of one DAC due to full-scale change at the output of another DAC. 0V to 10V range with internal reference. The measured DAC is at mid-scale. 2664fa For more information www.linear.com/LTC2664 7 LTC2664 Typical Performance Characteristics TA = 25°C, unless otherwise noted. LTC2664-16 Integral Nonlinearity (INL) 4 Differential Nonlinearity (DNL) 1.0 ±10V RANGE –1 0.2 INL (LSB) DNL (LSB) 0 –0.0 –0.2 –0.4 –2 16384 32768 CODE 49152 –1.0 65535 0 16384 32768 CODE 49152 2664 G01 ±10V RANGE 0.6 0.04 GE (%FS) DNL (NEG) –0.2 –0.4 –0.6 –0.8 –1.0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 0.02 –0.02 0.02 0.00 –0.02 –0.04 –0.04 –0.06 –0.06 0 20 40 60 80 100 120 TEMPERATURE (°C) 2664 G04 –0.08 –40 –20 INL vs Output Range Settling 10V Step CS/LD 3 CS/LD VOUT 1V/DIV VOLTAGE 2 0 20 40 60 80 100 120 TEMPERATURE (°C) 2664 G06 Settling 5V Step 1 0 2664 G05 4 INL (LSB) 0.04 0.00 –0.08 –40 –20 ±5V RANGE ±10V RANGE ±2.5V RANGE 0.06 VOUT 2V/DIV VOLTAGE DNL (LSB) 0.4 –0.0 20 40 60 80 100 120 TEMPERATURE (°C) Bipolar Zero Error vs Temperature 0.08 0V to 5V RANGE 0V to 10V RANGE ±5V RANGE ±10V RANGE ±2.5V RANGE 0.06 DNL (POS) 0 2664 G03 Gain Error vs Temperature 0.08 0.2 INL (NEG) –4 –40 –20 65535 BZE (%FS) 0.8 –1 2664 G02 DNL vs Temperature 1.0 0 –3 –0.8 0 INL (POS) 1 –2 –0.6 –3 ±10V RANGE 2 0.4 1 INL (LSB) 3 0.6 2 –4 ±10V RANGE 0.8 3 INL vs Temperature 4 VOUT RESIDUAL 500µV/DIV VOUT RESIDUAL 500µV/DIV tSETTLE = 9.3µs tSETTLE = 8.7µs –1 –2 2µs/DIV OUTPUT RANGE 8 0V TO 10V 0V TO 5V ±10V ±5V –4 ±2.5V –3 2664 G08 0V TO 5V RANGE; INTERNAL REFERENCE RISING 5V STEP; AVERAGE OF 128 EVENTS FALLING SETTLING IS SIMILAR OR BETTER RESIDUAL WAVEFORM INCLUDES 100ns FIXTURE DELAY 2664 G09 5µs/DIV 0V TO 10V RANGE; INTERNAL REFERENCE RISING 10V STEP; AVERAGE OF 128 EVENTS FALLING SETTLING IS SIMILAR OR BETTER RESIDUAL WAVEFORM INCLUDES 100ns FIXTURE DELAY 2664 G07 2664fa For more information www.linear.com/LTC2664 LTC2664 Typical Performance Characteristics Integral Nonlinearity (INL) (LTC2664-12) Settling 20V Step 1.0 CS/LD tSETTLE = 19.2µs 2664 G10 10µs/DIV ±10V RANGE; INTERNAL REFERENCE RISING 20V STEP; AVERAGE OF 64 EVENTS FALLING SETTLING IS SIMILAR OR BETTER RESIDUAL WAVEFORM INCLUDES 100ns FIXTURE DELAY 0.3 0.4 0.2 0.2 –0.0 –0.2 –0.2 –0.3 –0.8 –0.4 0.02 0.02 0.00 –0.02 –0.06 –0.06 1024 2048 CODE 3072 4095 Single-Supply Zero-Scale Error vs Temperature 4 3 1.0 1.5 2.0 2.5 VREF (V) 3.0 Minimum Output Voltage VOUT vs Load Current 0 0V TO 5V RANGE –1 –2 2.496 VOUT (V) [V+/ V –= ±4.5V] VOS (mV) 0V TO 10V RANGE 0.8 –3.9 0.6 –4.1 0.4 –4.3 0.2 VOUT (V) [V+/ V – = 4.5V/0V] 2.498 VOUT MIN (V+/ V –= 4.5V/0V) –3.7 1 1.0 VOUT MIN (V+/ V– = ±4.5V) 3 2.500 20 40 60 80 100 120 TEMPERATURE (°C) 2664 G15 –3.5 2 0 2664 G14 4 2.502 2 0 –40 –20 3.5 Unipolar Offset vs Temperature 2.504 0V TO 5V RANGE V+/V– = 5V/0V ALL CHANNELS 1 2664 G13 2.506 VREF (V) 0 2664 G12 ±10V RANGE ALL CHANNELS –0.08 0.5 3.5 Reference Output vs Temperature 2.494 –40 –20 –0.5 4095 –0.02 –0.04 3.0 3072 0.00 –0.04 2.0 2.5 VREF (V) 2048 CODE ZSE (mV) 0.06 BZE (%FS) GE (%FS) 0.08 0.04 1.5 1024 Bipolar Zero Error vs Reference Input 0.04 1.0 0 2664 G11 ±10V RANGE ALL CHANNELS –0.08 0.5 –0.1 –0.6 Gain Error vs Reference Input 0.06 0.1 –0.0 –0.4 –1.0 ±10V RANGE 0.4 0.6 LTC2664-16/LTC2664-12 0.08 0.5 DNL (LSB) INL (LSB) VOLTAGE VOUT RESIDUAL 500µV/DIV Differential Nonlinearity (DNL) (LTC2664-12) ±10V RANGE 0.8 VOUT 5V/DIV TA = 25°C, unless otherwise noted. –3 0 20 40 60 80 100 120 TEMPERATURE (°C) 2664 G16 –4 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 2664 G17 –4.5 0 2 4 6 8 OUTPUT CURRENT SINKING (mA) 10 0.0 2664 G18 2664fa For more information www.linear.com/LTC2664 9 LTC2664 Typical Performance Characteristics TA = 25°C, unless otherwise noted. LTC2664-16/LTC2664-12 Maximum Output Voltage VOUT vs Load Current 2.0 4.5 VOS (mV) VOUT (V) 4.1 3.9 3.5 VOUT MAX (V+/ V– = ±4.5V) VOUT MAX (V+/ V– = 4.5V/0V) 0 –2 –4 –6 –8 OUTPUT CURRENT SOURCING (mA) –10 1.0 2.0 0.5 1.0 0.0 –0.5 –1.5 –3.0 1.0 1.5 1.0 INTERNAL REFERENCE OUTPUTS UNLOADED SAME CODE ALL CHANNELS 2.0 2.5 VREF (V) 3.0 VCC Shutdown Current vs VCC IVCC (µA) I(VCC) (mA) 0.6 0.4 0.2 0 –10 –7.5 –5 –2.5 0 2.5 VOUT (V) 5 7.5 10 0.0 4.4 2664 G22 IOVCC Supply Current vs Logic Voltage 4.6 4.8 5.0 VCC (V) 5.2 2.0 2.5 VREF (V) 5.4 20 0 I(V –)SHUTDOWN –10 –20 –30 –40 4 6 8 10 12 V+/V– (V) 2664 G24 Hardware CLR to Zero-Scale I(IOVCC) (mA) 0.2 –0.1 0V to 5V RANGE VOUT 1V/DIV VOUT 5V/DIV IOVCC = 3.3V –0.0 FROM ZERO-SCALE CLR IOVCC = 1.8V 0 1 2 3 4 INPUT LOGIC VOLTAGE (V) VCC = 5V SCK, SDI, CS/LD, LDAC, CLR, TGP TIED TOGETHER 10 16 FROM FULL-SCALE 0.3 0.1 14 2664 G23 Hardware CLR to Mid-Scale IOVCC = 5V 2664 G21 I(V +)SHUTDOWN 10 ±10V RANGE 0.4 3.5 30 0.6 0.5 3.0 40 1.0 ±10V RANGE ±5V RANGE ±2.5V RANGE 1.5 V+/V– Shutdown Current vs Symmetric Supplies 2.0 0.5 1.0 2664 G20 0.8 1.5 –4.0 0.5 3.5 V+/V – SHUTDOWN CURRENT (µA) VCC Supply Current vs Bipolar Output Voltage 2.5 –1.0 –2.0 2664 G19 3.0 0.0 –1.0 –2.0 0.5 0V to 10V RANGE ALL CHANNELS 3.0 VOS (mV) 4.3 4.0 0V to 5V RANGE ALL CHANNELS 1.5 3.7 Unipolar Offset vs Reference Input Unipolar Offset vs Reference Input 5 2664 G25 CLR 2µs/DIV 2µs/DIV 2664 G26 2664 G27 2664fa For more information www.linear.com/LTC2664 LTC2664 Typical Performance Characteristics LTC2664-16/LTC2664-12 TA = 25°C, unless otherwise noted. Output 0.1Hz to 10Hz Voltage Noise Output Voltage Noise Density vs Frequency Reference 0.1Hz to 10Hz Voltage Noise 400 300 VREF 10µV/DIV VOUT 10µV/DIV 200 100 10 100 1k 10k FREQUENCY (Hz) 100k 1M DAC-to-DAC Crosstalk CS/LD CS/LD VCC, IOVCC: 5V V+/V–: ±15V 0V TO 5V RANGE INTERNAL REFERENCE CREF, CREFCOMP: 0.1µF 7nV–s TYP VOUT 10mV/DIV 1µs/DIV 2664 G32 10V TO 0V FALLING STEP: VOUT1 MEASURED CHANNEL: VOUT0 RISING STEP IS SIMILAR OR BETTER ALL CHANNELS ARE SIMILAR OR BETTER Load Regulation Large Signal Response 10 8 0V to 10V RANGE 6 78µV/mA TYP CODE: MID–SCALE INTERNAL REF 4 0V to 5V RANGE 0 –5 2 0 –2 –4 ±10V RANGE 0 to 5V RANGE V+/V– = 5V/0V ±10V RANGE V+/V– = ±15V –6 –10 –8 –15 3nV–s TYP 1µs/DIV 15 5 VCC, IOVCC: 5V V+/V–: ±15V 0V TO 10V RANGE INTERNAL REFERENCE CREF, CREFCOMP: 0.1µF 2664 G31 RISING MAJOR CARRY TRANSITION FALLING TRANSITION IS SIMILAR OR BETTER ALL CHANNELS ARE SIMILAR OR BETTER 10 2664 G30 VCC VREF = 2.5V (INTERNAL REFERENCE) CREF = CREFCOMP = 0.1µF Mid-Scale Glitch Impulse VOUT 10mV/DIV 1s/DIV = 5V; V+/V– = ±15V VCC 0V TO 5V RANGE CODE = MID–SCALE INTERNAL REFERENCE CREF = CREFCOMP = 0.1µF 2664 G28 AVP = 5V, V+/V– = ±15V 0V TO 5V RANGE CODE = MID-SCALE INTERNAL REFERENCE CREF = CREFCOMP = 0.1µF 2664 G29 1s/DIV = 5V; V+/V– = ±15V ∆VOUT (mV) 0 VOUT (V) NOISE DENSITY (nV/√Hz) 500 –10 –30 10µs/DIV 2664 G33 –20 –10 0 10 20 VOUT LOAD CURRENT (mA) 30 2664 G34 2664fa For more information www.linear.com/LTC2664 11 LTC2664 Pin Functions MSP2 (Pin 1): MSPAN Bit 2. Tie this pin to VCC or GND to select the power-on span and power-on-reset code for all four channels (see Table 4). MUXIN0 to MUXIN3 (Pins 2, 5, 20, 23): Analog Multiplexer Auxiliary Inputs. Can be used to monitor any external voltage within the compliance range (V– to V+ – 1.4V). Tie to GND if not used. VOUT0 to VOUT3 (Pins 3, 4, 21, 22): DAC Analog Voltage Outputs. DNC (Pins 6, 19): Do not connect. V+ (Pin 7): Analog Positive Supply. Typically 15V; 4.5V to 15.75V range. Bypass to GND with a 1µF capacitor. V– (Pin 8): Analog Negative Supply. Typically –15V; –4.5V to –15.75V range, or can be tied to GND. Bypass to GND with a 1µF capacitor unless V– is connected to GND. MUXOUT (Pin 9): Analog Multiplexer Output. VOUT0-VOUT3, MUXIN0 – MUXIN3, REFLO, REF, V+, V– and a temperature monitor output can be internally routed to the MUXOUT pin. When the mux is disabled, this pin becomes high impedance. REFLO (Pins 10, 27): Reference Low Pins. Signal ground for the reference and DAC outputs. These pins should be tied to GND. GND (Pins 11, 29): Analog Ground. Tie to a clean analog ground plane. LDAC (Pin 12): Active-low Asynchronous DAC Update Pin. If CS/LD is high, a falling edge on LDAC immediately updates all DAC registers with the contents of the input registers (similar to a software update). If CS/LD is low when LDAC goes low, the DAC registers are updated after CS/LD returns high. A low on the LDAC pin powers up the DACs. A software power-down command is ignored if LDAC is low. Logic levels are determined by IOVCC. Tie LDAC high (to IOVCC) if not used. Updates can then be performed through SPI commands (see Table 1). CS/LD (Pin 13): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. Logic levels are determined by IOVCC. 12 SCK (Pin 14): Serial Interface Clock Input. Logic levels are determined by IOVCC. SDO (Pin 15): Serial Interface Data Output. The serial output of the 32-bit shift register appears at the SDO pin. The data transferred to the device via the SDI pin is delayed 32 SCK rising edges before being output at the next falling edge. Can be used for data echo readback or daisy-chain operation (pull-up/down resistor required). The SDO pin becomes high impedance when CS/LD is high. Logic levels are determined by IOVCC. SDI (Pin 16): Serial Interface Data Input. Data on SDI is clocked into the DAC on the rising edge of SCK. The LTC2664 accepts input word lengths of either 24 or 32 bits. Logic levels are determined by IOVCC. TGP (Pin 17): Asynchronous Toggle Pin. A falling edge updates the DAC register with data from input register A. A rising edge updates the DAC register with data from input register B. Toggle operations only affect those DAC channels with their toggle select bit (Tx) set to 1. Tie the TGP pin to IOVCC if toggle operations are to be done through software. Tie the TGP pin to GND if not using toggle operations. Logic levels are determined by IOVCC. CLR (Pin 24): Active-low Asynchronous Clear Input. A logic low at this level-triggered input clears the part to the reset code and range determined by the hardwired option chosen using the MSPAN pins and specified in Table 4. The control registers are cleared to zero. Logic levels are determined by IOVCC. IOVCC (Pin 18): Digital Input/Output Supply Voltage. 1.71V ≤ IOVCC ≤ VCC + 0.3V. Bypass to GND with a 0.1µF capacitor. REF (Pin 25): Reference In/Out. The voltage at the REF pin sets the full-scale range of all channels. By default, the internal reference is routed to this pin. Must be buffered when driving external DC load currents. If the reference is disabled (see Reference Modes in the Operation section), its output is disconnected and the REF pin becomes a high impedance input to which you may apply a precision external reference. For low noise and reference stability, tie a capacitor from this pin to GND. The value must be ≤ CREFCOMP, where CREFCOMP is the capacitance tied to For more information www.linear.com/LTC2664 2664fa LTC2664 Pin Functions the REFCOMP pin. The allowable external reference input voltage range is 0.5V to VCC – 1.75V. temperature exceeds 160°C. This pin is released on the next CS/LD rising edge. A pull-up resistor is required. REFCOMP (Pin 26): Internal Reference Compensation Pin. For low noise and reference stability, tie a 0.1µF capacitor to GND. Tying REFCOMP to GND causes the part to power up with the internal reference disabled, allowing the use of an external reference at start-up. MSP0 (Pin 31): MSPAN Bit 0. Tie this pin to VCC or GND to select the power-on span and power-on-reset code for all four channels (see Table 4). VCC (Pin 28): Analog Supply Voltage Input. 4.5V ≤ VCC ≤ 5.5V. Bypass to GND with a 1µF capacitor. OVRTMP (Pin 30): Thermal Protection Interrupt Pin. This open-drain N-channel output pulls low when chip MSP1 (Pin 32): MSPAN Bit 1. Tie this pin to VCC or GND to select the power-on span and power-on-reset code for all four channels (see Table 4). Exposed Pad (Pin 33): Analog Negative Supply (V–). Must be soldered to PCB. 2664fa For more information www.linear.com/LTC2664 13 LTC2664 Block Diagram REFCOMP 26 25 REF INTERNAL REFERENCE 28 VCC SDI 16 SDO 15 MUXOUT 9 CONTROL LOGIC REGISTER V+ 8 V– 22 VOUT3 SPAN SPAN SPAN REGISTER SPAN RGSTR B RGSTR A DAC 2 21 VOUT2 20 MUXIN2 12 LDAC 17 TGP DECODE 32-BIT SHIFT REGISTER 7 VREF CS/LD 13 SCK 14 24 CLR 23 MUXIN3 DAC 3 MUX RGSTR B SPAN MUXIN1 5 MUX DAC 1 SPAN VOUT1 4 RGSTR A REGISTER VREF VREF MUX RGSTR B SPAN DAC 0 SPAN VOUT0 3 MUX RGSTR B MUXIN0 2 RGSTR A VREF REGISTER GND 11, 29 REFLO 10, 27 RGSTR A OVRTMP 30 31 MSP0 POWER-ON RESET 32 MSP1 1 MONITOR MUX TOGGLE SELECT REGISTER MSP2 18 IOVCC 2664 BD 14 2664fa For more information www.linear.com/LTC2664 LTC2664 Timing Diagram t1 t2 SCK t3 1 2 t6 t4 3 23 24 t10 SDI t5 t7 2664 F01 CS/LD Figure 1. Serial Interface Timing Operation The LTC2664 is a family of four-channel, ±10V digital-toanalog converters with selectable output ranges and an integrated precision reference. The DACs operate on positive 5V and bipolar ±15V supplies. The bipolar supplies can operate as low as ±4.5V, and need not be symmetrical. In addition, the negative V – supply can be operated at ground, making the parts compatible with single-supply systems. The outputs are driven by the bipolar supply rails. The output amplifiers offer true rail-to-rail operation. When drawing a load current from the V+ or V – rail, the output voltage headroom with respect to that rail is limited by the 60Ω typical channel resistance of the output devices. See the graph, Headroom at Rails vs Output Current, in the Typical Performance Characteristics section. The LTC2664 is controlled using a cascadable 3-wire SPI/ Microwire-compatible interface with echo readback. Power-On Reset The outputs reset when power is first applied, making system initialization consistent and repeatable. By tying the MSPAN pins (MSP2, MSP1, MSP0) to GND and/or VCC, you can select the initial output range and reset code (zero- or mid-scale), as well as selecting between a manual (fixed) range and SoftSpan operation. See Table 4 for pin configurations and available options. Power Supply Sequencing and Start-Up The supplies (VCC, IOVCC, V+ and V –) may be powered up in any convenient order. If an external reference is used, do not allow the input voltage at REF to rise above VCC + 0.3V during supply turnon and turn-off sequences (see the Absolute Maximum Ratings section). After start-up, DC reference voltages of 0.5V to VCC – 1.75V are acceptable. Supply bypassing is critical to achieving the best possible performance. Use at least 1μF to ground on VCC, V+ and V – supplies, and at least 0.1μF of low ESR capacitance for each supply, as close to the device as possible. The larger capacitor may be omitted for IOVCC. Hot-plugging or hard switching of supplies is to be avoided, as power supply cable or trace inductances combined with bypass capacitances can cause supply voltage transients beyond absolute maximum ratings, even if the bench supply has been carefully current-/voltage-limited. During start-up, limit the supply inrush currents to no more than 5A and supply slew rates to no more than 5V/µs. Internal protection circuitry can be damaged and long-term reliability adversely affected if these requirements are not met. 2664fa For more information www.linear.com/LTC2664 15 LTC2664 Operation C3 0 1 0 1 0 1 0 0 1 0 0 1 1 1 0 1 COMMAND C2 C1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 1 1 C0 0 0 0 0 1 1 1 0 0 0 1 1 0 1 1 1 Write Code to n Write Code to All Write Span to n Write Span to All Update n (Power Up) Update All (Power Up) Write Code to n, Update n (Power Up) Write Code to n, Update All (Power Up) Write Code to All, Update All (Power Up) Power Down n Power Down Chip (All DACs, Mux and Reference) Analog Mux Toggle Select Global Toggle Config No Operation For the LTC2664-16, the data word comprises the 16-bit input code, ordered MSB-to-LSB. For the LTC2664-12, the data word comprises the 12-bit input code, ordered MSB-to-LSB, followed by four don’t-care bits. Data can only be transferred to the LTC2664 when the CS/LD signal is low. The rising edge of CS/LD ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. The complete sequence is shown in Figure 3a. 10 5 ADDRESS A2 A1 0 0 0 0 0 1 0 1 2.5 0 –2.5 –5 Table 2. DAC Addresses, n A3 0 0 0 0 –7.5 A0 0 1 0 1 2.5V INTERNAL REFERENCE 7.5 VOUT (V) Table 1. Command Codes –10 0V TO 5V RANGE 0V TO 10V RANGE ±5V RANGE ±10V RANGE ±2.5V RANGE 32768 49152 65535 0 16384 STRAIGHT BINARY CODE (DECIMAL EQUIVALENT) DAC 0 DAC 1 DAC 2 DAC 3 2664 F02a Figure 2a. LTC2664-16 Transfer Function Transfer Functions 10 Serial Interface When the CS/LD pin is taken low, the data on the SDI pin is loaded into the shift register on the rising edge of the clock (SCK pin). The 4-bit command, C3-C0, is loaded first, followed by the 4-bit DAC address, A3-A0, and finally the 16-bit data word in straight binary format. 2.5V INTERNAL REFERENCE 7.5 5 VOUT (V) The DAC input-to-output transfer functions for all output ranges and resolutions are shown in Figures 2a and 2b. The input code is in straight binary format for all ranges. 2.5 0 –2.5 –5 –7.5 –10 0V TO 5V RANGE 0V TO 10V RANGE ±5V RANGE ±10V RANGE ±2.5V RANGE 2048 3072 4095 0 1024 STRAIGHT BINARY CODE (DECIMAL EQUIVALENT) 2664 F02b Figure 2b. LTC2664-12 Transfer Function 16 2664fa For more information www.linear.com/LTC2664 X X SDI SDO (HI-Z) SCK CS/LD 1 3 X 4 X X X 5 X DON’T CARE X C2 C1 3 X X 6 X X 7 X X C0 4 8 A1 7 ADDRESS WORD A2 6 A0 8 D15 9 D14 10 D12 12 D11 13 D10 14 24-BIT INPUT WORD D13 11 D9 15 D7 17 DATA WORD D8 16 D6 18 D5 19 For more information www.linear.com/LTC2664 C1 11 C2 C1 COMMAND WORD C2 10 C0 C0 A3 A3 A2 14 A1 15 A2 A0 16 D15 17 A1 A0 D15 18 D14 D14 32-BIT INPUT WORD ADDRESS WORD 13 PREVIOUS 32-BIT INPUT WORD 12 t2 t8 D9 D9 t4 23 PREVIOUS D15 t3 17 D10 D10 22 SDO t1 D11 D11 21 D15 D12 D12 20 SDI SCK D13 D13 19 24 Figure 3. LTC2664 Load Sequences 25 D7 D3 21 18 D7 D6 D6 26 22 D2 PREVIOUS D14 D14 D8 DATA WORD D8 D4 20 3b. LTC2664-16 32-Bit Load Sequence. LTC2664-12 SDI/SDO Data Word Is 12-Bit Input Code + 4 Don’t-Care Bits C3 C3 9 3a. LTC2664-16 24-Bit Load Sequence (Minimum Input Word). LTC2664-12 SDI Data Word Is 12-Bit Input Code + 4 Don’t-Care Bits A3 5 27 D5 D5 D1 23 28 D4 D4 D0 24 D3 D3 29 2664 F03a D2 D2 30 D1 D1 31 X (HI-Z) 2664 F03b CURRENT 32-BIT INPUT WORD D0 D0 32 Operation X X 2 C3 SDI 2 COMMAND WORD 1 SCK CS/LD LTC2664 2664fa 17 LTC2664 Operation While the minimum input word is 24 bits, it may optionally be extended to 32 bits. To use the 32-bit word width, 8 don’t-care bits must be transferred to the device first, followed by the 24-bit word, as just described. Figure 3b shows the 32-bit sequence. The 32-bit word is required for echo readback and daisy-chain operation, and is also available to accommodate processors that have a minimum word width of 16 or more bits. Note that updates always refresh both code and span data, but the values held in the DAC registers remain unchanged unless the associated input register values have been changed via a write operation. For example, if you write a new code and update the channel, the code is updated, while the span is refreshed unchanged. A channel update can come from a serial update command, an LDAC negative pulse, or a toggle operation. Table 3. Write Span Code Input and DAC Registers OUTPUT RANGE The LTC2664 has five internal registers for each DAC, in addition to the main shift register (see the Block Diagram). Each DAC channel has two sets of double-buffered registers: one set for the code data, and one set for the span (output range) of the DAC. Double buffering provides the capability to simultaneously update the span and code, which allows smooth voltage transitions when changing output ranges. It also permits the simultaneous updating of multiple DACs. 0 A2 A1 0 0 0 0 0 0V to 5V 0V to 2VREF 1 0V to 10V 0V to 4VREF 0 1 0 1 0 ±5V ±2VREF 1 ±10V ±4VREF 1 0 0 ±2.5V ±VREF Each channel has a set of double-buffered registers for range information (see the Block Diagram). Program the span input register using the Write Span n or Write Span All commands (0110b and 1110b, respectively). Figure 4 shows the syntax, and Table 3 shows the span codes and ranges. As with the double-buffered code registers, update operations copy the span input registers to the associated span DAC registers. ADDRESS A3 EXTERNAL REFERENCE SoftSpan operation (ranges controlled through the serial interface) is invoked by tying all three MSPAN pins (MSP2, MSP1 and MSP0) to VCC (see Table 4). In SoftSpan configuration, all channels initialize to zero-scale in 0V to 5V range at power-on. The range and code of each channel are then fully programmable. • DAC Register: The update operation copies the contents of an input register to its associated DAC register. The content of a DAC register directly controls the DAC output voltage or range. The update operation also powers up the selected DAC if it had been in powerdown mode. The data path and registers are shown in the Block Diagram. 1 INTERNAL REFERENCE SoftSpan Operation In the code data path, there are two input registers, A and B, for each DAC register. Register B is an alternate input register used only in the toggle operation, while register A is the default input register (see Block Diagram). 1 S0 The LTC2664 is a 4-channel DAC with selectable output ranges. Ranges can either be programmed in software or hardwired through pin strapping. • Input Register: The write operation shifts data from the SDI pin into a chosen input register. The input registers are holding buffers; write operations do not affect the DAC outputs. 0 S1 Output Ranges Each set of double-buffered registers comprises an input register and a DAC register: WRITE SPAN COMMAND S2 DON’T CARE A0 X X X X X X X X SPAN CODE X X X X X S2 S1 S0 2664 F04 Figure 4. Write Span Syntax 18 2664fa For more information www.linear.com/LTC2664 LTC2664 Operation The compliance range of the mux is from V– to V+ – 1.4V; but the channel that carries the V+ supply (control code 11011b) is an exception, pulling all the way to V+. MUXOUT is disabled (high impedance) at power-up. Manual Span Operation Multiple output ranges are not needed in all applications. By tying the MSPAN pins (MSP2, MSP1 and MSP0) to GND and/or VCC, any output range can be hardware-configured without additional operational overhead. Zero-scale and mid-scale reset options are also available for the unipolar modes (see Table 4). MUXOUT is designed to drive high-impedance loads only; internal circuits can be damaged if the output current at MUXOUT exceeds ±1mA. Table 4. MSPAN Pin Configurations MSP2 MSP1 MSP0 OUTPUT RANGE RESET CODE MANUAL SPAN 0 0 0 ±10V Mid-Scale X 0 0 VCC ±5V Mid-Scale X 0 VCC 0 ±2.5V Mid-Scale X 0 VCC VCC 0V to 10V Zero-Scale X VCC 0 0 0V to 10V Mid-Scale X VCC 0 VCC 0V to 5V Zero-Scale X VCC VCC 0 0V to 5V Mid-Scale X VCC VCC VCC 0V to 5V Zero-Scale The syntax and codes for the Mux command are shown in Figure 5 and Table 5. SOFTSPAN Table 5. Analog Mux Control Codes X Analog Mux The LTC2664 includes an analog multiplexer (mux) for surveying selected device voltages. In addition to individual DAC outputs, available multiplexer inputs include REF, REFLO, V+ and V– supplies, an internal temperature monitor, and four auxiliary inputs (MUXIN0 to MUXIN3). Any one of the mux’s inputs can be coupled to the MUXOUT pin by using the mux command (1011b) along with the control codes specified in Table 5. 1 0 1 M3 M2 M1 M0 MUX PIN OUTPUT 0 0 0 0 0 Disabled (Hi-Z) 1 0 0 0 0 MUXIN0 1 0 0 0 1 VOUT0 1 0 0 1 0 VOUT1 1 0 0 1 1 MUXIN1 1 0 1 0 0 MUXIN2 1 0 1 0 1 VOUT2 1 0 1 1 0 VOUT3 1 0 1 1 1 MUXIN3 1 1 0 0 0 REFLO 1 1 0 0 1 REF 1 1 0 1 0 Temperature Monitor 1 1 0 1 1 V+ 1 1 1 0 0 V– Temperature Monitor A biased temperature monitor diode stack is provided, and can be routed to MUXOUT by using the Mux command with control code 11010b. Typically VMUXOUT = 1.4V – 3.7mV/°C • (TJ – 25°C); the junction temperature can be calculated as TJ = 25°C + (1.4V –VMUXOUT)/(3.7mV/°C). For best accuracy, use the mux to sense REFLO at the bottom of the diode and calibrate the voltage at a known temperature. Typical uncalibrated accuracy is ±5°C. The auxiliary inputs, MUXIN0 to MUXIN3, can be used to monitor any external voltage within the compliance range (V– to V+ – 1.4V). The input pins present a high impedance until they are enabled; and when enabled, they load the driving source with approximately 2.2k in series with the external load impedance at MUXOUT. MUX COMMAND M4 DON’T CARE 1 X X X X X X X X MUX CONTROL CODE X X X X X X X M4 M3 M2 M1 M0 2664 F05 Figure 5. Mux Command 2664fa For more information www.linear.com/LTC2664 19 LTC2664 Operation Toggle Operations Some systems require that DAC outputs switch repetitively between two voltage levels. Examples include introducing a small AC bias, or independently switching between ‘on’ and ‘off’ states. The LTC2664 toggle function facilitates these kinds of operations by providing two input registers (A and B) per DAC channel. operations are directed to input register B of the addressed channel. When the bit is low, write-code operations are directed to input register A. Secondly, each toggle select bit enables the corresponding channel for a toggle operation. Writing to Input Registers A and B Toggling between A and B is controlled by three signals. The first of these is the toggle select command, which acts on a data field of 4 bits, each of which controls a single channel (see Figure 6). The second is the global toggle command, which controls all selected channels using the global toggle bit TGB (see Figure 7). Finally, the TGP pin allows the use of an external clock or logic signal to toggle the DAC outputs between A and B. The signals from these controls are combined as shown in Figure 8. Having chosen channels to toggle, write the desired codes to Input registers A for the chosen channels; then set the channels’ toggle select bits using the toggle select command; and finally, write the desired codes to input registers B. Once these steps are completed, the channels are ready to toggle. For example, to set up channel 3 to toggle between codes 4096 and 4200: If the toggle function is not needed, tie TGP (Pin 17) to ground and leave the toggle select register in its power-on reset state (cleared to zero). Input registers A then function as the sole input registers, and registers B are not used. 2) Toggle Select (set bit T3) 11000000 00000000 00001000 Toggle Select Register (TSR) The Write code of step (3) is directed to register B because in step (2), bit T3 was set to 1. Channel 3 now has Input registers A and B holding the two desired codes, and is prepared for the toggle operation. The Toggle Select command (1100b) syntax is shown in Figure 6. Each bit in the 4-bit TSR data field controls the DAC channel of the same name: T0 controls channel 0, T1 channel 1,…, and Tx controls channel x. The toggle select bits (T0, T1, T2, T3) have a dual function. First, each toggle select bit controls which input register (A or B) receives data from a write-code operation. When the toggle select bit of a given channel is high, write-code TOGGLE SELECT 1 1 0 1) Write code channel 3 (code = 4096) to register A 00000011 00010000 00000000 3) Write code channel 3 (code = 4200) to register B 00000011 00010000 01101000 Toggling Between Registers A and B Once Input registers A and B have been written to for all desired channels and the corresponding toggle select bits are set high, as in the previous example, the channels are ready for toggling. TOGGLE SELECT BITS (ONE FOR EACH CHANNEL) DON’T CARE 0 X X X X X X X X X X X X X X X X T3 T2 T1 T0 2664 F06 Figure 6. Toggle Select Syntax GLOBAL TOGGLE COMMAND 1 1 0 1 GLOBAL TOGGLE BIT DON’T CARE X X X X X X X X X X X X X X X X X X X TGB 2664 F07 Figure 7. Global Toggle Syntax 20 2664fa For more information www.linear.com/LTC2664 LTC2664 Operation The LTC2664 supports three types of toggle operations: a first in which all selected channels are toggled together using the SPI port; a second in which all selected channels are toggled together using an external clock or logic signal; and a third in which any combination of channels can be instructed to update from either input register A or B. The internal toggle-update circuit is edge triggered, so only transitions (of toggle bit TGB or toggle pin TGP) trigger an update from the respective input register. To toggle all selected channels together using the SPI port, ensure the TGP pin is high and that the bits in the toggle select register corresponding to the desired channels are also high. Use the global toggle command (1101b) to alternate codes, sequentially changing the global toggle bit TGB (see Figure 7). Changing TGB from 1 to 0 updates the DAC registers from their respective input registers A. Changing TGB from 0 to 1 updates the DAC registers from their respective input registers B. Note that in this way up to four channels may be toggled with just one serial command. To toggle all selected channels using an external logic signal, ensure that the TGB bit in the global toggle register is high and that in the toggle select register, the bits corresponding to the desired channels are also high. Apply a clock or logic signal to the TGP pin to alternate codes. TGP falling edges update the DAC registers from their associated input registers A. TGP rising edges update the DAC registers from their associated input registers B. Note that once the input registers are set up, all toggling is triggered by the signal applied to the TGP pin, with no further SPI instructions needed. To cause any combination of channels to update from either input register A or B, ensure the TGP pin is high and that the TGB bit in the global toggle register is also high. Using the toggle select command, set the toggle select bits as needed to select the input register (A or B) with which each channel is to be updated. Then update all channels, either by using the serial command (1001b) or by applying a negative pulse to the LDAC pin. Any channels whose toggle select bits are 0 update from input register LTC2664 CHANNEL 3 INPUT REGISTER A 16 (16 BIT) LOGIC 0 A/B MUX WR INPUT REGISTER B (16 BIT) LDAC 12 16 16 DAC REGISTER 16 16-BIT SOFTSPAN DAC 1 UPD T0 T1 T2 T3 TOGGLE SELECT BIT T3 TGB TOGGLE SELECT SDI 16 32-BIT SHIFT REGISTER SCK 14 CS/LD 13 GLOBAL TOGGLE BIT (TGB) TGP 17 2666 F08 Figure 8. Simplified Toggle Block Diagram. Conceptual Only, Actual Circuit May Differ 2664fa For more information www.linear.com/LTC2664 21 LTC2664 Operation A, while channels whose toggle select bits are 1 update from input register B (see Figure 8). By alternating toggleselect and update operations, up to four channels can be simultaneously switched to A or B as needed. Daisy-Chain Operation The serial output of the shift register appears at the SDO pin. Data transferred to the device from the SDI input is delayed 32 SCK rising edges before being output at the next SCK falling edge, suitable for clocking into the microprocessor on the next 32 SCK rising edges. The SDO output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., SCK, SDI and CS/LD). Such a daisy-chain series is configured by connecting the SDO of each upstream device to the SDI of the next device in the chain. The shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. Because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the first instruction addresses the last device in the chain and so forth. The SCK and CS/LD signals are common to all devices in the series. In use, CS/LD is first taken low. Then, the concatenated input data is transferred to the chain, using SDI of the first device as the data input. When the data transfer is complete, CS/LD is taken high, completing the instruction sequence for all devices simultaneously. A single device can be controlled by using the No-Operation command (1111) for all other devices in the chain. When CS/LD is taken high, the SDO pin presents a high impedance output, so a pull-up resistor is required at the SDO of each device (except the last) for daisy-chain operation. Echo Readback The SDO pin can be used to verify data transfer to the device. During each 32-bit instruction cycle, SDO outputs the previous 32-bit instruction for verification. When CS/LD is high, SDO presents a high impedance output, releasing the bus for use by other SPI devices. 22 Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four DAC outputs are needed. When in power-down, the output amplifiers and reference buffers are disabled. The DAC outputs are put into a high impedance state, and the output pins are passively pulled to ground through individual 42k (minimum) resistors. Register contents are not disturbed during power-down. Any channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address. In addition, all the DAC channels and the integrated reference together can be put into power-down mode using the Power-Down Chip command, 0101b. The 16-bit data word is ignored for all power-down commands. Normal operation resumes by executing any command which includes a DAC update—either in software, as shown in Table 1, by taking the asynchronous LDAC pin low, or by toggling (see the Types of Toggle Operations section). The selected DAC is powered up as its voltage output is updated. When updating a powered-down DAC, add wait time to accommodate the extra power-up delay. If the channels have been powered down (command 0100b) prior to the update command, the power-up delay time is 30μs. If, on the other hand, the chip has been powered down (command 0101b), the power-up delay time is 35μs. Asynchronous DAC Update Using LDAC In addition to the update commands shown in Table 1, the asynchronous, active-low LDAC pin updates all four DAC registers with the contents of the input registers. If CS/LD is high, a low on the LDAC pin causes all DAC registers to be updated with the contents of the input registers. If CS/LD is low, a low-going pulse on the LDAC pin before the rising edge of CS/LD powers up all DAC outputs, but does not cause the outputs to be updated. If LDAC remains low after the rising edge of CS/LD, then LDAC is recognized, the command specified in the 24-bit word is executed and the DAC outputs are updated. 2664fa For more information www.linear.com/LTC2664 LTC2664 Operation The DAC outputs are powered up when LDAC is taken low, independent of the state of CS/LD. The acceptable external reference voltage range is: 0.5V ≤ VREF ≤ VCC – 1.75V. If LDAC is low at the time CS/LD goes high, any software power-down command (power down n, power-down chip, config/select external reference) that was specified in the input word is inhibited. Integrated Reference Buffers Each channel has its own integrated high performance reference buffer. The buffers have very high input impedance and do not load the reference voltage source. These buffers shield the reference voltage from glitches caused by DAC switching and, thus, minimize DAC-to-DAC dynamic crosstalk. Typically DAC-to-DAC crosstalk is less than 3.5nV • s (0V to 10V range). See the DAC-to-DAC Crosstalk graph in the Typical Performance Characteristics section. Reference Modes The LTC2664 has two reference modes (internal and external) with which the reference source can be selected. In either mode, the voltage at the REF pin and the output range settings determine the full-scale voltage of each of the channels. Voltage Outputs The device has a precision 2.5V integrated reference with a typical temperature drift of 2ppm/°C. To use the internal reference, the REFCOMP pin should be left floating (no DC path to ground). In addition, the RD bit in the config register must have a value of 0. This value is reset to 0 at power-up, or it can be reset using the Config command, 0111b. Figure 9 shows the command syntax. An amplifier’s ability to maintain its rated voltage accuracy over a wide range of load conditions is characterized in its load regulation specification. The change in output voltage is measured per milliampere of forced load current change. Each of the LTC2664's high voltage, rail-to-rail output amplifiers has guaranteed load regulation when sourcing or sinking up to 10mA with supply headroom as low as 1.4V. Additionally, the amplifiers can drive up to ±14mA if available headroom is increased to 2.2V or more. A buffer is needed if the internal reference is to drive external circuitry. For reference stability and low noise, a 0.1μF capacitor should be tied between REFCOMP and GND. In this configuration, the internal reference can drive up to 0.1μF with excellent stability. In order to ensure stable operation, the capacitive load on the REF pin should not exceed that on the REFCOMP pin. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from µV/mA to Ohms. The amplifier’s DC output impedance is typically 0.08Ω when driving a load well away from the rails. To use an external reference, tie the REFCOMP pin to ground. This disables the output of the internal reference at start-up, so that the REF pin becomes a high impedance input. Apply the desired reference voltage at the REF pin after powering up, and set the RD bit to 1 using the Config command (0111b). This reduces VCC supply current by approximately 200µA. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 60Ω typical channel resistance of the output devices— e.g., when sinking 1mA, the minimum output voltage (above V –) is 60Ω • 1mA = 60mV. See the Headroom at Rails vs Output Current graphs in the Typical Performance Characteristics section. CONFIG COMMAND 0 1 1 1 CONFIG BITS DON’T CARE X X X X X X X X X X X X X X X X X X TS RD 2664 F09 Figure 9. Config Command Syntax—Thermal Shutdown (TS) and Reference Disable (RD) 2664fa For more information www.linear.com/LTC2664 23 LTC2664 Operation The amplifiers are stable driving capacitive loads of up to 1000pF. without using separate star traces. Resistance from the REFLO pin to the star point should be as low as possible. Thermal Overload Protection For best performance, stitch the ground plane with arrays of vias on 150 to 200 mil centers connecting it with the ground pours from the other board layers. This reduces overall ground resistance and minimizes ground loop area. The LTC2664 protects itself if the die temperature exceeds 160°C. All channels power down, and the open-drain OVRTMP interrupt pin pulls low. The reference and bias circuits stay powered on. Once triggered, the device stays in shutdown even after the die cools. The temperature of the die must fall to approximately 150°C before the channels can be returned to normal operation. Once the part has cooled sufficiently, the shutdown can be cleared with any valid update operation, including LDAC or a toggle operation. A CS/LD rising edge releases the OVRTMP pin regardless of the die temperature. Since the total load current of the device can easily exceed 50mA, die heating potential of the system design should be evaluated carefully. Grounded loads as low as 1k may be used and will not result in excessive heat. Thermal protection can be disabled by using the Config command to set the TS bit (see Figure 9). Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by minimizing common-mode resistance of signal and power grounds. As with any high resolution converter, clean board grounding is important. A low impedance analog ground plane is necessary, as are star-grounding techniques. Keep the board layer used for star ground continuous to minimize ground resistances; that is, use the star-ground concept 24 Using LTC2664 in 5V Single-Supply Systems LTC2664 can be used in single-supply systems simply by connecting the V – pin to ground along with REFLO and GND, while V+ and VCC are connected to a 5V supply. IOVCC can be connected to the 5V supply or to the logic supply voltage if lower than 5V. With the internal reference, use the 0V to 5V output range. As with any rail-to-rail device, the output is limited to voltages within the supply range. Since the outputs of the device cannot go below ground, they may limit at the lowest codes, as shown in Figure 10b. Similarly, limiting can occur near full-scale if full-scale error (FSE = VOS + GE) is positive, or if V+ < 2 • VREF. See Figure 10c. The multiplexer can be used and is fully functional. It can pull all the way to ground, but the upper headroom limitation means that it is useful for output voltages of 3.6V or below only (V+ = 5V). More flexibility can be afforded by using an external reference. For example, by using a 1.25V reference such as the LTC6655, we can now select between 0x to 2x and 0x to 4x ranges, which give full-scale voltages of 2.5V and 5V, respectively. Furthermore, the part can be configured for reset to zero- or mid-scale codes (see the Output Ranges section). 2664fa For more information www.linear.com/LTC2664 LTC2664 Operation V+ = 2VREF = 5V V+ = 2VREF = 5V POSITIVE FSE OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (10c) 2664 F10 OUTPUT VOLTAGE 0 NEGATIVE OFFSET 0V V– = V REFLO = 0V 32,768 INPUT CODE 65,535 (10a) INPUT CODE (10b) Figure 10. Effects of 0V to 5V Output Range for Single-Supply Operation. (10a) Overall Transfer Function (10b) Effect of Negative Offset for Codes Near Zero-Scale (10c) Effect of Positive Full-Scale Error for Codes Near Full-Scale 2664fa For more information www.linear.com/LTC2664 25 LTC2664 Package Description Please refer to http://www.linear.com/product/LTC2664#packaging for the most recent package drawings. UH Package 32-Lead Plastic QFN (5mm × 5mm) UH Package (Reference LTC DWG # 05-08-1693 Rev D) 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693 Rev D) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.50 REF (4 SIDES) 3.45 ±0.05 3.45 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ±0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.75 ±0.05 R = 0.05 TYP 0.00 – 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 31 32 0.40 ±0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.50 REF (4-SIDES) 3.45 ±0.10 3.45 ±0.10 (UH32) QFN 0406 REV D 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 26 0.25 ±0.05 0.50 BSC 2664fa For more information www.linear.com/LTC2664 LTC2664 Revision History REV DATE DESCRIPTION A 06/16 Fixed topmark information. PAGE NUMBER 3 2664fa For more information www.linear.com/LTC2664 27 LTC2664 Typical Application Using the Analog Multiplexer to Measure DAC Output Voltages Up to ±10.24V. Independent ADC Reference Cross-Checks LTC2664 Internal Reference 5V 0.1µF 1µF 5V 15 DAC OUTPUTS VCC OUT3 MUXIN0 2 MUXIN1 5 TGP CLR 5V MUXIN2 20 MUXIN3 23 LTC2664-16 SDI MUX INPUTS 2× 10µF 15V 2× 0.1µF SDO MUXOUT SCK 8 33 26 0.1µF OVRTMP 3 9 30 2 7 + LT1468 – 6 4 25 0.1µF 0.1µF –15V SDI CS1 CS2 SCK SDO 2 15 VDD OVDD 1 VDDLBYP SDO SCK RDL/SDI LTC2328-18 BUSY CNV IN– 5 REFBUF REFIN GND CHAIN 7 8 3, 16 4 47µF TO MICROCONTROLLER 10µF 0.1µF 27 10 11, 29 1µF 0.1µF CS/LD REFLO 14 LDAC REF 13 OUT1 VOUT2 21 22 V MSP2 REFCOMP 16 VOUT0 3 4 V MSP1 PAD 24 7 V– 17 28 GND 1 12 MSP0 REFLO 32 IOVCC 18 31 0.1µF V+ 1µF 15V IN+ 0.1µF 14 13 12 11 9 10 0.1µF 0.1µF –15V 2664 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC2666 8-Channel Serial 16-/12-Bit VOUT SoftSpan DACs with ±10ppm/°C Reference Software Programmable Output Ranges Up to ±10V, 5mm × 5mm QFN Package LTC2668 16-Channel Serial 16-/12-Bit VOUT SoftSpan DACs with ±10ppm/°C Reference Software Programmable Output Ranges Up to ±10V, 6mm × 6mm QFN Package LTC2704 Quad Serial 16-/14-/12-Bit VOUT SoftSpan DACs with ±2LSB Software Programmable Output Ranges Up to ±10V, SPI Interface, INL, ±1LSB DNL No External Amps Needed LTC2754 Quad Serial 16-/12-Bit IOUT SoftSpan DACs with ±1LSB INL, Software Programmable Output Ranges Up to ±10V, SPI Interface, ±1LSB DNL 7mm × 8mm QFN Package LTC2654 Quad Serial 16-/12- Bit VOUT DACs with Internal Reference ±10ppm/°C Internal Reference, 4mm × 4mm QFN and 16-Lead Narrow SSOP Packages LTC2634 Quad 12-/10-/8-Bit SPI VOUT DACs with Internal Reference ±10ppm/°C Internal Reference, 3mm × 3mm QFN and 10-Lead MSOP Packages Low Drift Precision Buffered Reference 0.025% Max Tolerance, 2ppm/°C Max, 0.25ppmP-P 0.1Hz to 10Hz Noise References LTC6655A 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2664 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2664 2664fa LT 0616 REV A • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2015