LTC2919 Precision Triple/Dual Input UV, OV and Negative Voltage Monitor U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Two Low Voltage Adjustable Inputs (0.5V) Accurate UVLO Provides a Third Monitor Input Open-Drain RST, OUT1 and OUT2 Outputs Pin Selectable Input Polarity Allows Negative, UV and OV Monitoring Guaranteed Threshold Accuracy: ±1.5% 6.5V Shunt Regulator for High Voltage Operation Low 50μA Quiescent Current Buffered 1V Reference for Negative Supply Offset Input Glitch Rejection Adjustable Reset Timeout Period Selectable Internal Timeout Saves Components Outputs Guaranteed Low With VCC = 0.5V Space Saving 10-Lead 3mm × 2mm DFN and MSOP Packages U APPLICATIO S ■ ■ ■ ■ Desktop and Notebook Computers Network Servers Core, I/O Monitor Automotive The LTC®2919 is a triple/dual input monitor intended for a variety of system monitoring applications. Polarity selection and a buffered reference output allow the LTC2919 to monitor positive and negative supplies for undervoltage (UV) and overvoltage (OV) conditions. The two adjustable inputs have a nominal 0.5V threshold, featuring tight 1.5% threshold accuracy over the entire operating temperature range. Glitch filtering ensures outputs operate reliably without false triggering. An accurate threshold at the VCC pin provides a third input supply monitor for a 2.5V, 3.3V or 5V supply. Two independent output pins indicate the status of each adjustable input. A third common output provides a configurable reset timeout that may be set by an accurate internal 200ms timer, programmed with an external capacitor, or disabled for a fast response. A three-state input pin sets the input polarity of each adjustable input without requiring any external components. The LTC2919 provides a highly versatile, precise, spaceconscious, micropower solution for supply monitoring. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6949965, 7292076. U TYPICAL APPLICATIO 3.3V UV/OV (Window) Monitor Application with 200ms Internal Timeout (3.3V Logic Out) SEL Pin Connection for Input Polarity Combinations 3.3V 10k LTC2919–2.5 10.7k ADJ1 OUT1 REF OUT2 76.8k SEL ADJ1 ADJ2 SEL PIN + + VCC + – OPEN – – GND 10k UV RST ADJ2 POLARITY 0.1μF VCC 453k TMR GND 10k OV FAULT 2919 TA01a 2919f 1 LTC2919 W W U W ABSOLUTE AXI U RATI GS (Notes 1, 2) Terminal Voltages VCC (Note 3)............................................. –0.3V to 6V OUT1, OUT2, RST ................................. –0.3V to 7.5V ADJ1, ADJ2 .......................................... –0.3V to 7.5V TMR, SEL..................................–0.3V to (VCC + 0.3V) Terminal Currents ICC (Note 3)......................................................±10mA IREF ....................................................................±1mA Operating Temperature Range LTC2919C ................................................ 0°C to 70°C LTC2919I..............................................– 40°C to 85°C LTC2919H .......................................... –40°C to 125°C Maximum Junction Temperature........................... 150°C Storage Temperature Range...................– 65°C to 150°C Lead Temperature (Soldering, 10 sec) MSOP-10 .......................................................... 300°C PIN CONFIGURATION TOP VIEW SEL 1 10 ADJ1 VCC 2 9 ADJ2 8 TMR OUT2 4 7 REF RST 5 6 GND OUT1 3 11 DDB PACKAGE 10-LEAD (3mm × 2mm) PLASTIC DFN TJMAX = 150°C, θJA = 76°C/W EXPOSED PAD (PIN 11) MAY BE LEFT OPEN OR TIED TO GND TOP VIEW SEL VCC OUT1 OUT2 RST 1 2 3 4 5 10 9 8 7 6 ADJ1 ADJ2 TMR REF GND MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 120°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2919CDDB-2.5#PBF LTC2919CDDB-2.5#TRPBF LDGT 10-Lead (3mm × 2mm) Plastic DFN 0°C to 70°C LTC2919IDDB-2.5#PBF LTC2919IDDB-2.5#TRPBF LDGT 10-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C LTC2919HDDB-2.5#PBF LTC2919HDDB-2.5#TRPBF LDGT 10-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C LTC2919CDDB-3.3#PBF LTC2919CDDB-3.3#TRPBF LDMW 10-Lead (3mm × 2mm) Plastic DFN 0°C to 70°C LTC2919IDDB-3.3#PBF LTC2919IDDB-3.3#TRPBF LDMW 10-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C LTC2919HDDB-3.3#PBF LTC2919HDDB-3.3#TRPBF LDMW 10-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C LTC2919CDDB-5#PBF LTC2919CDDB-5#TRPBF LDMX 10-Lead (3mm × 2mm) Plastic DFN 0°C to 70°C LTC2919IDDB-5#PBF LTC2919IDDB-5#TRPBF LDMX 10-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C LTC2919HDDB-5#PBF LTC2919HDDB-5#TRPBF LDMX 10-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C LTC2919CMS-2.5#PBF LTC2919CMS-2.5#TRPBF LTDGS 10-Lead Plastic MSOP 0°C to 70°C LTC2919IMS-2.5#PBF LTC2919IMS-2.5#TRPBF LTDGS 10-Lead Plastic MSOP –40°C to 85°C LTC2919HMS-2.5#PBF LTC2919HMS-2.5#TRPBF LTDGS 10-Lead Plastic MSOP –40°C to 125°C LTC2919CMS-3.3#PBF LTC2919CMS-3.3#TRPBF LTDMT 10-Lead Plastic MSOP 0°C to 70°C LTC2919IMS-3.3#PBF LTC2919IMS-3.3#TRPBF LTDMT 10-Lead Plastic MSOP –40°C to 85°C LTC2919HMS-3.3#PBF LTC2919HMS-3.3#TRPBF LTDMT 10-Lead Plastic MSOP –40°C to 125°C LTC2919CMS-5#PBF LTC2919CMS-5#TRPBF LTDMV 10-Lead Plastic MSOP 0°C to 70°C LTC2919IMS-5#PBF LTC2919IMS-5#TRPBF LTDMV 10-Lead Plastic MSOP –40°C to 85°C LTC2919HMS-5#PBF LTC2919HMS-5#TRPBF LTDMV 10-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2919f 2 LTC2919 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V (LTC2919-2.5), VCC = 3.3V (LTC2919-3.3), VCC = 5V (LTC2919-5), ADJ1 = ADJ2 = 0.55V, SEL = floating, unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS VCC(MIN) Operating Supply Voltage RST, OUT1, OUT2 in Correct State ● MIN 0.5 VCC(SHUNT) VCC Shunt Regulation Voltage ICC = 1mA, IREF = 0 ● 6.0 ICC VCC Input Current 2.175V < VCC < 6V (C-Grade, I-Grade) 2.175V < VCC < 6V (H-Grade) ● ● VRT ADJ Input Threshold UNITS V 7.1 V 50 50 220 280 μA μA 495.0 492.5 500 500 505.0 507.5 mV mV 1.5 3.5 10.0 mV 0 0 ±15 ±40 nA nA 2.175 2.871 4.350 2.213 2.921 4.425 2.250 2.970 4.500 V V V 0.3 0.7 2.0 % ● 0.990 0.985 1.000 1.000 1.010 1.015 V V VTMR = 1V ● –1.5 –2.2 –2.9 μA ΔVRT ADJ Hysteresis (Note 4) TMR = VCC IADJ ADJ Input Current VADJ = 0.55V (C-Grade, I-Grade) VADJ = 0.55V (H-Grade) ● ● VCC(UVLO) VCC –10% UVLO Threshold LTC2919-2.5 LTC2919-3.3 LTC2919-5 ● ● ● ΔVCC(UVLO) UVLO Hysteresis (Note 4) TMR = VCC VREF Buffered Reference Voltage VCC > 2.175V, IREF = ±1mA TMR Pull-Up Current MAX 6.5 ● ITMR(UP) TYP ITMR(DOWN) TMR Pull-Down Current VTMR = 1V ● 1.5 2.2 2.9 μA tRST(EXT) Reset Timeout Period, External CTMR = 2.2nF ● 15 20 27 ms tRST(INT) Reset Timeout Period, Internal VTMR = 0V ● 140 200 280 ms VTMR(DIS) Timer Disable Voltage VTMR Rising ● VCC – 0.40 VCC – 0.20 VCC – 0.10 ΔVTMR(DIS) Timer Disable Hysteresis VTMR Falling ● 40 100 160 mV VTMR(INT) Timer Internal Mode Voltage VTMR Falling ● 0.10 0.20 0.40 V ΔVTMR(INT) Timer Internal Mode Hysteresis VTMR Rising ● 40 100 160 mV tPROP ADJx Comparator Propagation Delay to OUTX ADJx Driven Beyond Threshold (VRTX) by 5mV ● 50 150 800 μs tUV VCC Undervoltage Detect to RST VCC Less Than UVLO Threshold (VCC(UVLO)) by 1% ● 50 150 800 μs VOL Output Voltage Low VCC = 0.5V, I = 5μA VCC = 1V, I = 100μA VCC = 3V, I = 2500μA ● ● ● 0 0 0 0.01 0.01 0.10 0.15 0.15 0.30 V V V IOH Output Voltage High Leakage Output = VCC (C-Grade, I-Grade) Output = VCC (H-Grade) ● ● 0 0 ±1 ±5 μA μA 0.4 V VCC V 1.0 V V Three-State Input SEL VIL Low Level Input Voltage VIH High Level Input Voltage VZ Pin Voltage when Left in Open State ISEL = 0μA ● 0 ● 1.4 0.8 0.9 2919f 3 LTC2919 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V (LTC2919-2.5), VCC = 3.3V (LTC2919-3.3), VCC = 5V (LTC2919-5), ADJ1 = ADJ2 = 0.55V, SEL = floating, unless otherwise noted. (Note 2) SYMBOL PARAMETER ISEL(Z) Allowable Leakage When Open CONDITIONS ISEL SEL Input Current MIN TYP ● ● SEL = VCC or SEL = GND Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to GND unless otherwise noted. Note 3: VCC maximum pin voltage is limited by input current. Since the VCC pin has an internal 6.5V shunt regulator, a low impedance supply ±17 MAX UNITS ±5 μA ±25 μA which exceeds 6V may exceed the rated terminal current. Operation from higher voltage supplies requires a series dropping resistor. See Applications Information. Note 4: Threshold voltages have no hysteresis unless the part is in comparator mode. Hysteresis is one-sided, affecting only invalid-to-valid transitions. See Applications Information. U W 506 504 502 500 498 496 494 492 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1.5 1.015 1.0 0.5 0 –0.5 VCC = 2.5V TA = 150°C 0.4 0.2 TA = 25°C 0.0 TA = 125°C –0.2 TA = –40°C –0.4 –0.6 –1 –0.5 0 0.5 LOAD CURRENT (mA) 1 2919 G04 1.005 1.000 0.995 –1.0 0.990 –1.5 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 0.985 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2919 G02 REF VOLTAGE VARIATION (% OF 2.5V SUPPLY AND 25°C VALUE) REF VOLTAGE, VARIATION (%OF NO LOAD AND 25°C VALUE) 0.6 IREF = 0A 1.010 2919 G01 REF Output Load Regulation REF Output Voltage vs Temperature REF VOLTAGE, VREF (V) THRESHOLD VOLTAGE, VRT (mV) 508 VCC UVLO Threshold Variation vs Temperature 2919 G03 Quiescent Supply Current vs Temperature REF Output Line Regulation 0.6 90 IREF = 0A QUIESCENT SUPPLY CURRENT, ICC (μA) ADJ Threshold Voltage vs Temperature THRESHOLD VOLTAGE VARIATION (% OF 25°C VALUE) TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted. TA = 150°C 0.4 0.2 TA = 25°C 0.0 TA = 125°C –0.2 TA = –40°C –0.4 –0.6 2 3 4 5 SUPPLY VOLTAGE (V) 6 2919 G05 80 ADJ1 = 0.55V ADJ2 = 0.45V SEL = OPEN 70 60 VCC = 5V VCC = 3.3V 50 VCC = 2.5V 40 30 20 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2919 G06 2919f 4 LTC2919 U W TYPICAL PERFOR A CE CHARACTERISTICS Reset Timeout Period vs Capacitance Propagation Delay vs Overdrive 700 260 400 300 200 RESET TIMEOUT PERIOD, tRST (ms) RESET TIMEOUT PERIOD, tRST (ms) 1000 0 0.1 1 10 100 GLITCH PERCENTAGE PAST THRESHOLD (%) 100 10 1 0.1 1 10 100 TMR PIN CAPACITANCE, CTMR (nF) Shunt Regulation Voltage vs Temperature ICC = 10mA 6.6 ICC = 1mA 6.4 ICC = 100μA 6.2 25 50 75 100 125 150 TEMPERATURE (°C) 7.6 6.8 6.4 WITH 10k PULL-UP 0.1 WITH 100k PULL-UP 0.2 0.3 0.4 0.5 0.6 SUPPLY VOLTAGE, VCC (V) 0.7 0.8 2919 G13 2 LTC2919-2.5 LTC2919-5 LTC2919-3.3 6.0 0.01 0 0.1 1 10 SUPPLY CURRENT, ICC (mA) 100 0 1 3 4 2 SUPPLY VOLTAGE, VCC (V) 2919 G12 1 ADJ1 = 0.45V ADJ2 = 0.55V 5 SEL = OPEN 4 OUTPUT AT 150mV 3 2 1 OUTPUT AT 50mV 0 1 5 OUT1, OUT2, RST Pull-Down Current vs VCC 0 0 3 OUT1, OUT2, RST Pull-Down Current vs VCC OUTPUT PULL-DOWN CURRENT (mA) 0.2 ADJ1 = 0.55V ADJ2 = 0.45V 4 SEL = OPEN 10k PULL-UP R TO VCC 1 6 VCC 25 50 75 100 125 150 TEMPERATURE (°C) 2919 G11 0.4 0.3 0 5 7.2 OUT1, OUT2, RST Output Voltage vs VCC 0.1 160 OUT1, OUT2, RST Output Voltage vs VCC TA = 25°C 2919 G10 0 EXTERNAL, CTMR = 22nF 180 2919 G09 OUTPUT VOLTAGE (V) SHUNT REGULATION VOLTAGE, VCC(SHUNT) (V) 6.8 0 200 Shunt Regulation Voltage vs Supply Current 7.0 INTERNAL 220 2919 G08 2919 G07 6.0 –50 –25 240 140 –50 –25 1000 OUTPUT PULL-DOWN CURRENT (mA) PROPAGATION DELAY (μs) 500 100 SHUNT REGULATOR VOLTAGE, VCC(SHUNT) (V) Reset Timeout Period vs Temperature 10000 600 OUTPUT VOLTAGE (V) TA = 25°C unless otherwise noted. 2 3 4 SUPPLY VOLTAGE, VCC (V) 5 2919 G14 OUTPUT AT 150mV 0.1 OUTPUT AT 50mV 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 SUPPLY VOLTAGE, VCC (V) 1 2919 G15 2919f 5 LTC2919 U W TYPICAL PERFOR A CE CHARACTERISTICS OUT1, OUT2, RST VOL vs Output Sink Current ISEL vs Temperature –10 1.0 VCC = 3V NO PULL-UP R SEL = GND –12 20 TA = 25°C –14 18 TA = 125°C 0.4 TA = –40°C 0.2 0 5 15 20 25 10 OUTPUT SINK CURRENT (mA) 30 ISEL (μA) 0.6 0 ISEL vs Temperature 22 SEL = VCC TA = 150°C ISEL (μA) OUTPUT, VOL (V) 0.8 TA = 25°C unless otherwise noted. –16 16 –18 14 –20 12 –22 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2919 G16 10 –50 –25 2919 G17 0 25 50 75 100 125 150 TEMPERATURE (°C) 2919 G18 U U U PI FU CTIO S (MSOP/DFN Package) SEL (Pin 1): Input Polarity Select Three-State Input. Connect to VCC, GND or leave unconnected in open state to select one of three possible input polarity combinations (refer to Table 1). VCC (Pin 2): Power Supply. Bypass this pin to ground with a 0.1μF (or greater) capacitor. Operates as a direct supply input for voltages up to 6V. Operates as a shunt regulator for supply voltages greater than 6V and should have a resistor between this pin and the supply to limit VCC input current to no greater than 10mA. When used without a current-limiting resistor, pin voltage must not exceed 6V. UVLO options allow VCC to be used as an accurate third fixed -10% UV supply monitor. Requires an external pull-up resistor and may be pulled above VCC. GND (Pin 6): Device Ground. REF (Pin 7): Buffered Reference Output. 1V nominal reference used for the offset of negative-monitoring applications. The buffered reference can source and sink up to 1mA. The reference can drive a capacitive load of up to 1000pF. Larger capacitance may degrade transient performance. This pin does not require a bypass capacitor, nor is one recommended. Leave open if unused. OUT2 (Pin 4): Open-Drain Logic Output 2. Asserts low when positive polarity ADJ2 voltage is below threshold or negative polarity ADJ2 voltage is above threshold. Requires an external pull-up resistor and may be pulled above VCC. TMR (Pin 8): Reset Timeout Control. Attach an external capacitor (CTMR) to GND to set a reset timeout period of 9ms/nF. A low leakage ceramic capacitor is recommended for timer accuracy. Capacitors larger than 1μF (9 second timeout) are not recommended. See Applications Information for further details. Leaving this pin open generates a minimum timeout of approximately 400μs. A 2.2nF capacitor will generate a 20ms timeout. Tying this pin to ground will enable the internal 200ms timeout. Tying this pin to VCC will disable the reset timer and put the part in comparator mode. Signals from the comparator outputs will then go directly to RST. RST (Pin 5): Open-Drain Inverted Reset Logic Output. Asserts low when any positive polarity input voltage is below threshold or any negative polarity input voltage is above threshold or VCC is below UVLO threshold. Held low for a timeout period after all voltage inputs are valid. ADJ2 (Pin 9): Adjustable Voltage Input 2. Input to voltage monitor comparator 2 (0.5V nominal threshold). The polarity of the input is selected by the state of the SEL pin (refer to Table 1). Tie to GND if unused (with SEL = GND or Open). OUT1 (Pin 3): Open-Drain Logic Output 1. Asserts low when positive polarity ADJ1 voltage is below threshold or negative polarity ADJ1 voltage is above threshold. Requires an external pull-up resistor and may be pulled above VCC. 2919f 6 LTC2919 U U U PI FU CTIO S (MSOP/DFN Package) Exposed Pad (Pin 11, DFN Only): The Exposed Pad may be left unconnected. For better thermal contact, tie to a PCB trace. This trace must be grounded or unconnected. ADJ1 (Pin 10): Adjustable Voltage Input 1. Input to voltage monitor comparator 1 (0.5V nominal threshold). The polarity of the input is selected by the state of the SEL pin (refer to Table 1). Tie to REF if unused (with SEL = VCC or Open). W BLOCK DIAGRA SEL VCC VCC THREE-STATE DECODE CONTROL 2 ADJ1 6.5V OUT1 CONTROL 1 + TMR – VCC THREE-STATE DECODE ADJUSTABLE PULSE GENERATOR + RST EN – ADJ2 GND 200ms PULSE GENERATOR OUT2 + – + – SEL GND OPEN VCC 500mV + REF + – 1.000V – CONTROL 1 H L L CONTROL 2 H H L CONTROL = H = NEGATIVE POLARITY CONTROL = L = POSITIVE POLARITY 2919 BD WU W TI I G DIAGRA S Positive Polarity Input Timing VRT + ΔVRT VRT VADJ tPROP tPROP tPROP 1V OUT Negative Polarity Input Timing VRT VADJ VRT – ΔVRT tPROP tPROP tPROP 1V OUT VCC(UVLO) + ΔVCC(UVLO) VCC VCC(UVLO) tUV tPROP OUT tRST 1V RST NOTES: 1. ΔVRT AND ΔVCC(UVLO) = 0, except in Comparator Mode 2. IN COMPARATOR MODE, tRST = tPROP. tRST 1V RST UVLO Timing tRST 1V RST tPROP 1V 2919 TD 2919f 7 LTC2919 U W U U APPLICATIO S I FOR ATIO The LTC2919 is a low power, high accuracy triple/dual supply monitor with two adjustable inputs and an accurate UVLO that can monitor a third supply. Reset timeout may be selected with an external capacitor, set to an internally generated 200ms, or disabled entirely. The three-state polarity select pin (SEL) chooses one of three possible polarity combinations for the adjustable input thresholds, as described in Table 1. An individual output is released when its corresponding ADJ input is valid (above threshold if configured for positive polarity, below threshold if configured for negative polarity). Both input voltages (VADJ1 and VADJ2) must be valid and VCC above the UVLO threshold for longer than the reset timeout period before RST is released. The LTC2919 asserts the reset output during power-up, power-down and brownout conditions on any of the voltage inputs. Power-Up The LTC2919 uses proprietary low voltage drive circuitry for the RST, OUT1 and OUT2 pins which holds them low with VCC as low as 200mV. This helps prevent indeterminate voltages from appearing on the outputs during power-up. In applications where the low voltage pull-down capability is important, the supply to which the external pull-up resistor connects should be the same supply which powers the part. Using the same supply for both ensures that RST, OUT1 and OUT2 never float above 200mV during power-up, as the pull-down ability of the pin will then increase as the required pull-down current to maintain a logic low increases. Once VCC passes the UVLO threshold, polarity selection and timer initialization will occur. If the monitored ADJ input is valid, the corresponding OUT will be released. When both ADJ1 and ADJ2 are valid, the appropriate timeout delay will begin, after which RST will be released. Power-Down On power-down, once VCC drops below the UVLO threshold or either VADJ becomes invalid, RST asserts logic low. VCC of at least 0.5V guarantees a logic low of 0.15V at RST. Shunt Regulator The LTC2919 contains an internal 6.5V shunt regulator on the VCC pin to allow operation from a high voltage supply. To operate the part from a supply higher than 6V, the VCC pin must have a current-limiting series resistor, RCC, to the supply. This resistor should be sized according to the following equation: VS(MAX) – 6.2V 10mA ≤ RCC ≤ VS(MIN) – 6.8V 200µA + IREF where VS(MIN) and VS(MAX) are the operating minimum and maximum of the supply, and IREF is the maximum current the user expects to draw from the reference output. As an example, consider operation from an automobile battery which might dip as low as 10V or spike to 60V. Assume that the user will be drawing 100μA from the reference. We must then pick a resistance between 5.4k and 10.7k. When the VCC pin is connected to a low impedance supply, it is important that the supply voltage never exceed 6V, or the shunt regulator may begin to draw large currents. Some supplies may have a nominal value sufficiently close to the shunt regulation voltage to prevent sizing of the resistor according to the above equation. For such supplies, a 470Ω series resistor may be used. Adjust Polarity Selection The external connection of the SEL pin selects the polarities of the LTC2919 adjustable inputs. SEL may be connected to GND, connected to VCC or left unconnected during normal operation. When left unconnected, the maximum leakage allowable from the pin is ±5μA. Table 1 shows the three possible selections of polarity based on SEL connection. Table 1. Voltage Threshold Selection ADJ1 INPUT ADJ2 INPUT SEL Positive Polarity (+) UV or (–) OV Positive Polarity (+) UV or (–) OV VCC Positive Polarity (+) UV or (–) OV Negative Polarity (–) UV or (+) OV Open Negative Polarity (–) UV or (+) OV Negative Polarity (–) UV or (+) OV Ground Note: Open = open circuit or driven by a three-state buffer in high impedance state with leakage current less than 5μA. 2919f 8 LTC2919 U U W U APPLICATIO S I FOR ATIO If the user’s application requires, the SEL pin may be driven using a three-state buffer which satisfies the VIL, VIH and leakage conditions of this three-state input pin. If the state of the SEL pin configures a given input as “negative polarity,” the voltage at that ADJ pin must be below the trip point (0.5V nominal), or the corresponding OUT and RST output will be pulled low. Conversely, if a given input is configured as “positive polarity”, the ADJ pin voltage must be above the trip point or the corresponding OUT and RST will assert low. Thus, a “negative polarity” input may be used to determine whether a monitored negative voltage is smaller in absolute value than it should be (–UV), or a monitored positive voltage is larger than it should be (+OV). The opposite is true for a “positive polarity” input (–OV or +UV). These polarity definitions are also shown in Table 1. For purposes of this data sheet, a negative voltage is considered “undervoltage” if it is closer to ground than it should be (e.g., –4.3V for a –5V supply). Proper configuration of the SEL pin and setting of the trip-points via external resistors allows for any two fault conditions to be detected. For example, the LTC2919 may monitor two supplies (positive, negative or one of each) for UV or for OV (or one UV and one OV). It may also monitor a single supply (positive or negative) for both UV and OV. Tables 2a and 2b show example configurations for monitoring possible combinations of fault condition and supply polarity. Table 2a. Possible Combinations of Supply Monitoring. For Example Purposes, All Supplies are Monitored at 5% Tolerance and Connections are Shown Only for ADJ1, ADJ2, REF, SEL, OUT1 and OUT2. Output Pull-up Resistors are Omitted for Clarity. SEL = GND SEL = VCC 15V RP2A 309k RP1A 11.5k 5V –15V RN2A 309k RP2B 115k ADJ1 OUT1 UV (15V) ADJ2 OUT2 UV (5V) RP1B 13.7k RN1A 10.7k REF –15V RN1A 30.9k 15V RP1 11.5k –5V 15V RP2A 619k ADJ1 OUT1 OV (–15V) ADJ2 OUT2 OV (–5V) RN1B 11.8k RP1A 20k UV (–5V) SEL 5V RP2B 133k ADJ1 OUT1 OV (15V) ADJ2 OUT2 0V (5V) RP1B 13.7k SEL REF SEL 2 Positive OV –15V 15V RP2 619k RN2 1.02M ADJ1 OUT1 UV (15V) ADJ2 OUT2 OV (–15V) RN1 30.9k RP1 20k REF ADJ2 OUT2 2 Negative UV 2 Negative OV RP2 309k UV (–15V) REF SEL RN2B 137k REF ADJ1 OUT1 RN1B 13.3k 2 Positive UV RN2A 1.02M –5V RN2B 137k SEL 1 Positive UV, 1 Negative OV –15V RN2 309k ADJ1 OUT1 OV (15V) ADJ2 OUT2 UV (–15V) RN1 10.7k REF SEL 1 Positive OV, 1 Negative UV 2919f 9 LTC2919 U U W U APPLICATIO S I FOR ATIO Table 2b. Possible Combinations of Supply Monitoring. For Example Purposes, All Supplies are Monitored at 5% Tolerance and Connections are Shown Only for ADJ1, ADJ2, REF, SEL, OUT1 and OUT2. Output Pull-up Resistors are Omitted for Clarity. SEL OPEN 15V –15V RP6 2.37M RN6 1.02M RP5 10.7k ADJ1 OUT1 UV ADJ2 OUT2 OV RN5 4.02k RP4 76.8k SEL –15V –15V RN2 1.02M ADJ1 OUT1 UV (15V) ADJ2 OUT2 UV (–15V) RN1 10.7k RN1 30.9k REF 15V RP1A 11.5k 15V ADJ1 OUT1 OV (–15V) ADJ2 OUT2 OV (15V) RP1 20k REF SEL 1 Negative OV, 1 Positive OV 5V –15V RP2B 133k ADJ1 OUT1 UV (15V) ADJ2 OUT2 OV (5V) RP1B 13.7k REF SEL RP2 619k SEL 1 Positive UV, 1 Negative UV RP2A 309k UV 1 Negative UV and OV RN2 309k RP1 11.5k ADJ2 OUT2 REF 1 Positive UV and OV 15V OV RN4 30.9k REF RP2 309k ADJ1 OUT1 SEL 1 Positive UV, 1 Positive OV Adjust Input Trip Point The trip threshold for the supplies monitored by the adjustable inputs is set with an external resistor divider, allowing the user complete control over the trip point. Selection of this trip voltage is crucial to the monitoring of the system. Any power supply has some tolerance band within which it is expected to operate (e.g., 5V ±10%). It is generally undesirable that a supervisor issue a reset when the power supply is inside this tolerance band. Such a “nuisance” reset reduces reliability by preventing the system from functioning under normal conditions. RN2A 1.02M RN1A 30.9k –5V RN2B 137k ADJ1 OUT1 OV (–15V) ADJ2 OUT2 UV (–5V) RN1B 13.3k REF SEL 1 Negative UV, 1 Negative OV To prevent nuisance resets, the supervisor threshold must be guaranteed to lie outside the power supply tolerance band. To ensure that the threshold lies outside the power supply tolerance range, the nominal threshold must lie outside that range by the monitor’s accuracy specification. All three of the LTC2919 inputs (ADJ1, ADJ2, VCC UVLO) have the same maximum threshold accuracy of ±1.5% of the programmed nominal input voltage (over the full operating temperature range). Therefore, using the LTC2919, the typical 10% UV threshold is at 11.5% below the nominal input voltage level. For a 5V input, the threshold is nominally 4.425V. With ±1.5% accuracy, the trip threshold range is 2919f 10 LTC2919 U W U U APPLICATIO S I FOR ATIO 4.425V ±75mV over temperature (i.e., 10% to 13% below 5V). The monitored system must thus operate reliably down to 4.35V or 13% below 5V over temperature. The above discussion is concerned only with the DC value of the monitored supply. Real supplies also have relatively high frequency variations from sources such as load transients, noise and pickup. The LTC2919 uses two techniques to combat spurious outputs toggling from high frequency variation. First, the timeout period helps prevent high frequency variation whose frequency is above 1/ tRST from appearing at the RST output. Second, the propagation delay versus overdrive function filters short glitches before the OUT1, OUT2 toggling or RST pulling low. it may be added externally. See 48V Telecom UV/OV with Hysteresis Applications on page 14 for an example. Selecting External Resistors In a typical positive supply monitoring application, the ADJx pin connects to a tap point on an external resistive divider between a positive voltage being monitored and ground, as shown in Figure 1. When monitoring a negative supply, the ADJx pin connects to a tap point on a resistive divider between the negative voltage being monitored and the buffered reference (REF), as shown in Figure 2. VMON When an ADJ becomes invalid, the corresponding OUT and RST pin assert low. When the supply recovers past the valid threshold, the reset timer starts (assuming it is not disabled) and RST does not go high until it finishes. If the supply becomes invalid any time during the timeout period, the timer resets and starts fresh when the supply next becomes valid. RP2 + RP1 – 0.5V + – 2919 F01 To reduce sensitivity of short glitches from toggling the output pins, the comparator outputs go through a lowpass filter before triggering the output logic. Any transient at the input of a comparator needs to be of sufficient magnitude and duration to pass the filter before it can change the monitor state. Figure 1. Setting Positive Supply Trip Point REF RN1 The combination of the reset timeout and comparator filtering prevents spurious changes in the output state without sacrificing threshold accuracy. If further supply glitch immunity is needed, the user may place an external capacitor from the ADJ input to ground. The resultant RC lowpass filter with the resistor divider will further reject high frequency components of the supply, at the cost of slowing the monitor’s response to fault conditions. A common solution to the problem of spurious reset is to introduce hysteresis around the nominal threshold. However, this hysteresis degrades the effective accuracy of the monitor and increases the range over which the system must operate. The LTC2919 therefore does not have hysteresis, except in comparator mode (by tying TMR pin to VCC). If hysteresis is desired in other modes, ADJx ADJx + RN2 – VMON 0.5V + – 2919 F02 Figure 2. Setting Negative Supply Trip Point Normally the user will select a desired trip voltage based on their supply and acceptable tolerances, and a value of RN1 or RP1 based on current draw. Current used by the resistive divider will be approximately: I= 0.5V 0.5V .OR = RP1 RN1 2919f 11 LTC2919 U W U U APPLICATIO S I FOR ATIO To minimize errors arising from ADJ input bias and to minimize loading on REF choose resistor RP1 (for positive supply monitoring) or RN1 (for negative supply monitoring) in the range of 5k to 100k. For a positive-monitoring application, RP2 is then chosen by: REF ADJ1 + RN4 RN5 – ADJ2 + RN6 RP2 = RP1(2VTRIP – 1) – –VMON For a negative-monitoring application: 0.5V The LTC2919 can also be used to monitor a single supply for both UV and OV. This may be accomplished with three resistors, instead of the four required for two independent supplies. Configurations are shown in Figures 3 and 4. RP4 or RN4 may be chosen as is RP1 or RN1 above. For a given RP4, monitoring a positive supply: VOV – VUV VUV VOV VUV For monitoring a negative supply with a given RN4: RN5 = RN4 OUT2 UV Figure 4. Setting UV and OV Trip Point for a Negative Supply For example, consider monitoring a –5V supply at ±10%. For this supply application: VOV = –5.575V and VUV = –4.425V. Suppose we wish to consume about 5μA in the divider, so RN4 = 100k. We then find RN5 = 21.0k, RN6 = 1.18M (nearest 1% standard values have been chosen). VCC Monitoring/UVLO The LTC2919 contains an accurate third -10% undervoltage monitor on the VCC pin. This monitor is fixed at a nominal 11.5% below the VCC specified in the part number. The standard part (LTC2919-2.5) is configured to monitor a 2.5V supply (UVLO threshold of 2.213V), but versions to monitor 3.3V and 5.0V (UVLO of 2.921V and 4.425V, respectively) are available. For applications that do not need VCC monitoring, the 2.5V version should be used, and the UVLO will simply guarantee that the VCC is above the minimum required for proper threshold and timer accuracy before the timeout begins. VUV – VOV 1– VUV RN6 = RN4 (1– 2VUV ) OV 2919 F04 Note that the value VTRIP should be negative for a negative application. RP6 = RP4 ( 2VUV – 1) LOGIC & OPEN DRAIN MOSFET OUT1 + – RN2 = RN1(1 – 2VTRIP) RP5 = RP4 LOGIC & OPEN DRAIN MOSFET 1– VOV 1– VUV Setting the Reset Timeout ADJ1 + VMON RP6 RP5 – ADJ2 + RP4 – 0.5V LOGIC & OPEN DRAIN MOSFET LOGIC & OPEN DRAIN MOSFET OUT1 UV OUT2 OV + – 2919 F03 RST goes high after a reset timeout period set by the TMR pin when the VCC and ADJ inputs are valid. This reset timeout may be configured in one of three ways: internal 200ms, programmed by external capacitor and no timeout (comparator mode). In externally-controlled mode, the TMR pin is connected by a capacitor to ground. The value of that capacitor allows for selection of a timeout ranging from about 400μs to 9 seconds. See the following section for details. Figure 3. Setting UV and OV Trip Point for a Positive Supply 2919f 12 LTC2919 U W U U APPLICATIO S I FOR ATIO If the user wishes to avoid having an external capacitor, the TMR pin should be tied to ground, switching the part to an internal 200ms timer. If the user requires a shorter timeout than 400μs, or wishes to perform application-specific processing of the reset output, the part may be put in comparator mode by tying the TMR pin to VCC. In comparator mode, the timer is bypassed and comparator outputs go straight to the reset output. The current required to hold TMR at ground or VCC is about 2.2μA. To force the pin from the floating state to ground or VCC may require as much as 100μA during the transition. When the part is in comparator mode, one of the two means of preventing false reset has been removed, so a small amount of one-sided hysteresis is added to the inputs to prevent oscillation as the monitored voltage passes through the threshold. This hysteresis is such that the valid-to-invalid transition threshold is unchanged, but the invalid-to-valid threshold is moved by about 0.7%. Thus, when the ADJ input polarity is positive, the threshold voltage is 500mV nominal when the input is above 500mV. As soon as the input drops below 500mV, the threshold moves up to 503.5mV nominal. Conversely, when configured as a negative-polarity input, the threshold is 500mV when the input is below 500mV, and switches to 496.5mV when the input goes above 500mV. The comparator mode feature is enabled by directly shorting the TMR pin to the VCC pin. Connecting the pin to any other voltage may have unpredictable results. Selecting the Reset Timing Capacitor Maximum length of the reset timeout is limited by the ability of the part to charge a large capacitor on start-up. Initially, with a large (discharged) capacitor on the TMR pin, the part will assume it is in internal timer mode (since the pin voltage will be at ground). If the 2.2μA flowing out of the TMR pin does not charge the capacitor to the ground-sense threshold within the first 200ms after supplies become good, the internal timer cycle will complete and RST will go high too soon. This imposes a practical limit of 1μF (9 second timeout) if the length of timeout during power-up needs to be longer than 200ms. If the power-up timeout is not important, larger capacitors may be used, subject to the limitation that the capacitor leakage current must not exceed 500nA, or the function of the timer will be impaired. Output Pins Characteristics The DC characteristics of the OUT1, OUT2 and RST pulldown strength are shown in the Typical Performance Characteristics section. OUT1, OUT2 and RST are opendrain pins and thus require external pull-up resistors to the logic supply. They may be pulled above VCC, providing the absolute maximum rating of the pin are observed. As noted in the discussion of power up and power down, the circuits that drive OUT1, OUT2 and RST are powered by VCC. During a fault condition, VCC of at least 0.5V guarantees a VOL of 0.15V. The open-drain nature of the RST pin allows for wired-OR connection of several LTC2919s to monitor more than two supplies (see Typical Applications). Other logic with opendrain outputs may also connect to the RST line, allowing other logic-determined conditions to issue a reset. Connecting a capacitor, CTMR, between the TMR pin and ground sets the reset timeout, tRST. The following formula approximates the value of capacitor needed for a particular timeout: CTMR = tRST • 110 [pF/ms] Leaving the TMR pin open with no external capacitor generates a reset timeout of approximately 400μs. 2919f 13 LTC2919 U TYPICAL APPLICATIO S Six Supply Undervoltage Monitor with 2.5V Reset Output and 20ms Timeout 15V 5V –5V –15V 3.3V 2.5V SYSTEM CBYP1 100nF RPU1 10k RPU5 10k RPU2 10k RN2A 137k RN1A 13.3k SYSTEM_OK SEL LTC2919-2.5 ADJ2 TMR OUT1 OUT2 GND ADJ1 RP1A 13.7k LTC2919-3.3 RST REF RP2A 115k VCC SEL RN1B 10.7k CTMR1 2.2nF RPU3 10k VCC ADJ1 RN2B 309k CBYP2 100nF RPU4 10k RST –5V_OK 5V_OK –15V_OK 15V_OK RP2B 309k REF RP1B 11.5k OUT1 ADJ2 2919 TA02 OUT2 TMR GND CTMR2 2.2nF 48V Telecom UV/OV Monitor with Hysteresis VIN 36V TO 72V SYSTEM RP2A 1.43M RP2A2 169k CBYP 100nF RCC 27k 0.25W RP2B 1.91M 5V M2 RPU3 10k VCC RST ADJ1 VUV(RISING): 43.3V VUV(FALLING): 38.7V LTC2919-2.5 VOV(RISING): 71.6V VOV(FALLING): 70.2V RP1A 18.7k RP1B 13.7k RP1B2 681k M1 ADJ2 OUT1 REF OUT2 SEL TMR RPU1 10k PWRGD RPU2 10k UV OV GND M1, M2: FDG6301N OR SIMILAR 2919 TA03 ±12V UV Monitor Powered from 12V, 20ms Timeout (1.8V Logic Out) CBYP 100nF RCC 10k 1.8V 12V 10k* MANUAL RESET PUSHBUTTON RP2 1.07M RN2 249k RST ADJ1 RP1 49.9k RN1 10.7k –12V RPU3 10k VCC RPU1 10k LTC2919-2.5 REF OUT1 ADJ2 OUT2 SEL TMR RPU2 10k 12V_OK –12V_OK CTMR 2.2nF GND *OPTIONAL FOR ESD 2919 TA01b 2919f 14 LTC2919 U PACKAGE DESCRIPTIO DDB Package 10-Lead Plastic DFN (3mm × 2mm) (Reference LTC DWG # 05-08-1722 Rev Ø) 0.64 ±0.05 (2 SIDES) 3.00 ±0.10 (2 SIDES) R = 0.05 TYP R = 0.115 TYP 6 0.40 ± 0.10 10 0.70 ±0.05 2.55 ±0.05 1.15 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 2.00 ±0.10 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6) 0.75 ±0.05 0.200 REF 0.50 BSC 2.39 ±0.05 (2 SIDES) 0.64 ± 0.05 (2 SIDES) 5 0.25 ± 0.05 1 (DDB10) DFN 0905 REV Ø 0.50 BSC 2.39 ±0.05 (2 SIDES) 0 – 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 R = 0.20 OR 0.25 × 45° CHAMFER BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev E) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 10 9 8 7 6 0.254 (.010) 0.889 ± 0.127 (.035 ± .005) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0.497 ± 0.076 (.0196 ± .003) REF 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.86 (.034) REF 1.10 (.043) MAX 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.18 (.007) SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.1016 ± 0.0508 (.004 ± .002) MSOP (MS) 0307 REV E NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 2919f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC2919 U TYPICAL APPLICATIO Powered from 12V, +5VOUT is Sequenced to Start-up First, Followed by –5VOUT, with ±5V UV Monitor, 200ms Timeout +12V RCC 4.7k CBYP 0.1μF DC/DC CONVERTER +5V VCC RP2 115k LTC2919-2.5 ADJ1 RP1 13.7k RN2 –5V 137k DC/DC CONVERTER +5V SEL REF OUT2 RPU2 10k PWRGD RN1 13.3k SHDN RST ADJ2 TMR OUT1 GND RPU3 10k SYS_RESET 2919 TA06 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1326/LTC1326-2.5 Micropower Precision Triple Supply Monitor for 5V/2.5V, 3.3V and ADJ 4.725V, 3.118V, 1V Threshold (±0.75%) LTC1536 Precision Triple Supply Monitor for PCI Applications Meets PCI tFAIL Timing Specifications LTC1540 Nanopower Comparator with Reference Adjustable Hysteresis LTC1726-2.5/LTC1726-5 Micropower Triple Supply Monitor for 2.5V/5V, 3.3V and ADJ Adjustable Reset and Watchdog Time-Outs LTC1727/LTC1728 Micropower Triple Supply Monitor with Open-Drain Reset Individual Monitor Outputs in MSOP/5-Lead SOT-23 LTC1985-1.8 Micropower Triple Supply Monitor with Push-Pull Reset Output 5-Lead SOT-23 Package LTC2900 Programmable Quad Supply Monitor Adjustable Reset, 10-Lead MSOP and 3mm × 3mm 10-Lead DFN Package LTC2901 Programmable Quad Supply Monitor Adjustable Reset and Watchdog Timer, 16-Lead SSOP Package LTC2902 Programmable Quad Supply Monitor Adjustable Reset and Tolerance, 16-Lead SSOP Package, Margining Functions LTC2903 Precision Quad Supply Monitor 6-Lead SOT-23 Package, Ultralow Voltage Reset LTC2904/LTC2905 3-State Programmable Precision Dual Supply Monitor Adjustable Tolerance and Reset Timer, 8-Lead SOT-23 Package LTC2906/LTC2907 Precision Dual Supply Monitor 1-Selectable and 1 Adjustable Separate VCC Pin, RST/RST Outputs/Adjustable Reset Timer LTC2908 Precision Six Supply Monitor (Four Fixed and 2 Adjustable) 8-Lead SOT-23 and DFN Packages LTC2909 Precision, Dual Input UV, OV and Negative Voltage Monitor 8-Lead SOT-23 and DFN Packages LTC2912-LTC2914 Single/Dual/Quad UV and OV Voltage Monitors Separate VCC Pin, Adjustable Reset Timer, H-Grade Temperature Range LTC2915-LTC2918 Single Voltage Monitor with 27 Unique Thresholds Manual Reset, Watchdog, TSOT-8/MSOP-10 and 3mm × 2mm DFN Package, H-Grade Temperature Range LT6700 Micropower, Low Voltage, Dual Comparator with 400mV Reference 6-Lead SOT-23 Package 2919f 16 Linear Technology Corporation LT 0208 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008