LINER LTC3864 60v low iq step-down dc/dc controller with 100% duty cycle capability Datasheet

LTC3864
60V Low IQ Step-Down
DC/DC Controller with
100% Duty Cycle Capability
Description
Features
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Wide Operating VIN Range: 3.5V to 60V
Wide VOUT Range: 0.8V to VIN
Low Operating IQ = 40µA
Very Low Dropout Operation: 100% Duty Cycle
Strong High Voltage MOSFET Gate Driver
Constant Frequency Current Mode Architecture
Verified FMEA for Adjacent Pin Open/Short
Selectable High Efficiency Burst Mode® Operation or
Pulse-Skipping Mode at Light Loads
Programmable Fixed Frequency: 50kHz to 850kHz
Phase-Lockable Frequency: 75kHz to 750kHz
Accurate Current Limit
Programmable Soft-Start or Voltage Tracking
Internal Soft-Start Guarantees Smooth Start-Up
Power Good Output Voltage Monitor
Low Shutdown IQ = 7µA
Available in Small 12-Pin Thermally Enhanced MSOP
and DFN Packages
The LTC®3864 is a robust, high voltage step-down DC/DC
controller optimized for automotive and industrial applications. It drives a P-channel power MOSFET switch allowing
100% duty cycle operation. The wide input and output voltage ranges cover a multitude of applications. This device
has been verified with the failure mode and effects analysis
(FMEA) procedure for operation during failure conditions.
The LTC3864 offers excellent light load efficiency, drawing only 40µA quiescent current in a user programmable
Burst Mode operation. Its peak current mode, constant
frequency PWM architecture provides for good control of
switching frequency and output current limit. The switching frequency can be programmed from 50kHz to 850kHz
with an external resistor and can be synchronized to an
external clock from 75kHz to 750kHz.
The LTC3864 offers programmable soft-start or output
tracking. Safety features include overvoltage protection,
overcurrent and short-circuit protection including frequency foldback and a power good output signal.
Applications
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The LTC3864 is available in thermally enhanced 12-Pin
MSOP and 3mm × 4mm DFN packages.
Industrial and Automotive Power Supplies
Telecom Power Supplies
Distributed Power Systems
L, LT, LTC, LTM, OPTI-LOOP, Linear Technology, Burst Mode and the Linear logo are registered
trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents including 5731694.
Typical Application
5.2V to 60V Input, 5V/2A Output, 350kHz Step-Down Converter
10µF
0.47µF
RUN
3.3nF
9.09k
90
VIN
25mΩ
PLLIN/MODE
SS
100
SENSE
LTC3864
GATE
ITH
FREQ
10µH
VOUT*
5V
2A
100k
422k
SGND
47µF
×2
PGOOD
PGND
*VOUT FOLLOWS VIN
WHEN 3.5V ≤ VIN ≤ 5.2V
EFFICIENCY (%)
350kHz
CAP
Efficiency
VIN*
5.2V TO 60V
80
PULSE-SKIPPING
70
60
50
0.01
VFB
80.6k
Burst Mode
OPERATION
VIN = 12V
VOUT = 5V
0.1
LOAD CURRENT (A)
1
3864 TA01b
3864 TA01a
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1
LTC3864
Absolute Maximum Ratings
(Note 1)
Input Supply Voltage (VIN).......................... –0.3V to 65V
VIN-VSENSE Voltage....................................... –0.3V to 6V
VIN-VCAP Voltage......................................... –0.3V to 10V
RUN Voltage............................................... –0.3V to 65V
PGOOD, PLLIN/MODE Voltages.................... –0.3V to 6V
SS, ITH, FREQ, VFB Voltages......................... –0.3V to 5V
Operating Junction Temperature Range (Notes 2, 3, 4)
LTC3864E,I ........................................ –40°C to 125°C
LTC3864H........................................... –40°C to 150°C
LTC3864MP........................................ –55°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSOP Package.................................................. 300°C
Pin Configuration
TOP VIEW
PLLIN/MODE
1
12 GATE
TOP VIEW
FREQ
2
11 VIN
SGND
3
10 SENSE
SS
4
VFB
ITH
13
PGND
9
CAP
5
8
RUN
6
7
PGOOD
DE PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 43°C/W, θJC = 5.5°C/W
EXPOSED PAD (PIN 13) IS PGND, MUST BE SOLDERED TO PCB FOR OPTIMAL
THERMAL PERFORMANCE
PLLIN/MODE
FREQ
SGND
SS
VFB
ITH
1
2
3
4
5
6
13
PGND
12
11
10
9
8
7
GATE
VIN
SENSE
CAP
RUN
PGOOD
MSE PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 40°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 13) IS PGND, MUST BE SOLDERED TO PCB FOR OPTIMAL
THERMAL PERFORMANCE
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3864EMSE#PBF
LTC3864EMSE#TRPBF
3864
12-Lead Plastic MSOP
–40°C to 125°C
LTC3864IMSE#PBF
LTC3864IMSE#TRPBF
3864
12-Lead Plastic MSOP
–40°C to 125°C
LTC3864HMSE#PBF
LTC3864HMSE#TRPBF
3864
12-Lead Plastic MSOP
–40°C to 150°C
LTC3864MPMSE#PBF
LTC3864MPMSE#TRPBF
3864
12-Lead Plastic MSOP
–55°C to 150°C
LTC3864EDE#PBF
LTC3864EDE#TRPBF
3864
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 125°C
LTC3864IDE#PBF
LTC3864IDE#TRPBF
3864
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 125°C
LTC3864HDE#PBF
LTC3864HDE#TRPBF
3864
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 150°C
LTC3864MPDE#PBF
LTC3864MPDE#TRPBF
3864
12-Lead (4mm × 3mm) Plastic DFN
–55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC3864
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) VIN = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply
VIN
Input Voltage Operating Range
VUVLO
Undervoltage Lockout
IQ
Input DC Supply Current
3.5
(VIN-VCAP) Ramping Up Threshold
(VIN-VCAP) Ramping Down Threshold
Hysteresis
l
l
3.25
3.00
60
V
3.50
3.25
0.25
3.8
3.50
V
V
V
0.77
1.2
mA
Pulse-Skipping Mode
PLLIN/MODE = 0V, FREQ = 0V,
VFB = 0.83V (No Load)
Burst Mode Operation
PLLIN/MODE = Open, FREQ = 0V,
VFB = 0.83V (No Load)
40
60
µA
Shutdown Supply Current
RUN = 0V
7
12
µA
0.800
0.809
V
0.005
%/V
Output Sensing
VREG
Regulated Feedback Voltage
VITH = 1.2V (Note 5)
∆VREG
∆VIN
Feedback Voltage Line Regulation
VIN = 3.8V to 60V (Note 5)
∆VREG
∆VITH
Feedback Voltage Load Regulation
VITH = 0.6V to 1.8V (Note 5)
gm(EA)
Error Amplifier Transconductance
VITH = 1.2V, ∆IITH = ±5µA (Note 5)
IFB
Feedback Input Bias Current
l
0.792
–0.005
–0.1
–0.015
0.1
1.8
%
mS
–50
–10
50
nA
85
95
103
mV
0.1
2
µA
1.26
1.32
V
Current Sensing
VILIM
Current Limit Threshold (VIN-VSENSE)
VFB = 0.77V
ISENSE
SENSE Pin Input Current
VSENSE = VIN
l
Start-Up and Shutdown
VRUN
RUN Pin Enable Threshold
VRUNHYS
RUN Pin Hysteresis
ISS
Soft-Start Pin Charging Current
VRUN Rising
l
1.22
VSS = 0V
150
mV
10
µA
Switching Frequency and Clock Synchronization
f
Programmable Switching Frequency
RFREQ = 24.9kΩ
RFREQ = 64.9kΩ
RFREQ = 105kΩ
375
105
440
810
505
kHz
kHz
kHz
fLO
Low Switching Frequency
FREQ = 0V
320
350
380
kHz
fHI
High Switching Frequency
FREQ = Open
485
535
585
kHz
750
kHz
fSYNC
Synchronization Frequency
l
VCLK(IH)
Clock Input High Level into PLLIN/MODE
l
VCLK(LO)
Clock Input Low Level into PLLIN/MODE
l
fFOLD
Foldback Frequency as Percentage of
Programmable Frequency
tON(MIN)
Minimum On-Time
75
2
V
0.5
VFB = 0V, FREQ = 0V
V
18
%
220
ns
Gate Driver
VCAP
Gate Bias LDO Output Voltage (VIN-VCAP)
IGATE = 0mA
VCAPDROP
Gate Bias LDO Dropout Voltage
VIN = 5V, IGATE = 15mA
∆VCAP(LINE) Gate Bias LDO Line Regulation
9V ≤ VIN ≤ 60V, IGATE = 0mA
∆VCAP(LOAD) Gate Bias LDO Load Regulation
Load = 0mA to 20mA
l
7.6
–3.5
8.0
8.5
V
0.2
0.5
V
0.002
0.03
%/V
%
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LTC3864
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) VIN = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RUP
Gate Pull-Up Resistance
Gate High
2
Ω
RDN
Gate Pull-Down Resistance
Gate Low
0.9
Ω
0.2
PGOOD and Overvoltage
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
IPG
PGOOD Leakage Current
VPGOOD = 5V
%PGD
PGOOD Trip Level
VFB Ramping Negative with Respect to VREG
Hysteresis
–13
VFB Ramping Positive with Respect to VREG
Hysteresis
7
0.4
V
1
µA
–10
2.5
–7
%
%
10
2.5
13
%
%
tPGDLY
PGOOD Delay
PGOOD Going High to Low
PGOOD Going Low to High
100
100
µs
µs
VFBOV
VFB Overvoltage Lockout Threshold
GATE Going High without Delay,
VFB(OV)-VFB(NOM) in Percent
10
%
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 3: The junction temperature (TJ in °C) is calculated from the ambient
temperature (TA in °C) and power dissipation (PD in Watts) as follows:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance provided in the Pin
Configuration section for the corresponding package.
Note 4: The LTC3864 is tested under pulsed loading conditions such that
TJ ≈ TA. The LTC3864E is guaranteed to meet performance specifications
from 0°C to 85°C operating junction temperature range. The LTC3864E
specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with statistical
process controls. The LTC3864I is guaranteed to meet performance
specifications over the –40°C to 125°C operating junction temperature
range, the LTC3864H is guaranteed over the –40°C to 150°C operating
junction temperature range, and the LTC3864MP is guaranteed and tested
over the full –55°C to 150°C operating junction temperature range. High
junction temperatures degrade operating lifetimes; operating lifetime is
derated for junction temperatures greater than 125°C. The maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors.
Note 5: The LTC3864 is tested in a feedback loop that adjust VFB to achieve
a specified error amplifier output voltage (on ITH pin).
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LTC3864
Typical Performance Characteristics
Pulse-Skipping Mode Operation
Waveforms
TA = 25°C, unless otherwise noted.
Burst Mode Operation
Waveforms
VOUT
50mV/DIV
VOUT
50mV/DIV
VSW
10V/DIV
VSW
10V/DIV
Transient Response:
Pulse-Skipping Mode Operation
ILOAD
2A/DIV
VOUT
500mV/DIV
IL
500mA/DIV
IL
500mA/DIV
IL
2A/DIV
2µs/DIV
VIN = 12V
VOUT = 5V
ILOAD = 100mA
FIGURE 8 CIRCUIT
10µs/DIV
100µs/DIV
VIN = 12V
VOUT = 5V
TRANSIENT = 100mA TO 2A
FIGURE 8 CIRCUIT
3864 G02
VIN = 12V
VOUT = 5V
ILOAD = 100mA
FIGURE 8 CIRCUIT
3864 G01
Transient Response:
Burst Mode Operation
Dropout Behavior (100% Duty
Cycle)
3864 G03
Low VIN Operation
VIN
2V/DIV
ILOAD
2A/DIV
VOUT
500mV/DIV
VIN
1V/DIV
VOUT
2V/DIV
GATE
10V/DIV
IL
2A/DIV
100µs/DIV
VIN = 12V
VOUT = 5V
TRANSIENT = 100mA TO 2A
FIGURE 8 CIRCUIT
VOUT
1V/DIV
VOUT = VIN IN DROPOUT
SW
5V/DIV
3864 G05
50ms/DIV
VIN TRANSIENT: 12V TO 4V
AND BACK TO 12V
VOUT = 5V, ILOAD = 100mA, FIGURE 8 CIRCUIT
3864 G04
20ms/DIV
3864 G06
VIN = 0V TO 3.8V
THEN BACK TO 0V
ILOAD = 100mA
FIGURE 8 CIRCUIT
Soft Start-Up into a Prebiased
Output
Normal Soft Start-Up
VOUT PROGRAMMED TO 5V,
BUT STARTS UP IN DROPOUT
SINCE VIN < 5V
Output Tracking
RUN
5V/DIV
VIN
5V/DIV
VOUT PREBIASED
TO 2.9V
SS
200mV/DIV
VOUT
1V/DIV
SS
200mV/DIV
SS
200mV/DIV
VOUT
1V/DIV
1ms/DIV
VIN = 12V, VOUT = 5V
FIGURE 8 CIRCUIT
3864 G07
VOUT
2V/DIV
1ms/DIV
VIN = 12V, VOUT = 5V
ILOAD = 0.5mA
FIGURE 8 CIRCUIT
3864 G08
20ms/DIV
VIN = 12V, VOUT = 5V
ILOAD = 100mA
FIGURE 8 CIRCUIT
3864 G09
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LTC3864
Typical Performance Characteristics
Overcurrent Protection
SHORTCIRCUIT
TRIGGER
1A
1A
SHORT-CIRCUIT REGION
VIN
20V/DIV
VOUT
5V/DIV
SOFT RECOVERY
FROM SHORT
IL
1A/DIV
VOUT
500mV/DIV
IL
2A/DIV
VOUT DROOPS DUE TO
REACHING CURRENT LIMIT
20ms/DIV
VIN = 12V, VOUT = 5V
FIGURE 8 CIRCUIT
Pulse-Skipping Mode Input
Current Over Input Voltage
(No Load)
950
VIN = 12V, VOUT = 5V
ILOAD = 0A
FIGURE 8 CIRCUIT
65
2ms/DIV
VIN = 12V, SURGE TO 48V
VOUT = 5V
ILOAD = 200mA, FIGURE 8 CIRCUIT
3864 G11
IVIN (µA)
55
50
45
40
25
VIN = 12V, VOUT = 5V
ILOAD = 0A
FIGURE 8 CIRCUIT
900
60
3864 G12
Shutdown Current Over Input
Voltage
FIGURE 8 CIRCUIT
20
850
15
IVIN (µA)
70
GATE
20V/DIV
VOUT
50mV/DIV
500µs/DIV
VIN = 12V, VOUT = 5V
FIGURE 8 CIRCUIT
3864 G10
Burst Mode Input Current Over
Input Voltage (No Load)
IVIN (µA)
VIN Line Transient Behavior
Short-Ciruit Protection
3.2A
ILOAD
1A/DIV
TA = 25°C, unless otherwise noted.
800
10
750
5
35
30
0
10
20
30
VIN(V)
40
50
700
60
0
10
20
30
VIN (V)
40
50
Output Regulation Over Input
Voltage
0.010
0
–0.010
1.0
VIN = 12V, VOUT = 5V
ILOAD NORMALIZED AT ILOAD = 1A
FIGURE 8 CIRCUIT
0.8
0.005
0
Burst Mode OPERATION
PULSE-SKIPPING
0
10
20
30
VIN (V)
40
50
60
3864 G16
30
VIN (V)
40
50
–0.010
–0.5
60
0.6
VIN = 12V, VOUT = 5V
ILOAD = 200mA
VOUT NORMALIZED TO TA = 25°C
FIGURE 8 CIRCUIT
0.4
0.2
0
–0.2
–0.4
–0.005
–0.005
20
Output Regulation Over
Temperature
NORMALIZED ∆VOUT (%)
NORMALIZED ∆VOUT (%)
NORMALIZED ∆VOUT (%)
0.005
10
3864 G15
Output Regulation Over Load
Current
VOUT = 5V
ILOAD = 200mA
VOUT NORMALIZED AT VIN = 12V
FIGURE 8 CIRCUIT
0
3864 G14
3864 G13
0.010
0
60
–0.6
Burst Mode OPERATION
PULSE-SKIPPING
0
0.5
1
1.5
ILOAD (A)
2
2.5
3864 G17
Burst Mode OPERATION
PULSE-SKIPPING
–0.8
–1.0
–75
–25
25
75
125
TEMPERATURE (°C)
175
3864 G18
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LTC3864
Typical Performance Characteristics
Free Running Frequency Over
Input Voltage
Free Running Frequency Over
Temperature
FREQ = OPEN
550
100
500
f (kHz)
500
f (kHz)
120
FREQUENCY FOLDBACK %
FREQ = OPEN
550
450
450
400
400
FREQ = 0V
350
0
20
10
30
VIN (V)
FREQ = 0V
350
40
50
300
–75
60
25
75
125
TEMPERATURE (°C)
–25
0.1
–0.3
–0.4
–3.0
5
10
IGATE (mA)
15
–0.5
20
0
5
10
IGATE (mA)
15
20
92
25
75
125
TEMPERATURE (°C)
70
60
50
40
30
20
10
175
3864 G25
0
0.4
0.8
1.2
ITH VOLTAGE (V)
RUN Pin Pull-Up Current Over
Temperature
0.65
12
10
8
6
–75
2
1.6
3864 G24
RUN PULL-UP CURRENT (µA)
94
–25
80
–10
14
SS PULL-UP CURRENT (µV)
CURRENT LIMIT SENSE VOLTAGE (mV)
100
800
Burst Mode OPERATION
PULSE-SKIPPING
90
SS Pin Pull-Up Current Over
Temperature
96
600
3864 G23
Current Sense Voltage Over
Temperature
98
400
VFB (mV)
0
3864 G22
90
–75
100
CURRENT SENSE VOLTAGE (mV)
–0.2
0
200
3864 G21
VIN = 5V
–0.1
–2.5
0
Current Sense Voltage Over ITH
Voltage
0.0
–2.0
0
175
(VIN - VCAP) DROPOUT (V)
(VIN - VCAP) REGULATION (%)
0.0
–1.5
40
GATE Bias LDO (VIN - VCAP)
Dropout Behavior
0.5
–1.0
60
3864 G20
GATE Bias LDO (VIN - VCAP) Load
Regulation
–0.5
80
20
3864 G19
–3.5
Frequency Foldback % Over
Feedback Voltage
600
600
300
TA = 25°C, unless otherwise noted.
–25
25
75
125
TEMPERATURE (°C)
175
3864 G26
0.55
0.45
0.35
0.25
–75
–25
25
75
125
TEMPERATURE (°C)
175
3864 G27
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LTC3864
Pin Functions
PLLIN/MODE (Pin 1): External Reference Clock Input
and Burst Mode Enable/Disable. When an external clock
is applied to this pin, the internal phase-locked loop will
synchronize the turn-on edge of the gate drive signal with
the rising edge of the external clock. When no external
clock is applied, this input determines the operation during
light loading. Floating this pin selects low IQ (40μA) Burst
Mode operation. Pulling to ground selects pulse-skipping
mode operation.
FREQ (Pin 2): Switching Frequency Set Point Input. The
switching frequency is programmed by an external setpoint resistor RFREQ connected between the FREQ pin and
signal ground. An internal 20µA current source creates
a voltage across the external setpoint resistor to set the
internal oscillator frequency. Alternatively, this pin can
be driven directly by a DC voltage to set the oscillator
frequency. Grounding selects a fixed operating frequency
of 350kHz. Floating selects a fixed operating frequency
of 535kHz.
SGND (Pin 3): Ground Reference for Small Signal Analog
Component (Signal Ground). Signal ground should be used
as the common ground for all small signal analog inputs
and compensation components. Connect signal ground to
power ground (ground reference for power components)
only at one point using a single PCB trace.
SS (Pin 4): Soft-Start and External Tracking Input. The
LTC3864 regulates the feedback voltage to the smaller of
0.8V or the voltage on the SS pin. An internal 10μA pull-up
current source is connected to this pin. A capacitor to
ground at this pin sets the ramp time to the final regulated
output voltage. Alternatively, another voltage supply connected through a resistor divider to this pin allows the
output to track the other supply during start-up.
VFB (Pin 5): Output Feedback Sense. A resistor divider
from the regulated output point to this pin sets the output
voltage. The LTC3864 will nominally regulate VFB to the
internal reference value of 0.8V. If VFB is less than 0.4V, the
switching frequency will linearly decrease and fold back
to about one-fifth of the internal oscillator frequency to
reduce the minimum duty cycle.
ITH (Pin 6): Current Control Threshold and Controller
Compensation Point. This pin is the output of the error
amplifier and the switching regulator’s compensation
8
point. The voltage ranges from 0V to 2.9V, with 0.8V corresponding to zero sense voltage (zero current).
PGOOD (Pin 7): Power Good Indicator Output. This open
drain logic output is pulled to ground when the output
voltage is outside of a ±10% window around the regulation
point. The PGOOD switches states only after a 100µs delay.
RUN (Pin 8): Digital Run Control Input. A RUN voltage
above the 1.26V threshold enables normal operation, while
a voltage below the threshold shuts down the controller.
An internal 0.4µA current source pulls the RUN pin up to
about 3.3V. The RUN pin can be connected to an external
power supply up to 60V.
CAP (Pin 9): Gate Driver (–) Supply. A low ESR ceramic
bypass capacitor of at least 0.47µF or 10X the effective
CMILLER of the P-channel power MOSFET, is required from
VIN to this pin to serve as a bypass capacitor for the internal regulator. To insure stable low noise operation, the
bypass capacitor should be placed adjacent to the VIN and
CAP pins and connected using the same PCB metal layer.
SENSE (Pin 10): Current Sense Input. A sense resistor
RSENSE from VIN pin to the SENSE pin sets the maximum
current limit. The peak inductor current limit is equal to
95mV/RSENSE. For accuracy, it is important that the VIN
pin and the SENSE pin route directly to the current sense
resistor and make a Kelvin (4-wire) connection.
VIN (Pin 11): Chip Power Supply. A minimum bypass
capacitor of 0.1µF is required from the VIN pin to power
ground. For best performance use a low ESR ceramic
capacitor placed near the VIN pin.
GATE (Pin 12): Gate Drive Output for External P-Channel
MOSFET. The gate driver bias supply voltage (VIN-VCAP)
is regulated to 8V when VIN is greater than 8V. The gate
driver is disabled when (VIN-VCAP) is less than 3.5V (typical), 3.8V maximum in startup and 3.25V (typical) 3.5V
maximum in normal operation.
PGND (Exposed Pad Pin 13): Ground Reference for Power
Components (Power Ground). The PGND exposed pad must
be soldered to the circuit board for electrical contact and
for rated thermal performance of the package. Connect
signal ground to power ground only at one point using a
single PCB trace.
For more information www.linear.com/LTC3864
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LTC3864
FUNCTIONAL Diagram
VIN
UVLO
+
–
0.4µA
CIN
VIN
3.25V
RSENSE
SENSE
RUN
RUN
1.26V
+
–
–
LOGIC
CONTROL
DRV
GATE
MP
L
Q
S
R
CLOCK
PLLIN/MODE
20µA
FREQ
MODE/CLOCK
DETECT
+
PLL
SYSTEM
–
VCO
ICMP
VOUT
COUT
IN
Burst Mode
OPERATION
LDO
OUT
VIN – 8V
O.425V
–
10µA
+
+
–
SGND
VOUT
SLOPE
COMPENSATION
RPGD
OV
PGOOD
+
UV
PGND
SS
0.8V
CSS
EA
(Gm = 1.8mS)
O.88V
–
DELAY
100µs
RFB2
VFB
+
–
D1
+
+
RFREQ
CCAP
CAP
O.72V
RFB1
ITH
3864 FD
RITH
CITH1
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9
LTC3864
Operation
Main Control Loop (Refer to Functional Diagram)
Shutdown and Soft-Start
The LTC3864 uses a peak current-mode control architecture to regulate the output in an asynchronous step-down
DC/DC switching regulator. The VFB input is compared to
an internal reference by a transconductance error amplifier (EA). The internal reference can be either a fixed 0.8V
reference VREF or the voltage input on the SS pin. In normal
operation VFB regulates to the internal 0.8V reference
voltage. In soft-start or tracking mode, when the SS pin
voltage is less than the internal 0.8V reference voltage,
VFB will regulate to the SS pin voltage. The error amplifier
output connects to the ITH (current [I] threshold [TH])
pin. The voltage level on the ITH pin is then summed with
a slope compensation ramp to create the peak inductor
current set point.
When the RUN pin is below 0.7V, the controller and most
internal circuits are disabled. In this micropower shutdown
state, the LTC3864 draws only 7µA. Releasing the RUN
pin allows a small internal pull up current to pull the RUN
pin above 1.26V and enable the controller. The RUN pin
can be pulled up to an external supply of up to 60V or it
can be driven directly by logic levels.
The peak inductor current is measured through a sense
resistor RSENSE placed across the VIN and SENSE pins.
The resultant differential voltage from VIN to SENSE is
proportional to the inductor current and is compared to the
peak inductor current set point. During normal operation
the P-channel power MOSFET is turned on when the clock
leading edge sets the SR latch through the S input. The
P-channel MOSFET is turned off through the SR latch R
input when the differential voltage from VIN to SENSE is
greater than the peak inductor current set point and the
current comparator, ICMP, trips high.
Power CAP and VIN Undervoltage Lockout (UVLO)
Power for the P-channel MOSFET gate driver is derived
from the CAP pin. The CAP pin is regulated to 8V below
VIN in order to provide efficient P-channel operation. The
power for the VCAP supply comes from an internal LDO,
which regulates the VIN-CAP differential voltage. A minimum capacitance of 0.47µF (low ESR ceramic) is required
between VIN and CAP to assure stability.
For VIN ≤ 8V, the LDO will be in dropout and the CAP voltage will be at ground, i.e. the VIN-CAP differential voltage
will equal VIN. If VIN-CAP is less than 3.25V (typical), the
LTC3864 enters a UVLO state where the GATE is prevented
from switching and most internal circuitry is shut down.
In order to exit UVLO, the VIN-CAP voltage would have to
exceed 3.5V (typical).
The start-up of the output voltage VOUT is controlled by
the voltage on the SS pin. When the voltage on the SS
pin is less than the 0.8V internal reference, the VFB pin is
regulated to the voltage on the SS pin. This allows the SS
pin to be used to program a soft-start by connecting an
external capacitor from the SS pin to signal ground. An
internal 10µA pull-up current charges this capacitor, creating a voltage ramp on the SS pin. As the SS voltage rises
from 0V to 0.8V, the output voltage VOUT rises smoothly
from zero to its final value.
Alternatively, the SS pin can be used to cause the startup of VOUT to track that of another supply. Typically, this
requires connecting the SS pin to an external resistor
divider from the other supply to ground. (See Applications
Information section.) Under shutdown or UVLO, the SS
pin is pulled to ground and prevented from ramping up.
If the slew rate of the SS pin is greater than 1.2V/ms, the
output will track an internal soft-start ramp instead of the
SS pin. The internal soft-start will guarantee a smooth
start-up of the output under all conditions, including in the
case of a short-circuit recovery where the output voltage
will recover from near ground.
Light Load Current Operation (Burst Mode Operation
or Pulse-Skipping Mode)
The LTC3864 can be enabled to enter high efficiency Burst
Mode operation or pulse-skipping mode at light loads. To
select pulse-skipping operation, tie the PLLIN/MODE pin
to signal ground. To select Burst Mode operation, float
the PLLIN/MODE pin.
In Burst Mode operation, if the VFB is higher than the reference voltage, the error amplifier will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.425V,
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LTC3864
Operation
the internal sleep signal goes high, enabling sleep mode.
The ITH pin is then disconnected from the output of the
error amplifier and held at 0.55V.
In sleep mode, much of the internal circuitry is turned
off, reducing the quiescent current to 40µA while the load
current is supplied by the output capacitor. As the output
voltage and hence the feedback voltage decreases, the
error amplifier’s output will rise. When the output voltage
drops enough, the ITH pin is reconnected to the output
of the error amplifier, the sleep signal goes low, and the
controller resumes normal operation by turning on the
external P-MOSFET on the next cycle of the internal oscillator. In Burst Mode operation, the peak inductor current
has to reach at least 25% of current limit for the current
comparator, ICMP, to trip and turn the P-MOSFET back off,
even though the ITH voltage may indicate a lower current
setpoint value.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3864 will skip pulses during light loads. In
this mode, ICMP may remain tripped for several cycles and
force the external MOSFET to stay off, thereby skipping
pulses. This mode offers the benefits of smaller output
ripple, lower audible noise, and reduced RF interference,
at the expense of lower efficiency when compared to Burst
Mode operation.
Frequency Selection and Clock Synchronization
The switching frequency of the LTC3864 can be selected
using the FREQ pin. If the PLLIN/MODE pin is not being
driven by an external clock source, the FREQ pin can be
tied to signal ground, floated, or programmed through an
external resistor. Tying FREQ pin to signal ground selects
350kHz, while floating selects 535kHz. Placing a resistor
between FREQ pin and signal ground allows the frequency
to be programmed between 50kHz and 850kHz.
The phase-locked loop (PLL) on the LTC3864 will synchronize the internal oscillator to an external clock source
when connected to the PLLIN/MODE pin. The PLL forces
the turn-on edge of the external P-channel MOSFET to be
aligned with the rising edge of the synchronizing signal.
The oscillator’s default frequency is based on the operating
frequency set by the FREQ pin. If the oscillator’s default
frequency is near the external clock frequency, only slight
adjustments are needed for the PLL to synchronize the
external P-channel MOSFET’s turn-on edge to the rising
edge of the external clock. This allows the PLL to lock
rapidly without deviating far from the desired frequency.
The PLL is guaranteed from 75kHz to 750kHz. The clock
input levels should be greater than 2V for HI and less
than 0.5V for LO.
Power Good and Fault Protection
The PGOOD pin is an open-drain output. An internal
N-channel MOSFET pulls the PGOOD pin low when the VFB
pin voltage is outside a ±10% window from the 0.8V internal
voltage reference. The PGOOD pin is also pulled low when
the RUN pin is low (shut down). When the VFB pin voltage
is within the ±10% window, the MOSFET is turned off and
the pin is allowed to be pulled up by an external resistor
to a source no greater than 6V. The PGOOD open-drain
output has a 100µs delay before it can transition states.
When the VFB voltage is above +10% of the regulated
voltage of 0.8V, this is considered as an overvoltage condition and the external P-MOSFET is immediately turned
off and prevented from ever turning on until VFB returns
below +7.5%.
In the event of an output short circuit or overcurrent condition that causes the output voltage to drop significantly
while in current limit, the LTC3864 operating frequency
will fold back. Anytime the output feedback VFB voltage is
less than 50% of the 0.8V internal reference (i.e., 0.4V),
frequency foldback is active. The frequency will continue
to drop as VFB drops until reaching a minimum foldback
frequency of about 18% of the setpoint frequency. Frequency foldback is designed, in combination with peak
current limit, to limit current in start-up and short-circuit
conditions. Setting the foldback frequency as a percentage
of operating frequency assures that start-up characteristics
scale appropriately with operating frequency.
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LTC3864
Applications Information
The LTC3864 is a current mode, constant frequency PWM
controller for an asynchronous step-down DC/DC regulator
with a P-channel power MOSFET acting as the main switch
and a Schottky power diode acting as the commutating
(catch) diode. The input range extends from 3.5V to 60V.
The output range can be programmed from 0.8V to all the
way up to VIN. The LTC3864 can transition from regulation
to 100% duty cycle when the input voltage drops below
the programmed output voltage. Additionally, the LTC3864
offers Burst Mode operation with 40µA quiescent current,
which delivers outstanding efficiency in light load operation. The LTC3864 is a low pin count, robust and easy to
use solution in applications which require high efficiency
and operate with widely varying high voltage inputs.
The typical application on the front page is a basic LTC3864
application circuit. The LTC3864 can sense the inductor
current through a high side series sense resistor, RSENSE,
placed between VIN and the source of the external PMOSFET. Once the required output voltage and operating
frequency have been determined, external component
selection is driven by load requirements, and begins with
the selection of inductor and RSENSE. Next, the power
MOSFET and catch diode are selected. Finally, input and
output capacitors are selected.
Output Voltage Programming
The output voltage is programmed by connecting a
feedback resistor divider from the output to the VFB pin
as shown in Figure 1. The output voltage in steady state
operation is set by the feedback resistors according to
the equation:
 R 
VOUT = 0.8V •  1+ FB2 
 RFB1 
VOUT
LTC3864
RFB2
CFF
VFB
RFB1
3864 F01
Figure 1. Setting the Output Voltage
Switching Frequency and Clock Synchronization
The choice of operating frequency is a trade-off between
efficiency and component size. Lowering the operating frequency improves efficiency by reducing MOSFET switching
losses but requires larger inductance and/or capacitance
to maintain low output ripple voltage. Conversely, raising
the operating frequency degrades efficiency but reduces
component size.
The LTC3864 can free run at a user programmed switching frequency, or it can synchronize with an external
clock to run at the clock frequency. When the LTC3864
is synchronized, the GATE pin will phase synchronize
with the rising edge of the applied clock in order to turn
the external P-MOSFET on. The switching frequency of
the LTC3864 is programmed with the FREQ pin, and the
external clock is applied at the PLLIN/MODE pin. Table 1
highlights the different states in which the FREQ pin can
be used in conjunction with the PLLIN/MODE pin.
Table 1
FREQ PIN
PLLIN/MODE PIN
FREQUENCY
0V
DC Voltage
350kHz
Floating
DC Voltage
535kHz
Resistor to GND
DC Voltage
50kHz to 850kHz
Any of the Above
External Clock
Phase Locked to External
Clock
To improve the transient response, a feedforward capacitor
CFF may be used. Great care should be taken to route the
VFB line away from noise sources, such as the inductor
or the GATE signal that drives the external P-MOSFET.
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LTC3864
Applications Information
The free-running switching frequency can be programmed
from 50kHz to 850kHz by connecting a resistor from FREQ
pin to signal ground. The resulting switching frequency as
a function of resistance on FREQ pin is shown in Figure 2.
1000
900
FREQUENCY (kHz)
800
700
A reasonable starting point for ripple current is 40% of
IOUT(MAX) at nominal VIN. The largest ripple current occurs
at the highest VIN. To guarantee that the ripple current does
not exceed a specified maximum, the inductance should
be chosen according to:
V
 VOUT  

L=
1– OUT 


 f • ∆IL(MAX)   VIN(MAX) 
600
500
400
300
200
100
0
this requires a large inductor. There is a trade-off between
component size, efficiency, and operating frequency.
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
3864 F02
Figure 2. Switching Frequency vs Resistor on FREQ Pin
Set the free-running frequency to the desired synchronization frequency using the FREQ pin so that the internal
oscillator is prebiased to approximately the synchronization
frequency. While it is not required that the free-running
frequency be near the external clock frequency, doing so
will minimize synchronization time.
Inductor Selection
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of
smaller inductor and capacitor values. A higher frequency
generally results in lower efficiency because of MOSFET
gate charge and transition losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
Given the desired input and output voltages, the inductor
value and operation frequency determine the ripple current:
V  V 
∆IL =  OUT   1– OUT 
 f •L  
VIN 
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and results in lower
output ripple. Highest efficiency operation is obtained at
low frequency with small ripple current. However, achieving
Once the inductance value has been determined, the type
of inductor must be selected. Core loss is independent of
core size for a given inductor value, but it is very dependent on the inductance selected. As inductance increases,
core losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
High efficiency converters generally cannot tolerate the
core loss of low cost powdered iron cores, forcing the use
of more expensive ferrite materials. Ferrite designs have
very low core loss and are preferred at high switching
frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material
saturates hard, which means that inductance collapses
abruptly when the peak design current is exceeded. This
will result in an abrupt increase in inductor ripple current
and output voltage ripple. Do not allow the core to saturate!
A variety of inductors are available from manufacturers
such as Sumida, Panasonic, Coiltronics, Coilcraft, Toko,
Vishay, Pulse, and Würth.
Current Sensing and Current Limit Programming
The LTC3864 senses the inductor current through a current sense resistor, RSENSE, placed across the VIN and
SENSE pins. The voltage across the resistor, VSENSE, is
proportional to inductor current and in normal operation
is compared to the peak inductor current setpoint. A
current limit condition is detected when VSENSE exceeds
95mV. When the current limit threshold is exceeded, the
P-channel MOSFET is immediately turned off by pulling
the GATE voltage to VIN regardless of the controller input.
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13
LTC3864
Applications Information
The peak inductor current limit is equal to:
 95mV 
IL(PEAK) ≅ 
 RSENSE 
This inductor current limit would translate to an output
current limit based on the inductor ripple:
I LIMIT ≅
95mV ∆IL
–
RSENSE 2
The SENSE pin is a high impedance input with a maximum
leakage of ±2µA. Since the LTC3864 is a peak current
mode controller, noise on the SENSE pin can create pulse
width jitter. Careful attention must be paid to the layout of
RSENSE. To ensure the integrity of the current sense signal,
VSENSE, the traces from VIN and SENSE pins should be
short and run together as a differential pair and Kelvin
(4-wire) connected across RSENSE (Figure 3).
drain current ID(MAX), and the MOSFET’s thermal resistance
θJC(MOSFET) and θJA(MOSFET).
The gate driver bias voltage VIN-VCAP is set by an internal
LDO regulator. In normal operation, the CAP pin will be
regulated to 8V below VIN. A minimum 0.1µF capacitor
is required across the VIN and CAP pins to ensure LDO
stability. If required, additional capacitance can be added
to accommodate higher gate currents without voltage
droop. In shutdown and Burst Mode operation, the CAP
LDO is turned off. In the event of CAP leakage to ground,
the CAP voltage is limited to 9V by a weak internal clamp
from VIN to CAP. As a result, a minimum 10V VGS rated
MOSFET is required.
The power dissipated by the P-channel MOSFET when the
LTC3864 is in continuous conduction mode is given by:
PMOSFET ≅ D • IOUT2 • ρ t • RDS(ON) +
I 
VIN2 •  OUT • (CMILLER ) •
 2 
VIN

RUP 
RDN
+

•f
V
–
V
–
V
V
(
)
IN
CAP
MILLER
MILLER


VIN
LTC3864
SENSE
OPTIONAL
FILTERING
CF
RSENSE
RF
MP
3864 F03
Figure 3. Inductor Current Sensing
The LTC3864 has internal filtering of the current sense
voltage which should be adequate in most applications.
However, adding a provision for an external filter offers
added flexibility and noise immunity, should it be necessary. The filter can be created by placing a resistor from the
RSENSE resistor to the SENSE pin and a capacitor across
the VIN and SENSE pins.
where D is duty factor, RDS(ON) is on-resistance of
P-MOSFET, ρt is temperature coefficient of on-resistance,
RDN is the pull-down driver resistance specified at 0.9Ω
typical and RUP is the pull-up driver resistance specified at
2Ω typical. VMILLER is the Miller effective VGS voltage and
is taken graphically from the power MOSFET data sheet.
The power MOSFET input capacitance C MILLER is
the most important selection criteria for determining the transition loss term in the P-channel MOSFET
but is not directly specified on MOSFET data sheets.
CMILLER is a combination of several components, but
it can be derived from the typical gate charge curve
included on most data sheets (Figure 4). The curve is
Power MOSFET Selection
The LTC3864 drives a P-channel power MOSFET that
serves as the main switch for the asynchronous stepdown converter. Important P-channel power MOSFET
parameters include drain-to-source breakdown voltage
VBR(DSS), threshold voltage VGS(TH), on-resistance RDS(ON),
gate-to-drain reverse transfer capacitance CRSS, maximum
VSG
MILLER EFFECT
G
S
D
a
b
IGATE
RLOAD
+
V
– SD(TEST)
QIN
CMILLER = (QB – QA)/VSD(TEST)
3864 F04
(b)
(a)
Figure 4. (a) Typical P-MOSFET Gate Charge Characteristics
and (b) Test Set-Up to Generate Gate Charge Curve
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LTC3864
Applications Information
generated by forcing a constant current out of the gate of a
common-source connected P-MOSFET that is loaded with
a resistor, and then plotting the gate voltage versus time.
The initial slope is the effect of the gate-to-source and
gate-to-drain capacitances. The flat portion of the curve
is the result of the Miller multiplication effect of the drainto-gate capacitance as the drain voltage rises across the
resistor load. The Miller charge (the increase in coulombs
on the horizontal axis from a to b while the curve is flat) is
specified for a given VSD test voltage, but can be adjusted
for different VSD voltages by multiplying by the ratio of
the adjusted VSD to the curve specified VSD value. A way
to estimate the CMILLER term is to take the change in gate
charge from points a and b (or the parameter QGD on a
manufacturer’s data sheet) and dividing it by the specified
VSD test voltage, VSD(TEST).
CMILLER ≅
Q GD
VSD(TEST)
The term with CMILLER accounts for transition loss, which
is highest at high input voltages. For VIN < 20V, the highcurrent efficiency generally improves with larger MOSFETs,
while for VIN > 20V, the transition losses rapidly increase
to the point that the use of a higher RDS(ON) device with
lower CMILLER actually provides higher efficiency.
Schottky Diode Selection
When the P-MOSFET is turned off, a power Schottky diode
is required to function as a commutating diode to carry the
inductor current. The average diode current is therefore
dependent on the P-MOSFET’s duty factor. The worst case
condition for diode conduction is a short-circuit condition
where the Schottky must handle the maximum current
as its duty factor approaches 100% (and the P-channel
MOSFET’s duty factor approaches 0%). The diode therefore must be chosen carefully to meet worst case voltage
and current requirements. The equation below describes
the continuous or average forward diode current rating
required, where D is the regulator duty factor.
IF(AVG) ≅ I OUT(MAX) • (1–D)
Once the average forward diode current is calculated,
the power dissipation can be determined. Refer to the
Schottky diode data sheet for the power dissipation
PDIODE as a function of average forward current IF(AVG).
PDIODE can also be iteratively determined by the two
equations below, where VF(IOUT, TJ) is a function of both
IF(AVG) and junction temperature TJ. Note that the thermal
resistance θJA(DIODE) given in the data sheet is typical and
can be highly layout dependent. It is therefore important
to make sure that the Schottky diode has adequate heat
sinking.
TJ ≅ PDIODE • θJA(DIODE)
PDIODE ≅ I F(AVG)• VF(IOUT,TJ)
The Schottky diode forward voltage is a function of both
IF(AVG) and TJ, so several iterations may be required to
satisfy both equations. The Schottky forward voltage VF
should be taken from the Schottky diode data sheet curve
showing Instantaneous Forward Voltage. The forward
voltage will increase as a function of both TJ and IF(AVG).
The nominal forward voltage will also tend to increase as
the reverse breakdown voltage increases. It is therefore
advantageous to select a Schottky diode appropriate to
the input voltage requirements.
CIN and COUT Selection
The input capacitance CIN is required to filter the square
wave current through the P-channel MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
V
VIN
ICIN(RMS) ≅ IOUT(MAX) • OUT •
–1
VIN
VOUT
The formula has a maximum at VIN = 2VOUT, where
ICIN(RMS) = IOUT(MAX)/2. This simple worst-case condition
is commonly used for design because even significant
deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based
on only 2000 hours of life, which makes it advisable to
derate the capacitor.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step transients.
The ∆VOUT is approximately bounded by:
1

∆VOUT ≤ ∆IL ESR+
8
•
f
•C

OUT 
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15
LTC3864
Applications Information
Since ∆IL increases with input voltage, the output ripple
is highest at maximum input voltage. Typically, once the
ESR requirement is satisfied, the capacitance is adequate
for filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, specialty polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
packages. Specialty polymer capacitors offer very low
ESR but have lower specific capacitance than other types.
Tantalum capacitors have the highest specific capacitance,
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications provided that
consideration is given to ripple current ratings and longterm reliability. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient and
audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing. When used as input
capacitors, care must be taken to ensure that ringing from
inrush currents and switching does not pose an overvoltage hazard to the power switch and controller. To dampen
input voltage transients, add a small 5μF to 40μF aluminum
electrolytic capacitor with an ESR in the range of 0.5Ω to
2Ω. High performance through-hole capacitors may also
be used, but an additional ceramic capacitor in parallel
is recommended to reduce the effect of lead inductance.
Discontinuous and Continuous Operation
The LTC3864 operates in discontinuous conduction (DCM)
until the load current is high enough for the inductor
current to be positive at the end of the switching cycle.
The output load current at the continuous/discontinuous
boundary IOUT(CDB) is given by the following equation:
I OUT(CDB) ≅
(VIN – VOUT)( VOUT+ VF )
2 • L • f • (VIN + VF )
The continuous/discontinuous boundary is inversely
proportional to the inductor value. Therefore, if required,
IOUT(CDB) can be reduced by increasing the inductor value.
External Soft-Start and Output Tracking
Start-up characteristics are controlled by the voltage on
the SS pin. When the voltage on the SS pin is less than
the internal 0.8V reference, the LTC3864 regulates the VFB
pin voltage to the voltage on the SS pin. When the SS pin
is greater than the internal 0.8V reference, the VFB pin
voltage regulates to the 0.8V internal reference. The SS
pin can be used to program an external soft-start function
or to allow VOUT to track another supply during start-up.
Soft-start is enabled by connecting a capacitor from
the SS pin to ground. An internal 10µA current source
charges the capacitor, providing a linear ramping voltage
at the SS pin that causes VOUT to rise smoothly from 0V
to its final regulated value. The total soft-start time will
be approximately:
tSS = CSS •
0.8V
10µA
When the LTC3864 is configured to track another supply,
a voltage divider can be used from the tracking supply to
the SS pin to scale the ramp rate appropriately. Two common implementations of tracking as shown in Figure 5a
are coincident and ratiometric. For coincident tracking,
make the divider ratio from the external supply the same
as the divider ratio for the feedback voltage. Ratiometric
tracking could be achieved by using a different ratio than
the feedback (Figure 5b).
Note that the soft-start capacitor charging current is always
flowing, producing a small offset error. To minimize this
error, select the tracking resistive divider values to be small
enough to make this offset error negligible.
Short-Circuit Faults: Current Limit and Foldback
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3864, the maximum sense voltage is 95mV,
measured across the inductor sense resistor RSENSE,
placed across the VIN and SENSE pins. The output current
limit is approximately:
ILIMIT ≅
95mV ∆I L
–
RSENSE 2
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LTC3864
Applications Information
The current limit must be chosen to ensure that ILIMIT(MIN)
> IOUT(MAX) under all operating conditions. The minimum
current limit value should be greater than the inductor
current required to produce maximum output power at
worst case efficiency. Worst-case efficiency typically occurs at the highest VIN.
Short-circuit fault protection is assured by the combination
of current limit and frequency foldback. When the output
feedback voltage VFB drops below 0.4V, the operating
frequency f will fold back to a minimum value of 0.18 • f
when VFB reaches 0V. Both current limit and frequency
foldback are active in all modes of operation. In a shortcircuit fault condition, the output current is first limited by
current limit and then further reduced by folding back the
operating frequency as the short becomes more severe.
Short-Circuit Recovery and Internal Soft-Start
An internal soft-start feature guarantees a maximum positive output voltage slew rate in all operational cases. In a
short-circuit recovery condition for example, the output
recovery rate is limited by the internal soft-start so that
output voltage overshoot and excessive inductor current
buildup is prevented.
The internal soft-start voltage and the external SS pin
operate independently. The output will track the lower of
the two voltages. The slew rate of the internal soft-start
voltage is roughly 1.2V/ms, which translates to a total
soft-start time of 650µs. If the slew rate of the SS pin
is greater than 1.2V/ms the output will track the internal
soft-start ramp. To assure robust fault recovery, the
VOUT
EXTERNAL
SUPPLY
VOLTAGE
VOLTAGE
EXTERNAL
SUPPLY
VOUT
TIME
TIME
Coincident Tracking
Ratiometric Tracking
3864 F05a
Figure 5(a). Two Different Modes of Output Tracking
EXT. V
VOUT
RFB2
TO VFB
TO SS
RFB1
RFB1
VOUT
EXT. V
RFB2
R1
TO SS
R2
0.8V
≥
R1+ R2 EXT. V
R2
RFB2
TO VFB
RFB1
3864 F05b
Coincident Tracking Setup
Ratiometric Tracking Setup
Figure 5(b): Setup for Ratiometric and Coincident Tracking
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LTC3864
Applications Information
internal soft-start feature is active in all operational cases.
If a short-circuit condition occurs which causes the output
to drop significantly, the internal soft-start will assure a
soft recovery when the fault condition is removed.
The internal soft-start assures a clean soft ramp-up from
any fault condition that causes the output to droop, guaranteeing a maximum ramp rate in soft-start, short-circuit
fault release, or output recovery from drop out. Figure 6
illustrates how internal soft-start controls the output
ramp-up rate under varying scenarios.
VIN
INTERNAL SOFT-START INDUCED START-UP
(NO EXTERNAL SOFT-START CAPACITOR)
~ 650µs
TIME
VOLTAGE
(a)
VOUT
SHORT-CIRCUIT
INTERNAL SOFT-START
INDUCED RECOVERY
TIME
(b)
VOLTAGE
VIN
VIN
DROPOUT
VOUT
INTERNAL SOFT-START
INDUCED RECOVERY
TIME
(c)
The implications of both the UVLO rising and UVLO falling
specifications must be carefully considered for low VIN
operation. The UVLO threshold with VIN rising is typically 3.5V (with a maximum of 3.8V) and UVLO falling is
typically 3.25V (with a maximum of 3.5V). The operating
input voltage range of the LTC3864 is guaranteed to be
3.5V to 60V over temperature, but the initial VIN ramp
must exceed 3.8V to guarantee start-up.
For example, Figure 7 illustrates LTC3864 operation when
an automotive battery droops during a cold crank condition. The typical automotive battery is 12V to 14V, which is
more than enough headroom above 3.8V for the LTC3864
to start up. Onboard electronics which are powered by a
DC/DC regulator require a minimum supply voltage for
seamless operation during the cold crank condition, and
the battery may droop close to these minimum supply
requirements during a cold crank. The DC/DC regulator
should not exacerbate the situation by having excessive
dropout between the already suppressed battery voltage
input and the output of the regulator which power these
electronics. As seen in Figure 7, the LTC3864’s 100%
duty cycle capability allows virtually no dropout (only the
IOUT • (RSENSE + RDS(ON)) drop across the sense resistor
and P-MOSFET if there is a significant IOUT) from the battery
to the output. The 3.5V guaranteed UVLO point assures
sufficient margin for continuous, uninterrupted operation in
extreme cold crank battery drooping conditions. However,
additional input capacitance or slower soft start-up time
may be required at low VIN (e.g. 3.5V to 4.5V) in order to
limit VIN droop caused by inrush currents, especially if
the battery or input source has a sufficiently large input
impedance.
3864 F06
Figure 6. Internal Soft-Start (a) Allows Soft Start-Up without
an External Soft-Start Capacitor and Allows Soft Recovery from
(b) a Short-Circuit or (c) a VIN Dropout
VIN Undervoltage Lockout (UVLO)
The LTC3864 is designed to accommodate applications
requiring widely varying power input voltages from 3.5V
to 60V. To accommodate the cases where VIN drops
significantly once in regulation, the LTC3864 is
VBATTERY
12V
VOLTAGE
VOLTAGE
VOUT
guaranteed to operate down to a VIN of 3.5V over the full
temperature range.
VOUT
5V
LTC3864’s 100% DUTY CYCLE CAPABILITY ALLOWS
VOUT TO RIDE VIN WITHOUT SIGNIFICANT DROP-OUT
TIME
3864 F07
Figure 7. Typical Automotive Cold Crank
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LTC3864
Applications Information
Minimum On-Time Considerations
The minimum on-time, tON(MIN), is the smallest time
duration that the LTC3864 is capable of turning on the
power MOSFET, and is typically 220ns. It is determined
by internal timing delays and the gate charge required to
turn on the MOSFET. Low-duty-cycle applications may
approach this minimum on-time limit, so care should be
taken to ensure that:
t ON(MIN) <
I 
PPMOSTRL = VIN2 •  OUT  • (CMILLER) •
 2 

RUP 
RDN
+
 (V – V ) – V
•f
 IN CAP
MILLER VMILLER 
VOUT
VIN(MAX) • f
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will skip cycles.
However, the output voltage will continue to regulate.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
the dominant contributors and therefore where efficiency
improvements can be made. Percent efficiency can be
expressed as:
% Efficiency = 100% - (L1+L2+L3+…)
where L1, L2, L3, etc., are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources account for most of the losses
in LTC3864 application circuits.
1.
2. Transition Loss: Transition loss of the P-channel MOSFET becomes significant only when operating at high
input voltages (typically 20V or greater.) The P-channel
transition losses (PPMOSTRL) can be determined from
the following equation:
I2R Loss: I2R losses result from the P-channel MOSFET
resistance, inductor resistance, the current sense resistor, and input and output capacitor ESR. In continuous
mode operation the average output current flows through
L but is chopped between the P-channel MOSFET and
the bottom side Schottky diode. The following equation
may be used to determine the total I2R loss:
PI2R ≈(I2OUT +∆I2L/12)•[ RDCR+D•(RDS(ON)+RSENSE
+ RESR(CIN))] + ∆I2L/ 12 • RESR(COUT)
3. Gate Charging Loss: Charging and discharging the gate
of the MOSFET will result in an effective gate charging current. Each time the P-channel MOSFET gate is
switched from low to high and low again, a packet of
charge dQ moves from the capacitor across VIN – VCAP
and is then replenished from ground by the internal VCAP
regulator. The resulting dQ/dt current is a current out
of VIN flowing to ground. The total power loss in the
controller including gate charging loss is determined
by the following equation:
PCNTRL = VIN • (IQ + f •QG(PMOSFET))
4. Schottky Loss: The Schottky diode loss is most significant at low duty factors (high step down ratios). The
critical component is the Schottky forward voltage as
a function of junction temperature and current. The
Schottky power loss is given by the equation below.
PDIODE ≅ (1–D)•IOUT • VF(IOUT,TJ)
When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency.
If changes cause the input current to decrease, then the
efficiency has increased. If there is no change in input
current, there is no change in efficiency.
OPTI-LOOP® Compensation
OPTI-LOOP compensation, through the availability of the
ITH pin, allows the transient response to be optimized for
a wide range of loads and output capacitors. The ITH pin
not only allows optimization of the control loop behavior
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LTC3864
Applications Information
but also provides a test point for the step-down regulator ’s
DC-coupled and AC-filtered closed-loop response. The DC
step, rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at this pin.
The ITH series RITH-CITH1 filter sets the dominant pole-zero
loop compensation. Additionally, a small capacitor placed
from the ITH pin to signal ground, CITH2, may be required to
attenuate high frequency noise. The values can be modified
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because their various types and values determine
the loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1μs to 10μs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The general
goal of OPTI-LOOP compensation is to realize a fast but
stable ITH response with minimal output droop due to
the load step. For a detailed explanation of OPTI-LOOP
compensation, refer to Application Note 76.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ∆ILOAD • ESR, where
ESR is the effective series resistance of COUT . ∆ILOAD also
begins to charge or discharge COUT , generating a feedback
error signal used by the regulator to return VOUT to its
steady-state value. During this recovery time, VOUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
Connecting a resistive load in series with a power MOSFET,
then placing the two directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce a realistic load-step condition. The initial output voltage step resulting from the step
change in output current may not be within the bandwidth
of the feedback loop, so this signal cannot be used to
determine phase margin. This is why it is better to look
at the ITH pin signal which is in the feedback loop and
is the filtered and compensated feedback loop response.
The gain of the loop increases with RITH and the bandwidth
of the loop increases with decreasing CITH1. If RITH is
increased by the same factor that CITH1 is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, a feedforward capacitor, CFF, can
be added to improve the high frequency response, as shown
in Figure 1. Capacitor CFF provides phase lead by creating
a high frequency zero with RFB2 which improves the phase
margin. The output voltage settling behavior is related to
the stability of the closed-loop system and will demonstrate
overall performance of the step-down regulator.
In some applications, a more severe transient can be caused
by switching in loads with large (>10μF) input capacitors.
If the switch connecting the load has low resistance and
is driven quickly, then the discharged input capacitors are
effectively put in parallel with COUT , causing a rapid drop in
VOUT . No regulator can deliver enough current to prevent
this problem. The solution is to limit the turn-on speed of
the load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates current limiting, short-circuit protection and soft starting.
Design Example
Consider a step-down converter with the following
specifications: VIN = 5V to 55V, VOUT = 5V, IOUT(MAX) = 2A,
and f = 350kHz (Figure 8).
The output voltage is programmed according to:
 R 
VOUT = 0.8V •  1+ FB2 
 RFB1 
If RFB1 is chosen to be 80.6k, then RFB2 would have to
be 422k.
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LTC3864
Applications Information
Next, set the RSENSE resistor value to ensure that the
converter can deliver a maximum output current of 2.0A
with sufficient margin to account for component variations and worst-case operating conditions. Using a 30%
margin factor:
The FREQ pin is tied to signal ground in order to program
the switching frequency to 350kHz. The on-time required
at 55V to generate a 5V output can be calculated as:
V
5V
tON = OUT =
≈ 260ns
VIN • f 55V • 350kHz
RSENSE ≅
This on-time is larger than LTC3864’s minimum on-time
with sufficient margin to prevent cycle skipping.
Next, set the inductor value to give 60% worst-case ripple
at maximum VIN = 55V.
Use a more readily available 25mΩ sense resistor.
The current limit is:

  5V 
5V
L=
1–
 ≈ 10.8µH
350kHz •(0.6 • 2A)   55V
ILIMIT ≅
Select 10µH, which is a standard value.

  5V 
5V
1–
≈ 1.3A
∆IL = 
350kHz •10µH  55V 
CAP
VIN
MODE/PLLN
RITH 9.53k
CVIN
0.1µF
LTC3864
CIN1
12µF
63V
90
RSENSE
25mΩ
MP
GATE
ITH
SW
CITH2 100pF
D1
FREQ
PGOOD
SGND
PGND
CIN1: NICHICON UPJ1J120MDD
D1: DIODES INC SBR3U100LP
L1: TOKO 1217AS-H-100M
MP: FAIRCHILD FDMC5614P
+
100
SENSE
SS
CITH1
3.3nF
CIN2
4.7µF
Efficiency
VIN*
5.2V TO 55V
EFFICIENCY (%)
CCAP
0.47µF
RUN
CSS
0.1µF
95mV 1.3A
–
≈ 3.15A
25mΩ
2
Next choose a P-channel MOSFET with the appropriate BVDSS and ID rating. In this example, a good choice
is the Fairchild FDMC5614P (BVDSS = 60V, ID = 5.7A,
RDS(ON) = 105mΩ, ρ100°C = 1.5, CMILLER = 100pF,
θJA = 60°C/W). The expected power dissipation and the
The resulting maximum ripple current is:
RRUN
100k
95mV
≈ 27.5mΩ
1.3A 

1.3 •  2A +


2 
L1
10µH
RPGD
100k
CFF
47pF
VOUT*
5V
47µF 2A
×2
RFB2
422k
Burst Mode
OPERATION
80
PULSE-SKIPPING
70
60
50
0.01
VIN = 12V
VOUT = 5V
0.1
LOAD CURRENT (A)
1
3864 F08b
VFB
RFB1
80.6k
3864 F08a
*VOUT FOLLOWS VIN WHEN 3.5V ≤ VIN ≤ 5.2V
SEE DROPOUT BEHAVIOR IN TYPICAL PERFORMANCE CHARACTERISTICS
Figure 8. Design Example (5V, 2A 350kHz Step-Down Converter)
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21
LTC3864
Applications Information
resulting junction temperature for the MOSFET can be
calculated at TA = 70°C, VIN(MAX) = 55V and IOUT(MAX) = 2A:
5V
(2A)2 •1.5 •105mΩ +
55V
 0.9Ω  2Ω
+
(55V)2 •(2A / 2)•100pF • 
• 350kHz
 8V – 3V  3V
≈ 57mW + 90mW = 147mW
PPMOS =
TJ = 70°C+147mW • 60°C/W ≈ 80°C
The calculations can be repeated for VIN(MIN) = 5V:
5V
(2A)2 •1.5 •105mΩ +
5V
2Ω 
 0.9Ω
• 350kHz
(5.2V)2 •100pF • 
+
 5.2V – 3V 3V 
≈ 630mW +1mW ≈ 631mW
TJ = 70°C+ 631mW • 60°C / W ≈ 108°C
PPMOS =
Next choose an appropriate Schottky diode that will handle
the power requirements. The Diodes Inc. SBR3U100LP
Schottky diode is selected (VF(2A,125°C) = 0.5V, θJA = 61°C/W)
for this application. The power dissipation and junction
temperature at TA = 70°C can be calculated as:
 5V 
• 0.5V ≈ 909mW
PDIODE = 2A • 1–
 55V 
TJ = 70°C+909mW • 61°C/W = 125°C
These power dissipation calculations show that careful
attention to heat sinking will be necessary.
For the input capacitance, a combination of ceramic and
electrolytic capacitors are chosen to handle the maximum
RMS current of 1A. COUT will be selected based on the
ESR that is required to satisfy the output voltage ripple
requirement. For this design, two 47µF ceramic capacitors
are chosen to offer low ripple in both normal operation
and in Burst Mode operation.
A soft-start time of 8ms can be programmed through a
0.1µF capacitor on the SS pin:
CSS =
8ms •10µA
= 0.1µF
0.8V
Loop compensation components on the ITH pin are chosen
based on load step transient behavior (as described under
OPTI-LOOP Compensation) and is optimized for stability. A
pull-up resistor is used on the RUN pin for FMEA compliance (see Failure Modes and Effects Analysis).
Gate Driver Component Placement,
Layout and Routing
It is important to follow recommended power supply PC
board layout practices such as placing external power elements to minimize loop area and inductance in switching
paths. Be careful to pay particular attention to gate driver
component placement, layout and routing.
The effective CCAP capacitance should be greater than 0.1µF
minimum in all operating conditions. Operating voltage
and temperature both decrease the rated capacitance to
varying degrees depending on dielectric type. The LTC3864
is a PMOS controller with an internal gate driver and bootstrapped LDO that regulates the differential CAP voltage
(VIN – VCAP) to 8V nominal. The CCAP capacitance needs
to be large enough to assure stability and provide cycleto-cycle current to the PMOS switch with minimum series
inductance. We recommend a ceramic 0.47µF 16V capacitor
with a high quality dielectric such as X5R or X7R. Some
high current applications with large Qg PMOS switches
may benefit from an even larger CCAP capacitance.
Figure 9 shows the LTC3864 Generic Application Schematic which includes an optional current sense filter and
series gate resistor. Figure 10 illustrates the recommended
gate driver component placement, layout and routing of
the GATE, VIN, SENSE and CAP pins and key gate driver
components. It is recommended that the gate driver layout
follow the example shown in Figure 10 to assure proper
operation and long term reliability.
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LTC3864
Applications Information
The LTC3864 gate driver should connect to the external
power elements in the following manner. First route the
VIN pin using a single low impedance isolated trace to
the positive RSENSE resistor PAD without connection to
the VIN plane. The reason for this precaution is that the
VIN pin is internally Kelvin connected to the current sense
comparator, internal VIN power and the PMOS gate driver.
Connecting the VIN pin to the VIN power plane adds noise
and can result in jitter or instability. Figure 10 shows a
single VIN trace from the positive RSENSE pad connected
to CSF, CCAP, VIN pad and CINB. The total trace length to
RSENSE should be minimized and the capacitors CSF, CCAP
and CINB should be placed near the VIN pin of the LTC3864.
CINB
VIN
CIN
CCAP
CAP
RUN
CSS
VIN
CPITH
SENSE
SS
GATE
CITH
CSF
PLLIN/MODE
RITH
RFREQ
RGATE
RSENSE
–
Q1 D1
VOUT
COUT
LTC3864
L1
ITH
RPGD
FREQ
SGND
GROUND
PLANE
TO PGND
RSF
+
PGOOD
RFB2
PGND
VFB
RFB1
3864 F09
Figure 9. LTC3864 Generic Application Schematic with Optional
Current Sense Filter and Series Gate Resistor
CINB
TO Q1 GATE
RGATE
GATE
CSF
TO RSENSE+
VIN
SENSE
CAP
CCAP should be placed near the VIN and CAP pins. Figure 10
shows CCAP placed adjacent to the VIN and CAP pins with
SENSE routed between the pads. This is the recommended
layout and results in the minimum parasitic inductance.
The gate driver is capable of providing high peak current.
Parasitic inductance in the gate drive and the series inductance between VIN to CAP can cause a voltage spike
between VIN and CAP on each switching cycle. The voltage
spike can result in electrical over-stress to the gate driver
and can result in gate driver failures in extreme cases. It
is recommended to follow the example shown in Figure 10
for the placement of CCAP as close as is practical.
RGATE resistor pads can be added with a 0Ω resistor to
allow the damping resistor to be added later. The total
length of the gate drive trace to the PMOS gate should
be minimized and ideally be less than 1cm. In most cases
with a good layout the RGATE resistor is not needed. The
RGATE resistor should be located near the gate pin to reduce peak current through GATE and minimize reflected
noise on the gate pin.
The RSF and CSF pads can be added with a zero ohm resistor for RSF and CSF not populated. In most applications,
external filtering is not needed. The current sense filter
RSF and CSF can be added later if noise if demonstrated
to be a problem.
The bypass capacitor CINB is used to locally filter the
VIN supply. CINB should be tied to the VIN pin trace and
to the PGND exposed pad. The CINB positive pad should
connect to RSENSE positive though the VIN pin trace. The
CINB ground trace should connect to the PGND exposed
pad connection.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3864.
1. Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking pur-
CCAP
RSF
TO RSENSE–
3864 F10
Figure 10. LTC3864 Recommended Gate Driver PC
Board Placement, Layout and Routing
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23
LTC3864
Applications Information
poses. Use wide rails and/or entire planes for VIN, VOUT
and GND for good filtering and minimal copper loss. If
a ground layer is used, then it should be immediately
below (and/or above) the routing layer for the power
train components which consist of CIN, sense resistor,
P-MOSFET, Schottky diode, inductor, and COUT. Flood
unused areas of all layers with copper for better heat
sinking.
2. Keep signal and power grounds separate except at the
point where they are shorted together. Short signal and
power ground together only at a single point with a
narrow PCB trace (or single via in a multilayer board).
All power train components should be referenced to
power ground and all small signal components (e.g.,
CITH1, RFREQ, CSS etc.) should be referenced to signal
ground.
3. Place CIN, sense resistor, P-MOSFET, inductor, and
primary COUT capacitors close together in one compact
area. The junction connecting the drain of P-MOSFET,
cathode of Schottky, and (+) terminal of inductor (this
junction is commonly referred to as switch or phase
node) should be compact but be large enough to handle
the inductor currents without large copper losses. Place
the sense resistor and source of P-channel MOSFET
as close as possible to the (+) plate of CIN capacitor(s)
that provides the bulk of the AC current (these are
normally the ceramic capacitors), and connect the
anode of the Schottky diode as close as possible to
the (–) terminal of the same CIN capacitor(s). The high
dI/dt loop formed by CIN, the MOSFET, and the Schottky
diode should have short leads and PCB trace lengths to
minimize high frequency EMI and voltage stress from
inductive ringing. The (–) terminal of the primary COUT
capacitor(s) which filter the bulk of the inductor ripple
current (these are normally the ceramic capacitors)
should also be connected close to the (–) terminal of CIN.
4. Place pins 7 to 12 facing the power train components.
Keep high dV/dt signals on GATE and switch away from
sensitive small signal traces and components.
5. Place the sense resistor close to the (+) terminal of CIN
and source of P-MOSFET. Use a Kelvin (4-wire) connection across the sense resistor and route the traces
together as a differential pair into the VIN and SENSE
pins. An optional RC filter could be placed near the VIN
and SENSE pins to filter the current sense signal.
6. Place the resistive feedback divider RFB1/2 as close as
possible to the VFB pin. The (+) terminal of the feedback
divider should connect to the output regulation point
and the (–) terminal of feedback divider should connect
to signal ground.
7. Place the ceramic CCAP capacitor as close as possible
to VIN and CAP pins. This capacitor provides the gate
discharging current for the power P-MOSFET.
8. Place small signal components as close to their respective pins as possible. This minimizes the possibility of
PCB noise coupling into these pins. Give priority to
VFB, ITH, and FREQ pins. Use sufficient isolation when
routing a clock signal into PLLIN /MODE pin so that the
clock does not couple into sensitive small signal pins.
Failure Mode and Effects Analysis (FMEA)
A FMEA study on the LTC3864 has been conducted through
adjacent pin opens and shorts. The device was tested
in a step-down application (Figure 8) from VIN = 12V to
VOUT = 5V with a current load of 1A on the output. One
group of tests involved the application being monitored
while each pin was disconnected from the PC board
and left open while all other pins remained intact. The
other group of tests involved each pin being shorted to
its adjacent pins while all other pins were connected as
it would be normally in the application. The results are
shown in Table 2.
For FMEA compliance, the following design implementations are recommended:
• If the RUN pin is being pull-up to a voltage greater than
6V, then it is done so through a pull-up resistor (100k
to 1M) so that the PGOOD pin is not damaged in case
of a RUN to PGOOD short.
• The gate of the external P-MOSFET be pulled through
a resistor (20k to 100k) to the input supply, VIN so that
the P-MOSFET is guaranteed to turn off in case of a
GATE open.
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LTC3864
Applications Information
Table 2
FAILURE MODE
None
RECOVERY
WHEN
FAULT IS
REMOVED? BEHAVIOR
VOUT
IOUT
IVIN
f
5V
1A
453mA
350kHz
N/A
Normal Operation.
5V
1A
453mA
350kHz
OK
Pin already left open in normal application, so no difference.
Pin Open
Open Pin 1 (PLLIN/MODE)
Open Pin 2 (FREQ)
5V
1A
453mA
535kHz
OK
Frequency jumps to default open value.
Open Pin 3 (GND)
5V
1A
453mA
350kHz
OK
Exposed pad still provides GND connection to device.
Open Pin 4 (SS)
5V
1A
453mA
350kHz
OK
External soft-start removed, but internal soft-start still available.
Open Pin 5 (VFB)
0V
0A
0.7mA
0kHz
OK
Controller stops switching. VFB internally self biases HI to prevent
switching.
Open Pin 6 (ITH)
5V
1A
507mA
40kHz
OK
Output still regulating, but the switching is erratic. Loop not stable.
Open Pin 7 (PGOOD)
5V
1A
453mA
350kHz
OK
No PGOOD output, but controller regulates normally.
Open Pin 8 (RUN)
5V
1A
453mA
350kHz
OK
Controller does not start-up.
Open Pin 9 (CAP)
5V
1A
453mA
350kHz
OK
More jitter during switching, but regulates normally.
Open Pin 10 (SENSE)
0V
0A
0.7mA
0kHz
OK
SENSE internally prebiases to 0.6V below VIN. This prevents
controller from switching.
5.4V
1A
597mA
20kHz
OK
VIN able to bias internally through SENSE. Regulates with high VOUT
ripple.
Open Pin 12 (GATE)
0V
0A
Open Pin 13 (PGND)
5V
Open Pin 11 (VIN)
0.7mA
0kHz
OK
Gate does not drive external power FET, preventing output regulation.
453mA
350kHz
OK
Pin 3 (GND) still provides GND connection to device.
Pins Shorted
Short Pins 1, 2
(PLLIN/MODE and FREQ)
5V
1A
453mA
350kHz
OK
Burst Mode operation disabled, but runs normally as in pulse-skipping
mode.
Short Pins 2, 3
(FREQ and GND)
5V
1A
453mA
0kHz
OK
FREQ already shorted to GND, so regulates normally.
Short Pins 3, 4
(GND and SS)
0V
0A
0.7mA
0kHz
OK
SS short to GND prevents device from starting up.
Short Pins 4, 5
(SS and VFB)
1V(DC)
3VP-P
50mA
9mA
Erratic
OK
VOUT oscillates from 0V to 3V.
Short Pins 5, 6
(VFB and ITH)
3.15V
625mA
181mA
350kHz
OK
Controller loop does not regulate to proper output voltage.
Short Pins 7, 8
(PGOOD and RUN)
5V
1A
453mA
350kHz
OK
Controller does not start-up.
Short Pins 8, 9
(RUN and CAP)
5V
1A
453mA
350kHz
OK
Able to start-up and regulate normally.
Short Pins 9, 10
(CAP and SENSE)
0V
0A
181mA
0kHz
OK
CAP ~ VIN, which prevents turning on external P-MOSFET.
Short Pins 10, 11
(SENSE and VIN)
5V
1A
453mA
50kHz
OK
Regulates with high VOUT ripple.
Short Pins 11, 12
(VIN and GATE)
0V
0A
29mA
0kHz
OK
Power MOSFET is always kept OFF, preventing regulation.
3864fa
For more information www.linear.com/LTC3864
25
LTC3864
Typical Applications
24V to 60V Input, 24V/1A Output at 750kHz
Efficiency
CCAP
0.47µF
CIN2
2.2µF
+
RUN
VIN
MODE/PLLN
CVIN
0.1µF
VIN
24V TO 60V
90
80
EFFICIENCY (%)
CAP
CIN1
33µF
63V
100
RSENSE
50mΩ
SENSE
CITH1
6.8nF
RITH 30.1k
SS
ITH
MP
GATE
LTC3864
CITH2 100pF
RFREQ 97.6k
PGOOD
SGND
VFB
PGND
CIN1: NICHICON UPJ1J100MPD
D1: DIODES INC SBR3U100LP
L1: TOKO 1217AS-H-470M
MP: VISHAY/SILICONIX SI7113DN
70
60
PULSE-SKIPPING
50
L1
47µH
RPGD2
768k
D1
FREQ
Burst Mode
OPERATION
10µF
VOUT*
24V
1A
40
30
0.01
RFB2
887k
RPGD1
200k
VIN = 48V
VOUT = 24V
0.1
LOAD CURRENT (A)
1
3864 TA02b
RFB1
30.1k
3864 TA02a
*VOUT FOLLOWS VIN WHEN 3.5V ≤ VIN ≤ 24V
3.5V to 48V Input, 1.8V/4A Output at 100kHz
Efficiency
CIN2
10µF
×2
CAP
RUN
CSS
0.1µF
CITH1
10nF
VIN
MODE/PLLN
ITH
LTC3864
GATE
CITH2 100pF
RFREQ 24.3k
70
RSENSE
15mΩ
MP
D1
PGOOD
FREQ
SGND
CIN1
33µF
63V
SENSE
SS
RITH 14k
CVIN
0.1µF
+
EFFICIENCY (%)
CCAP
0.47µF
80
VIN
3.5V TO 48V
VFB
PGND
L1
10µH
100µF
×2
RPGD
100k
RFB2
102k
+
VOUT
1.8V
4A
330µF
6.3V
Burst Mode
OPERATION
60
PULSE-SKIPPING
50
40
30
0.01
VIN = 12V
VOUT = 1.8V
0.1
1
LOAD CURRENT (A)
3864 TA03b
RFB1
80.6k
3864 TA03a
CIN1: SANYO 63ME33AX
D1: VISHAY V10P10
L1: WÜRTH 7447709100
MP: VISHAY/SILICONIX SI7461DP
3864fa
26
For more information www.linear.com/LTC3864
LTC3864
Typical Applications
12V to 58V Input, 12V/2A Output at 535kHz
CCAP
0.47µF
CIN2
4.7µF
+
CAP
VIN
MODE/PLLN
CVIN
0.1µF
VIN
12V TO 58V
Efficiency
90
RSENSE
30mΩ
SENSE
CITH1
3300pF
SS
RITH 11.3k
LTC3864
MP
GATE
L1
22µH
ITH
CITH2 100pF
D1
FREQ
RPGD2
549k
PGND
CIN1: SANYO 63ME33AX
D1: DIODES INC SBR3U100LP
L1: TOKO 1217AS-H-220M
MP: VISHAY/SILICONIX SI7465DP
10µF
×2
VOUT*
12V
2A
VFB
RPGD1
402k
70
PULSE-SKIPPING
60
RFB2
845k
PGOOD
SGND
Burst Mode
OPERATION
80
EFFICIENCY (%)
RUN
CIN1
33µF
63V
VIN = 48V
VOUT = 12V
50
0.01
0.1
LOAD CURRENT (A)
RFB1
60.4k
1
3864 TA04b
3864 TA04a
*VOUT FOLLOWS VIN WHEN 3.5V ≤ VIN ≤ 12V
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
4.00 ±0.10
(2 SIDES)
7
0.70 ±0.05
3.60 ±0.05
2.20 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
0.40 ± 0.10
12
R = 0.05
TYP
3.30 ±0.05
1.70 ± 0.05
R = 0.115
TYP
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
1.70 ± 0.10
0.75 ±0.05
6
0.25 ± 0.05
1
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
(UE12/DE12) DFN 0806 REV D
0.50 BSC
2.50 REF
2.50 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3864fa
For more information www.linear.com/LTC3864
27
LTC3864
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
5.23
(.206)
MIN
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
6
1
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102 3.20 – 3.45
(.065 ±.004) (.126 – .136)
12
0.65
0.42 ±0.038
(.0256)
(.0165 ±.0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
7
NO MEASUREMENT PURPOSE
0.406 ±0.076
(.016 ±.003)
REF
12 11 10 9 8 7
DETAIL “A”
0° – 6° TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
1 2 3 4 5 6
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.86
(.034)
REF
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE12) 0911 REV F
3864fa
28
For more information www.linear.com/LTC3864
LTC3864
Revision History
REV
DATE
DESCRIPTION
A
6/14
Modified VIN to CAP capacitance
PAGE NUMBER
Updated Notes 2 and 3
1, 8, 10, 21,
25, 26, 28
2
3864fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
information
www.linear.com/LTC3864
tion that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
29
LTC3864
Typical Application
3.5V to 38V Input, 3.3V/3A Output at 300kHz
CIN2
10µF
×2
CAP
RUN
CSS
0.1µF
CITH1
10nF
VIN
CIN1
33µF
63V
RSENSE
20mΩ
LTC3864
ITH
MP
GATE
VOUT
3.3V
47µF 3A
×2
L1
6.8µH
RFREQ 42.2k
SGND
PGND
RPGD
100k
60
PULSE-SKIPPING
40
0.01
RFB2
634k
PGOOD
FREQ
70
50
CITH2 100pF
D1
Burst Mode
OPERATION
80
SENSE
SS
RITH 20k
CVIN
0.1µF
MODE/PLLN
+
90
EFFICIENCY (%)
CCAP
0.47µF
Efficiency
VIN
3.5V TO 60V
VIN = 12V
VOUT = 3.3V
0.1
LOAD CURRENT (A)
1
3864 TA05b
VFB
RFB1
200k
3864 TA05a
CIN1: SANYO 63ME33AX
D1: VISHAY V15P45S
L1: WÜRTH 7447709100
MP: VISHAY/SILICONIX Si7611DN
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC3891
60V, Low IQ, Synchronous Step-Down DC/DC
Controller
Phase-Lockable Fixed Frequency 50kHz to 900kHz 4V ≤ VIN ≤ 60V,
0.8V ≤ VOUT ≤ 24V, IQ = 50µA
LTC3890
60V, Low IQ, Dual 2-Phase Synchronous
Step-Down DC/DC Controller
Phase-Lockable Fixed Frequency 50kHz to 900kHz 4V ≤ VIN ≤ 60V,
0.8V ≤ VOUT ≤ 24V, IQ = 50µA
LTC3824
60V, Low IQ, Step-Down DC/DC Controller, 100%
Duty Cycle
Selectable Fixed Frequency 200kHz to 600kHz 4V≤ VIN ≤ 60V,
0.8V ≤ VOUT ≤ VIN, IQ = 40µA, MSOP-10E
LT3845A
60V, Low IQ, Single Output Synchronous
Step-Down DC/DC Controller
Synchronizable Fixed Frequency 100kHz to 600kHz 4V ≤ VIN ≤ 60V,
1.23V ≤ VOUT ≤ 36V, IQ = 120µA, TSSOP-16
LTC3863
60V Low IQ Inverting DC/DC Controller
PLL Fixed Frequency 75kHz to 750kHz, 3.5V ≤ VIN ≤ 60V –150V ≤ VOUT ≤
–0.4V, IQ = 70µA, 3mm × 4mm DFN-12, MSOP-12
LTC3834/LTC3834-1
LTC3835/LTC3835-1
Low IQ, Single Output Synchronous Step-Down
DC/DC Controller with 99% Duty Cycle
Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V ≤ VIN ≤ 36V,
0.8V ≤ VOUT ≤ 10V, IQ = 30µA/80µA
LTC3857/LTC3857-1
LTC3858/LTC3858-1
Low IQ, Dual Output 2-Phase Synchronous
Step-Down DC/DC Controllers with 99% Duty
Cycle
Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 24V, IQ = 50µA/170µA
LTC3859AL
Low IQ, Triple Output Buck/Buck/Boost
Synchronous DC/DC Controller
All Outputs Remain in Regulation Through Cold Crank 2.5V ≤ VIN ≤ 38V,
VOUT(BUCKS) Up to 24V, VOUT(BOOST) Up to 60V, IQ = 28µA
3864fa
30 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC3864
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC3864
LT 0614 REV A • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2012
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