LTC4263-1 High Power Single PSE Controller with Internal Switch FEATURES DESCRIPTION n The LTC®4263-1 is a high power, single PSE controller for use in Power over Ethernet systems. The internal current limit and short-circuit protection are designed to provide up to 30W of PSE output power for power hungry PoE applications such as WAPs, security cameras and RFID readers. n n n n n n n n n n n n 30W PSE Output Power IEEE 802®.3af Compatible Operation from a Single 56V Supply Fully Autonomous Operation Without a Microcontroller Internal MOSFET with Thermal Protection Precision Inrush Control with Internal Sense Resistor Forced Current PD Detection for Noise Immunity AC and DC Disconnect Sensing Legacy PD Detection Robust Short-Circuit Protection Pin-Selectable Detection Backoff for Midspan PSEs LED Driver Indicates Port On and Blinks Status Codes Available in a Miniature14-Pin 4mm × 3mm DFN Package APPLICATIONS n n n n n High Power Endpoint/Midspan PSEs Single-Port or Multi-Port Power Injectors Low Port Count PSEs Environment B PSEs Standalone PSEs The LTC4263-1 includes IEEE 802.3af compliant PD detection circuitry along with selectable AC and DC disconnect sensing, allowing seamless operation in conventional IEEE 802.3af systems as well as propriety, high power applications. The LTC4263-1 simplifies PSE implementation, needing only a single supply and a small number of passive support components. Onboard control algorithms provide complete PSE functionality without the need of a microcontroller and built-in foldback and thermal shutdown provide comprehensive fault protection. An LED pin indicates the state of the port and detection backoff timing is configurable for either endpoint or midspan operation. The LTC4263-1 is available in a miniature 14-pin 4mm × 3mm DFN package. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Single-Port Fully Autonomous High Power PSE 1A + 0.1μF 100V ISOLATED 56V SUPPLY LED 0.1μF LEGACY MIDSPAN – 0.1μF 100V LTC4263-1 VSS VDD5 VSS SMAJ58A TO PORT MAGNETICS SD VDD48 VSS OUT VSS OUT OSC ACOUT 42631 TA01 42631fa 1 LTC4263-1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1, Note 2) Supply Voltages VSS – VDD48 ........................................... 0.3V to –80V VDD5........................................VSS – 0.3V to VSS + 6V Pin Voltages and Currents LEGACY, MIDSPAN, SD, OSC ..VSS – 0.3V to VSS +6V LED .......................................VSS – 0.3V to VSS + 80V OUT, ACOUT ............................................ (See Note 3) Operating Ambient Temperature Range LTC4263CDE-1 ............................................ 0°C to 70°C LTC4263IDE-1 ......................................... –40°C to 85°C Junction Temperature (Note 4) ............................. 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) .................. 300°C TOP VIEW LED 1 14 VDD5 LEGACY 2 MIDSPAN 3 13 VSS 12 SD 15 VSS 4 VSS 5 10 OUT VSS 6 9 OUT OSC 7 8 ACOUT 11 VDD48 DE14 PACKAGE 14-LEAD (4mm s 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W, θJC = 4.3°C/W EXPOSED PAD (PIN 15) IS VSS, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4263CDE-1#PBF LTC4263IDE-1#PBF LTC4263CDE-1#TRPBF LTC4263IDE-1#TRPBF 42631 42631 14-Lead (4mm × 3mm) Plastic DFN 14-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD48 – VSS = 48V and VDD5 not driven externally. All voltages are relative to VSS unless otherwise noted. (Note 2, Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX VSUPPLY Supply Voltage VDD48 – VSS 30W Output Power VUVLO_OFF UVLO Turn-Off Voltage VDD48 – VSS Decreasing VUVLO_HYS UNITS l 33 48 56 66 V V l 29 31 33 V UVLO Hysteresis l 0.1 1 V VOVLO_OFF OVLO Turn-Off Voltage l 66 VOVLO_HYS OVLO Hysteresis l 0.2 VDD5 VDD5 Supply Voltage Driven Externally l 4.5 VDD5 Internal Supply Driven Internally l 4.3 IDD48 VDD48 Supply Current l l IDD5 VDD5 Supply Current VDD5 – VSS = 5V Internal VDD5 VDD5 – VSS = 5V Power Supplies VDD48 – VSS Increasing l 70 74 V 2 V 5 5.5 V 4.4 4.5 V 1 2 1 2 4 2 mA mA mA 42631fa 2 LTC4263-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD48 – VSS = 48V and VDD5 not driven externally. All voltages are relative to VSS unless otherwise noted. (Note 2, Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX RON On-Resistance I = 350mA, Measured From OUT to VSS IOUT_LEAK OUT Pin Leakage VOUT – VSS = VDD48 – VSS = 57V l RPU OUT Pin Pull-Up Resistance to VDD48 0V ≤ (VDD48 – VOUT) ≤ 5V l 360 l UNITS 1.5 1 2.4 3.0 10 Ω Ω μA 500 640 kΩ 540 570 600 mA Power MOSFET l Current Control ICUT Overload Current Threshold ILIM Short-Circuit Current Limit VOUT – VSS = 5V VDD48 – VOUT = 30V l l 615 615 645 645 675 675 mA mA IFB Foldback Current Limit VDD48 – VOUT = 0V (Note 6) VDD48 – VOUT = 10V l l 45 165 90 220 180 275 mA mA IMIN DC Disconnect Current Threshold IFAULT High Speed Fault Current Limit IDET l 5.2 7.5 9.8 mA (Note 7) l 750 1000 1200 mA Detection Current First Point, VDD48 – VOUT = 10V Second Point, VDD48 – VOUT = 3.5V l l 235 160 255 180 275 200 μA μA VDET Detection Voltage Compliance VDD48 – VOUT, Open Port VDD48 – VSS = 57V l 21 V RDETMIN Minimum Valid Signature Resistance l 15.5 17 18.5 kΩ RDETMAX Maximum Valid Signature Resistance l 27.5 29.7 32 kΩ ROPEN Open-Circuit Threshold l 500 2000 kΩ 325 kΩ 140 μA Detection AC Disconnect ROSC OSC Pin Input Impedance 2V ≤ (VOSC – VSS) ≤ 3V l 175 IOSC OSC Pin Output Current VOSC – VSS = 2V l –140 fOSC OSC Pin Frequency VOSC – VSS = 2V l 103 110 115 Hz AVACD Voltage Gain OSC to ACOUT 2V ≤ (VOSC – VSS) ≤ 3V l 0.95 1.0 1.05 V/V IACDMAX AC Disconnect Output Current VOSC – VSS = 2V, 0V ≤ (VACOUT – VSS) ≤ 4V l –1 1 mA 130 190 μA 1.5 IACDMIN Remain Connected AC Pin Current VOSC – VSS = 2V l VACDEN AC Disconnect Enable Signal VOSC – VSS, Port On l 250 160 V Digital Interface (Note 8) VOLED LED Output Low Voltage ILED = 10mA l VILD Digital Input Low Voltage MIDSPAN, SD LEGACY l l VIHD Digital Input High Voltage MIDSPAN, SD LEGACY l l 2.2 2.2 VOZ Voltage of Legacy Pin if Left Floating l 1.1 IOLEG Current In/Out of Legacy Pin l l IFLT Maximum Allowed Leakage at Legacy Pin When Floating 0V ≤ (VLEGACY – VSS) ≤ 5V 1.1 2.2 V 0.8 0.4 V V V V 1.25 1.4 V –60 60 μA –10 10 μA 42631fa 3 LTC4263-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD48 – VSS = 48V and VDD5 not driven externally. All voltages are relative to VSS unless otherwise noted. (Note 2, Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 290 310 ms 620 ms 155 ms Timing Characteristics tDET Detection Time Beginning to End of Detection l 270 tDETDLY Detection Delay PD Insertion to Detection Complete l 300 tPON Power Turn-On Delay End of Valid Detect to Application of Power l 135 145 tRISE Turn-On Rise Time VDD48 – VOUT : 10% to 90% CPSE = 0.1μF l 40 170 tOVLD Overload/Short-Circuit Time Limit tED Error Delay tMPDO μs l 52 62 72 ms ICUT Fault to Next Detect l 3.8 4.0 4.2 s Maintain Power Signature (MPS) Disconnect Delay PD Removal to Power Removal l 320 350 380 ms tMPS MPS Minimum Pulse Width PD Minimum Current Pulse Width Required to Stay Connected (Note 9) l 20 ms tDBO Midspan Mode Detection Backoff RPORT = 15.5kΩ l 3.0 3.2 3.4 s tDISDLY Power Removal Detection Delay l 0.8 0.95 1.1 s Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VSS unless otherwise specified. Note 3: 80mA of current may be pulled from the OUT or ACOUT pin without damage whether the LTC4263-1 is powered or not. These pins will also withstand a positive voltage of VSS + 80V. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: The LTC4263-1 operates with a negative supply voltage. To avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. Note 6: In order to reduce power dissipated in the switch while charging the PD, the LTC4263-1 reduces the current limit when VOUT – VSS is large. Refer to the Typical Performance Characteristics for more information. Note 7: The LTC4263-1 includes a high-speed current limit circuit intended to protect against faults. The fault protection is activated for port current in excess of IFAULT. After the high-speed current limit activates, the short-circuit current limit (ILIM) engages and restricts current to IEEE 802.3af levels. Note 8: The LTC4263-1 digital interface operates with respect to VSS. All logic levels are measured with respect to VSS. Note 9: The IEEE 802.3af specification allows a PD to present its Maintain Power Signature (MPS) on an intermittent basis without being disconnected. In order to stay powered, the PD must present the MPS for tMPS within any tMPDO time window. 42631fa 4 LTC4263-1 TYPICAL PERFORMANCE CHARACTERISTICS Powering a Legacy PD with 470μF Bypass Capacitor Powering an IEEE 802.3af PD VDD48 VOUT 10V/DIV DETECTION DETECTION PHASE 1 PHASE 2 POWER ON VDD48 VOUT 20V/DIV VDD48 VSS VOUT 10V/DIV tED LOAD FULLY CHARGED 570mA CURRENT LIMIT 600mA IOUT 300mA/DIV 0mA VSS 100ms/DIV FOLDBACK 42631 G01 VSS IPORT 1A/DIV 500ms/DIV 42631 G02 25ms/DIV Midspan Backoff with Invalid PD VDD48 Overload Restart Delay Response to PD Removal with AC Disconnect Enabled Overcurrent Response Time VDD48 tDBO VDD48 VOUT 20V/DIV PORT OFF VOUT 10V/DIV VSS VOUT 2V/DIV PD REMOVAL 600mA IOUT 300mA/DIV 0mA RPORT = 15.5k 500ms/DIV tOVLD 10ms/DIV tMPDO 42631 G12 VDD48 VDD48 VOUT 20V/DIV VOUT 20V/DIV 1Ω SHORT APPLIED IPORT = CURRENT IN 1Ω RESISTOR APPLIED TO OUTPUT OF CIRCUIT ON FRONT PAGE 1μs/DIV 50ms/DIV 42631 G13 Rapid Response to Momentary 33Ω Short Rapid Response to 1Ω Short IPORT 20A 20A/DIV 0A PORT OFF VSS LOAD APPLIED 42631 G11 VSS 42631 G10 42631 G14 VSS 600mA IPORT 300mA/DIV 0mA 33Ω SHORT APPLIED SHORT CURRENT REMOVED LIMIT ACTIVE FOLDBACK CURRENT LIMIT 100μs/DIV 42631 G15 IPORT = CURRENT IN 33Ω RESISTOR APPLIED TO OUTPUT OF CIRCUIT ON FRONT PAGE 42631fa 5 LTC4263-1 TYPICAL PERFORMANCE CHARACTERISTICS 675 4 450 375 300 225 150 TA = 25°C 25k LOAD WITH AC ENABLED 2.0 3 IDD48 (mA) VLED PIN PULL-DOWN (V) 525 2.5 TA = 25°C INTERNAL VDD5 600 IOUT (mA) IDD48 DC Supply Current vs Supply Voltage with Internal VDD5 LED Pin Pull-Down vs Load Current Current Limit and Foldback 2 1 1.5 NO LOAD 1.0 0.5 75 0 0 0 5 10 15 20 25 30 35 40 45 50 VDD48 – VOUT (V) 0 10 20 30 40 ILED LOAD CURRENT (mA) 0 50 42631 G03 25k LOAD WITH AC ENABLED 1.0 30 40 VDD48 (V) 50 60 42631 G07 IDD5 DC Supply Current vs Supply Voltage 2 TA = 25°C 20 42631 G04 IDD48 DC Supply Current vs Supply Voltage with VDD5 = 5V 1.2 10 0 VDD48 = 48V 25k LOAD WITH AC ENABLED 1 NO LOAD IDD5 (mA) IDD48 (mA) 0.8 NO LOAD 0.6 0 –1 0.4 –2 0.2 0 –3 0 10 20 30 40 50 60 4.5 4.0 VDD48 (V) 5.0 VDD5 (V) 5.5 6.0 42631 G08 42631 G09 RON vs Temperature Legacy Pin Current vs Voltage 40 2.0 LEGACY MODE 20 ILEGACY (μA) RON (Ω) 1.8 1.6 1.4 FORCE POWER ON MODE 0 –20 1.2 1.0 –40 COMPLIANT DETECTION MODE –40 –20 40 20 0 60 TEMPERATURE (°C) 80 100 42631 G16 0 1 3 2 VLEGACY (V) 4 5 42631 G17 42631fa 6 LTC4263-1 TEST TIMING Detect and Turn-On Timing Current Limit Timing PD INSERTED ILIM IOUT VDD48 ICUT tOVLD VDD48 VOUT tDET VSS VOUT 42631 TT02 PORT TURN-ON tDETDLY tPON 42631 TT01 DC Disconnect Timing IOUT AC Disconnect Timing IMIN VOSC VDD48 VDD48 VOUT VSS VOUT tMPS tMPDO VSS 42631 TT03 IACOUT IACDMIN PD REMOVED tMPDO 42631 TT04 42631fa 7 LTC4263-1 PIN FUNCTIONS LED (Pin 1): Port State LED Drive. This pin is an opendrain output that pulls down when the port is powered. Under port fault conditions, the LED will flash in patterns to indicate the nature of the port fault. See the Applications Information section for a description of these patterns. When the LTC4263-1 is operated from a single 48V supply, this pin is pulsed low with a 6% duty cycle during the periods when the LED should be on. This allows use of a simple inductor, diode, and resistor circuit to avoid excess heating due to the large voltage drop from VDD48. See the Applications Information section for details on this circuit. LEGACY (Pin 2): Legacy Detect. This pin controls whether legacy detect is enabled. If held at VDD5, legacy detect is enabled and testing for a large capacitor is performed to detect the presence of a legacy PD on the port. See the Applications Information section for descriptions of legacy PDs that can be detected. If held at VSS, only IEEE 802.3af compliant PDs are detected. If left floating, the LTC4263-1 enters force-power-on mode and any PD that generates between 1V and 10V when biased with 270μA of detection current will be powered as a legacy device. This mode is useful if the system uses a differential detection scheme to detect legacy devices. MIDSPAN (Pin 3): Midspan Enable. If this pin is connected to VDD5, Midspan backoff is enabled and a 3.2 second delay occurs after every failed detect cycle unless the result is open circuit. If held at VSS, no delay occurs after failed detect cycles. VSS (Pins 4, 5, 6, 13): Negative Power Supply. Pins 4, 5, 6 and 13 should be tied together on the PCB. For optimum power delivery, supply voltage should be maximized. See Applications Information section for more information. ACOUT (Pin 8): AC Disconnect Sense. Senses the port to determine whether a PD is still connected when in AC disconnect mode. If port capacitance drops below about 0.15μF for longer than TMPDO the port is turned off. If AC disconnect is used, connect this pin to the port with a series combination of a 1k resistor and a 0.47μF 100V X7R capacitor. See the Applications Information section for more information. OUT (Pins 9, 10): Port Output. If DC disconnect is used, these pins are connected to the port. If AC disconnect is used, these pins are connected to the port through a parallel combination of a 1A diode and a 500k resistor. Pins 9 and 10 should be tied together on the PCB. See the Applications Information section for more information. VDD48 (Pin 11): Power Return for VSS. Must be bypassed with a 0.1μF capacitor to VSS. For optimum power delivery, supply voltage should be maximized. See Applications Information section for more information. SD (Pin 12): Shutdown. If held low, the LTC4263-1 is prevented from performing detection or powering the port. Pulling SD low will turn off the port if it is powered. When released, a 4-second delay will occur before detection is attempted. If not used, tie to VDD5. VDD5 (Pin 14): Logic Power Supply. Apply 5V referenced to VSS, if such a supply is available, or place a 0.1μF bypass capacitor to VSS to enable the internal regulator. When the internal regulator is used, this pin should only be connected to the bypass capacitor and to any logic pins of the LTC4263-1 that are being held at VDD5. Exposed Pad (Pin 15): VSS. Must be connected to VSS on the PCB. The Exposed Pad acts as a heat sink for the internal MOSFET. OSC (Pin 7) Oscillator for AC Disconnect. If AC disconnect is used, connect a 0.1μF X7R capacitor from OSC to VSS. Tie OSC to VSS to disable AC disconnect and enable DC disconnect. 42631fa 8 LTC4263-1 BLOCK DIAGRAM 1A 11 14 VDD5 VDD5 RLED INT5 EXT5 VDD48 12 SD 5V REG 0.1μF 2 LEGACY 3 MIDSPAN + 1 56V 3 LED – TO PORT MAGNETICS 500k CONTROL + SMAJ58A 5V – Hot SwapTM 13 4 5 6 IDET 500k 9 VSS 10 OUT 0.47μF 0.1μF 1k 7 OSC BOLD LINES INDICATE HIGH CURRENT Hot Swap IS A TRADEMARK OF LINEAR TECHNOLOGY CORPORATION 8 ACOUT 42631 BD 42631fa 9 LTC4263-1 APPLICATIONS INFORMATION POE OVERVIEW A PSE is required to provide 44V to 57V DC between either the signal pairs or the spare pairs as shown in Figure 1. The power is applied as a voltage between two of the pairs, typically by powering the center taps of the isolation transformers used to couple the differential data signals to the wire. Since Ethernet data is transformer coupled at both ends and is sent differentially, a voltage difference between the transmit pairs and the receive pairs does not affect the data. A 10Base-T/ 100Base-TX Ethernet connection only uses two of the four pairs in the cable. The unused or spare pairs can optionally be powered directly, as shown in Figure 1, without affecting the data. 1000Base-T uses all four pairs and power must be connected to the transformer center taps if compatibility with 1000Base-T is required. Over the years, twisted-pair Ethernet has become the most commonly used method for local area networking. The IEEE 802.3 group, the originator of the Ethernet standard, has defined an extension to the standard, IEEE 802.3af, which allows DC power to be delivered simultaneously over the same cable used for data communication. This has enabled a whole new class of Ethernet devices, including IP telephones, wireless access points, and PDA charging stations which do not require additional AC wiring or external power transformers, a.k.a. “wall warts.” These small data devices can now be powered directly from their Ethernet connection. Sophisticated detection and power monitoring techniques prevent damage to legacy data-only devices while still supplying power to newer, Ethernet-powered devices over the twisted-pair cable. The LTC4263-1 provides a complete high power PSE solution for powering newer power hungry PDs such as dual-radio wireless access points, security cameras and RFID readers. With proper system design, proprietary high power PoE solutions using the LTC4263-1 can deliver 25W (min) to a high power 2-pair PD at the end of a 100 meter CAT5 cable and 50W (min) using a 4-pair solution. The device that supplies power is called the Power Sourcing Equipment (PSE). A device that draws power from the wire is called a Powered Device (PD). A PSE is typically an Ethernet switch, router, hub, or other network switching equipment that is commonly found in the wiring closets where cables converge. PDs can take many forms. Digital IP telephones, wireless network access points, PDA or notebook computer docking stations, cell phone chargers, and HVAC thermostats are examples of devices that can draw power from the network. PSE RJ45 4 CAT 5 CABLE 5 PD RJ45 4 5 1N4002 s4 SPARE PAIR + 0.1μF 0.1μF VDD48 1 1 2 2 Tx SMAJ58A 58V Rx DATA PAIR CIN ≥ 5mF LTC4263-1 56V 3 VDD5 3 Rx Tx 6 0.1μF – The LTC4263-1 provides a high power PSE solution while simultaneously being compatible with existing IEEE 802.3af systems. By maintaining a compliant detection protocol, the LTC4263-1 insures legacy data-only devices are not DATA PAIR 6 1N4002 s4 SMAJ58A 58V VSS OUT 7 7 6 6 0.1μF GND RCLASS –48VOUT LTC4264-BASED OUT PD/SWITCHER –48VIN + VOUT – SPARE PAIR 42631 F01 Figure 1. 2-Pair High Power PoE System Diagram 42631fa 10 LTC4263-1 accidentally powered. Disconnect with either AC or DC methods using the LTC4263-1 is fully compliant and insures safe power removal after PD disconnect. Command and control for the LTC4263-1 is handled internally without the need of a microcontroller, thereby simplifying system design. LTC4263-1 OPERATION The IEEE 802.3af specification defines a specific pair-topair signature resistance used to identify a device that can accept power via its Ethernet connection. When the port voltage is below 10V, an IEEE 802.3af compliant PD will have an input resistance of approximately 25kΩ. Figure 2 illustrates the relationship between the PD signature resistance and the required resistance ranges the PSE must accept and reject. According to the IEEE 802.3af specification, the PSE must accept PDs with signatures between 19kΩ and 26.5kΩ and may or may not accept resistances in the two ranges of 15kΩ to 19kΩ and 26.5kΩ to 33kΩ. The black box in Figure 2 represents the typical 150Ω pair-to-pair termination used in Ethernet devices like a computer’s network interface card (NIC) that cannot accept power. 10k 20k 30k 23.75k 26.25k PD PSE 255 25k | SLOPE 180 VALID PD Signature Detection RESISTANCE 0Ω CURRENT (μA) APPLICATIONS INFORMATION 150Ω (NIC) REJECT ACCEPT 15k 19k 0V-2V OFFSET FIRST DETECTION POINT SECOND DETECTION POINT VOLTAGE 42631 F03 Figure 3. PD 2-Point Detection The LTC4263-1 uses a force-current detection method in order to reduce noise sensitivity and provide a more robust detection algorithm. The first test point is taken by forcing a test current into the port, waiting a short time to allow the line to settle and measuring the resulting voltage. This result is stored and the second current is applied to the port, allowed to settle and the voltage measured. The LTC4263-1 will not power the port if the PD has more than 5μF in parallel with its signature resistor unless legacy mode is enabled. The LTC4263-1 autonomously tests for a valid PD connected to the port. It repeatedly queries the port every 580ms, or every 3.2s if midspan backoff mode is active (see below). If detection is successful, it then powers up the port. REJECT 26.5k 33k 42631 F02 Figure 2. IEEE 802.3af Signature Resistance Ranges The LTC4263-1 checks for the signature resistance by forcing two test currents on the port in sequence and measuring the resulting voltages. It then subtracts the two V-I points to determine the resistive slope while removing voltage offset caused by any series diodes or current offset caused by leakage at the port (see Figure 3). The LTC4263-1 will typically accept any PD resistance between 17kΩ and 29.7kΩ as a valid PD. Values outside this range (excluding open and short-circuits) are reported to the user by a code flashed via the LED pin. Midspan Backoff IEEE 802.3af requires the midspan PSE to wait two seconds after a failed detection before attempting to detect again unless the port resistance is greater than 500kΩ. This requirement is to prevent the condition of an endpoint PSE and a midspan PSE, connected to the same PD at the same time, from each corrupting the PD signature and preventing power-on. After the first corrupted detection cycle, the midspan PSE waits while the endpoint PSE completes detection and turns the port on. If the midspan mode of the LTC4263-1 is enabled by connecting the MIDSPAN pin to VDD5, a 3.2 second delay occurs after every failed detect cycle unless the result is an open circuit. 42631fa 11 LTC4263-1 APPLICATIONS INFORMATION Power Control The primary function of the LTC4263-1 is to control the delivery of power to the PSE port. In order to provide a robust solution, a variety of current limit and current monitoring functions are needed, as shown in Figure 4. All control circuitry is integrated and the LTC4263-1 requires no external MOSFET, sense resistor, or microcontroller. The LTC4263-1 includes an internal MOSFET for driving the PSE port. The LTC4263-1 drives the gate of the internal MOSFET while monitoring the current and the output voltage at the OUT pin. This circuitry couples the 56V input supply to the port in a controlled manner that satisfies the PD’s power needs while minimizing disturbances on the 56V backplane. PORT CURRENT 750mA CURRENT LIMIT PORT OFF IN tOVLD 600mA 450mA NORMAL OPERATION 300mA DC DISCONNECT CUT (IMIN) (ICUT) LIMIT (ILIM) If at any time the port is shorted or an excessive load is applied, the LTC4263-1 limits port current to avoid a hazardous condition. The current is limited to ILIM for port voltages above 30V and is reduced for lower port voltages (see the Foldback section). Inrush and short-circuit current limit are allowed to be active for 62ms (typ) before the port is shut off. Port Fault If the port is suddenly shorted, the internal MOSFET power dissipation can rise to very high levels until the short-circuit current limit circuit can respond. A separate high-speed current limit circuit detects severe fault conditions (IOUT > 1000mA (typ)) and quickly turns off the internal MOSFET if such an event occurs. The circuit then limits current to ILIM while the tOVLD timer increments. During a short-circuit, ILIM will be reduced by the foldback circuitry. tOVLD Timing 150mA 0mA rise until the PD reaches its input turn-on threshold. At this point, the PD begins to draw current to charge its bypass capacitance, slowing the rate of port voltage increase. DC DISCONNECT PORT OFF IN tMPDO 42631 F07 Figure 4. Current Thresholds and Current Limits Port Overload Based on the IEEE 802.3af standard, the LTC4263-1 detects port overload conditions by monitoring port current. This ensures the port stays within the designed continuous power budget while allowing for brief power surges. If the port current exceeds 570mA (typ) for greater than 62ms (typ), power is removed and the LTC4263-1 waits 4 seconds (typ) before returning to detection mode. Port Inrush and Short-Circuit When 56V power is applied to the port, the LTC4263-1 is designed to power-up the PD in a controlled manner without causing transients on the input supply. To accomplish this, the LTC4263-1 implements inrush current limit. At turn-on, current limit will allow the port voltage to quickly For overload, inrush, and short-circuit conditions, the LTC4263-1 includes a 62ms (typ) tOVLD timer to limit the duration of these events. The timer is incremented whenever current greater than ICUT flows through the port. If the current is still above ICUT when the tOVLD timer expires, the LTC4263-1 will turn off power to the port and flash the LED. In this situation, the LTC4263-1 waits four seconds and then restarts detection. If the overload condition is removed before the t OVLD timer expires, the port stays powered and the timer is reset. Foldback Foldback is designed to limit power dissipation in the LTC4263-1 during power-up and momentary short-circuit conditions. At low port output voltages, the voltage across the internal MOSFET is high, and power dissipation will be large if significant current is flowing. Foldback monitors the port output voltage and reduces the ILIM current limit level for port voltages of less than 28V, as shown in Figure 5. 42631fa 12 LTC4263-1 APPLICATIONS INFORMATION If the undercurrent condition goes away before tMPDO (350ms (typ)), the timer is reset to zero. The DC disconnect circuit includes a glitch filter to prevent noise from falsely resetting the timer. The current must be present for a period of at least 20ms to guarantee reset of the timer. To enable DC disconnect, tie the OSC pin to VSS . 750 ILIM (mA) 600 450 300 AC Disconnect 150 0 5 0 10 15 20 25 30 35 40 45 50 VDD48 – VOUT (V) 42631 F07 Figure 5. Current Limit Foldback Thermal Protection The LTC4263-1 includes thermal overload protection in order to provide full device functionality in a miniature package while maintaining safe operating temperatures. Several factors create the possibility for very large power dissipation within the LTC4263-1. At port turn-on, while ILIM is active, the instantaneous power dissipated by the LTC4263-1 can be as high as 18W. This can cause 40ºC or more of die heating in a single turn-on sequence. Similarly, excessive heating can occur if an attached PD repeatedly pushes the LTC4263-1 into ILIM by drawing too much current. Excessive heating can also occur if the VDD5 pin is shorted or overloaded. AC disconnect is an alternate method of sensing the presence or absence of a PD by monitoring the port impedance. The LTC4263-1 forces an AC signal from an internal sine wave generator on to the port. The ACOUT pin current is then sampled once per cycle and compared to IACDMIN. Like DC disconnect, the AC disconnect sensing circuitry controls the tMPDO disconnect timer. When the connection impedance rises due to the removal of the PD, AC peak current falls below IACDMIN and the disconnect timer increments. If the impedance remains high (AC peak current remains below IACDMIN), the disconnect timer counts to tMPDO and the port is turned off. If the impedance falls, causing AC peak current to rise above IACDMIN for two consecutive samples before the maximum count of the disconnect timer, the timer resets and the port remains powered. DC Disconnect The AC disconnect circuitry senses the port via the ACOUT pin. Connect a 0.47μF 100V X7R capacitor (CDET) and a 1k resistor (RDET) from the DETECT pin to the port output as shown in Figure 6. This provides an AC path for sensing the port impedance. The 1k resistor, RDET, limits current flowing through this path during port power-on and poweroff. An AC blocking diode (DAC) is inserted between the OUT pin and the port to prevent the AC signal from being shorted by the LTC4263-1’s power control MOSFET. The 500k resistor across DAC allows the port voltage to decay after disconnect occurs. The DC disconnect circuit monitors port current whenever power is on to detect continued presence of the PD. IEEE 802.3af mandates a minimum current of 10mA that the PD must draw for periods of at least 75ms with optional dropouts of no more than 250ms. The tMPDO disconnect timer increments whenever port current is below 7.5mA (typ). If the timer expires, the port is turned off and the LTC4263-1 waits 1.5 seconds before restarting detection. Sizing of capacitors is critical to ensure proper function of AC disconnect. CPSE (Figure 6) controls the connection impedance on the PSE side. Its capacitance must be kept low enough for AC disconnect to be able to sense the PD. On the other hand, CDET has to be large enough to pass the signal at 110Hz. The recommended values are 0.1μF for CPSE and 0.47μF for CDET. The sizes of CPSE, CDET, and RDET are chosen to create an economical, physically The LTC4263-1 protects itself from thermal damage by monitoring die temperature. If the die temperature exceeds the overtemperature trip point, the LTC4263-1 removes port power and shuts down all functions including the internal 5V regulator. Once the die cools, the LTC4263-1 waits four seconds, then restarts detection. 42631fa 13 LTC4263-1 APPLICATIONS INFORMATION 1A + 0.1μF 100V ISOLATED 56V SUPPLY CPSE 0.1μF X7R, 100V LTC4263-1 NC 0.1μF LED LEGACY MIDSPAN – 0.1μF X7R VDD5 SMAJ58A VSS 500k SD VSS VDD48 VSS OUT VSS OUT CMLSH05-4 42631 F06 DAC RDET 1k OSC CDET 0.47μF X7R, 100V ACOUT Figure 6. LTC4263-1 Using AC Disconnect compact and functionally robust system. Moreover, the complete Power over Ethernet AC disconnect system (PSE, transformers, cabling, PD, etc.) is complex; deviating from the recommended values of CDET, RDET and CPSE is strongly discouraged. Contact the Linear Technology Applications department for additional support. Internal 110Hz AC Oscillator The LTC4263-1 includes onboard circuitry to generate a 110Hz (typ), 2VP-P sine wave on its OSC pin when a 0.1μF capacitor is connected between the OSC pin and VSS. This sine wave is synchronized to the controller inside the LTC4263-1 and should not be externally driven. Tying the OSC pin to VSS shuts down the oscillator and enables DC disconnect. Power-On Reset and Reset/Backoff Timing Upon startup, the LTC4263-1 waits four seconds before starting its first detection cycle. Depending on the results of this detection it will either power the port, repeat detection, or wait 3.2 seconds before attempting detection again if in midspan mode. The LTC4263-1 may be reset by pulling the SD pin low. The port is turned off immediately and the LTC4263-1 sits idle. After SD is released there will be a 4-second delay before the next detection cycle begins. VDD5 Logic-Level Supply The VDD5 supply for the LTC4263-1 can either be supplied externally or generated internally from the VDD48 supply. If supplied externally, a voltage between 4.5V and 5.5V should be applied to the VDD5 pin to cause the internal regulator to shut down. If VDD5 is to be generated internally, the voltage will be 4.4V (typ) and a 0.1μF capacitor should be connected between VDD5 and VSS. Do not connect the internally generated VDD5 to anything other than a bypass capacitor and the logic control pins of the same LTC4263-1. LED Flash Codes The LTC4263-1 includes a multi-function LED driver to inform the user of the port status. The LED is turned on when the port is connected to a PD and power is applied. If the port is not connected or is connected to a non-powered device with a 150Ω or shorted termination, the port will not be powered and the LED will be off. For other port conditions, the LTC4263-1 blinks a code to communicate the status to the user as shown in Table 1. One flash indicates low signature resistance, two flashes indicates high resistance and five flashes indicates an overload fault. When active, the LED flash codes are repeated every 1.2 seconds. The duration of each LED flash is 75ms. Multiple LED flashes occur at a 300ms interval. The LTC4263-1 includes a feature for efficiently driving the LED from a 56V power supply without the wasted power caused by having to drop over 52V in a current limit resistor. When operating the VDD5 supply internally, the LTC4263-1 drives the LED pin with a 6% duty cycle PWM signal. This allows use of the simple LED drive circuit in Figure 7 to minimize power dissipation. The modulation frequency of the LED drive is 28kHz, making the on period 42631fa 14 LTC4263-1 APPLICATIONS INFORMATION Table 1. Port Status and LED Flash Codes PORT STATUS LED FLASH CODE FLASH PATTERN Non-Powered Device 0Ω < RPORT < 200Ω Off LED Off Port Open RPORT > 1MΩ Off LED Off Port On 25kΩ On LED On Low Signature Resistance 300Ω < RPORT < 15kΩ 1 Flash High Signature Resistance 33kΩ < RPORT < 500kΩ 2 Flashes Port Overload Fault 5 Flashes EXTERNAL COMPONENT SELECTION VDD48 This section discusses the other elements needed to make a system including the LTC4263-1 function correctly. It is recommended to adhere closely to the example application circuits provided. For further assistance contact the Linear Technology Applications department. D1 10mH, 21mA COILCRAFT DS1608C-106 D2 BAS19 RLED 1k PoE System Power Delivery LED VDD48 LTC4263-1 VDD5 0.1μF VSS 4263 F07 Figure 7. LED Drive Circuit with Single 48V Supply 2.2μs. During the 2.2μs that the LED pin is pulled low, current ramps up in the inductor, limited by RLED. Diode D2 completes the circuit by allowing current to circulate while the LED pin is open circuit. Since current is only drawn from the power supply 6% of the time, power dissipation is substantially reduced. When VDD5 is powered from an external supply, the PWM signal is disabled and the LED pin will pull down continuously when on. In this mode, the LED can be powered from the 5V supply with a simple series resistor. The LTC4263-1 can output over 30W(typ) and is designed to deliver 25W(min) to the PD over a 100 meter CAT5 cable for high power applications such as wireless access points, security cameras and RFID readers. There are several parameters external to the LTC4263-1 that limit the power available to the PD. Figure 8 provides a simple model used to calculate this power delivery. The primary element affecting the delivery of power to the PD is the supply feeding the LTC4263-1. By maximizing this voltage, the highest and most efficient power delivery can be obtained. However, in order to adhere to common safety requirements, the supply is normally limited to 60V and the IEEE 802.3af committee has chosen 57V as a nominal maximum. In this example, a 56±1V power supply output sets the lower limit to 55V. The LTC4263-1 overload current limit monitors port current and removes 42631fa 15 LTC4263-1 APPLICATIONS INFORMATION POUT(MIN) = 28.8W (MIN, DC DISCONNECT) = 28.5W (MIN, AC DISCONNECT) POWER (MIN) = 55V (MIN) • 540mA (MIN) = 29.7W (MIN) LTC4263-1 POWER SUPPLY VSUPPLY 55V TO 57V ICUT(MIN) = 540mA RON(MAX) = 3Ω CABLE LOSS (MAX) = (540mA)2 • 12.5Ω = 3.6W AC DISCONNECT DIODE (OPTIONAL) PD 100M CAT5 CABLE 12.5Ω (MAX) PLOSS_AC DIODE(MAX) = 0.5V • 540mA = 0.3W (MAX) PLOSS_4263-1(MAX) = (540mA)2 • 3Ω = 0.9W (MAX) 42631 F08 POUT(MIN) = 25.2W (MIN, DC DISCONNECT) = 24.9W (MIN, AC DISCONNECT) Figure 8. Example of Power Delivery Calculation Using the LTC4263-1 power if the port exceeds 540mA(min). This sets the maximum system operating current and along with the working voltage, limits the power available to the PD. The power at the PSE output is reduced by the resistance of the LTC4263-1 internal power MOSFET and the voltage drop of the AC blocking diode if used for AC disconnect as shown in Figure 8. The cabling can be responsible for the largest loss. In our example based on a worst-case 100 meter CAT5 cable and connectors, the power loss can be as much as 3.6W. Obviously for shorter cable runs the loss is less and lower resistance cables such as CAT6 will have correspondingly lower losses. The total power available at the PD can be calculated taking in to account these losses using the formula: ( PPD = (VSUPPLY • ICUT ) – ICUT 2 • RON ( ) – (VDAC • ICUT ) – ICUT 2 • RCABLE ) For many PoE systems, the only parameter affecting power delivery that is under the control of the PSE designer is the power supply. Optimum power delivery can be obtained by maximizing this power supply voltage. 4-pair systems can be treated as two independent 2-pair systems and therefore the power will be twice that of the 2-pair. 2-Pair vs 4-Pair One of the basic architectural decisions associated with a high power PoE system is whether to deliver power using four conductors (2-pair) or all eight conductors (4-pair). Each method provides advantages and the system vendor needs to decide which method best suits their application. 2-pair power is used today in IEEE 802.3af systems (see Figure 1). One pair of conductors is used to deliver the current and a second pair is used for the return while two conductor pairs are not powered. This architecture offers the simplest implementation method but suffers from higher cable loss than an equivalent 4-pair system. 4-pair power delivers current to the PD via two conductor pairs in parallel (Figure 9). This lowers the cable resistance but raises the issue of current balance between each conductor pair. Differences in resistance of the transformer, cable and connectors along with differences in diode bridge forward voltage in the PD can cause an imbalance in the currents flowing through each pair. The 4-pair system in Figure 9 solves this problem by using two independent DC/DC converters in the PD. Using a 2-pair architecture with the LTC4263-1 allows delivery of 25W to the PD while using a 4-pair architecture allows delivery of 50W. Contact Linear Technology applications support for detailed information on implementing 2-pair and 4-pair PoE systems. Common Mode Chokes Both non-powered and powered Ethernet connections achieve best performance for data transfer and EMI when a common mode choke is used on each port. For cost reduction reasons, some designs share a common mode choke between two adjacent ports. This is not recommended. 42631fa 16 LTC4263-1 APPLICATIONS INFORMATION PSE PD + 0.1μF 0.1μF VDD48 56V 1 1 2 2 Rx Tx DATA PAIR 0.1μF SMAJ58A GND RCLASS PWRGD LTC4263-1 3 VDD5 3 6 DATA PAIR VIN 6 VOUT SMAJ58A 58V – VSS OUT 0.1μF VDD48 4 4 Tx Rx 5 56V DATA PAIR 5 – – DC/DC CONVERTER VOUT 7 Rx Tx 8 0.1μF + 5μF MIN GND RCLASS PWRGD VIN 7 + + LTC4264 LTC4263-1 VDD5 – SMAJ58A 0.1μF 0.1μF – VOUT 8s B2100 + DC/DC CONVERTER LTC4264 Tx Rx 0.1μF 5μF MIN DATA PAIR 8 SMAJ58A 58V VSS OUT 42631 F Figure 9. 4-Pair High Power PoE Gigabit Ethernet System Diagram Sharing a common mode choke between two ports couples start-up, disconnect and fault transients from one port to the other. The end result can range from intermittent behavior to excessive voltages that may damage circuitry in both the PSE and PD connected to the port. Transient Suppressor Diode Power over Ethernet is a challenging Hot Swap application because it must survive unintentional abuse by repeated plugging in and out of devices at the port. Ethernet cables could potentially be cut or shorted together. Consequently, the PSE must be designed to handle these events without damage. The most severe of these events is a sudden short on a powered port. What the PSE sees depends on how much CAT-5 cable is between it and the short. If the short occurs on the far end of a long cable, the cable inductance will prevent the current in the cable from increasing too quickly and the LTC4263-1 built-in short-circuit protection will control the current and turn off the port. However, the high current along with the cable inductance causes a large flyback voltage to appear across the port when the MOSFET is turned off. In the case of a short occurring with a minimum length cable, the instantaneous current can be extremely high due to the lower inductance. The LTC4263-1 has a high speed fault current limit circuit that shuts down the port in 20μs (typ). In this case, there is lower inductance but higher current so the event is still severe. A transient suppressor is required to clamp the port voltage and prevent damage to the LTC4263-1. An SMAJ58A or equivalent device works well to maintain port voltages within a safe range. A bidirectional transient suppressor should not be used. Good layout practices place the transient voltage suppressor close to the LTC4263-1, before the common mode choke (if used) and data magnetics to enhance the protective function. 42631fa 17 LTC4263-1 APPLICATIONS INFORMATION If the port voltage reverses polarity and goes positive, the OUT pin can be overstressed because this voltage is stacked on top of the 56V supply. In this case, the transient suppresser is used to clamp the voltage to a small positive value to protect the LTC4263-1 and the PSE capacitor. For this reason, it is critical that only a unidirectional TVS be used. Component leakages across the port can have an adverse affect on AC disconnect and even affect DC disconnect if the leakage becomes severe. The SMAJ58A is rated at less than 5μA leakage at 58V and works well in this application. There is a potential for stress induced leakage, so sufficient margins should be used when selecting transient suppressors for these applications. Capacitors Sizing of both the CDET and CPSE capacitors is critical for proper operation of the LTC4263-1 AC disconnect sensing. See the AC Disconnect section for more information. Note that many ceramic capacitors have dramatic DC voltage and temperature coefficients. Use 100V or higher rated X7R capacitors for CDET and CPSE , as these have reduced voltage dependence while also being relatively small and inexpensive. Bypass the 48V supply with a 0.1μF, 100V capacitor located close to the LTC4263-1. The VDD5 supply also requires a 0.1μF bypass capacitor. Fuse While the LTC4263-1 does not require a fuse for proper operation, some safety requirements state that the output current must be limited to less than 2A in less than 60 seconds if any one component fails or is shorted. Since the LTC4263-1 is the primary current limiter, its failure could result in excess current to the port. To meet these safety requirements, a fuse can be placed in the positive leg of the port. The fuse must be large enough that it will pass at least 675mA when derated for high temperature but small enough that it will fuse at less than 2A at cold temperature. This requirement can usually be satisfied with a 1A fuse or PTC. Placing the fuse between the RJ-45 connector and the LTC4263-1 and its associated circuitry provides additional protection for this circuitry. Consult a safety requirements expert for the application specific requirements. Isolation The IEEE 802.3af standard requires Ethernet ports to be electrically isolated from all other conductors that are user accessible. This includes the metal chassis, other connectors, and the AC power line. Environment A isolation is the most common and applies to wiring within a single building serviced by a single AC power system. For this type of application, the PSE isolation requirement can be met with the use of a single, isolated 56V supply powering several LTC4263-1 ports. Environment B, the stricter isolation requirement, is for networks that cross an AC power distribution boundary. In this case, electrical isolation must be maintained between each port in the PSE. The LTC4263-1 can be used to build a multi-port Environment B PSE by powering each LTC4263-1 from a separate, isolated 56V supply. In all PSE applications, there should be no user accessible connections to the LTC4263-1 other than the RJ-45 port. 42631fa 18 LTC4263-1 PACKAGE DESCRIPTION DE Package 14-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1708 Rev B) 0.70 ±0.05 3.30 ±0.05 3.60 ±0.05 2.20 ±0.05 1.70 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 3.00 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R = 0.115 TYP 4.00 ±0.10 (2 SIDES) R = 0.05 TYP 3.00 ±0.10 (2 SIDES) 0.40 ± 0.10 8 14 3.30 ±0.10 1.70 ± 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 s 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) (DE14) DFN 0806 REV B 7 0.200 REF 1 0.25 ± 0.05 0.50 BSC 0.75 ±0.05 3.00 REF 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 42631fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC4263-1 TYPICAL APPLICATION Complete High Power Single Port Endpoint PSE L2 6 + ISOLATED 56V – L1: COILCRAFT DS1608C-106 L2: COILCRAFT ETH1-230LD • • 9 • • 1 2 10 11 PHY L1 10mH R2 1k • 5 D1 BAS19 LTC4263-1 11 14 VDD48 VDD5 1 12 LED SD 7 2 OSC LEGACY 3 MIDSPAN 13 VSS 4 8 VSS ACOUT 5 10 VSS OUT 6 9 VSS OUT C1 0.1μF LED1 LN1351C-TR GRN C3 0.1μF 100V • C5 0.1μF X7R C7 0.47μF R6 100V, X7R 1k D5 CMLSHO5-4 4 3 OUT TO CABLE 12 2 1 • • • • 13 • • 3 6 14 F1 1A D2 SMAJ58A C4 0.1μF 100V, X7R 4 5 C8 0.01μF 200V R5 510k 2kV 1000pF C9 0.01μF 200V R7 75Ω R8 75Ω 7 8 R9 75Ω R10 75Ω RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1737 High Power Isolated Flyback Controller Sense Output Voltage Directly from Primary-Side Winding LTC3803 Current Mode Flyback DC/DC Controller in ThinSOTTM 200kHz Constant-Frequency, Adjustable Slope Compensation, Optimized for High Input Voltage Applications LTC4257 IEEE 802.3af PD Interface Controller 100V 400mA Internal Switch, Programmable Classification LTC4257-1 IEEE 802.3af PD Interface Controller 100V 400mA Dual Current Limit LTC4258 Quad IEEE 802.3af Power Over Ethernet Controller DC Disconnect Only LTC4259A-1 Quad IEEE 802.3af Power Over Ethernet Controller With AC Disconnect LTC4263 Single IEEE 802.3af Compliant PSE Controller IEEE 802.3af Power Levels LTC4264 High Power PD Interface Controller 100V 750mA Internal Switch, Programmable Classification LTC4267 IEEE 802.3af PD Interface with Switcher Integrated Current Mode Switching Regulator ThinSOT is a trademark of Linear Technology Corporation. 42631fa 20 Linear Technology Corporation LT 1007 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007