LINER LTC4263CS Single ieee 802.3af compliant pse controller with internal switch Datasheet

LTC4263
Single IEEE 802.3af
Compliant PSE Controller
with Internal Switch
DESCRIPTION
FEATURES
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IEEE 802®.3af Compliant
Operation from a Single 48V Supply
Fully Autonomous Operation without
Microcontroller
Internal MOSFET with Thermal Protection
Power Management Works Across Multiple Ports
with Simple RC Network
Precision Inrush Control with Internal Sense Resistor
Powered Device (PD) Detection and Classification
AC and DC Disconnect Sensing
Robust Short-Circuit Protection
Pin-Selectable Detection Backoff for Midspan PSEs
Classification Dependent ICUT Current Threshold
LED Driver Indicates Port On and Blinks
Status Codes
Available in 14-Pin SO and 4mm × 3mm DFN Packages
APPLICATIONS
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IEEE 802.3af Compliant Endpoint/Midspan PSEs
Single-Port or Multi-Port Power Injectors
Power Forwarders
Low-Port Count PSEs
Environment B PSEs
Standalone PSEs
The LTC®4263 is an autonomous single-channel PSE
controller for use in IEEE 802.3af compliant Power over
Ethernet systems. It includes an onboard power MOSFET,
internal inrush, current limit, and short-circuit control,
IEEE 802.3af compliant PD detection and classification
circuitry, and selectable AC or DC disconnect sensing.
Onboard control algorithms provide complete IEEE 802.3af
compliant operation without the need of a microcontroller.
The LTC4263 simplifies PSE implementation, needing
only a single 48V supply and a small number of passive
support components.
Programmable onboard power management circuitry
permits multiple LTC4263s to allocate and share power
in multi-port systems, allowing maximum utilization of
the 48V power supply—all without the intervention of a
host processor. The port current limit can be configured
to automatically adjust to the detected PD class. Detection backoff timing is configurable for either Endpoint or
Midspan operation. Built-in foldback and thermal protection
provide comprehensive fault protection.
An LED pin indicates the state of the port controlled by
the LTC4263. When run from a single 48V supply, the LED
pin can operate as a simple switching current source to
reduce power dissipation in the LED drive circuitry.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of
Linear Technology Corporation. Hot Swap and ThinSOT are trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners.
The LTC4263 is available in 14-pin 4mm × 3mm DFN and
14-pin SO packages.
TYPICAL APPLICATION
Single-Port Fully Autonomous PSE
1A
+
ISOLATED
48V SUPPLY
0.1μF
100V
0.1μF
LEGACY
MIDSPAN
–
0.1μF
100V
LTC4263
LED
PWRMGT
VSS
VDD5
ENFCLS
SMAJ58A
TO PORT
MAGNETICS
SD
VDD48
OUT
VSS
OUT
OSC
ACOUT
4263 TA01
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LTC4263
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages
VSS – VDD48 ........................................... 0.3V to –80V
VDD5........................................ VSS – 0.3V to VSS + 6V
Pin Voltages and Currents
LEGACY, MIDSPAN, ENFCLS, PWRMGT
SD, OSC .................................. VSS – 0.3V to VSS + 6V
LED ....................................... VSS – 0.3V to VSS + 80V
OUT, ACOUT ............................................ (See Note 3)
Operating Ambient Temperature Range
LTC4263C................................................ 0°C to 70°C
LTC4263I ............................................. –40°C to 85°C
Junction Temperature (Note 4) ............................. 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
SO..................................................................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
14 VDD5
LED 1
LED
1
LEGACY
2
14 VDD5
13 ENFCLS
MIDSPAN
3
12 SD
MIDSPAN 3
12 SD
PWRMGT
4
11 VDD48
PWRMGT 4
VSS
5
10 OUT
11 VDD48
VSS
6
9 OUT
OSC
7
15
13 ENFCLS
LEGACY 2
8 ACOUT
VSS 5
10 OUT
VSS 6
9
OUT
OSC 7
8
ACOUT
DE14 PACKAGE
14-LEAD (4mm s 3mm) PLASTIC DFN
S PACKAGE
14-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 43°C/W, θJC = 4.3°C/W
EXPOSED PAD (PIN 15) IS VSS, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 90°C/W, θJC = 37°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4263CDE#PBF
LTC4263CDE#TRPBF
4263
14-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC4263IDE#PBF
LTC4263IDE#TRPBF
4263
14-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
LTC4263CS#PBF
LTC4263CS#TRPBF
4263CS
14-Lead Plastic SO
0°C to 70°C
LTC4263IS#PBF
LTC4263IS#TRPBF
4263IS
14-Lead Plastic SO
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD48 – VSS = 48V and VDD5 not driven externally. All voltages are
relative to VSS unless otherwise noted. (Notes 2, 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supplies
VSUPPLY
48V Supply Voltage
VDD48 – VSS
To Maintain IEEE Compliant Output
l
l
33
46
48
66
57
V
V
VUVLO_OFF
UVLO Turn-Off Voltage
VDD48 – VSS Decreasing
l
29
31
33
V
l
0.1
VUVLO_HYS UVLO Hysteresis
1
V
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LTC4263
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD48 – VSS = 48V and VDD5 not driven externally. All voltages are
relative to VSS unless otherwise noted. (Notes 2, 5)
SYMBOL
PARAMETER
CONDITIONS
VOVLO_OFF
OVLO Turn-Off Voltage
VDD48 – VSS Increasing
VOVLO_HYS OVLO Hysteresis
MIN
TYP
MAX
UNITS
l
66
70
74
V
l
0.2
2
V
VDD5 Supply Voltage
Driven Externally
l
4.5
5
5.5
V
VDD5 Internal Supply
Driven Internally
l
4.3
4.4
4.5
V
IDD48
VDD48 Supply Current
VDD5 – VSS = 5V
Internal VDD5
l
l
1
2
2
4
mA
mA
IDD5
VDD5 Supply Current
VDD5 – VSS = 5V
l
1
2
mA
1.5
2.4
3.0
Ω
Ω
1
10
μA
VDD5
Power MOSFET
RON
On-Resistance
I = 350mA, Measured From OUT to VSS
IOUT_LEAK
OUT Pin Leakage
VOUT – VSS = VDD48 – VSS = 57V
l
RPU
OUT Pin Pull-Up Resistance to VDD48
0V ≤ (VDD48 – VOUT) ≤ 5V
l
360
500
640
kΩ
l
Current Control
ICUT
Overload Current Threshold
Class 0, Class 3, Class 4 (Note 6)
Class 2
Class 1
l
l
l
355
165
95
375
175
100
395
185
105
mA
mA
mA
ILIM
Short-Circuit Current Limit
VOUT – VSS = 5V
VDD48 – VOUT = 30V
l
l
405
405
425
425
445
445
mA
mA
IFB
Foldback Current Limit
VDD48 – VOUT = 0V (Note 7)
VDD48 – VOUT = 10V
l
l
30
110
60
140
120
180
mA
mA
IMIN
DC Disconnect Current Threshold
IFAULT
High Speed Fault Current Limit
IDET
l
5.2
7.5
9.8
mA
(Note 8)
l
500
650
800
mA
Detection Current
First Point, VDD48 – VOUT = 10V
Second Point, VDD48 – VOUT = 3.5V
l
l
235
160
255
180
275
200
μA
μA
VDET
Detection Voltage Compliance
VDD48 – VOUT, Open Port
VDD48 – VSS = 57V
l
21
V
RDETMIN
Minimum Valid Signature Resistance
l
15.5
17
RDETMAX
Maximum Valid Signature Resistance
l
27.5
29.7
ROPEN
Open Circuit Threshold
l
500
Detection
18.5
kΩ
32
kΩ
2000
kΩ
Classification
VCLASS
Classification Voltage
VDD48 – VOUT, 0mA ≤ ICLASS ≤ 50mA
l
16.5
ICLASS
Classification Current Compliance
VOUT = VDD48
l
55
60
75
mA
ITCLASS
Classification Threshold Current
Class 0 – 1
Class 1 – 2
Class 2 – 3 (Note 9)
l
l
l
5.5
13.5
21.5
6.5
14.5
23
7.5
15.5
24.5
mA
mA
mA
20.5
V
Power Management
VPWRMGT
Power Management Pin Threshold
IPWRMGT
Power Management Pin Output Current
l
0.98
1
1.02
V
Class 0, Class 3, Class 4
Class 1
Class 2
l
l
l
–75.6
–19.6
–34.3
–72.3
–18.8
–32.8
–69
–17.9
–31.3
μA
μA
μA
2V ≤ (VOSC – VSS) ≤ 3V
l
175
250
325
kΩ
140
μA
115
Hz
AC Disconnect
ROSC
OSC Pin Input Impedance
IOSC
OSC Pin Output Current
VOSC – VSS = 2V
l
–140
fOSC
OSC Pin Frequency
VOSC – VSS = 2V
l
103
110
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LTC4263
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD48 – VSS = 48V and VDD5 not driven externally. All voltages are
relative to VSS unless otherwise noted. (Notes 2, 5)
SYMBOL
PARAMETER
CONDITIONS
AVACD
Voltage Gain OSC to ACOUT
2V ≤ (VOSC – VSS) ≤ 3V
l
MIN
TYP
MAX
UNITS
0.95
1.0
1.05
V/V
1
mA
160
190
μA
IACDMAX
AC Disconnect Output Current
VOSC – VSS = 2V, 0V ≤ (VACOUT – VSS) ≤ 4V
l
–1
IACDMIN
Remain Connected AC Pin Current
VOSC – VSS = 2V
l
130
VACDEN
AC Disconnect Enable Signal
VOSC – VSS, Port On
l
1.5
l
V
Digital Interface (Note 10)
VOLED
LED Output Low Voltage
ILED = 10mA
VILD
Digital Input Low Voltage
MIDSPAN, PWRMGT, ENFCLS, SD LEGACY l
VIHD
Digital Input High Voltage
MIDSPAN, PWRMGT, ENFCLS, SD LEGACY l
l
2.2
2.2
VOZ
Voltage of Legacy Pin if Left Floating
l
1.1
l
l
IOLEG
Current In/Out of Legacy Pin
IFLT
Maximum Allowed Leakage of External Components
at Legacy Pin in Force Power-On Mode
1.1
l
0V ≤ (VLEGACY – VSS) ≤ 5V
2.2
V
0.8
0.4
V
V
V
1.25
1.4
V
–60
60
μA
–10
10
μA
Timing Characteristics
tDET
Detection Time
Beginning to End of Detection
l
270
tDETDLY
Detection Delay
PD Insertion to Detection Complete
l
300
290
310
ms
620
ms
tPDC
Classification Duration
l
34
37
39
ms
tPON
Power Turn-On Delay
End of Valid Detect to Application of Power l
135
145
155
ms
tRISE
Turn-On Rise Time
VDD48 – VOUT : 10% to 90%
CPSE = 0.1μF
l
40
170
tOVLD
Overload/Short-Circuit Time Limit
tED
Error Delay
ICUT Fault to Next Detect
μs
l
52
62
72
ms
l
3.8
4.0
4.2
s
320
350
380
ms
20
ms
tMPDO
Maintain Power Signature (MPS) Disconnect Delay PD Removal to Power Removal
l
tMPS
MPS Minimum Pulse Width
PD Minimum Current Pulse Width
Required to Stay Connected (Note 11)
l
tDBO
Midspan Mode Detection Backoff
RPORT = 15.5kΩ
l
3.0
3.2
3.4
s
tDISDLY
Power Removal Detection Delay
l
0.8
0.95
1.1
s
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to VSS unless otherwise
specified.
Note 3: 80mA of current may be pulled from the OUT or ACOUT pin
without damage whether the LTC4263 is powered or not. These pins will
also withstand a positive voltage of VSS + 80V.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: The LTC4263 operates with a negative supply voltage. To avoid
confusion, voltages in this data sheet are referred to in terms of absolute
magnitude.
Note 6: If the ENFCLS pin is high, ICUT depends on the result of
classification. If ENFCLS pin is low, ICUT reverts to its Class 0 specification.
Note 7: In order to reduce power dissipated in the switch while charging
the PD, the LTC4263 reduces the current limit when VOUT – VSS is large.
Refer to the Typical Performance Characteristics for more information.
Note 8: The LTC4263 includes a high speed current limit circuit intended to
protect against faults. The fault protection is activated for port current
in excess of IFAULT. After the high speed current limit activates, the shortcircuit current limit (ILIM) engages and restricts current to IEEE 802.3af
levels.
Note 9: Class 4 or higher classification current is treated as Class 3.
Note 10: The LTC4263 digital interface operates with respect to VSS. All
logic levels are measured with respect to VSS.
Note 11: The IEEE 802.3af specification allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
tMPS within any tMPDO time window.
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LTC4263
TYPICAL PERFORMANCE CHARACTERISTICS
Classification Transient
Response to 40mA Load Step
Powering a Legacy PD with
220μF Bypass Capacitor
Powering an IEEE 802.3af PD
VDD48
VDD48
DETECTION DETECTION
VOUT PHASE 1
PHASE 2
10V/DIV
CLASSIFICATION
POWER
ON
VSS
425mA CURRENT LIMIT
400mA
IOUT CLASSIFICATION
200mA/DIV
0mA
VSS
100ms/DIV
VOUT
20V/DIV
FOLDBACK
LOAD
FULLY
CHARGED
4263 G01
25ms/DIV
Overload Restart Delay
VDD48
4263 G02
100μs/DIV
VOUT
10V/DIV
400mA
IOUT
200mA/DIV
0mA
RPORT = 15.5kΩ
4263 G10
VDD48
VOUT
10V/DIV
500ms/DIV
4263 G12
Rapid Response to
Momentary 50Ω Short
VDD48
VOUT
20V/DIV
VOUT
20V/DIV
IPORT 20A
20A/
DIV 0A
tMPDO
LOAD
APPLIED
10ms/DIV
VDD48
IPORT = CURRENT IN
1Ω RESISTOR APPLIED
TO OUTPUT OF CIRCUIT
ON FRONT PAGE
PORT OFF
tOVLD
4263 G11
Rapid Response to 1Ω Short
VSS
VSS
PORT OFF
VSS
VSS
Response to PD Removal with
AC Disconnect Enabled
Overcurrent Response Time
VOUT
20V/DIV
VOUT
2V/DIV
IPORT
500mA/
DIV
4263 G06
VDD48
tDBO
tED
PD REMOVAL
40mA
IOUT
20mA/DIV
0mA
Midspan Backoff with Invalid PD
VDD48
500ms/DIV
VOUT
2V/DIV
VDD48 – 18V
VDD48 – 19V
VDD48 – VSS = 48V
TA = 25°C
1Ω SHORT
APPLIED
VSS
800mA
IPORT
400mA/DIV
0mA
50Ω SHORT APPLIED
SHORT
CURRENT
REMOVED
LIMIT ACTIVE
FOLDBACK CURRENT LIMIT
50ms/DIV
4263 G13
1μs/DIV
4263 G14
100μs/DIV
4263 G15
IPORT = CURRENT IN 50Ω RESISTOR APPLIED
TO OUTPUT OF CIRCUIT ON FRONT PAGE
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LTC4263
TYPICAL PERFORMANCE CHARACTERISTICS
LED Pin Pulldown
vs Load Current
Current Limit and Foldback
450
4
TA = 25°C
INTERNAL VDD5
400
IOUT (mA)
300
250
200
150
100
VDD48 – VSS = 48V
TA = 25°C
70
60
3
IOUT (mA)
VLED PIN PULLDOWN (V)
350
Classification Current Compliance
80
2
1
50
40
30
20
10
50
0
0
0
5
10 15 20 25 30 35 40 45 50
VDD48 – VOUT
0
10
20
30
40
ILED LOAD CURRENT (mA)
0
50
4263 G03
16
25k LOAD WITH
AC ENABLED
25k LOAD WITH
AC ENABLED
1.0
2.0
IDD5 DC Supply Current
vs Supply Voltage
2
TA = 25°C
20
4263 G05
IDD48 DC Supply Current vs
Supply Voltage with VDD5 = 5.0V
1.2
TA = 25°C
8
12
VDD48 – VOUT (V)
4
4263 G04
IDD48 DC Supply Current vs Supply
Voltage with Internal VDD5
2.5
0
25k LOAD WITH
AC ENABLED
VDD48 = 48V
1
NO LOAD
NO LOAD
1.0
IDD5 (mA)
IDD48 (mA)
IDD48 (mA)
0.8
1.5
NO LOAD
0.6
0
–1
0.4
0.5
–2
0.2
0
0
0
10
20
30
40
50
60
–3
10
0
VDD48 (V)
20
30
40
50
60
4263 G07
5.0
VDD5
4263 G08
RON vs Temperature
5.5
6.0
4263 G09
Legacy Pin Current vs Voltage
40
2.0
LEGACY MODE
1.8
20
ILEGACY (μA)
RON (Ω)
4.5
4.0
VDD48 (V)
1.6
1.4
FORCE POWER ON MODE
0
–20
1.2
1.0
–40
COMPLIANT MODE
–40
–20
40
20
0
60
TEMPERATURE (°C)
80
100
4263 G16
0
1
3
2
VLEGACY (V)
4
5
4263 G17
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LTC4263
TEST TIMING
Detect, Class and Turn-On Timing
Current Limit Timing
PD
INSERTED
VDD48
ILIM
IOUT
tDET
VOUT
PORT
TURN-ON
VCLASS
tOVLD
VDD48
VOUT
tPDC
tDETDLY
ICUT
VSS
tPON
4263 TT02
4263 TT01
DC Disconnect Timing
IOUT
AC Disconnect Timing
VOSC
IMIN
VDD48
VDD48
VOUT
VSS
VOUT
tMPS
tMPDO
VSS
4263 TT03
IACOUT
IACDMIN
PD REMOVED
tMPDO
4263 TT04
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LTC4263
PIN FUNCTIONS
(DFN/SO)
LED (Pin 1): Port State LED Drive. This pin is an open drain
output that pulls down when the port is powered. Under port
fault conditions, the LED will flash in patterns to indicate
the nature of the port fault. See the Applications Information section for a description of these patterns. When the
LTC4263 is operated from a single 48V supply, this pin is
pulsed low with a 6% duty cycle during the periods when
the LED should be on. This allows use of a simple inductor,
diode, and resistor circuit to avoid excess heating due to
the large voltage drop from VDD48. See the Applications
Information section for details on this circuit.
LEGACY (Pin 2): Legacy Detect. This pin controls whether
legacy detect is enabled. If held at VDD5 , legacy detect is
enabled and testing for a large capacitor is performed to
detect the presence of a legacy PD on the port. See the
Applications Information section for descriptions of legacy
PDs that can be detected. If held at VSS , only IEEE 802.3af
compliant PDs are detected. If left floating, the LTC4263
enters force-power-on mode and any PD that generates
between 1V and 10V when biased with 270μA of detection
current will be powered as a legacy device. This mode is
useful if the system uses a differential detection scheme
to detect legacy devices. Warning: Legacy modes are not
IEEE 802.3af compliant.
MIDSPAN (Pin 3): Midspan Enable. If this pin is connected
to VDD5, Midspan backoff is enabled and a 3.2 second
delay occurs after every failed detect cycle unless the
result is open circuit. If held at VSS , no delay occurs after
failed detect cycles.
PWRMGT (Pin 4): Power Management. The LTC4263
sources current at the PWRMGT pin proportional to the
class of the PD that it is powering. The voltage of this pin
is checked before powering the port. The port will not
turn on if this pin is more than 1V above VSS. Connect the
PWRMGT pins of multiple LTC4263s together with a resistor
and capacitor to VSS to implement power management. If
power management is not used, tie this pin to VSS.
VSS (Pins 5, 6): Negative 48V Supply. Pins 5 and 6 should
be tied together on the PCB.
OSC (Pin 7) Oscillator for AC Disconnect. If AC disconnect is used, connect a 0.1μF X7R capacitor from OSC to
VSS. Tie OSC to VSS to disable AC disconnect and enable
DC disconnect.
ACOUT (Pin 8): AC Disconnect Sense. Senses the port
to determine whether a PD is still connected when in AC
disconnect mode. If port capacitance drops below about
0.15μF for longer than TMPDO the port is turned off. If
AC disconnect is used, connect this pin to the port with
a series combination of a 1k resistor and a 0.47μF 100V
X7R capacitor. See the Applications Information section
for more information.
OUT (Pins 9, 10): Port Output. If DC disconnect is used,
these pins are connected to the port. If AC disconnect
is used, these pins are connected to the port through a
parallel combination of a 1A diode and a 500k resistor.
Pins 9 and 10 should be tied together on the PCB. See the
Applications Information section for more information.
VDD48 (Pin 11): 48V Return. Must be bypassed with a
0.1μF capacitor to VSS.
SD (Pin 12): Shutdown. If held low, the LTC4263 is prevented from performing detection or powering the port.
Pulling SD low will turn off the port if it is powered. When
released, a 4-second delay will occur before detection is
attempted.
ENFCLS (Pin 13): Enforce Class Current Limits. If held
at VDD5, the LTC4263 will reduce the ICUT threshold for
class 1 or class 2 PDs. If ENFCLS is held at VSS, ICUT
remains at 375mA (typ) for all classes.
VDD5 (Pin 14): Logic Power Supply. Apply 5V referenced
to VSS, if such a supply is available, or place a 0.1μF
bypass capacitor to VSS to enable the internal regulator.
When the internal regulator is used, this pin should only
be connected to the bypass capacitor and to any logic pins
of the LTC4263 that are being held at VDD5.
Exposed Pad (Pin 15, DE Package Only): VSS . Must be
connected to VSS on the PCB. The Exposed Pad acts as a
heatsink for the internal MOSFET.
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LTC4263
BLOCK DIAGRAM
1A
11
VDD48
12 SD
14
VDD5
VDD5
RLED
INT5 EXT5
13 ENFCLS
5V REG
0.1μF
2 LEGACY
3 MIDSPAN
+
1
48V
4
LED
–
TO PORT
MAGNETICS
500k
CONTROL
TO OTHER LTC4263s
4
+
PWRMGT
SMAJ58A
5V
–
HOT SWAP
IDET
CPM
500k
RPM
5
6
9
VSS
10
OUT
0.47μF
0.1μF
1k
7
OSC
8
ACOUT
4263 BD
BOLD LINES INDICATE HIGH CURRENT
4263fe
9
LTC4263
APPLICATIONS INFORMATION
POE OVERVIEW
Over the years, twisted-pair Ethernet has become the most
commonly used method for local area networking. The
IEEE 802.3 group, the originator of the Ethernet standard,
has defined an extension to the standard, IEEE 802.3af,
which allows DC power to be delivered simultaneously
over the same cable used for data communication. This
has enabled a whole new class of Ethernet devices, including IP telephones, wireless access points, and PDA
charging stations which do not require additional AC
wiring or external power transformers, a.k.a. “wall warts.”
With about 13W of power available, small data devices
can be powered by their Ethernet connections, free from
AC wall outlets. Sophisticated detection and power monitoring techniques prevent damage to legacy data-only
devices while still supplying power to newer, Ethernetpowered devices over the twisted-pair cable.
The device that supplies power is called the Power Sourcing
Equipment (PSE). A device that draws power from the
wire is called a Powered Device (PD). A PSE is typically an
Ethernet switch, router, hub, or other network switching
equipment that is commonly found in the wiring closets
where cables converge. PDs can take many forms. Digital
IP telephones, wireless network access points, PDA or
notebook computer docking stations, cell phone chargers,
PSE
RJ45
4
CAT 5
20Ω MAX
ROUNDTRIP
0.05μF MAX
5
–48V RETURN
and HVAC thermostats are examples of devices that can
draw power from the network.
A PSE is required to provide a nominal 48V DC between
either the signal pairs or the spare pairs (but not both)
as shown in Figure 1. The power is applied as a voltage
between two of the pairs, typically by powering the center taps of the isolation transformers used to couple the
differential data signals to the wire. Since Ethernet data
is transformer coupled at both ends and is sent differentially, a voltage difference between the transmit pairs and
the receive pairs does not affect the data. A 10Base-T/
100Base-TX Ethernet connection only uses two of the four
pairs in the cable. The unused or spare pairs can optionally be powered directly, as shown in Figure 1, without
affecting the data. 1000Base-T uses all four pairs and
power must be connected to the transformer center taps
if compatibility with 1000Base-T is required.
The LTC4263 provides a complete PSE solution for detection and powering of PD devices in an IEEE 802.3af
compliant system. The LTC4263 controls a single PSE
port that will detect, classify, and provide isolated 48V
power to a PD device connected to the port. The LTC4263
senses removal of a PD with IEEE 802.3af compliant AC
or DC methods and turns off 48V power when the PD is
disconnected. An internal control circuit takes care of
system configuration and timing.
PD
RJ45
4
5
1N4002
s4
SPARE PAIR
0.1μF
0.1μF
VDD48
1
1
2
2
Tx
SMAJ58A
58V
Rx
DATA PAIR
5mF ≤ CIN
≤ 300μF
LTC4263
3
VDD5
3
Rx
6
0.1μF
0.1μF
Tx
DATA PAIR
6
SMAJ58A
58V
–48V SUPPLY
VSS
OUT
7
7
6
6
1N4002
s4
GND
RCLASS
–48VOUT
LTC4267-BASED
OUT
PD/SWITCHER
–48VIN
+
VOUT
–
SPARE PAIR
4263 F01
Figure 1. System Diagram
4263fe
10
LTC4263
APPLICATIONS INFORMATION
LTC4263 OPERATION
The IEEE 802.3af specification defines a specific pair-topair signature resistance used to identify a device that
can accept power via its Ethernet connection. When the
port voltage is below 10V, an IEEE 802.3af compliant
PD will have an input resistance of approximately 25kΩ.
Figure 2 illustrates the relationship between the PD signature resistance and the required resistance ranges the
PSE must accept and reject. According to the IEEE 802.3af
specification, the PSE must accept PDs with signatures
between 19kΩ and 26.5kΩ and may or may not accept
resistances in the two ranges of 15kΩ to 19kΩ and 26.5kΩ
to 33kΩ. The black box in Figure 2 represents the typical
150Ω pair-to-pair termination used in Ethernet devices
like a computer’s network interface card (NIC) that cannot
accept power.
RESISTANCE 0Ω
10k
20k
30k
23.75k 26.25k
PD
PSE
150Ω (NIC)
REJECT
ACCEPT
15k
19k
REJECT
26.5k
33k
4263 F02
Figure 2. IEEE 802.3af Signature Resistance Ranges
The LTC4263 checks for the signature resistance by forcing
two test currents on the port in sequence and measuring
the resulting voltages. It then subtracts the two V-I points
to determine the resistive slope while removing voltage
offset caused by any series diodes or current offset caused
by leakage at the port (see Figure 3). The LTC4263 will
typically accept any PD resistance between 17kΩ and
29.7kΩ as a valid PD. Values outside this range (excluding open and short-circuits) are reported to the user by a
code flashed via the LED pin.
The LTC4263 uses a force-current detection method in
order to reduce noise sensitivity and provide a more robust
detection algorithm. The first test point is taken by forcing
a test current into the port, waiting a short time to allow
CURRENT (μA)
Signature Detection
255
25kΩ SLOPE
180
VALID PD
0V-2V
OFFSET
FIRST
DETECTION
POINT
SECOND
DETECTION
POINT
VOLTAGE
4263 F03
Figure 3. PD 2-Point Detection
the line to settle and measuring the resulting voltage. This
result is stored and the second current is applied to the
port, allowed to settle and the voltage measured.
The LTC4263 will not power the port if the PD has more
than 5μF in parallel with its signature resistor unless legacy
mode is enabled.
The LTC4263 autonomously tests for a valid PD connected
to the port. It repeatedly queries the port every 580ms, or
every 3.2s if midspan backoff mode is active (see below).
If detection is successful, it performs classification and
power management and then powers up the port.
Midspan Backoff
IEEE 802.3af requires the midspan PSE to wait two seconds
after a failed detection before attempting to detect again
unless the port resistance is greater than 500kΩ. This
requirement is to prevent the condition of an endpoint PSE
and a midspan PSE, connected to the same PD at the same
time, from each corrupting the PD signature and preventing
power-on. After the first corrupted detection cycle, the
midspan PSE waits while the endpoint PSE completes
detection and turns the port on. If the midspan mode of
the LTC4263 is enabled by connecting the MIDSPAN pin to
VDD5 , a 3.2 second delay occurs after every failed detect
cycle unless the result is an open circuit.
4263fe
11
LTC4263
APPLICATIONS INFORMATION
Classification
An IEEE 802.3af PD has the option of presenting a
classification signature to the PSE to indicate how much
power it will draw when operating. This signature consists
of a specific constant-current draw when the PSE port
voltage is between 15.5V and 20.5V, with the current level
60
PSE LOAD
OVER
LINE
CURRENT
50
indicating the power class to which the PD belongs. Per
the IEEE 802.3af specification, there are five classes and
three power levels for a PD as shown in Table 1. Note that
class 4 is presently reserved by the IEEE for future use.
Figure 4 shows an example PD load line, starting with the
shallow slope of the 25k signature resistor below 10V, then
drawing the classification current (in this case, class 3)
between 15.5V and 20.5V. Also shown is the load line for
the LTC4263. It maintains a low impedance until reaching
current limit at 60mA (typ).
CURRENT (mA)
48mA
40
CLASS 4
30
CLASS 3
The LTC4263 will classify a port immediately after a
successful detection. It measures the PD classification
signature current by applying 18V (typ) to the port and
measuring the resulting current. The LTC4263 identifies
the three IEEE power levels and stores the detected class
internally for use by the power management circuitry. In
addition, the LTC4263 allows selectable enforcement of
IEEE classification power levels. With the ENFCLS pin
high, the LTC4263 reduces the ICUT current threshold if it
detects class 1 or class 2, thereby insuring that PDs which
violate their advertised class are shut down.
33mA
23mA
20
TYPICAL
CLASS 3
PD LOAD
LINE
10
0
0
5
CLASS 2
14.5mA
CLASS 1
CLASS 0
10
15
VDD48 – VOUT
6.5mA
20
25
4263 F04
Figure 4. Classification Load Lines
Table 1. IEEE 802.3af Classification, PD Power Consumption, and LTC4263 Enforced Power Output
IEEE 802.3af
CLASS
CLASSIFICATION
CURRENT
MAXIMUM
IEEE ALLOWABLE
PD POWER
LTC4263
ENFORCED ICUT
THRESHOLD*
0
0mA to 5mA
12.95W
375mA (typ)
PD Does Not Implement Classification, Unknown Power
1
8mA to 13mA
3.84W
100mA (typ)
Low Power PD
2
16mA to 21mA
6.49W
175mA (typ)
Medium Power PD
3
25mA to 31mA
12.95W
375mA (typ)
Full Power PD
4
35mA to 45mA
12.95W
375mA (typ)
Reserved, Power as Class 0
CLASS DESCRIPTION
*Enforced ICUT active if ENFCLS pin is high. Otherwise, ICUT is 375mA (typ).
4263fe
12
LTC4263
APPLICATIONS INFORMATION
Power Management
The LTC4263 includes a power management feature
allowing simple implementation of power management
across multiple ports driven by a single power supply. The
PWRMGT pins of all LTC4263 devices are tied together
along with an RC network to prevent over-allocation of
power in a multi-port system.
Immediately following classification, the LTC4263 performs
a power management check to ensure power is available
to supply the newly classed PD. The allocated power is
represented by the voltage on the shared PWRMGT node
and the LTC4263 checks the allocated power by measuring this voltage. If the PWRMGT voltage is less than 1V,
there is power available and the power needs of the new
PD are added to the already allocated power on the node.
To allocate power, a current proportional to the power
needs for the new PD is sourced out of the PWRMGT pin
(Table 2).
For multiple LTC4263s implementing power management,
the PWRMGT pins are connected together and to a RC
network connected to VSS as shown in Figure 5. The value of
RPM represents the full load output capability of the system
power supply (PFULL_LOAD). Select a 1% resistor to set the
full load output power using the following formula:
RPM =
213kΩ • W
PFULL _ LOAD
The LTC4263 power management uses pulse width
modulation to set the power requirements of each PD.
Capacitor CPM is used as a lowpass filter to generate the
average power requirement for all PDs in the system. Set
CPM to 1μF.
If power management is not used, tie PWRMGT to VSS.
PWRMGT
LTC4263
Table 2. LTC4263 Power Management
IEEE 802.3af
CLASS
PSE OUTPUT
POWER REQUIRED
LTC4263 PWRMGT
CURRENT
0, 3, 4
15.4W
–72.3μA
2
7W
–32.8μA
1
4W
–18.8μA
When additional current is added to the PWRMGT node,
the voltage rises toward the 1V threshold. After adding
current, the LTC4263 verifies that the power supply is not
over-allocated by verifying the node voltage remains below
1V. If the voltage is below 1V, the LTC4263 proceeds to
power the port. If over 1V, the current is removed from
the node, port powering is aborted, and the LTC4263 goes
back into detection mode.
VSS
PWRMGT
LTC4263
VSS
PWRMGT
LTC4263
VSS
PWRMGT
RPM
VSS
CPM
1μF
LTC4263
VSS
4263 F05
Figure 5. PWRMGT Pin Connections
4263fe
13
LTC4263
APPLICATIONS INFORMATION
Power Control
The primary function of the LTC4263 is to control the
delivery of power to the PSE port. In order to meet IEEE
802.3af requirements and provide a robust solution, a
variety of current limit and current monitoring functions
are needed, as shown in Figure 6. All control circuitry
is integrated and the LTC4263 requires no external
MOSFET, sense resistor, or microcontroller to achieve
IEEE compliance.
The LTC4263 includes an internal MOSFET for driving
the PSE port. The LTC4263 drives the gate of the internal
MOSFET while monitoring the current and the output voltage at the OUT pin. This circuitry couples the 48V input
supply to the port in a controlled manner that satisfies
the PD’s power needs while minimizing disturbances on
the 48V backplane.
PORT CURRENT
500mA
CURRENT LIMIT
PORT OFF IN tOVLD
400mA
IINRUSH refers to current at port turn-on and ILIM is the
maximum allowable current in the case of a short after the
port is powered. Because the IEEE specification calls out
identical values, the LTC4263 implements both as a single
current limit referred to as ILIM .
When 48V power is applied to the port, the LTC4263 is
designed to power-up the PD in a controlled manner without
causing transients on the input supply. To accomplish this,
the LTC4263 implements inrush current limit. At turn-on,
current limit will allow the port voltage to quickly rise
until the PD reaches its input turn-on threshold. At this
point, the PD begins to draw current to charge its bypass
capacitance, slowing the rate of port voltage increase.
If at any time the port is shorted or an excessive load is
applied, the LTC4263 limits port current to avoid a hazardous condition. The current is limited to ILIM for port
voltages above 30V and is reduced for lower port voltages
(see the Foldback section). Inrush and short-circuit current limit are allowed to be active for 62ms (typ) before
the port is shut off.
Port Fault
300mA
NORMAL
OPERATION
200mA
100mA
0mA
DC DISCONNECT CUT
(IMIN)
(ICUT)
LIMIT
(ILIM)
DC DISCONNECT
PORT OFF IN tMPDO
4263 F07
Figure 6. Current Thresholds and Current Limits
Port Overload
A PSE port is permitted to supply up to 15.4W continuously
and up to 400mA (ICUT) for up to 75ms (tOVLD) when in
overload. Per the IEEE 802.3af specification, the PSE is
required to remove power if a port stays in an overload
condition. The LTC4263 monitors port current and removes
port power if port current exceeds 375mA (typ) for greater
than 62ms (typ).
Port Inrush and Short-Circuit
The IEEE 802.3af standard lists two separate maximum
current limits, IINRUSH and ILIM, that a PSE must implement.
If the port is suddenly shorted, the internal MOSFET power
dissipation can rise to very high levels until the short-circuit
current limit circuit can respond. A separate high speed
current limit circuit detects severe fault conditions (IOUT >
650mA (typ)) and quickly turns off the internal MOSFET if
such an event occurs. The circuit then limits current to ILIM
while the tOVLD timer increments. During a short-circuit,
ILIM will be reduced by the foldback circuitry.
tOVLD Timing
For overload, inrush, and short-circuit conditions, the
IEEE 802.3af standard limits the duration of these events
to 50ms-75ms. The LTC4263 includes a 62ms (typ) tOVLD
timer to monitor overload conditions. The timer is incremented whenever current greater than ICUT flows through
the port. If the current is still above ICUT when the tOVLD
timer expires, the LTC4263 will turn off power to the port
and flash the LED. In this situation, the LTC4263 waits
four seconds and then restarts detection. If the overload
4263fe
14
LTC4263
APPLICATIONS INFORMATION
condition is removed before the t OVLD timer expires, the
port stays powered and the timer is reset.
power and shuts down all functions including the internal
5V regulator. Once the die cools, the LTC4263 waits four
seconds, then restarts detection.
Foldback
Foldback is designed to limit power dissipation in the
LTC4263 during power-up and momentary short-circuit
conditions. At low port output voltages, the voltage
across the internal MOSFET is high, and power dissipation will be large if significant current is flowing. Foldback
monitors the port output voltage and reduces the ILIM
current limit level for port voltages of less than 28V, as
shown in Figure 7.
200
The DC disconnect circuit monitors port current whenever
power is on to detect continued presence of the PD. IEEE
802.3af mandates a minimum current of 10mA that the
PD must draw for periods of at least 75ms with optional
dropouts of no more than 250ms. The tMPDO disconnect
timer increments whenever port current is below 7.5mA
(typ). If the timer expires, the port is turned off and the
LTC4263 waits 1.5 seconds before restarting detection. If
the undercurrent condition goes away before tMPDO (350ms
(typ)), the timer is reset to zero. The DC disconnect circuit
includes a glitch filter to prevent noise from falsely resetting
the timer. The current must be present for a period of at
least 20ms to guarantee reset of the timer. To enable DC
disconnect, tie the OSC pin to VSS .
100
AC Disconnect
500
400
ILIM (mA)
DC Disconnect
300
0
0
5
10 15 20 25 30 35 40 45 50
VDD48 – VOUT (V)
4263 F07
Figure 7. Current Limit Foldback
Thermal Protection
The LTC4263 includes thermal overload protection in
order to provide full device functionality in a miniature
package while maintaining safe operating temperatures.
Several factors create the possibility for very large power
dissipation within the LTC4263. At port turn-on, while
ILIM is active, the instantaneous power dissipated by the
LTC4263 can be as high as 12W. This can cause 40ºC or
more of die heating in a single turn-on sequence. Similarly,
excessive heating can occur if an attached PD repeatedly
pushes the LTC4263 into ILIM by drawing too much current. Excessive heating can also occur if the VDD5 pin is
shorted or overloaded.
The LTC4263 protects itself from thermal damage by
monitoring die temperature. If the die temperature exceeds
the overtemperature trip point, the LTC4263 removes port
AC disconnect is an alternate method of sensing the presence or absence of a PD by monitoring the port impedance.
The LTC4263 forces an AC signal from an internal sine wave
generator on to the port. The ACOUT pin current is then
sampled once per cycle and compared to IACDMIN . Like DC
disconnect, the AC disconnect sensing circuitry controls the
tMPDO disconnect timer. When the connection impedance
rises due to the removal of the PD, AC peak current falls
below IACDMIN and the disconnect timer increments. If the
impedance remains high (AC peak current remains below
IACDMIN), the disconnect timer counts to tMPDO and the
port is turned off. If the impedance falls, causing AC peak
current to rise above IACDMIN for two consecutive samples
before the maximum count of the disconnect timer, the
timer resets and the port remains powered.
The AC disconnect circuitry senses the port via the ACOUT
pin. Connect a 0.47μF 100V X7R capacitor (CDET) and
a 1kΩ resistor (RDET) from the DETECT pin to the port
output as shown in Figure 8. This provides an AC path for
sensing the port impedance. The 1kΩ resistor, RDET, limits
current flowing through this path during port power-on and
power-off. An AC blocking diode (DAC) is inserted between
the OUT pin and the port to prevent the AC signal from
4263fe
15
LTC4263
APPLICATIONS INFORMATION
1A
+
0.1μF
100V
CPSE
0.1μF
X7R, 100V
LTC4263
NC
0.1μF
ISOLATED
48V SUPPLY
–
LED
LEGACY
VDD5
500k
ENFCLS
MIDSPAN
SD
PWRMGT
VDD48
VSS
OUT
VSS
OUT
DAC
CMLSH05-4
0.1μF
4263 F08
RDET
1k
OSC
SMAJ58A
CDET
0.47μF
X7R, 100V
ACOUT
Figure 8. LTC4263 Using AC Disconnect
being shorted by the LTC4263’s power control MOSFET.
The 500k resistor across DAC allows the port voltage to
decay after disconnect occurs.
Sizing of capacitors is critical to ensure proper function
of AC disconnect. CPSE (Figure 8) controls the connection
impedance on the PSE side. Its capacitance must be kept
low enough for AC disconnect to be able to sense the PD.
On the other hand, CDET has to be large enough to pass
the signal at 110Hz. The recommended values are 0.1μF
for CPSE and 0.47μF for CDET. The sizes of CPSE, CDET,
and RDET are chosen to create an economical, physically
compact and functionally robust system. Moreover, the
complete Power over Ethernet AC disconnect system (PSE,
transformers, cabling, PD, etc.) is complex; deviating from
the recommended values of CDET, RDET and CPSE is strongly
discouraged. Contact the Linear Technology Applications
department for additional support.
Internal 110Hz AC Oscillator
The LTC4263 includes onboard circuitry to generate a
110Hz (typ), 2VP-P sine wave on its OSC pin when a
0.1μF capacitor is connected between the OSC pin and
VSS. This sine wave is synchronized to the controller
inside the LTC4263 and should not be externally driven.
Tying the OSC pin to VSS shuts down the oscillator and
enables DC disconnect.
Power-On Reset and Reset/Backoff Timing
Upon start-up, the LTC4263 waits four seconds before
starting its first detection cycle. Depending on the results of this detection it will either power the port, repeat
detection, or wait 3.2 seconds before attempting detection
again if in midspan mode.
The LTC4263 may be reset by pulling the SD pin low. The
port is turned off immediately and the LTC4263 sits idle.
After SD is released there will be a 4-second delay before
the next detection cycle begins.
VDD5 Logic-Level Supply
The VDD5 supply for the LTC4263 can either be supplied
externally or generated internally from the VDD48 supply.
If supplied externally, a voltage between 4.5V and 5.5V
should be applied to the VDD5 pin to cause the internal
regulator to shut down. If VDD5 is to be generated internally, the voltage will be 4.4V (typ) and a 0.1μF capacitor
should be connected between VDD5 and VSS. Do not
connect the internally generated VDD5 to anything other
than a bypass capacitor and the logic control pins of the
same LTC4263.
LED Flash Codes
The LTC4263 includes a multi-function LED driver to inform
the user of the port status. The LED is turned on when the
port is connected to a PD and power is applied. If the port
is not connected or is connected to a non-powered device
with a 150Ω or shorted termination, the port will not be
powered and the LED will be off. For other port conditions,
the LTC4263 blinks a code to communicate the status
to the user as shown in Table 3. One flash indicates low
signature resistance, two flashes indicates high resistance,
five flashes indicates an overload fault, and nine flashes
indicates that power management is preventing the port
from turning on.
4263fe
16
LTC4263
APPLICATIONS INFORMATION
When active, the LED flash codes are repeated every 1.2
seconds. The duration of each LED flash is 75ms. Multiple
LED flashes occur at a 300ms interval.
The LTC4263 includes a feature for efficiently driving the
LED from a 48V power supply without the wasted power
caused by having to drop over 45V in a current limit
resistor. When operating the VDD5 supply internally, the
LTC4263 drives the LED pin with a 6% duty cycle PWM
signal. This allows use of the simple LED drive circuit in
Figure 9 to minimize power dissipation. The modulation
frequency of the LED drive is 28kHz, making the on period
2.2μs. During the 2.2μs that the LED pin is pulled low, current ramps up in the inductor, limited by RLED. Diode D2
completes the circuit by allowing current to circulate while
the LED pin is open circuit. Since current is only drawn
from the power supply 6% of the time, power dissipation
is substantially reduced.
When VDD5 is powered from an external supply, the PWM
signal is disabled and the LED pin will pull down continuously when on. In this mode, the LED can be powered from
the 5V supply with a simple series resistor.
IEEE 802.3af COMPLIANCE AND EXTERNAL
COMPONENT SELECTION
VDD48
D1
10mH, 21mA
COILCRAFT
DS1608C-106
D2
BAS19
RLED
1k
LED
VDD48
LTC4263
VDD5
0.1μF
VSS
4263 F09
Figure 9. LED Drive Circuit with Single 48V Supply
This section discusses the other elements that go along
with the LTC4263 to make an IEEE 802.3af compliant PSE.
The LTC4263 is designed to control power delivery in IEEE
802.3af compliant Power Sourcing Equipment. Because
proper operation of the LTC4263 also depends on external
components and power sources like the 48V supply, using
the LTC4263 in a PSE does not in itself guarantee IEEE
802.3af compliance. To ensure a compliant PSE design,
it is recommended to adhere closely to the example application circuits provided. For further assistance contact
the Linear Technology Applications department.
Table 3. Port Status and LED Flash Codes
PORT STATUS
LED FLASH CODE
FLASH PATTERN
Non-Powered Device
0Ω < RPORT < 200Ω
Off
LED Off
Port Open
RPORT > 1MΩ
Off
LED Off
Port On
25kΩ
On
LED On
Low Signature Resistance
300Ω < RPORT < 15kΩ
1 Flash
High Signature Resistance
33kΩ < RPORT < 500kΩ
2 Flashes
Port Overload Fault
5 Flashes
Power Management
Allocation Exceeded
9 Flashes
4263fe
17
LTC4263
APPLICATIONS INFORMATION
Common Mode Chokes
Both non-powered and powered Ethernet connections
achieve best performance for data transfer and EMI
when a common mode choke is used on each port. For
cost reduction reasons, some designs share a common
mode choke between two adjacent ports. This is not
recommended. Sharing a common mode choke between
two ports couples start-up, disconnect and fault transients
from one port to the other. The end result can range
from momentary noncompliance with IEEE 802.3af to
intermittent behavior and even to excessive voltages that
may damage circuitry in both the PSE and PD connected
to the port.
Transient Suppressor Diode
IEEE 802.3af Power over Ethernet is a challenging Hot
Swap™ application because it must survive unintentional
abuse by repeated plugging in and out of devices at the
port. Ethernet cables could potentially be cut or shorted
together. Consequently, the PSE must be designed to
handle these events without damage.
The most severe of these events is a sudden short on
a powered port. What the PSE sees depends on how
much CAT-5 cable is between it and the short. If the short
occurs on the far end of a long cable, the cable inductance
will prevent the current in the cable from increasing too
quickly and the LTC4263 built-in short-circuit protection
will control the current and turn off the port. However,
the high current along with the cable inductance causes
a large flyback voltage to appear across the port when the
MOSFET is turned off. In the case of a short occurring
with a minimum length cable, the instantaneous current
can be extremely high due to the lower inductance. The
LTC4263 has a high speed fault current limit circuit that
shuts down the port in 20μs (typ). In this case, there is
lower inductance but higher current so the event is still
severe. A transient suppressor is required to clamp the port
voltage and prevent damage to the LTC4263. An SMAJ58A
or equivalent device works well to maintain port voltages
within a safe range. A bidirectional transient suppressor
should not be used. Good board layout places the transient
suppressor between the port and the LTC4263 to enhance
the protective function.
If the port voltage reverses polarity and goes positive,
the OUT pin can be overstressed because this voltage is
stacked on top of the 48V supply. In this case, the transient
suppressor must clamp the voltage to a small positive value
to protect the LTC4263 and the PSE capacitor.
Component leakages across the port can have an adverse
affect on AC disconnect and even affect DC disconnect
if the leakage becomes severe. The SMAJ58A is rated
at less than 5μA leakage at 58V and works well in this
application. There is a potential for stress induced leakage,
so sufficient margins should be used when selecting
transient suppressors for these applications.
Capacitors
Sizing of both the CDET and CPSE capacitors is critical for
proper operation of the LTC4263 AC disconnect sensing.
See the AC Disconnect section for more information. Note
that many ceramic capacitors have dramatic DC voltage
and temperature coefficients. Use 100V or higher rated
X7R capacitors for CDET and CPSE , as these have reduced
voltage dependence while also being relatively small and
inexpensive. Bypass the 48V supply with a 0.1μF, 100V
capacitor located close to the LTC4263. The VDD5 supply
also requires a 0.1μF bypass capacitor.
4263fe
18
LTC4263
APPLICATIONS INFORMATION
Fuse
While the LTC4263 does not require a fuse for proper
operation or for compliance with IEEE 802.3af, some
safety requirements state that the output current must be
limited to less than 2A in less than 60 seconds if any one
component fails or is shorted. Since the LTC4263 is the
primary current limiter, its failure could result in excess
current to the port. To meet these safety requirements, a
fuse can be placed in the positive leg of the port. The fuse
must be large enough that it will pass at least 450mA when
derated for high temperature but small enough that it will
fuse at less than 2A at cold temperature. This requirement
can usually be satisfied with a 1A fuse or PTC. Placing the
fuse between the RJ-45 connector and the LTC4263 and
its associated circuitry provides additional protection for
this circuitry. Consult a safety requirements expert for the
application specific requirements.
Power Supply
Poor regulation on the 48V supply can lead to
noncompliance. The IEEE specification requires a PSE
output voltage between 44V and 57V. When the LTC4263
begins powering an Ethernet port, it controls the current
through the port to minimize disturbances on VSS. However,
if the VSS supply is underdamped or otherwise unstable,
its voltage could go outside of the IEEE-specified limits,
causing the PSE to be noncompliant. This scenario can be
even worse when a PD is unplugged because the current
can drop immediately to zero. In both cases the port voltage
must always stay between 44V and 57V. Beyond this, the
IEEE 802.3af specification places specific ripple, noise and
load regulation requirements on the PSE. Disturbances
on VSS can also adversely affect detection, classification
and AC disconnect sensing. For these reasons, proper
bypassing and stability of the VSS supply is important.
Another problem that can affect the VSS supply is
insufficient power, leading to the supply voltage dropping
out of the specified range. The 802.3af specification states
that if a PSE powers a PD it must be able to provide the
maximum power level requested by the PD based on
the PD’s classification. The specification does allow a
PSE to choose not to power a port, typically because the
PD requires more power than the PSE has available to
deliver. If a PSE is built with a VSS supply not capable of
delivering full power to all ports, it is recommended to
use the LTC4263 power management feature to prevent
ports from being turned on when there is insufficient
power. Because the specification also requires the PSE
to supply an inrush current of 400mA at up to a 5% duty
cycle, the VSS supply capability should be at least a few
percent higher than the maximum total power the PSE
needs to supply to the PDs.
Isolation
The IEEE 802.3af standard requires Ethernet ports to be
electrically isolated from all other conductors that are
user accessible. This includes the metal chassis, other
connectors, and the AC power line. Environment A isolation
is the most common and applies to wiring within a single
building serviced by a single AC power system. For this
type of application, the PSE isolation requirement can be
met with the use of a single, isolated 48V supply powering
several LTC4263 ports. Environment B, the stricter isolation
requirement, is for networks that cross an AC power
distribution boundary. In this case, electrical isolation
must be maintained between each port in the PSE. The
LTC4263 can be used to build a multi-port Environment B
PSE by powering each LTC4263 from a separate, isolated
48V supply. In all PSE applications, there should be no
user accessible connections to the LTC4263 other than
the RJ-45 port.
4263fe
19
LTC4263
TYPICAL APPLICATIONS
Three Port Midspan PSE with Power Management Set for 30W
MIDSPAN
IN
ISOLATED
48V
12
0.1μF
2
3
13
5
6
LTC4263
VDD5
VDD48
SD
LED
LEGACY
PWRMGT
MIDSPAN
ENFCLS
OSC
ACOUT
VSS
OUT
VSS
OUT
11
1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
0.1μF
100V
14
MIDSPAN
OUT
1k
4
7
RJ45
RJ45
8
0.1μF
100V
10
9
SMAJ58A
MIDSPAN
OUT
MIDSPAN
IN
14
12
0.1μF
2
3
13
5
6
LTC4263
VDD5
VDD48
SD
LED
LEGACY
PWRMGT
MIDSPAN
ENFCLS
OSC
ACOUT
VSS
OUT
VSS
OUT
11
1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
0.1μF
100V
1k
4
7
RJ45
RJ45
8
0.1μF
100V
10
9
SMAJ58A
MIDSPAN
IN
12
0.1μF
2
3
13
5
6
LTC4263
VDD5
SD
LEGACY
MIDSPAN
ENFCLS
VDD48
LED
PWRMGT
OSC
ACOUT
VSS
OUT
VSS
OUT
11
1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
0.1μF
100V
14
MIDSPAN
OUT
1k
4
7
RJ45
RJ45
8
0.1μF
100V
10
9
SMAJ58A
4263 TA02
RPM
7.15k
1%
CPM
1μF
4263fe
20
LTC4263
PACKAGE DESCRIPTION
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
0.70 ±0.05
3.30 ±0.05
3.60 ±0.05
2.20 ±0.05
1.70 ± 0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
4.00 ±0.10
(2 SIDES)
R = 0.05
TYP
3.00 ±0.10
(2 SIDES)
8
0.40 ± 0.10
14
3.30 ±0.10
1.70 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
(DE14) DFN 0806 REV B
7
0.200 REF
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
3.00 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
4263fe
21
LTC4263
PACKAGE DESCRIPTION
S Package
14-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.337 – .344
(8.560 – 8.738)
NOTE 3
.045 ±.005
.050 BSC
14
N
12
11
10
9
8
N
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
1
.030 ±.005
TYP
13
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
1
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
2
3
4
5
.053 – .069
(1.346 – 1.752)
NOTE:
1. DIMENSIONS IN
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
7
.004 – .010
(0.101 – 0.254)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
6
.050
(1.270)
BSC
S14 0502
4263fe
22
LTC4263
REVISION HISTORY
(Revision history begins at Rev E)
REV
DATE
DESCRIPTION
E
6/10
Replaced Figure 3 in Applications Information section
PAGE NUMBER
11
4263fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC4263
TYPICAL APPLICATION
Complete Single-Port Endpoint PSE with Integrated RJ45
J1
1 TD+
TX+
1
ISOLATED
48V
7 CT
LED1
LN1351C-TR
GRN
C3
0.1μF
100V
D1
BAS19
C1
0.1μF
TX–
RX+
R2
1k
9 RD–
RX–
1:1
R6
1k
2
3
OUT TO CABLE
1:1
L1
10mH, 21mA
DS1608C-106
COILCRAFT
U1
LTC4263
11
VDD48
1
14
LED
VDD5
4
12
PWRMGT
SD
7
2
OSC
LEGACY
3
MIDSPAN
8
13
ACOUT
ENFCLS
10
5
VSS
OUT
9
6
VSS
OUT
PHY
8 TD–
2 RD+
C7, 0.47μF
100V, X7R
D5 CMLSHO5-4
F1
1A
C5
0.1μF
C4
0.1μF
100V
D2
SMAJ58A
5
10
6
11
4
VC1A
VC1B
VC2A
VC2B
5
7
22nF 22nF
2kV
1000pF
R5
510k
6
22nF
22nF
75Ω
75Ω
8
75Ω
75Ω
4263 TA03
JKO-0044
PULSE
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1737
High Power Isolated Flyback Controller
Sense Output Voltage Directly from Primary-Side Winding
TM
LTC3803
Current Mode Flyback DC/DC Controller in ThinSOT
200kHz Constant-Frequency, Adjustable Slope Compensation,
Optimized for High Input Voltage Applications
LTC4257
IEEE 802.3af PD Interface Controller
100V 400mA Internal Switch, Programmable Classification
LTC4257-1
IEEE 802.3af PD Interface Controller
100V 400mA Dual Current Limit
LTC4258
Quad IEEE 802.3af Power Over Ethernet Controller
DC Disconnect Only
LTC4259A-1
Quad IEEE 802.3af Power Over Ethernet Controller
With AC Disconnect
LTC4267
IEEE 802.3af PD Interface with Switcher
Integrated Current Mode Switching Regulator
4263fe
24
Linear Technology Corporation
LT 0610 REV E • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
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