LINER LTM4601HV 24v, 15a monolithic step down regulator Datasheet

LTC3613
24V, 15A Monolithic
Step Down Regulator with
Differential Output Sensing
DESCRIPTION
FEATURES
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Wide VIN Range: 4.5V to 24V;
VOUT Range: 0.6V to 5.5V at up to 15A
0.67% Output Voltage Accuracy
Controlled On-Time Valley Current Mode Architecture,
Excellent Current Sharing Capability
Frequency Programmable from 200kHz to 1MHz
and Synchronizable to External Clock
RSENSE or Inductor DCR Current Sensing With
Accurate Current Limit
Fast Transient Response
Differential Output Voltage Sensing Allowing 500mV
Common Mode Remote Ground
tON(MIN) = 65ns; tOFF(MIN) = 105ns
Overvoltage Protection and Current Limit Foldback
Power Good Output Voltage Monitor
Voltage Tracking Start-Up
External VCC Input for Bypassing Internal LDO
Micropower Shutdown: IQ = 15μA
7mm × 9mm 56-pin QFN Package
APPLICATIONS
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The LTC®3613 is a monolithic synchronous step-down
switching regulator capable of regulating outputs from 0.6V
to 5.5V with up to 15A output current. The controlled on-time
constant frequency valley current mode architecture allows for
both fast transient response and constant frequency switching in steady-state operation, independent of VIN, VOUT and
load. This also provides excellent current sharing capability.
Differential output voltage sensing along with a precision
internal reference combine to offer ±0.67% output regulation, even if the output ground reference deviates from
local ground by 500mV. The switching frequency can be
programmed from 200kHz to 1MHz with an external resistor. The switching frequency is also phase synchronizable
to an external clock in applications where switching noise/
EMI reduction is crucial.
Very low tON and tOFF times allow for near 0% and near 100%
duty cycles, respectively. Voltage tracking soft start-up is
provided for tracking and sequencing applications. Safety features include output overvoltage protection, programmable
current limit with foldback, and power good monitoring.
L, LT, LTC, LTM, OPTI-LOOP, Linear Technology and the Linear logo are registered trademarks
and Hot Swap and No RSENSE is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
5481178, 5487554, 6580258, 6304066, 6476589, 6774611.
Distributed Power System
Point-of-Load Converters
Servers
TYPICAL APPLICATION
Efficiency and Power Loss
vs Load Current
High Efficiency High Power Step-Down Converter
100k
PVIN
SVIN
RUN
MODE/PLLIN
EXTVCC
0.1μF
47pF
270pF
TRACK/SS
SENSE+
1000pF
ITH
RT
SGND
1.5mΩ
SW
0.1μF
15k
VOUT
1.5V
15A
BOOST
PGND
VOSNS+
VOSNS–
3.0
2.5
70
60
2.0
FORCED
CONTINUOUS
MODE
50
40
1.5
30
1.0
20
+
VIN = 12V
VOUT = 1.5V
10
10k
4.7μF
115k
10Ω
0.47μH
PULSE-SKIPPING MODE
80
10Ω
INTVCC
21k
82μF
0.1μF
SENSE–
VRNG
90
POWER LOSS (W)
LTC3613
VOUT
PGOOD
3.5
100
VIN
4.5V TO 24V
+
EFFICIENCY (%)
INTVCC
330μF
×2
0
0.01
0.5
0
0.1
10
1
LOAD CURRENT (A)
3613 TA01a
3613 TA01
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LTC3613
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
56 PVIN
55 PVIN
54 PVIN
53 PVIN
52 NC
51 SW
50 SW
49 SW
48 SW
47 SW
46 SW
45 SW
TOP VIEW
PVIN 1
PVIN 2
PVIN 3
PVIN 4
PVIN 5
PVIN 6
PVIN 7
PVIN 8
PVIN 9
SW 10
BOOST 11
SGND 12
PGOOD 13
SNS+ 14
SNS– 15
SGND 16
44 PGND
43 PGND
42 PGND
41 PGND
40 PGND
39 PGND
38 PGND
37 PGND
36 PGND
35 SW
34 INTVCC
33 INTVCC
32 SVIN
31 MODE/PLLIN
30 EXTVCC
29 SGND
SW
58
PVIN
57
SGND
59
SGND 17
VOUT 18
SGND 19
VOSNS– 20
VOSES+ 21
TRACK/SS 22
ITH 23
VRNG 24
RT 25
RUN 26
NC 27
SGND 28
Supply Voltage (PVIN, SVIN)....................... –0.3V to 24V
Boost Voltage ............................................ –0.3V to 30V
SW Voltage ................................................ –0.3V to 24V
INTVCC, EXTVCC, (BOOST-SW), MODE /PLLIN,
VRNG, PGOOD, RUN Voltages....................... –0.3V to 6V
VOSNS+, VOSNS – Voltages ........ –0.6V to (INTVCC + 0.3V)
VOUT, SENSE+, SENSE– Voltages ................. –0.6V to 6V
RT, ITH Voltages ..................... –0.3V to (INTVCC + 0.3V)
TRACK/SS Voltages ..................................... –0.3V to 5V
Operating Junction Temperature Range
(Notes 2, 4) ............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
WKH PACKAGE
56-LEAD (7mm × 9mm) MULTIPAD QFN
TJMAX = 125°C, θJA = 29°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3613EWKH#PBF
LTC3613EWKH#TRPBF
LTC3613WKH
56-Lead (7mm × 9mm) Plastic QFN
–40°C to 125°C
LTC3613IWKH#PBF
LTC3613IWKH#TRPBF
LTC3613WKH
56-Lead (7mm × 9mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC3613
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. SVIN = 15V, VFB = VOSNS+ – VOSNS–, unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
VIN
Input Voltage Operating Range
l
4.5
24
V
VOUT
Output Voltage Operating Range
l
0.6
5.5
V
IQ
Input DC Supply Current
Normal
Shutdown Supply Current
2
15
4
25
mA
μA
VREG
MODE/PLLIN = INTVCC
RUN = 0V
Regulated Differential Feedback Voltage
(VOSNS+ – VOSNS–)
ITH = 1.2V (Note 3)
TA = 25°C
TA = 0°C to 85°C
TA = –40°C to 125°C
l
l
0.5985
0.596
0.594
0.6
0.6
0.6
0.6015
0.604
0.606
V
V
V
Regulated Differential Feedback
Voltage Over Line, Load and Common Mode
(VOSNS+ – VOSNS–)
VIN = 4.5V to 24V, ITH = 0.5V to 1.9V,
VOSNS– = ±500mV (Note 3)
TA = 0°C to 85°C
TA = –40°C to 125°C
l
l
0.594
0.591
0.6
0.6
0.606
0.609
V
V
tON(MIN)
Minimum On-Time
65
ns
tOFF(MIN)
Minimum Off-Time
105
ns
gm(EA)
Error Amplifier Transconductance
ITH = 1.2V (Note 3)
l
1.4
1.7
2
mS
VRNG = 2V, VFB = 0.57V
VRNG = 0V, VFB = 0.57V
VRNG = INTVCC, VFB = 0.57V
l
l
l
80
22
39
100
30
50
120
38
61
mV
mV
mV
VSENSE(MAX)
Valley Current Sense Threshold,
VSENSE+ – VSENSE–,
Peak Current = Valley + Ripple
VSENSE(MIN)
Minimum Current Sense Threshold,VSENSE+ – VRNG = 2V, VFB = 0.63V
VSENSE–, Force Continuous Operation
VRNG = 0V, VFB = 0.63V
VRNG = INTVCC, VFB = 0.63V
VSENSE(CM)
SENSE+, SENSE– Voltage Range (Common
Mode)
ISENSE
SENSE+, SENSE– Input Bias Current
VSENSE(CM) = 0.6V
VSENSE(CM) = 5V
VRUN(TH)
RUN Pin On Threshold
VRUN Rising
VRUN(HYS)
RUN Pin Hysteresis
–50
–15
–25
l
l
–0.5
1.1
mV
mV
mV
5.5
V
±5
1
±50
4
nA
μA
1.2
1.3
V
80
ISS
Soft-Start Charging Current
VTRACKSS = 0V
UVLO
INTVCC Undervoltage Lockout
INTVCC Undervoltage Lockout Release
Falling
Rising
IVOSNS+
VOSNS+ Input Bias Current
IVOSNS–
VOSNS– Input Bias Current
mV
1.0
l
l
3.4
μA
3.65
4.2
4.0
4.5
V
V
VFB = 0.6V
±5
±25
nA
VFB = 0.6V
–15
–50
μA
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LTC3613
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. SVIN = 15V, VFB = VOSNS+ – VOSNS–, unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RT = 205k
RT = 80.6k
RT = 38.8k
175
450
900
200
500
1000
225
550
1100
kHz
kHz
kHz
Oscillator and Clock Synchronization
fOSC
Free Running Switching Frequency
CLKIH
Clock Input High Level Into Mode/PLLIN
CLKIL
Clock Input Low Level Into Mode/PLLIN
2
V
0.5
V
5.3
5.55
V
–1
–2
%
4.6
4.75
V
Internal VCC Regulator and External VCC
INTVCC
Internal VCC Voltage
6V < VIN < 24V
5.1
INTVCC(%)
Internal VCC Load Regulation
ICC = 0mA to 50mA
EXTVCC(TH)
EXTVCC Switchover Voltage
EXTVCC Rising
EXTVCC(HYS)
EXTVCC Switchover Hysteresis
ΔINTVCC
EXTVCC Voltage Drop
VEXTVCC = 5V. ICC = 50mA
PGDOV
PGOOD Upper Threshold
VFB Rising (With Respect to Regulated
Feedback Voltage VREG)
5
7.5
10
%
PGDUV
PGOOD Lower Threshold
VFB Falling (With Respect to Regulated
Feedback Voltage VREG)
–10
–7.5
–5
%
4.4
200
mV
200
mV
PGOOD Output
PGDHYS
PGOOD Hysteresis
VFB Returning
2
VPGD(LO)
PGOOD Low Voltage
IPGOOD = 5mA
0.15
%
tPGD(FALL)
Delay from OV/UV Fault to PGOOD Falling
(Note 5)
20
μs
tPGD(RISE)
Delay from OV/UV Recovery to PGOOD Rising (Note 5)
10
μs
Top Switch On-Resistance
Bottom Switch On-Resistance
7.5
5.5
mohm
mohm
0.4
V
RDS(ON)
RDS(ON)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: TJ is calculated from the ambient temperature, TA, and power
dissipation, PD, as follows:
TJ = TA + (PD • 29°C/W) (θJA is simulated per JESD51-7 high effective
thermal conductivity test board)
θJC =1°C/W (θJC is simulated when heat sink is applied at the bottom
of the package.)
Note 3: The LTC3613 is tested in a feedback loop that adjusts VFB = VOSNS+
– VOSNS– to achieve a specified error amplifier output voltage (ITH).
Note 4: The LTC3613 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3613E is guaranteed to meet specifications from
0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3613I is guaranteed over the full –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 5: Delay times are measured using 50% levels.
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LTC3613
TYPICAL PERFORMANCE CHARACTERISTICS
Transient Response:
Forced Continuous Mode
TA = 25°C unless otherwise noted
Load Step:
Forced Continuous Mode
VOUT
100mV/DIV
Load Release:
Forced Continuous Mode
VOUT
100mV/DIV
VOUT
100mV/DIV
IL
10A/DIV
IL
10A/DIV
IL
10A/DIV
ILOAD
10A/DIV
ILOAD
10A/DIV
ILOAD
10A/DIV
40μs/DIV
LOAD TRANSIENT = 0A TO 15A
VIN = 12V, VOUT = 1.5V
FIGURE 10 CIRCUIT
3613 G01
10μs/DIV
LOAD STEP = 0A TO 15A
VIN = 12V, VOUT = 1.5V
FIGURE 10 CIRCUIT
Transient Response:
Pulse-Skipping Mode
3613 G02
10μs/DIV
LOAD RELEASE = 15A TO 0A
VIN = 12V, VOUT = 1.5V
FIGURE 10 CIRCUIT
Load Release:
Pulse-Skipping Mode
Load Step: Pulse-Skipping Mode
VOUT
100mV/DIV
VOUT
100mV/DIV
VOUT
100mV/DIV
IL
10A/DIV
IL
10A/DIV
IL
10A/DIV
ILOAD
10A/DIV
ILOAD
10A/DIV
ILOAD
10A/DIV
40μs/DIV
LOAD TRANSIENT = 500mA TO 15A
VIN = 12V, VOUT = 1.5V
FIGURE 10 CIRCUIT
3613 G04
10μs/DIV
LOAD STEP = 500mA TO 15A
VIN = 12V, VOUT = 1.5V
FIGURE 10 CIRCUIT
3613 G05
10μs/DIV
LOAD RELEASE = 15A TO 500mA
VIN = 12V, VOUT = 1.5V
FIGURE 10 CIRCUIT
Soft Start-Up into
a Pre-Biased Output
Normal Soft Start-Up
3613 G03
3613 G06
Output Tracking
VIN
5V/DIV
VIN
5V/DIV
TRACK/SS
500mV/DIV
TRACK/SS
500mV/DIV
TRACK/SS
500mV/DIV
VOUT
1V/DIV
VOUT
1V/DIV
4ms/DIV
VIN = 12V
VOUT = 1.5V
FIGURE 10 CIRCUIT
3613 G07
VOUT
1V/DIV
VOUT PRE-BIASED TO 0.75V
2ms/DIV
VIN = 12V
VOUT = 1.5V
FIGURE 10 CIRCUIT
3613 G08
VIN = 12V
10ms/DIV
VOUT = 1.5V
FIGURE 10 CIRCUIT
3613 G09
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LTC3613
TYPICAL PERFORMANCE CHARACTERISTICS
Overcurrent Protection
LOAD-STEP
TRIGGER 7.5A
Short-Circuit Protection
SHORTCIRCUIT
TRIGGER
VOUT DROOPS
DUE TO
REACHING CURRENT LIMIT
VOUT
1V/DIV
TA = 25°C unless otherwise noted
Overvoltage Protection
VOUT
200mV/DIV
SHORT-CIRCUIT
REGION
OVERVOLTAGE
TRIGGER
VOUT
1V/DIV
IL
10A/DIV
NOTE
ILOAD
10A/DIV
ILOAD
10A/DIV
3613 G10
VIN = 12V
4ms/DIV
VOUT = 1.5V
FIGURE 10 CIRCUIT
Output Regulation
vs Input Voltage
VIN = 12V
20μs/DIV
VOUT = 1.5V
FIGURE 10 CIRCUIT
NOTE: SW IS FORCED LOW
FOR EXTENDED PERIODS TO
REMOVE OVERVOLTAGE
Output Regulation
vs Load Current
Output Regulation
vs Temperature
0.1
–0.1
3613 G12
0.2
VIN = 12V
ILOAD = 4A
0.3 FIGURE 10 CIRCUIT
ΔVOUT ERROR (%)
ΔVOUT ERROR (%)
3613 G11
200μs/DIV
VIN = 12V
VOUT = 1.5V
FIGURE 10 CIRCUIT
NOTE: INDUCTOR CURRENT REACHES
CURRENT LIMIT BEFORE FOLDBACK
AND DURING SHORT-CIRCUIT RECOVERY
0.5
VIN = 12V
ILOAD = 5A
FIGURE 10 CIRCUIT
0.3
SW
20V/DIV
NORMALIZED ΔVOUT (%)
0.5
OVERVOLTAGE REGION
0.1
–0.1
VIN = 12V
ILOAD = 0A
VOUT NORMALIZED AT TA = 25°C
0.1 FIGURE 10 CIRCUIT
0
–0.1
–0.3
–0.3
–0.5
0
4
8
12
16
INPUT VOLTAGE (V)
20
–0.5
24
0
3
9
6
LOAD CURRENT (A)
12
3613 G13
–0.2
–50 –25
Non-Synchronized Switching
Frequency vs Temperature
0.5
2.0
1.0
VIN = 12V
ILOAD = 4A
0.3 FIGURE 10 CIRCUIT
0
–1.0
0
4
8
12
VIN (V)
0.1
16
–0.1
–0.5
20
24
3613 G16
VIN = 12V
ILOAD = 0A
FREQUENCY NORMALIZED AT TA = 25°C
FIGURE 10 CIRCUIT
0
–0.5
–0.3
VIN = 12V
ILOAD = 5A
FIGURE 10 CIRCUIT
–0.5
0.5
NORMALIZED Δf (%)
NORMALIZED Δf (%)
1.5
0.5
25 50 55 100 125 150
TEMPERATURE (°C)
3613 G15
Switching Frequency
vs Load Current
1.0
0
3613 G14
Switching Frequency
vs Input Voltage
NORMALIZED Δf (%)
15
–1.0
–1.5
0
3
9
6
LOAD CURRENT (A)
12
15
3613 G17
–2.0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3613 G18
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LTC3613
TYPICAL PERFORMANCE CHARACTERISTICS
Error Amplifier Transconductance
vs Temperature
TA = 25°C unless otherwise noted
Current Sense Voltage
vs ITH Voltage
Maximum Current Sense Voltage
vs Temperature
MAXIMUM CURRENT SENSE VOLTAGE (mV)
120
1.80
CURRENT SENSE VOLTAGE (mV)
1.70
1.65
1.60
1.55
80
60
40
20
0
VRNG = 0.6V
VRNG = 0.9V
VRNG = 1.3V
VRNG = 1.6V
VRNG = 2.0V
–20
–40
1.50
–50 –25
0
0
0.5
1.5
1
ITH VOLTAGE (V)
2
3613 G22
UVLO THRESHOLDS (V)
RUN PIN THRESHOLDS (V)
STANDBY REGION
0.6
SHUTDOWN REGION
0.4
0
25 50 75 100 125 150
TEMPERATURE (°C)
3613 G25
40
VRNG = 0.6V
20
0
25 50 75 100 125 150
TEMPERATURE (°C)
3613 G24
RUN and TRACK/SS Pull-Up
Currents vs Temperature
UVLO RELEASE
(INTVCC RISING)
1.6
RUN
4.1
3.9
UVLO LOCK
(INTVCC FALLING)
3.7
3.5
0.2
VRNG = 1V
1.8
4.3
0.8
0
–50 –25
2.5
4.5
SWITCHING REGION
1.0
60
Input Undervoltage Lockout
Thresholds vs Temperature
1.6
1.2
80
3613 G23
RUN Thresholds vs Temperature
1.4
VRNG = 2V
100
0
–50 –25
–60
25 50 75 100 125 150
TEMPERATURE (°C)
CURRENT (μA)
TRANSCONDUCTANCE (mS)
100
1.75
120
3.3
–50 –25
1.4
1.2
TRACK/SS
1.0
0.8
0
25 50 75 100 125 150
TEMPERATURE (°C)
3613 G26
0.6
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3613 G27
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LTC3613
PIN FUNCTIONS
PVIN (Pins 1-9, 53-56, 57 Exposed Pad): Power Supply
Inputs. These pins connect to the drain of the internal
power MOSFETS. The PVIN exposed pad must be soldered
to the circuit board for electrical contact and rated thermal
performance. The supply voltage can range from 4.5V to
24V. The voltage on this pin is also used to adjust the TG
on-time in order to maintain constant frequency operation.
SW (Pins 10, 35, 45-51, 58 Exposed Pad): Switch Node
Connection. The (–) terminal of the bootstrap capacitor,
CB, connects to this node. This pin swings from a diode
voltage below ground up to VIN. The SW exposed pad must
be soldered to the circuit board for electrical contact and
rated thermal performance.
BOOST (Pin 11): Boosted Driver Supply Connection. The
(+) terminal of the bootstrap capacitor, CB, as well as
the cathode of the Schottky diode, DB , connects to this
node. This node swings from INTVCC – VSCHOTTKY to VIN
+ INTVCC – VSCHOTTKY.
VOUT (Pin 18): Output voltage sense for adjusting the
on-time for constant frequency operation. Tying this pin to
the local output (instead of the remote output) is recommended for most applications. This pin can be programmed
as needed for achieving the steady-state on-time required
for constant frequency operation.
VOSNS– (Pin 20): Differential Output Sensing (–) Input.
Connect this pin to the negative terminal of the output
capacitor. There is a bias current of 35μA (typical) flowing
out of this pin.
VOSNS+ (Pin 21): Differential Output Sensing (+) Input.
Connect this pin to the feedback resistor divider between
the positive and negative output capacitor terminals. In
normal operation the LTC3613 will regulate the differential output voltage which is divided down to 0.6V by the
feedback resistor divider.
SGND (Pins 12, 16, 17, 19, 28, 29, 59 Exposed Pad):
Signal Ground Connection. The SGND exposed pad must
be soldered to the circuit board for electrical contact and
rated thermal performance. All small-signal components
should be connected to the signal ground. Connect signal
ground to power ground only at one point using a single
PCB trace.
TRACK/SS (Pin 22): External Tracking and Soft-Start Input.
The LTC3613 regulates the differential feedback voltage
(VOSNS+ − VOSNS–) to the smaller of 0.6V or the voltage
on the TRACK/SS pin. An internal 1.0μA pull-up current
source is connected to this pin. A capacitor to ground at
this pin sets the ramp time to the final regulated output
voltage. Alternatively, another voltage supply connected
through a resistor divider to this pin allows the output to
track the other supply during start-up.
PGOOD (Pin 13): Power Good Indicator Output. This
open-drain logic output is pulled to ground when the
output voltage is outside of a ±7.5% window around the
regulation point.
ITH (Pin 23): Current Control Voltage and Switching Regulator Compensation Point. The current sense threshold
increases with this control voltage which ranges from
0V to 2.4V.
SENSE+ (Pin 14): Differential Current Sensing (+) Input.
For RSENSE current sensing, Kelvin (4-wire) connect
SENSE+ and SENSE– pins across the sense resistor. For
DCR sensing, Kelvin connect SENSE+ and SENSE– pins
across the sense filter capacitor.
VRNG (Pin 24): Current Sense Voltage Range Input. The
maximum allowed sense voltage between SENSE+ and
SENSE– is equal to 0.05 • VRNG . If VRNG is tied to SGND,
the device operates with a maximum sense voltage of
30mV. If VRNG is tied to INTVCC, the device operates with
a maximum sense voltage of 50mV.
SENSE– (Pin 15): Differential Current Sensing (–) Input.
For RSENSE current sensing, Kelvin (4-wire) connect the
SENSE+ and SENSE– pins across the sense resistor. For
DCR sensing, Kelvin connect the SENSE+ and SENSE– pins
across the sense filter capacitor.
RT (Pin 25): Switching Frequency Programming Pin.
Connect an external resistor from RT to signal ground to
program the switching frequency between 200kHz and
1MHz. An external clock applied to MODE/PLLIN must
be within ±30% of this free-running frequency to ensure
frequency lock.
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LTC3613
PIN FUNCTIONS
RUN (Pin 26): Digital Run Control Input. RUN self biases
high with an internal 1.3μA pull-up. Forcing RUN below
1.2V disables switching. Taking RUN below 0.75V shuts
down all bias and places the LTC3613 into micropower
shutdown mode of approximately 15μA.
EXTVCC (Pin 30): External VCC Input. When EXTVCC exceeds
4.6V, an internal switch connects this pin to INTVCC and
shuts down the internal regulator so that the controller and
gate drive power is drawn from EXTVCC. EXTVCC should
not exceed VIN.
MODE/PLLIN (Pin 31): External Clock Synchronization
Input and/or Forced Continuous Mode Input. When an
external clock is applied to this pin, the rising switching
cycle will be synchronized with the rising edge of the
external clock. Additionally, this pin determines operation
under light load conditions. When either a clock input is
detected or MODE/PLLIN is tied to INTVCC, forced continuous mode operation is selected. Tying this pin to SGND
allows discontinuous pulse-skipping mode operation at
light loads.
SVIN (Pin 32): Signal Input Supply. This pin powers the
internal control circuitry.
INTVCC (Pins 33, 34): Internal 5.3V Regulator Output. The
driver and control circuits are powered from this voltage.
Decouple this pin to power ground with a minimum of
4.7μF ceramic capacitor (CVCC). The anode of the Schottky
diode, DB, connects to this pin.
PGND (Pins 36-44): Power Ground Connection. Connect
this pin as close as practical to the (–) terminal of CVCC
and the (–) terminal of CIN.
3613fa
9
LTC3613
FUNCTIONAL DIAGRAM
VIN
CIN
PVIN
SVIN
IN
LDO
OUT EN
UVLO
+
–
–
INPUT SUPPLY
CIN
BO0ST
DB
3.65V
4.2V
TG DRV
MT
CB
L
SW
1.3μA
RUN
VOUT
–
START
ONE-SHOT
TIMER
VOUT
EXTVCC
+
+
–
–
0.75V
1.2V
RSENSE
4.6V
LOGIC
CONTROL
COUT
INTVCC
INTVCC
STOP
CVCC
MB
BG DRV
TIME
ADJUST
RFB2
RFB1
PGND
CLOCK
MODE/PLLIN
–
CLOCK
DETECT
ICMP
–
+
IREV
+
PLL
SYSTEM
SENSE+
SENSE–
RT
OSCILLATOR
RT
1μA
+
+
–
INTVCC
RPGD
PGOOD
+
–
0.645V
OV
+
–
UV
VRNG
ITH
CSS
0.6V
EA
(gm(EA) = 1.7mS)
0.555V
TRACK/SS
+
DA
(A = 1)
–
VOSNS+
VOSNS–
3613 FD
SGND
INTVCC
R1
RITH
CITH1
R2
OPERATION
(Refer to Functional Diagram)
Main Control Loop
The LTC3613 uses valley current mode control to regulate
the output voltage in a monolithic, all N-channel MOSFET
DC/DC step-down converter. Current control is achieved by
sensing the inductor current across SENSE+ and SENSE–,
either by using an explicit resistor connected in series with
the inductor or by implicitly sensing the inductor’s resistive (DCR) voltage drop through an RC filter connected
across the inductor.
In normal steady-state operation, the top MOSFET is turned
on for a fixed time interval proportional to the delay in the
one-shot timer. The PLL system adjusts the delay in the
one-shot timer until the top MOSFET turn-on is synchronized either to the internal oscillator or the external clock
input if provided. As the top MOSFET turns off, the bottom
MOSFET turns on with a small time delay (dead time) to
avoid shoot-through current. The next switching cycle is
initiated when the current comparator, ICMP, senses that
inductor current has reached the valley threshold point
3613fa
10
LTC3613
OPERATION
(Refer to Functional Diagram)
and turns the bottom MOSFET off immediately and the
top MOSFET on. Again in order to avoid shoot-through
current there is a small dead time delay before the top
MOSFET turns on.
The voltage on the ITH pin sets the ICMP valley threshold
point. The error amplifier, EA, adjusts this ITH voltage
by comparing the differential feedback signal, VOSNS+ −
VOSNS–, to a 0.6V internal reference voltage. Consequently,
the LTC3613 regulates the output voltage by forcing the
differential feedback voltage to be equal to the 0.6V internal
reference. The difference amplifier, DA, converts the differential feedback signal to a single-ended input for the
EA. If the load current increases, it causes a drop in the
differential feedback voltage relative to the reference. The
EA forces ITH voltage to rise until the average inductor
current again matches the load current.
Differential Output Sensing
The output voltage is resistively divided externally to create
a feedback voltage for the controller. The internal difference
amplifier, DA, senses this feedback voltage along with the
output’s remote ground reference to create a differential
feedback voltage. This scheme overcomes any ground
offsets between local ground and remote output ground,
resulting in a more accurate output voltage. The LTC3613
allows for remote output ground deviations as much as
±500mV with respect to local ground.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin. Power
on the INTVCC pin is derived in two ways: if the EXTVCC
pin is below 4.6V, then an internal 5.3V low dropout linear
regulator, LDO, supplies INTVCC power from PVIN; if the
EXTVCC pin is tied to an external source larger than 4.6V,
then the LDO is shut down and an internal switch shorts
the EXTVCC pin to the INTVCC pin, thereby powering the
INTVCC pin with the external source and helping to increase
overall efficiency and decrease internal self heating through
power dissipated in the LDO. This external power source
could be the output of the step-down switching regulator
itself if the output is programmed to higher than 4.6V.
The top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during
each off cycle through an external Schottky diode when
the top MOSFET turns off. If the VIN voltage is low and
INTVCC drops below 3.65V, undervoltage lockout circuitry
disables the external MOSFET driver and prevents the
power switches from turning on.
Shutdown and Start-Up
The LTC3613 can be shut down using the RUN pin. Pulling this pin below 1.2V prevents switching, and less than
0.75V disables most of the internal bias circuitry, including
the INTVCC regulator. When RUN is less than 0.75V, the
shutdown IQ is about 15μA. Pulling the RUN pin between
0.75V and 1.2V enables the controller into a standby mode
where all internal circuitry is powered-up except for the
MOSFET driver. The standby IQ is about 2mA. Releasing
the RUN pin from ground allows an internal 1.3μA current
to pull the pin above 1.2V and fully enable the controller
including the MOSFET driver. Alternatively, the RUN pin
may be externally pulled up or driven directly by logic. Be
careful not to exceed the absolute maximum rating of 6V
on this pin. When pulled up by a resistor to an external
voltage, the RUN pin will sink about 35μA of current before
reaching 6V. If the external voltage is above 6V (e.g., VIN),
select a large enough resistor value so that the voltage on
RUN will not exceed 6V.
The start-up of the output voltage, VOUT, is controlled by
the voltage on the TRACK/SS pin. When the voltage on
the TRACK/SS pin is less than the 0.6V internal reference,
the LTC3613 regulates the differential feedback voltage to
the TRACK/SS voltage instead of the 0.6V reference. This
allows the TRACK/SS pin to be used for programming a
ramp-up time for VOUT by connecting an external capacitor
from the TRACK/SS pin to SGND. An internal 1μA pull-up
current charges this capacitor, creating a voltage ramp on
the TRACK/SS pin. As the TRACK/SS voltage rises from
0V to 0.6V (and beyond), the LTC3613 forces the output
voltage, VOUT , to ramp up smoothly to its final value.
Alternatively, the TRACK/SS pin can be used to track the
start-up of VOUT to another external supply as in a master
slave configuration. Typically, this requires connecting a
resistor divider from the master supply to the TRACK/SS
pin (see Soft-Start and Tracking).
3613fa
11
LTC3613
OPERATION
When the RUN pin is pulled low to disable the controller or
when INTVCC drops below its undervoltage lockout threshold of 3.65V, the TRACK/SS pin is pulled low internally.
Light Load Current Operation
When the DC load current is less than 1/2 of the peakto-peak inductor current ripple, the inductor current can
drop to zero or become negative. If the MODE/PLLIN pin
is connected to SGND, the LTC3613 will transition into
discontinuous mode operation (also called pulse-skipping
mode), where a current reversal comparator, IREV , detects
and prevents negative inductor current by shutting off the
bottom MOSFET, MB. In this mode, both switches remain
off with the output capacitor supplying the load current.
As the output capacitor discharges and the output voltage droops lower, the EA will eventually move the ITH
voltage above the zero current level to initiate another
switching cycle.
If the MODE/PLLIN pin is tied to INTVCC or an external
clock is applied to MODE/PLLIN, the LTC3613 will be forced
to operate in continuous mode (forced continuous mode)
and not transition into discontinuous mode. In this case
the current reversal comparator, IREV , is disabled, allowing
the inductor current to become negative and thus maintain
constant frequency operation.
Frequency Selection and External Clock
Synchronization
The steady-state switching frequency of the LTC3613 is
set by an internal oscillator. The frequency of this internal
oscillator can be programmed from 200kHz to 1MHz by
connecting a resistor from the RT pin to SGND. The RT
pin is forced to 1.2V internally. A phase-locked loop (PLL)
system synchronizes the turn-on of the switching cycle to
this internal oscillator when no external clock is provided.
For applications with stringent frequency or interference requirements, an external clock source connected
to the MODE/PLLIN pin can be used to synchronize the
switching cycle turn-on to the rising edge of the clock.
The LTC3613 operates in forced continuous mode when
it is synchronized to the external clock. The external clock
frequency has to be within ±30% of the internal oscillator
frequency for successful synchronization and the clock
input levels should be greater than 2V for HI and less
than 0.5V for LO. The MODE/PLLIN pin has an internal
600kΩ pull-down resistor.
Power Good and Fault Protection
The power good pin, PGOOD, is connected internally to an
open-drain N-channel MOSFET. An external pull-up resistor
to a voltage supply of up to 6V (or INTVCC) completes the
power good detection scheme. Overvoltage and undervoltage comparators OV and UV turn on the MOSFET and pull
the PGOOD pin low when the differential feedback voltage
is outside a ±7.5% window of the 0.6V reference voltage.
The PGOOD pin is also pulled low when the LTC3613 is
in the soft-start or tracking phase, when in undervoltage
lockout, or when the RUN pin is low (shut down).
When the differential feedback voltage is within the ±7.5%
requirement, the open-drain NMOS is turned off and the
pin is pulled up by an external resistor. There is an internal
delay of 10μs before the PGOOD pin will indicate power
good once the differential feedback voltage is within the
±7.5% window. When the feedback voltage goes out of
the ±7.5% window, there is an internal 20μs delay before
PGOOD is pulled low. In an overvoltage condition, MT is
turned off and MB is turned on immediately without any
delay and held on until the overvoltage condition clears.
Foldback current limiting is provided if the output is shorted
to ground. As the differential feedback voltage drops, the
current threshold voltage on the ITH pin is pulled down
and clamped to 1.2V. This reduces the inductor valley
current level to one-fourth of its maximum value as the
differential feedback approaches 0V. Foldback current
limiting is disabled at start-up.
3613fa
12
LTC3613
APPLICATIONS INFORMATION
The Typical Application on the first page of this data sheet
is a basic LTC3613 application circuit. The LTC3613 can
be configured to sense the inductor current either through
a series sense resistor, RSENSE, or through an RC filter
across the inductor (DCR). The choice between the two
current sensing schemes is largely a design trade-off
between cost, power consumption and accuracy. DCR
sensing is becoming popular because it saves expensive
current sensing resistors and is more power efficient,
especially in high current applications. However, current sensing resistors provide the most accurate current
limits for the controller. Once the required output voltage
and operating frequency have been determined, external
component selection is driven by load requirements, and
begins with the selection of inductor and current sensing
components. Next, the proper current sense threshold is
programmed using the VRNG pin. Finally, input and output
capacitors are selected.
Output Voltage Programming and
Differential Output Sensing
The LTC3613 integrates differential output sensing with
output voltage programming, allowing for simple and
seamless design. As shown in Figure 1, the output voltage
is programmed by an external resistor divider from the
regulated output point to its ground reference. The resistive divider is tapped by the VOSNS+ pin, and the ground
reference is sensed by VOSNS–. An optional feed-forward
capacitor, CFF , can be used to improve the transient performance of the regulator system as discussed under
OPTI-LOOP® Compensation. The resulting output voltage
is given according to the following equation:
⎛ R ⎞
VOUT =0.6V• ⎜ 1+ FB2 ⎟
⎝ RFB1 ⎠
More precisely, the VOUT value programmed in the previous
equation is with respect to the output’s ground reference,
and thus is a differential quantity. For example, if VOUT
is programmed to 5V and the output ground reference
is at –0.5V, then the output will be 4.5V with respect to
signal ground. The minimum differential output voltage is
limited to the internal reference, 0.6V, and the maximum
differential output voltage is 5.5V.
SW
LTC3613
VOUT
CFF
(OPT)
RFB2
+
COUT
VOSNS
RFB1
VOSNS–
3613 F01
Figure 1. Setting Output Voltage
The VOSNS+ pin is high impedance with no input bias current. The VOSNS– pin has about 35μA of current flowing
out of the pin.
Differential output sensing allows for more accurate output
regulation in high power distributed systems having large
line losses. Figure 2 illustrates the potential variations in
the power and ground lines due to parasitic elements.
These variations are exacerbated in multi-application
systems with shared ground planes. Without differential
output sensing, these variations directly reflect as an error
in the regulated output voltage. The LTC3613’s differential
output sensing can correct for up to ±500mV of variation
in the output’s power and ground lines.
The LTC3613’s differential output sensing scheme is
distinct from conventional schemes where the regulated
output and its ground reference are directly sensed with
a difference amplifier whose output is then divided down
with an external resistive divider and fed into the error
amplifier input. This conventional scheme is limited by
the common mode input range of the difference amplifier
and typically limits differential sensing to the lower range
of output voltages.
The LTC3613 allows for seamless differential output
sensing by sensing the resistively divided feedback voltage differentially. This allows for differential sensing in
the full output range from 0.6V to 5.5V. The difference
amplifier of the LTC3613 has a –3dB bandwidth of 8MHz,
high enough to not affect main loop compensation and
transient behavior.
3613fa
13
LTC3613
APPLICATIONS INFORMATION
CIN
PVIN
+
–
VIN
POWER TRACE
PARASITICS
L
LTC3613
SW
±VDROP(PWR)
VOSNS+
RFB2
VOSNS–
PGND
RFB1
COUT1
ILOAD
COUT2 I
LOAD
GROUND TRACE
PARASITICS
±VDROP(GND)
OTHER CURRENTS
FLOWING IN
SHARED GROUND
PLANE
3613 F02
Figure 2. Differential Output Sensing Used to Correct Line Loss Variations
in a High Power Distributed System with a Shared Ground Plane
To avoid noise coupling into VOSNS+, the resistor divider
should be placed near the VOSNS+ and VOSNS– pins and
physically close to the LTC3613. The remote output and
ground traces should be routed together as a differential
pair to the remote output. These traces should be terminated as close as physically possible to the remote output
point that is to be accurately regulated through remote
differential sensing.
Switching Frequency Programming
The choice of operating frequency is a trade-off between
efficiency and component size. Lowering the operating frequency improves efficiency by reducing MOSFET switching
losses but requires larger inductance and/or capacitance
to maintain low output ripple voltage. Conversely, raising
the operating frequency degrades efficiency but reduces
component size.
The switching frequency of the LTC3613 can be programmed from 200kHz to 1MHz by connecting a resistor
from the RT pin to signal ground. The value of this resistor
is given by the following empirical formula:
R T [kΩ ] =
Not counting resistor tolerances, the switching frequency could still have a ±10% deviation from the ideal
programmed value. The internal PLL has a synchronization range of ±30% around this programmed frequency.
Therefore, during external clock synchronization be sure
that the external clock frequency is within this ±30% range
of the RT programmed frequency. It is advisable that the
RT programmed frequency be equal to the external clock
for maximum synchronization margin. Refer to Phase and
Frequency Synchronization for further details.
Inductor Selection
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of
smaller inductor and capacitor values. A higher frequency
generally results in lower efficiency because of MOSFET
gate charge losses and top MOSFET transition losses.
In addition to this basic trade-off, the effect of inductor
value on ripple current and low current operation must
also be considered.
41550
–2.2
f [kHz ]
3613fa
14
LTC3613
APPLICATIONS INFORMATION
The inductor value has a direct effect on ripple current.
The inductor ripple current, ΔIL, decreases with higher
inductance or frequency and increases with higher VIN:
ΔIL =
VOUT
f •L
⎛ V ⎞
• ⎜ 1– OUT ⎟
VIN ⎠
⎝
Accepting larger values of ΔIL allows the use of low inductances, but results in higher output voltage ripple, higher
ESR losses in the output capacitor, and greater core losses.
A reasonable starting point for setting ripple current is
ΔIL = 0.4 • IOUT(MAX) where IOUT(MAX) is the maximum
output current for the application. The maximum ΔIL
occurs at the maximum input voltage. To guarantee that
ripple current does not exceed a specified maximum, the
inductance should be chosen according to:
L=
⎛
⎞
VOUT
V
• ⎜ 1– OUT ⎟
f • ΔIL(MAX) ⎝ VIN(MAX) ⎠
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
tolerate the core loss of low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mμ cores. Ferrite core material saturates hard,
meaning that inductance collapses abruptly when the
peak design current is exceeded. This results in an abrupt
increase in inductor ripple current and consequent output
voltage ripple. Do not allow the core to saturate!
A variety of inductors designed for high current, low voltage applications are available from manufacturers such as
Sumida, Panasonic, Coiltronics, Coilcraft, Toko, Vishay,
Pulse and Würth.
Current Sense Pins and Current Limit Programming
Inductor current is sensed through the SENSE+ and
SENSE– pins and fed into the internal current comparators. The common mode input voltage range of the cur-
rent comparators is –0.5V to 5.5V. Both SENSE pins are
high impedance inputs. When the common mode range
is between –0.5V to 1.1V, there is no input bias current,
and when between 1.4V and 5.5V, there is less than 1μA
of current flowing into the pins. Between 1.1V and 1.4V,
the input bias current will be zero if the common mode
voltage is ramped up from 1.1V and less than 1μA if the
common mode voltage is ramped down from 1.4V. The
high impedance inputs to the current comparator allow
accurate DCR sensing. However, care must be taken not
to float these pins during normal operation.
The maximum allowed sense voltage VSENSE(MAX) between
SENSE+ and SENSE– is set by the voltage applied to the
VRNG pin and is given by:
VSENSE(MAX) = 0.05 • VRNG
The current mode control loop does not allow the inductor current valleys to exceed 0.05 • VRNG. The maximum
output current is given by:
IOUT(MAX) =
VSENSE(MAX) 1
+ ΔIL
RSENSE
2
The VSENSE(MAX) is shown in the figure “Maximum Current
Sense Voltage vs Temperature” in the Typical Performance
Characteristics. Note that ITH is close to 2.4V when in
current limit.
An external resistive divider from INTVCC can be used
to set the voltage on the VRNG pin between 0.6V and 2V,
resulting in maximum sense voltages between 30mV and
100mV. The wide voltage sense range allows for a variety of
applications. The VRNG pin can also be tied to either SGND
or INTVCC to force internal defaults. When VRNG is tied to
SGND, the device operates with a maximum sense voltage
of 30mV. When the VRNG pin is tied to INTVCC, the device
operates with a maximum sense voltage of 50mV. When
setting current limit, ensure that the junction temperature
does not exceed the rating of 125°C.
3613fa
15
LTC3613
APPLICATIONS INFORMATION
RSENSE RESISTOR
AND
PARASITIC INDUCTANCE
R
ESL
VOUT
SW
LTC3613
RF
SENSE+
CF
SENSE–
RF
3613 F03
FILTER COMPONENTS
PLACED NEAR SENSE PINS
Figure 3. RSENSE Current Sensing
RSENSE Inductor Current Sensing
A typical RSENSE inductor current sensing scheme is
shown in Figure 3. RSENSE is chosen based on the required
maximum output current. Given the maximum current,
IOUT(MAX), maximum sense voltage, VSENSE(MAX), set by the
VRNG pin, and maximum inductor ripple current, ΔIL(MAX),
the value of RSENSE can be chosen as:
RSENSE =
VSENSE(MAX)
ΔIL(MAX)
IOUT(MAX) –
2
Conversely, given RSENSE and IOUT(MAX), VSENSE(MAX)
and thus the VRNG voltage could be determined from the
above equation. To assure that the maximum rated output
current can be supplied for different operating conditions
and component variations, sufficient design margin should
be built into these calculations.
Because of possible PCB noise in the current sensing loop,
the current ripple of ΔVSENSE = ΔIL • RSENSE also needs
to be checked in the design to get a good signal-to-noise
ratio. In general, for a reasonably good PCB layout, a
10mV ΔVSENSE voltage is recommended as a conservative
number to start with, either for RSENSE or DCR sensing
applications.
For today’s highest current density solutions the value of
the sense resistor can be less than 1mΩ and the maximum sense voltage can be as low as 30mV. In addition,
inductor ripple currents greater than 50% with operation
up to 1MHz are becoming more common. Under these
conditions, the voltage drop across the sense resistor’s
parasitic inductance becomes more relevant. A small RC
filter placed near the IC has been traditionally used to reduce the effects of capacitive and inductive noise coupled
in the sense traces on the PCB. A typical filter consists of
two series 10Ω resistors connected to a parallel 1000pF
capacitor, resulting in a time constant of 20ns.
The filter components need to be placed close to the IC.
The positive and negative sense traces need to be routed
as a differential pair and Kelvin (4-wire) connected to the
sense resistor.
DCR Inductor Current Sensing
For applications requiring higher efficiency at high load
currents, the LTC3613 is capable of sensing the voltage
drop across the inductor DCR, as shown in Figure 4. The
DCR of the inductor represents the small amount of DC
winding resistance, which can be less than 1mΩ for today’s low value, high current inductors. In a high current
application requiring such an inductor, conduction loss
through a sense resistor would cost several points of
efficiency compared to DCR sensing.
INDUCTOR
L
DCR
VOUT
SW
COUT
L/DCR = (R1||R2) C1
LTC3613
R1
SENSE+
C1
SENSE–
R2
(OPT)
3613 F04
C1 NEAR SENSE PINS
Figure 4. DCR Current Sensing
3613fa
16
LTC3613
APPLICATIONS INFORMATION
The inductor DCR is sensed by connecting an RC filter
across the inductor. This filter typically consists of one
or two resistors (R1 and R2) and one capacitor (C1) as
shown in Figure 4. If the external R1||R2 • C1 time constant
is chosen to be exactly equal to the L/DCR time constant,
the voltage drop across the external capacitor is equal
to the voltage drop across the inductor DCR multiplied
by R2/(R1 + R2). Therefore, R2 may be used to scale
the voltage across the sense terminals when the DCR is
greater than the target sense resistance. With the ability
to program current limit through the VRNG pin, R2 may
be optional. C1 is usually selected to be in the range of
0.01μF to 0.47μF. This forces R1|| R2 to around 2k to 4k,
reducing error that might have been caused by the sense
pins’ input bias currents.
The first step in designing DCR current sensing is to
determine the DCR of the inductor. Where provided, use
the manufacturer’s maximum value, usually given at 25°C.
Increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/°C. A
conservative value for inductor temperature TL is 100°C.
The DCR of the inductor can also be measured using a good
RLC meter, but the DCR tolerance is not always the same
and varies with temperature; consult the manufacturers’
datasheets for detailed information.
From the DCR value, VSENSE(MAX) is calculated as:
(
)
VSENSE(MAX) =DCRMAX at 25°C• ⎡1+0.4% TL(MAX) –25°C ⎤
⎣
⎦
• ⎡⎣IOUT(MAX) –ΔIL /2⎤⎦
If VSENSE(MAX) is within the maximum sense voltage of
the LTC3613 as programmed by the VRNG pin (30mV to
100mV), then the RC filter only needs R1. If VSENSE(MAX) is
higher, then R2 may be used to scale down the maximum
sense voltage so that it falls within range.
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
PLOSS (R1) =
( VIN(MAX) –VOUT ) • VOUT
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
RSENSE sensing. Light load power loss can be modestly
higher with a DCR network than with a sense resistor due
to the extra switching losses incurred through R1. However,
DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
To maintain a good signal-to-noise ratio for the current
sense signal, use a minimum ΔVSENSE of 10mV. For a
DCR sensing application, the actual ripple voltage will be
determined by:
ΔVSENSE =
VIN –VOUT VOUT
•
R1• C1 VIN • f
Operating Multiple Units in Parallel
The LTC3613’s current mode control architecture makes
it straightforward to parallel multiple units for higher
output current. Figure 13 shows an example circuit of two
LTC3613s placed in parallel to provide 30A at 1.2V from
a 6V to 24V input. The signals at MODE/PLLIN are 180°
out of phase, to reduce stress on the input and output
capacitors.
Since the ITH pin voltage determines the cycle-by-cycle
valley inductor current, sharing is achieved by connecting
the ITH pins together. Because the ITH pin is sensitive to
noise, a small 22pF to 47pF decoupling capacitor should
3613fa
17
LTC3613
APPLICATIONS INFORMATION
be placed close to each ITH pin. If a compensation scheme
is stable on a single phase application, a polyphase application with N phases should be compensated as:
CITH1 = N • CITH(SINGLE), CITH2 = N • CITH2(SINGLE) and
RITH = RITH(SINGLE)/N.
The TRACK/SS pins should be connected together so
that all LTC3613s start up with the same slew rate. The
VOSENSE+ pins of paralleled LTC3613s should be connected
together to prevent any false triggering of overvoltage and
short circuit protection. Only one divider is necessary. The
remote output and ground traces should be routed together
as differential pairs and terminated at the same remote
sensing location (preferably Kelvin connected across the
bulk capacitors at the remote output point). The smaller
value ceramic input and output capacitors, however, should
be in close proximity to the ICs.
CIN and COUT Selection
In continuous mode, the current into PVIN is a square wave
of duty cycle VOUT/VIN. To prevent large voltage transients,
a low ESR input capacitor sized for the maximum RMS
current must be used. The maximum RMS capacitor current is given by:
IRMS ≅IOUT(MAX) •
VOUT
•
VIN
VIN
–1
VOUT
This formula has a maximum at VIN = 2VOUT , where IRMS
= IOUT(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturers’ ripple current ratings for electrolytic and conductive
polymer capacitors are often based on only 2000 hours of
life. This makes it advisable to further derate the capacitor
or to choose a capacitor rated at a higher temperature
than required.
The selection of COUT is primarily determined by the effective series resistance, ESR, to minimize voltage ripple. The
output ripple, ΔVOUT, in continuous mode is determined by:
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage. Typically, once the
ESR requirement for COUT has been met, the RMS current
rating generally far exceeds the peak-to-peak current ripple
requirement. The choice of using smaller output capacitance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
very low ESR to maintain the ripple voltage.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but
have lower capacitance density than other types. Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested
for use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications provided that consideration
is given to ripple current ratings and long-term reliability.
Ceramic capacitors have excellent low ESR characteristics
but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace
inductance can also lead to significant ringing. When using
ceramic input capacitors, care must be taken to ensure
that ringing from inrush currents and switching does not
pose an overvoltage hazard to the regulator.
For high switching frequencies, reducing output ripple and
better EMI filtering may require small-value capacitors that
have low ESL (and correspondingly higher self resonant
frequencies) to be placed in parallel with larger value
capacitors that have higher ESL. This will ensure good
noise and EMI filtering in the entire frequency spectrum
of interest. Even though ceramic capacitors generally
have good high frequency performance, small ceramic
capacitors may still have to be parallel connected with
large ones to optimize performance.
⎛
⎞
1
ΔVOUT ≤ΔIL ⎜ RESR +
8 • f • COUT ⎟⎠
⎝
3613fa
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LTC3613
APPLICATIONS INFORMATION
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor, CB, connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises to
approximately PVIN + INTVCC. The boost capacitor needs to
store approximately 100 times the gate charge required by
the top MOSFET. In most applications a 0.1μF to 0.47μF, X5R
or X7R dielectric capacitor is adequate. It is recommended
that the BOOST capacitor be no larger than 10% of the
INTVCC capacitor, CVCC, to ensure that the CVCC can supply
the upper MOSFET gate charge and BOOST capacitor under
all operating conditions. Variable frequency in response
to load steps offers superior transient performance but
requires higher instantaneous gate drive. Gate charge
demands are greatest in high frequency low duty factor
applications under high dI/dt load steps and at start-up.
In order to minimize SW node ringing and EMI, connect a
5Ω to 10Ω resistor in series with the BOOST pin. Make the
CB and DB connections on the other side of the resistor. This
series resistor helps to slow down the SW node rise time,
limiting the high dI/dt current through the top MOSFET that
causes SW node ringing.
INTVCC Regulator and EXTVCC Power
The LTC3613 features a PMOS low dropout linear regulator
(LDO) that supplies power to INTVCC from the SVIN supply.
INTVCC powers much of the LTC3613’s internal circuitry.
The LDO regulates the voltage at the INTVCC pin to 5.3V.
The LDO can supply a maximum current of 50mARMS and
must be bypassed to ground with a minimum of 4.7μF
ceramic capacitor. Good bypassing is needed to supply
the high transient currents required by the power MOSFET
gate drivers.
When the voltage applied to EXTVCC pin rises above 4.6V,
the INTVCC LDO is turned off and the EXTVCC is connected
to INTVCC with an internal switch. This switch remains on
as long as the voltage applied to EXTVCC remains above
4.4V. Using the EXTVCC allows the MOSFET driver and
control power to be derived from the LTC3613’s switching
regulator output during normal operation and from the
LDO when the output is out of regulation (e.g., start-up,
short circuit). If more than 50mARMS current is required
through EXTVCC, then an external Schottky diode can be
added between the EXTVCC and INTVCC pins. Do not apply
more than 6V to the EXTVCC pin and make sure that this
external voltage source is less than SVIN.
Significant efficiency and thermal gains can be realized
by powering INTVCC from the switching regulator output,
since the VIN current resulting from the driver and control
currents will be scaled by a factor of (Duty Cycle)/(Switcher
Efficiency).
The following list summarizes the four possible connections for EXTVCC:
1. EXTVCC left open (or grounded). This will cause INTVCC
to be powered from the internal 5.3V LDO resulting
in an efficiency penalty of up to 10% at high input
voltages.
2. EXTVCC connected directly to switching regulator output
VOUT > 4.6V. This provides the highest efficiency.
3. EXTVCC connected to an external supply. If a 4.6V or
greater external supply is available, it may be used to
power EXTVCC provided that the external supply is sufficient enough for MOSFET gate drive requirements.
4. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage converters, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.6V.
3613fa
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LTC3613
APPLICATIONS INFORMATION
For applications where the main input power is less than
5.3V, tie the VIN and INTVCC pins together and tie the
combined pins to the PVIN input with an optional 1Ω or
2.2Ω resistor as shown in Figure 5 to minimize the voltage
drop caused by the gate charge current. This will override
the INTVCC LDO and will prevent INTVCC from dropping
too low due to the dropout voltage.
LTC3613
VIN
PVIN
CIN
INTVCC
SVIN
RVIN
CVCC
3613 F05
Figure 5. Setup for VIN ≤ 5V
VIN Undervoltage Lockout (UVLO)
The LTC3613 has two functions that help protect the controller in case of input undervoltage conditions. A precision
UVLO comparator constantly monitors the INTVCC voltage
to ensure that an adequate gate-drive voltage is present.
The comparator enables UVLO and locks out the switching action until INTVCC rises above 4.2V. Once UVLO is
released, the comparator does not retrigger UVLO until
INTVCC falls below 3.65V. This hysteresis prevents oscillations when there are disturbances on INTVCC .
Another way to detect an undervoltage condition is to
monitor the VIN supply. Because the RUN pin has a precision
turn-on voltage of 1.2V, one can use a resistor divider from
VIN to turn on the IC when VIN is high enough. The RUN pin
has bias currents that depend on the RUN voltage as well as
SVIN voltage. These bias currents should be taken into account when designing the voltage divider and UVLO circuit
to prevent faulty conditions. Generally for RUN < 3V a bias
current of 1.3μA flows out of the RUN pin, and for RUN >
3V, correspondingly increasing current flows into the pin,
reaching about 35μA for RUN = 6V.
Soft-Start and Tracking
The LTC3613 has the ability to either soft-start by itself
with a capacitor or track the output of an external supply.
Soft-start or tracking features are achieved not by limiting
the maximum output current of the switching regulator
but by controlling the regulator’s output voltage according
to the ramp rate on the TRACK/SS pin.
When configured to soft-start by itself, a capacitor should
be connected to the TRACK/SS pin. TRACK/SS is pulled
low until the RUN pin voltage exceeds 1.2V and UVLO is
released, at which point an internal current of 1μA charges
the soft-start capacitor, CSS, connected to TRACK/SS.
Current foldback is disabled during this phase to ensure
smooth soft-start or tracking. The soft-start or tracking
range is defined to be the voltage range from 0V to 0.6V
on the TRACK/SS pin. The total soft-start time can be
calculated as:
C
tSOFTSTART =0.6V • SS
1μA
When the LTC3613 is configured to track another supply,
a voltage divider can be used from the tracking supply to
the TRACK/SS pin to scale the ramp rate appropriately.
Two common implementations of tracking as shown in
Figure 6 are coincident and ratiometric. For coincident
tracking, make the divider ratio from the external supply
the same as the divider ratio for the differential feedback
voltage. Ratiometric tracking could be achieved by using
a different ratio than the differential feedback (Figure 7).
Note that the small soft-start capacitor charging current is
always flowing, producing a small offset error. To minimize
this error, select the tracking resistive divider values to be
small enough to make this offset error negligible.
3613fa
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LTC3613
APPLICATIONS INFORMATION
VOUT
EXTERNAL
SUPPLY
VOLTAGE
VOLTAGE
EXTERNAL
SUPPLY
VOUT
TIME
TIME
Coincident Tracking
Ratiometric Tracking
3613 F06
Figure 6. Two Different Modes of Output Tracking
EXT. V
VOUT
RFB2
TO
TRACK/SS
TO VOSNS+
RFB1
RFB1
VOUT
EXT. V
RFB2
R1
TO
TRACK/SS
R2
0.6V
≥
R1+ R2 EXT. V
R2
TO VOSNS–
RFB2
TO VOSNS+
RFB1
TO VOSNS–
3613 F07
Coincident Tracking Setup
Ratiometric Tracking Setup
Figure 7. Setup for Coincident and Ratiometric Tracking
Phase and Frequency Synchronization
For applications that require better control of EMI and
switching noise or have special synchronization needs,
the LTC3613 can phase and frequency synchronize the
turn-on of the switching cycle to an external clock signal
applied to the MODE/PLLIN pin. The applied clock signal
needs to be within ±30% of the RT pin programmed freerunning frequency to assure proper frequency and phase
lock. The clock signal levels should generally comply to VIH
> 2V and VIL < 0.5V. The MODE/PLLIN pin has an internal
600k pull-down resistor to ensure pulse-skipping mode
if the pin is left floating.
The LTC3613 uses the voltages on SVIN and VOUT pins as
well as the RT programmed frequency to determine the
steady-state on-time as follows:
tON ≈
VOUT
VIN • f
An internal PLL system adjusts this on-time dynamically
in order to maintain phase and frequency lock with the
external clock. The LTC3613 will maintain phase and frequency lock under steady-state conditions for VIN, VOUT
and load current.
As shown in the previous equation, the on-time is a
function of the switching regulator’s output. This output
is measured by the VOUT pin and is used to calculate the
required on-time. Therefore, simply connecting VOUT to
the regulator’s local output point is preferable for most
applications. However, there could be applications where
the internally calculated on-time differs significantly from
the real on-time required by the application. For example,
if there are differences between the local output point and
the remotely regulated output point due to line losses, then
the internally calculated on-time will be inaccurate. Lower
efficiencies in the switching regulator can also cause the
real on-time to be significantly different from the internally
3613fa
21
LTC3613
APPLICATIONS INFORMATION
calculated on-time (see Efficiency Considerations). For
these circumstances, the voltage on the VOUT pin can
be programmed with a resistive divider from INTVCC or
from the regulator’s output itself. Note that there is a 500k
nominal resistance looking into the VOUT pin.
The PLL adjusted on-time achieved after phase locking is
the steady-state on-time required by the switching regulator, and if the VOUT programmed on-time is substantially
equal to this steady-state on-time, then the PLL system
does not have to use its ±30% frequency lock range for
systematic corrections. Instead the lock range can be used
to correct for component variations or other operating point
conditions. If needed, the VOUT pin can be programmed to
achieve the steady-state on-time as required by the application and therefore maintain constant frequency operation.
If the application requires very low on-times approaching
minimum on-time, the PLL system may not be able to
maintain a ±30% synchronization range. In fact, there is
a possibility of losing phase/frequency lock at minimum
on-time, and definitely losing phase/frequency lock for
applications requiring less than minimum on-time. This
is discussed further under Minimum On-Time, Minimum
Off-Time and Dropout Operation.
During dynamic transient conditions either in the line or
load (e.g., load step or release), the LTC3613 may lose
phase and frequency lock in the process of achieving
faster transient response. For large slew rates (e.g., 10A/
μs), phase and frequency lock will be lost (see Figure 8)
until the system returns back to a steady-state condition
at which point the device will resume frequency lock and
eventually achieve phase lock to the external clock. For
relatively small slew rates (10A/s), phase and frequency
lock can still be maintained.
For light loading conditions, the phase and frequency
synchronization will be active if there is a clock input applied. If there is no clock input during light loading, then
the switching frequency is based on what the MODE/PLLIN
pin is tied to. When MODE/PLLIN is tied to INTVCC, the
LTC3613 will operate in forced continuous mode at the RT
programmed free-running frequency. When MODE/PLLIN
pin is tied to signal ground, the LTC3613 will operate in
pulse-skipping discontinuous conduction mode for light
loading and will switch to continuous conduction (at the
free-running frequency) for normal and heavy loads.
ILOAD
CLOCK
INPUT
PHASE LOCKED
LOSES PHASE
LOCK DUE
TO FAST
LOAD STEP
ESTABLISHES
FREQUENCY
LOCK SOON
ESTABLISHES
PHASE LOCK
AFTER ~600μs
LOSES PHASE
LOCK DUE TO
FAST LOAD
RELEASE
ESTABLISHES
FREQUENCY
LOCK SOON
SW
VOUT
3613 F08
Figure 8. Phase and Frequency Locking Behavior During Transient Load Conditions
3613fa
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LTC3613
APPLICATIONS INFORMATION
Minimum On-Time, Minimum Off-Time
and Dropout Operation
The minimum on-time is the smallest duration of time in
which the LTC3613 can keep its top power MOSFET in its
on state. This minimum on-time is 65ns for the LTC3613
and is achieved when the VOUT pin is tied to its minimum
value of 0.6V while the PVIN is tied to its maximum value
of 24V. For larger values of VOUT or smaller values of
PVIN, the minimum on-time achievable will be longer than
65ns. The minimum on-time will have a dependency on
the operating conditions of the switching regulator, but is
intended to be smaller for high step-down ratio applications that will require low on-times.
In continuous mode operation, the minimum on-time limit
imposes a minimum duty cycle of:
DMIN = f • tON(MIN)
where tON(MIN) is the minimum on-time for the switching
regulator. As the equation shows, reducing the operating
frequency will alleviate the minimum duty cycle constraint.
If the application requires a smaller than minimum duty
cycle, the output voltage will still remain in regulation, but
the switching frequency will decrease from its programmed
value or lose frequency synchronization if using an external
clock. Depending on the application, this may not be of
critical importance.
The minimum off-time is the smallest duration of time
that the top power MOSFET can be turned off and then
immediately turned back on. The minimum off-time that
the LTC3613 can achieve is 105ns.
The minimum off-time limit imposes a maximum duty
cycle of:
DMAX = 1 – f • tOFF(MIN)
where tOFF(MIN) is the minimum off-time of the switching
regulator. Reducing the operating frequency alleviates the
maximum duty cycle constraint. If the maximum duty cycle
is reached, due to a drooping input voltage for example,
then the output will drop out of regulation. The minimum
input voltage to avoid dropout is:
VIN(MIN) =
VOUT
DMAX
At the onset of dropout, there is a region of PVIN about
500mV that generates two discrete off-times, one being
the minimum off-time and the other being an off-time that
is about 40ns to 60ns larger than the minimum off-time.
This secondary off-time is due to the longer delay in tripping the internal current comparator. The two off-times
average out to the required duty cycle to keep the output
in regulation with the output ripple remaining the same.
However, there is higher SW node jitter, especially apparent when synchronized to an external clock. Depending
on the application, this may not be of critical importance.
Fault Conditions: Current Limiting and Overvoltage
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3613, the maximum sense voltage is controlled
by the voltage on the VRNG pin. With valley current mode
control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley
current. The corresponding output current limit is:
ILIMIT =
VSENSE(MAX) 1
+ • ΔIL
RSENSE
2
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The current limit value should
be greater than the inductor current required to produce
maximum output power at the worst-case efficiency.
Worst-case efficiency typically occurs at the highest PVIN
and highest ambient temperature.
3613fa
23
LTC3613
APPLICATIONS INFORMATION
To further limit current in the event of a short circuit to
ground, the LTC3613 includes foldback current limiting.
If the output fails by more than 50%, then the maximum
sense voltage is progressively lowered to about one-fourth
of its full value.
If the output exceeds 7.5% of the programmed value,
then it is considered as an overvoltage (OV) condition.
In such a case, the top MOSFET is immediately turned
off and the bottom MOSFET is turned on indefinitely until
the OV condition is removed. Current limiting is not active during an OV. If the output returns to a nominal level,
then normal operation resumes. If the OV persists a long
time, the current through the inductor could exceed its
maximum rating.
OPTI-LOOP Compensation
OPTI-LOOP compensation, through the availability of the
ITH pin, allows the transient response to be optimized for
a wide range of loads and output capacitors. The ITH pin
not only allows optimization of the control loop behavior
but also provides a test point for the step-down regulator ’s
DC-coupled and AC-filtered closed-loop response. The DC
step, rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at this pin.
The ITH series RITH-CITH1 filter sets the dominant pole-zero
loop compensation. Additionally, a small capacitor placed
from the ITH pin to SGND, CITH2, may be required to attenuate high frequency noise. The values can be modified
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because their various types and values determine
the loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1μs to 10μs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The general
goal of OPTI-LOOP compensation is to realize a fast but
stable ITH response with minimal output droop due to
the load step. For a detailed explanation of OPTI-LOOP
compensation, refer to Application Note 76.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESR, where
ESR is the effective series resistance of COUT . ΔILOAD also
begins to charge or discharge COUT , generating a feedback
error signal used by the regulator to return VOUT to its
steady-state value. During this recovery time, VOUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
Connecting a resistive load in series with a power MOSFET,
then placing the two directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce a realistic load-step condition. The initial output voltage step resulting from the step
change in output current may not be within the bandwidth
of the feedback loop, so this signal cannot be used to
determine phase margin. This is why it is better to look
at the ITH pin signal which is in the feedback loop and
is the filtered and compensated feedback loop response.
The gain of the loop increases with RITH and the bandwidth
of the loop increases with decreasing CITH1. If RITH is
increased by the same factor that CITH1 is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, a feedforward capacitor, CFF, can
be added to improve the high frequency response, as shown
in Figure 1. Capacitor CFF provides phase lead by creating
a high frequency zero with RFB2 which improves the phase
margin. The output voltage settling behavior is related to
the stability of the closed-loop system and will demonstrate
overall performance of the step-down regulator.
3613fa
24
LTC3613
APPLICATIONS INFORMATION
In some applications, a more severe transient can be caused
by switching in loads with large (>10μF) input capacitors.
If the switch connecting the load has low resistance and
is driven quickly, then the discharged input capacitors are
effectively put in parallel with COUT , causing a rapid drop in
VOUT . No regulator can deliver enough current to prevent
this problem. The solution is to limit the turn-on speed of
the load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates current limiting, short-circuit protection and soft starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in
the circuit produce losses, four main sources account for
most of the losses:
1. I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause
the efficiency to drop at high output currents. In
continuous mode the average output current flows
though the inductor L, but is chopped between the
top and bottom MOSFETs.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the
input voltage, load current, driver strength and MOSFET
capacitance, among other factors. The loss is significant
at input voltages above 20V.
3. INTVCC current. This is the sum of the MOSFET driver
and control currents. The MOSFET driver current results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
controller IQ current.
Supplying INTVCC power through EXTVCC could save
several points of efficiency, especially for high VIN applications. Connecting EXTVCC to an output-derived
source will scale the VIN current required for the driver
and controller circuits by a factor of Duty Cycle/Efficiency. For example, in a 20V to 5V application, 10mA
of INTVCC current results in approximately 2.5mA of VIN
current. This reduces the mid-current loss from 10%
or more (if the driver was powered directly from VIN)
to only a few percent.
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss
and sufficient capacitance to prevent the RMS current
from causing additional upstream losses in cabling,
fuses or batteries.
Other losses, which include the COUT ESR loss, bottom
MOSFET reverse-recovery loss and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current there is no change in efficiency.
Power losses in the switching regulator will reflect as a
longer than ideal on-time. This efficiency accounted ontime in continuous mode can be calculated as:
tON(REAL) ≈
tON(IDEAL)
Efficiency
3613fa
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LTC3613
APPLICATIONS INFORMATION
Design Example
Consider a step-down converter with VIN = 6V to 24V, VOUT
= 1.2V, IOUT(MAX) = 15A, and f = 350kHz (see Figure 9).
The minimum on-time occurs for maximum VIN and should
be greater than 65ns, which is the best that the LTC3613
can achieve. The minimum on-time for this application is:
The regulated output voltage is determined by:
tON(MIN) =
⎛ R ⎞
VOUT =0.6V • ⎜ 1+ FB2 ⎟
⎝ RFB1 ⎠
Using a 20k resistor from VOSNS+ to VOSNS–, the top
feedback resistor is also 20k.
1.2V
≈ 143ns
VIN(MAX) • f 24V • 350kHz
=
Set the inductor value to give 40% ripple current at maximum VIN:
L=
The frequency is programmed by:
R T [kΩ ] =
VOUT
1.2V
⎛ 1.2V ⎞
• ⎜ 1–
⎟ ≈ 0.54μH
350kHz • 40%• 15A ⎝ 24V ⎠
Select 0.56μH, which is the nearest standard value.
41550
41550
–2.2=
–2.2 ≈ 116.5k
f [kHz ]
350
Select the nearest standard value of 115k.
SVIN
RPGD
100k
PVIN
CIN2
10μF
VOUT
PGOOD
LTC3613
RDIV1
52.3k
VRNG
RDIV2
10k
RUN
CITH1
220pF RITH
28k
SENSE+
90
CDCR RDCR
0.1μF 3.09k
SW
VOUT
1.2V
15A
CB 0.1μF
BOOST
TRACK/SS
DB
INTVCC
INTVCC
CVCC
4.7μF
ITH
CITH2 100pF
RFB2
20k
RFB1
20k
COUT2
100μF
×2
+
COUT1
330μF
2.5V
×2
60
50
FORCED
CONTINUOUS
MODE
40
30
20
VIN = 12V
VOUT = 1.2V
10
1
10
LOAD CURRENT (A)
100
3613 F10a
VOSNS+
VOSNS–
CIN1: SANYO 25SVPD82M
COUT1: SANYO 2R5TPE330M9
70
0
0.1
PGND
RT
SGND
PULSE-SKIPPING
MODE
80
L1
0.56μH
MODE/PLLIN
EXTVCC
RT
115k
100
SENSE–
350kHz
CSS
0.1μF
VIN
CIN1 6V TO 24V
82μF
25V
+
EFFICIENCY (%)
INTVCC
3613 F10
DB: CENTRAL CMDSH-3
L1: VISHAY IHLP4040DZ-056μH
Figure 9. 1.2V, 15A, 350kHz Step-Down Converter
3613fa
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LTC3613
APPLICATIONS INFORMATION
The resulting maximum ripple current is:
ΔIL =
1.2V
⎛ 1.2V ⎞
• ⎜ 1–
⎟ ≈ 5.8A
350kHz • 0.56μH ⎝ 24V ⎠
Often in high power applications, DCR current sensing is
preferred over RSENSE in order to maximize efficiency. In
order to determine the DCR filter values, first the inductor manufacturer has to be chosen. For this design, the
Vishay IHLP-4040DZ-01 model is chosen with a value of
0.56μH and DCRMAX =1.8mΩ. This implies that:
VSENSE(MAX) = DCRMAX at 25°C • [1 + 0.4% (TL(MAX)
– 25°C)] • [IOUT(MAX) – ΔIL/2]
= 1.8mΩ • [1 + 0.4% (100°C – 25°C)] •
[15A – 5.8A/2]
≈ 28.3mV
The maximum sense voltage is within the range that
LTC3613 can handle without any additional scaling. Therefore, the DCR filter consists of a simple RC filter across
the inductor. If the C is chosen to be 0.1μF, then the R can
be calculated as:
RDCR =
L
DCRMAX • CDCR
=
0.56μH
≈ 3.11k
1.8mΩ • 0.1μF
The closest standard value is 3.09k.
The resulting value of VRNG with a 50% design margin
factor is:
VRNG = VSENSE(MAX)/0.05 • MF
= 28.3mV/0.05 • 1.5 ≈ 850mV
To generate the VRNG voltage, connect a resistive divider
from INTVCC to SGND with RDIV1 = 52.3k and RDIV2 = 10k.
Select CIN to give an RMS current rating greater than 7A
at 75°C. The output capacitor COUT is chosen for a low
ESR of 4.5mΩ to minimize output voltage changes due to
inductor ripple current and load steps. The output voltage
ripple is given as:
ΔVOUT(RIPPLE) = ΔIL(MAX) • ESR = (5.8A)(4.5mΩ)
≈ 26mV
However, a 0A to 10A load step will cause an output
change of up to:
ΔVOUT(STEP) = ΔILOAD • ESR = (10A)(4.5mΩ) = 45mV
Optional 100μF ceramic output capacitors are included to
minimize the effect of ESR and ESL in the output ripple
and to improve load step response.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3613.
• Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking purposes. Use wide rails and/or entire planes for VIN, VOUT
and PGND nodes for good filtering and minimal copper
loss. Flood unused areas of all layers with copper for
better heat sinking.
• Keep signal and power grounds separate except at the
point where they are shorted together. Short signal and
power ground together only at a single point with a narrow PCB trace (or single via in a multilayer board). All
power train components should be referenced to power
ground and all small-signal components (e.g., CITH1,
RT , CSS etc.) should be referenced to signal ground.
• Place CIN, inductor, sense resistor (if used), and primary
COUT capacitors close together in one compact area.
The SW node should be compact but be large enough
to handle the inductor currents without large copper
losses. Connect PVIN as close as possible to the (+)
plate of CIN capacitor(s) that provides the bulk of the
AC current (these are normally the ceramic capacitors), and connect PGND as close as possible to the
(–) terminal of the same CIN capacitor(s). The high dI/
dt loop formed by CIN, the top MOSFET, and the bottom MOSFET should have short leads and PCB trace
lengths to minimize high frequency EMI and voltage
stress from inductive ringing. The (–) terminal of the
primary COUT capacitor(s) which filter the bulk of the
inductor ripple current (these are normally the ceramic
capacitors) should also be connected close to the (–)
terminal of CIN.
3613fa
27
LTC3613
APPLICATIONS INFORMATION
• Place the BOOST, PVIN, SW, and PGND pins facing the
power train components. Keep high dV/dt signals on
BOOST and SW away from sensitive small-signal traces
and components.
• For RSENSE current sensing, place the sense resistor
close to the inductor on the output side. Use a Kelvin
(4-wire) connection across the sense resistor and
route the traces together as a differential pair. RC filter
the differential sense signal close to SENSE+/SENSE–
pins, placing the filter capacitor as close as possible
to the pins. For DCR sensing, Kelvin connect across
the inductor and place the DCR sensing resistor closer
to the SW node and further away from the SENSE+/
SENSE– pins. Place the DCR capacitor close to the
SENSE+/SENSE– pins.
• Place the ceramic CVCC capacitor as close as possible to
the INTVCC and PGND pins. Likewise, the CB capacitor
should be as close as possible to BOOST and SW pins.
These capacitors provide the gate charging currents for
the onboard power MOSFETs.
• Place small-signal components as close to their respective pins as possible. This minimizes the possibility of
PCB noise coupling into these pins. Give priority to
VOSNS+/VOSNS–, SENSE+/SENSE–, ITH, RT and VRNG
pins. Use sufficient isolation when routing a clock signal
into MODE/PLLIN pin so that the clock does not couple
into sensitive small-signal pins.
• Filter the SVIN input to the LTC3613 with a simple RC
filter close to the pin. The RC filter should be referenced
to signal ground.
• Place the resistive feedback divider RFB1/2 as close as
possible to VOSNS+/VOSNS– pins and route the remote
output and ground traces together as a differential
pair and terminate as close to the regulation point as
possible (preferably Kelvin connect across the capacitor
at the remote output point).
3613fa
28
LTC3613
APPLICATIONS INFORMATION
PVIN
INTVCC
RVIN
2.2Ω
SVIN
RPGD
100k
CVIN
0.1μF
LTC3613
VOUT
PGOOD
CIN1
82μF
25V
RSENSE
1.5mΩ
L1
0.47μH
VRNG
CB
0.1μF
RFB2
15k
BOOST
DB
TRACK/SS
RFB1
10k
CITH2 47pF
INTVCC
RITH 21k
INTVCC
CVCC
4.7μF
PGND
ITH
RT 115k
VOSNS+
VOSNS–
RT
SGND
COUT2
100μF
×2
+
COUT1
330μF
2.5V
×2
3833 F11
CIN1: SANYO 25SVPD82M
COUT1: SANYO 2R5TPE330M9
DB: CENTRAL CMDSH-3
L1: COILTRONICS FP1109-R47
Efficiency
100
PULSE-SKIPPING
MODE
90
EFFICIENCY (%)
CITH1 270pF
VOUT
1.5V
15A
SW
EXTVCC
CSS 0.1μF
VIN
4.5V TO 24V
CF
RF1
1000pF 10Ω
SENSE+
MODE/PLLIN
+
RF2
10Ω
SENSE–
RUN
CIN2
22μF
×2
FORCED
CONTINUOUS
MODE
80
70
60
50
VIN = 12V
VOUT = 1.5V
40
0.1
1
10
LOAD CURRENT (A)
100
3613 F11a
Figure 10. 1.5V, 15A, 350kHz High Current Step-Down Converter
3613fa
29
LTC3613
TYPICAL APPLICATIONS
PVIN
RVIN
2.2Ω
SVIN
INTVCC
RPGD
100k
EXTVCC
PGOOD
30.9k
10k
VOUT
SENSE–
CSS
0.1μF
SENSE+
LTC3613
VIN
7V TO 24V
VOUT
5V
8A
SW
CB
0.1μF
RB
10Ω
BOOST
RFB2
147k
DB
ITH
RT
205k
CIN1
100μF
50V
L1
4.7μH
TRACK/SS
CITH1
1000pF RITH
49.9k
+
CDCR RDCR
0.1μF 8.25k
RUN
VRNG
CIN2
10μF
×3
CVIN
0.1μF
INTVCC
INTVCC
RFB1
20k
CVCC
4.7μF
RT
COUT2
100μF
×2
+
COUT1
330μF
6.3V
×2
MODE/PLLIN PGND
SGND
VOSNS+
VOSNS–
3613 TA02
CIN1: NICHICON UCJ1H101MCL1GS
COUT1: SANYO 6TPE330MIL
DB: DIODES INC. SDM10K45
L1: COILCRAFT XAL1010-472ME
Efficiency
100
EFFICIENCY (%)
95
VIN = 12V
VOUT = 5V
90
FORCED
CONTINUOUS
MODE
85
80
PULSE-SKIPPING
MODE
75
70
0.01
VIN = 12V
VOUT = 5V
1
0.1
LOAD CURRENT (A)
10
3613 TA03
Figure 11. 5V, 8A, 200kHz High Efficiency Step-Down Converter
3613fa
30
LTC3613
TYPICAL APPLICATIONS
PVIN
INTVCC
SVIN
RPGD
100k
LTC3613
PGOOD
RVIN
2.2Ω
CVIN
0.1μF
VOUT
MODE/PLLIN
VRNG
SENSE–
SENSE+
RUN
CIN2
10μF
×3
VIN
CIN1 4.5V TO 14V
82μF
25V
RF2
10Ω
RF1
CF
1000pF 10Ω
CSS
0.1μF
L1
1μH
RSENSE
3mΩ
SW
TRACK/SS
CITH1
470pF
+
+
CB
0.1μF
RITH
17.4k
BOOST
ITH
COUT1
330μF
2.5V
×2
VOUT
0.6V
10A
DB
RT
205k
INTVCC
RT
EXTVCC
INTVCC
CVCC
4.7μF
COUT2
100μF
×2
PGND
VOSNS+
VOSNS–
SGND
3613 TA04
DB: DIODES INC. SDM10K45
L1: IHLP-2525EZERR82M01
CIN1: SANYO 25SVPD82M
COUT: SANYO 2R5TPE330M9
Efficiency
100
90
EFFICIENCY (%)
80
70
PULSE-SKIPPING
MODE
60
50
40
FORCED
CONTINUOUS
MODE
30
20
VIN = 12V
VOUT = 0.6V
10
0
0.01
0.10
1
LOAD CURRENT (A)
10
3613 TA05
Figure 12. 0.6V, 10A, 200kHz Low Output Voltage Step-Down Converter
3613fa
31
LTC3613
TYPICAL APPLICATIONS
INTVCC
RPGD
100k
VIN
CIN2
10μF
VOUT
PGOOD
LTC3613
RDIV1
56.2k
VRNG
RDIV2
10k
RUN
+
CIN1
82μF
25V
VIN
6V TO 24V
SENSE–
SENSE+
CDCR
0.1μF
350kHz
MODE/PLLIN
BOOST
EXTVCC
CSS
0.1μF
TRACK/SS
CITH1
330pF
CB
0.1μF 0.47μH
SW
DB
INTVCC
RITH
10k
ITH
CITH2
47pF
INTVCC
CVCC
4.7μF
+
RT
SGND
RFB2
20k
COUT2
100μF
×2
RFB1
20k
PGND
RT
115k
2mΩ
VOSNS
VOSNS–
VOUT
1.2V
30A
VIN
CIN2
10μF
VOUT
PGOOD
LTC3613
VRNG
RUN
350kHz
(θ1 → θ2 = 180° OUT OF PHASE)
+
COUT1
330μF
2.5V
×4
+
CIN1
82μF
25V
SENSE–
SENSE+
CDCR
0.1μF
MODE/PLLIN
BOOST
EXTVCC
CB
0.1μF 0.47μH
2mΩ
SW
TRACK/SS
DB
INTVCC
47pF
ITH
INTVCC
CVCC
4.7μF
COUT2
100μF
×2
PGND
RT
115k
RT
SGND
VOSNS+
VOSNS–
CIN1: SANYO 25SVPD82M
COUT1: SANYO 2R5TPE330M9
DB: CENTRAL CMDSH-3
L1: COILTRONICS FP1109-R47
3613 TA12
Figure 13. 2 Phase, 1.2V, 30A, 350kHz Step-Down Converter
3613fa
32
LTC3613
TYPICAL APPLICATIONS
Efficiency
100
EFFICIENCY (%)
VIN = 12V
90 VOUT = 1.2V
80
FORCED
CONTINUOUS
MODE
70
60
50
40
30
20
10
0
0.1
1
10
LOAD CURRENT (A)
100
3613 TA013
Transient Response
VOUT(AC)
100mV/DIV
ILOAD
10A/DIV
20μs/DIV
LOAD STEP = 0A TO 30A
VIN = 12V
3613 TA14
3613fa
33
LTC3613
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
WKH Package
56-Lead QFN Multipad (7mm × 9mm)
(Reference LTC DWG # 05-08-1870 Rev Ø)
SEATING PLANE
A
7.00
BSC
2.63 REF
0.00 – 0.05
45
B
PAD 1
CORNER
3
2.90 REF
0.50 BSC
44
1
3.82 REF
bbb M C A B
4
9.00
BSC
PIN 1 ID
56
3.15 ± 0.10
4.76 ± 0.10
1.97
± 0.10
4.06 ± 0.10
0.95
REF
1.50 REF
NX b
12
aaa C 2x
2.25 ± 0.10
4.27 ± 0.10
16
29
0.58 ± 0.05
0.40 ± 0.05
28
aaa C 2x
0.90 ± 0.10
TOP VIEW
6
NX
0.08 C
// ccc C
7.50 ± 0.05
2.90 REF
5
2.63 REF
0.50 BSC
1.97
± 0.05
4.06 ± 0.05
0.25 ± 0.05
BOTTOM VIEW
(BOTTOM METALLIZATION DETAILS)
3
THE LOCATION OF THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING
CONVENTION CONFORMS TO JEDEC PUBLICATION 95 SPP-002
4
DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.20mm AND 0.30mm FROM THE TERMINAL TIP. IF THE TERMINAL
HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE
DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
5
COPLANARITY APPLIES TO THE TERMINALS AND ALL OTHER SURFACE
METALLIZATION
6
DRAWING SHOWN ARE FOR ILLUSTRATION ONLY
3.82 REF
3.15 ± 0.05
4.76 ± 0.05
9.50 ± 0.05
1.50 REF
MLP56 QFN REV Ø 0310
SYMBOL TOLERANCE
aaa
0.15
bbb
0.10
ccc
0.10
4.27 ± 0.05
2.25 ± 0.05
1.78
REF
17
NOTE:
1. DIMENSIONING AND TOLERANCING CONFORM TO ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS, ANGLES ARE IN DEGREES (°)
PIN 1
3.82 REF
1.35
± 0.05
19
PACKAGE
OUTLINE
0.40 ± 0.05
0.25 ± 0.05
1.78
REF
1.35
± 0.05
RECOMMENDED SOLDER PAD LAYOUT
TOP VIEW
3613fa
34
LTC3613
REVISION HISTORY
REV
DATE
DESCRIPTION
A
07/12
Clarified Electrical Characteristics
PAGE NUMBER
3, 4
Clarified PIn Functions
8
Modified Application Circuit
33
3613fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3613
TYPICAL APPLICATION
High Frequency 5V, 4A, 1MHz Step-Down Converter
PVIN
SVIN
PGOOD
MODE/PLLIN
RDIV1
0Ω
VRNG
CIN2
4.7μF
×2
CVIN
0.1μF
EXTVCC
VOUT
RUN
TRACK/SS
CITH1
220pF RITH
20k
SENSE+
LTC3613
CF
1000pF
SW
SGND
RSENSE
10mΩ
90
80
VOUT
5V
4A
CB
0.1μF
60
50
PULSESKIPPING
MODE
FORCED
CONTINUOUS
MODE
40
30
20
VIN = 12V
VOUT = 5V
10
CFF
22pF
DB
INTVCC
100
VIN
7V TO 24V
RF1
10Ω
BOOST
RT
CIN1
47μF
35V
70
L1
1.2μH
ITH
RT
40.2k
+
RF2
10Ω
SENSE–
CSS
0.1μF
Efficiency
RVIN
2.2Ω
EFFICIENCY (%)
RPGD
100k
INTVCC
RFB2
147k
INTVCC
CVCC
4.7μF
RFB1
20k
COUT1
22μF
×2
0
0.01
10
0.10
1
LOAD CURRENT (A)
3613 TA11
PGND
VOSNS+
VOSNS–
CIN1: KEMET T521X476M035ATE070
DB: DIODES, INC. SDM10K45
3613 TA10
L1: WÜRTH 744313120
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC3602
2.5A (IOUT), 3MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN: 4.5V to 10V, VOUT(MIN) = 0.6V, IQ = 75μA, ISD <1μA,
4mm × 4mm QFN-20, TSSOP-16E Packages
LTC3608
18V, 8A (IOUT), 1MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN: 4V to 18V, VOUT(MIN) = 0.6V, IQ = 900μA, ISD <15μA,
7mm × 8mm QFN-52 Package
LTC3610
24V, 12A (IOUT), 1MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN: 4V to 24V, VOUT(MIN) = 0.6V, IQ = 900μA, ISD <15μA,
9mm × 9mm QFN-64 Package
LTC3611
32V, 10A (IOUT), 1MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN: 4V to 32V, VOUT(MIN) = 0.6V, IQ = 900μA, ISD <15μA,
9mm × 9mm QFN-64 Package
LTC3414/
LTC3416
4A (IOUT), 4MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA, ISD <1μA,
TSSOP20E Package
LTC3415
7A (IOUT), 1.5MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 450μA, ISD <1μA,
5mm × 7mm QFN-38 Package
LTC3418
LTM4600HV
8A (IOUT), 4MHz, Synchronous Step-Down DC/DC
Converter
10A Complete Switch Mode Power Supply
LTM4601HV
12A Complete Switch Mode Power Supply
LTM4602HV
6A Complete Switch Mode Power Supply
LTM4603HV
6A Complete Switch Mode Power Supply
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 380μA, ISD <1μA,
5mm × 7mm QFN-38 Package
92% Efficiency, VIN: 4.5V to 28V, VOUT: 0.6V, True Current Mode Control,
Ultrafast Transient Response
92% Efficiency, VIN: 4.5V to 28V, VOUT: 0.6V, True Current Mode Control,
Ultrafast Transient Response
92% Efficiency, VIN: 4.5V to 28V, VOUT: 0.6V, True Current Mode Control,
Ultrafast Transient Response
93% Efficiency, VIN: 4.5V to 28V, with PLL, Output Tracking and Margining
3613fa
36 Linear Technology Corporation
LT 0712 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2011
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