Data Sheet November 2001 L9218A/G Low-Cost Line Interface Features ■ Basic forward battery only SLIC functionality at a low cost ■ Pin compatible with Agere Systems Inc. L9219 and L9217 SLIC ■ Low active power (typical 138 mW during on-hook transmission) ■ Low-power scan mode for low-power, on-hook power dissipation (59 mW typical) ■ Minimal external components ■ Distortion-free, on-hook transmission ■ Convenient operating states: — Forward battery low current limit — Forward battery high current limit — Low-power scan — Disconnect (high impedance) ■ Adjustable supervision functions: — Off-hook detector with hysteresis — Ring trip detector ■ Logic controlled high and low current limit ■ Two gain options to optimize the codec interface ■ Thermal protection with thermal shutdown indication Description This general-purpose electronic subscriber loop interface circuit (SLIC) is optimized for low cost, while still providing a satisfactory set of features. The L9218 is pin-for-pin compatible with the Agere L9219 and L9217 SLICs. The L9218 requires a 5 V power supply and single battery to operate. This is a forward battery only device. Additionally, a low-power scan mode, wherein all circuitry except the off-hook supervision is shut down to conserve power, is available. Via the logic inputs, a low or high current limit may be selected. The low value is set via a single external resistor, and the high value is 1.4 times the low value. Device overhead is fixed and is adequate for 3.14 dBm into 900 Ω of on-hook transmission. Both the loop supervision and ring trip supervision functions are offered with user-controlled thresholds via external resistors. The L9218 is offered with a receive gain that is optimized for interface to a first-generation type codec (L9218A). It is also offered with a gain option that is optimized for interface to a third- or fourth-generation type codec (L9218G). In both cases, minimizing external components required at this interface. In the receive direction, the device may be dc-coupled to a third-generation codec. No dc blocking capacitors are needed. Data control is via a parallel data control scheme. The device is available in a 28-pin PLCC package. It is built by using a 90 V complementary bipolar (CBIC) process. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Table of Contents Contents Page Features ......................................................................1 Description...................................................................1 Pin Information ............................................................4 Functional Description .................................................6 Absolute Maximum Ratings (at TA = 25 °C) ................7 Recommended Operating Conditions .........................7 Electrical Characteristics .............................................8 Ring Trip Requirements ..........................................12 Test Configurations ...................................................13 Applications ...............................................................15 dc Applications....................................................... 19 Battery Feed.........................................................19 Current Limit.........................................................19 Overhead Voltage ............................................... 19 Loop Range..........................................................20 Off-Hook Detection...............................................20 Ring Trip Detection...............................................21 Longitudinal Balance.............................................. 21 ac Design ............................................................... 22 Codec Types ........................................................22 ac Interface Network ............................................22 Receive Interface .................................................22 Example 1: Real Termination (FirstGeneration Codec) .............................................. 23 Example 2: Complex Termination (FirstGeneration Codec) ...............................................25 Power Derating ...................................................... 27 Pin-for-Pin Compatibility with L9217/L9219 ........... 27 PCB Layout Information ............................................27 Outline Diagram.........................................................28 28-Pin PLCC .......................................................... 28 Ordering Information..................................................29 Figures Figures Page Figure 15. Ring Trip Equivalent Circuit and Equivalent Application ........................... 21 Figure 16. ac Equivalent Circuit .............................. 23 Figure 17. Interface Circuit Using FirstGeneration Codec (±5 V Battery) .......... 26 Figure 18. Interface Circuit Using FirstGeneration Codec (5 V Only Codec) ..... 26 Tables Page Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 9. Pin Descriptions ...................................... 4 Input State Coding .................................. 6 Supervision Coding ................................. 6 Power Supply .......................................... 8 2-Wire Port .............................................. 9 Analog Pin Characteristics .................... 10 ac Feed Characteristics ...................... 11 Parts List for Loop Start Application Circuit Using T7504-Type Codec .......... 16 200 Ω + 680 Ω || 0.1 µF FirstGeneration Codec Design Parameters . 17 Parts List for Loop Start Application Circuit Using T8536-Type Codec .......... 18 Table 10. Table 11. Page Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Functional Diagram...................................3 28-Pin PLCC.............................................4 Ring Trip Circuits ....................................12 L9218 Basic Test Circuit.........................13 Metallic PSRR.........................................13 Longitudinal PSRR .................................13 Longitudinal Balance ..............................14 RFI Rejection ..........................................14 Longitudinal Impedance..........................14 ac Gains..................................................14 Basic Loop Start Application Circuit Using T7504-Type Codec............15 Figure 12. Basic Loop Start Application Circuit Using T8536-Type Codec............17 Figure 13. Loop Current vs. Loop Voltage ...............19 Figure 14. Off-Hook Detection Circuit ......................20 2 Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface CF2 CF1 AGND VCC IPROG BGND Description (continued) POWER CONDITIONING AND REFERENCE FORWARD AND REVERSE BATTERY DCOUT 3 RECTIFIER + AX – VTX β = 41 V/A TG TXI AAC – A=1 PT β = 9.66 + TIP/RING CURRENT SENSE A VERSION GAIN = 3.93 G VERSION GAIN = 1 + A = –1 – PR VITR – RCVN + RCVP B0 BATTERY FEED STATE CONTROL B1 B2/NC LCTH LOOP CLOSURE DETECTOR + – THERMAL SHUTDOWN + RTSP RTSN TSD RING TRIP DETECTOR NSTAT – 12-3557 (F).d Figure 1. Functional Diagram Agere Systems Inc. 3 Data Sheet November 2001 L9218A/G Low-Cost Line Interface VCC NC NC IPROG NC TSD TG Pin Information 4 3 2 1 28 27 26 RCVP 5 25 VTX RCVN 6 24 TXI LCTH 7 23 VITR DCOUT 8 22 NSTAT VBAT 9 21 NC PR 10 20 RTSP CF2 11 19 RTSN 12 13 14 15 16 17 18 CF1 B2/NC B1 B0 AGND BGND PT 28-PIN PLCC 12-3552 (F) Figure 2. 28-Pin PLCC Table 1. Pin Descriptions PLCC 1 2 3 4 5 6 4 Symbol Type Description IPROG I Current-Limit Program Input. A resistor to DCOUT sets the dc current limit of the device. NC — No Connect. NC — No Connect. CC V — 5 V Power Supply. RCVP I Receive ac Signal Input (Noninverting). This high-impedance input controls the ac differential voltage on tip and ring. RCVN I Receive ac Signal Input (Inverting). This high-impedance input controls the ac differential voltage on tip and ring. Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Pin Information (continued) Table 1. Pin Descriptions (continued) PLCC 7 Symbol Type Description LCTH I Loop Closure Threshold Input. Connect a resistor to VTX to set off-hook threshold. 8 DCOUT O dc Output Voltage. This output is a voltage that is directly proportional to the absolute value of the differential tip/ring current. 9 VBAT — Battery Supply. Negative high-voltage power supply. 10 PR I/O Protected Ring. The output of the ring driver amplifier and input to loop sensing circuitry. Connect to the loop through overvoltage protection. 11 CF2 — Filter Capacitor 2. Connect a 0.1 µF capacitor from this pin to AGND. 12 CF1 — Filter Capacitor 1. Connect a 0.47 µF capacitor from this pin to pin CF2. 13 B2/NC — Dummy Pin. Used for exact pin-for-pin compatibility with L9219. There is no physical connection to this pin, however, it may be connected to the B2 control latch to get an exact PWB footprint match with L9219. 14 B1 I State Control Input. B0 and B1 determine the state of the SLIC. See Table 2. Pin B1 has an internal pull-down. 15 B0 I State Control Input. B0 and B1 determine the state of the SLIC. See Table 2. Pin B0 has an internal pull-down. 16 AGND — Analog Signal Ground. 17 BGND — Battery Ground. Ground return for the battery supply. 18 PT I/O Protected Tip. The output of the tip driver amplifier and input to loop-sensing circuitry. Connect to loop through overvoltage protection. 19 RTSN I Ring Trip Sense Negative. Connect this pin to the ringing generator signal through a high-value resistor. 20 RTSP I Ring Trip Sense Positive. Connect this pin to the ring relay and the ringer series resistor through a high-value resistor. 21 NC — No Connect. 22 NSTAT O Loop Detector Output/Ring Trip Detector Output. When low, this logic output indicates that an off-hook condition exists or that ringing is tripped. 23 VITR O 24 TXI — Transmit ac Output Voltage. This output is a voltage that is directly proportional to the differential tip/ring current. ac/dc Separation. Connect a 0.1 µF capacitor from this point to VTX. 25 VTX O Transmit ac/dc Output Voltage. This output is a voltage that is directly proportional to the differential tip/ring current. 26 TG — 27 TSD O Transmit Gain. Connect an 8.06 kΩ from TG to VTX to set the transmit gain of the SLIC. Thermal Shutdown. When high, this logic output indicates the device is in thermal shutdown. 28 NC — Agere Systems Inc. No Connect. 5 Data Sheet November 2001 L9218A/G Low-Cost Line Interface Functional Description Table 2. Input State Coding B0 1 1 0 0 B1 State/Definition 1 Powerup, Forward Battery. Normal talk and battery feed state. Pin PT is positive with respect to PR. On-hook transmission is enabled. Low current limit is selected. 0 Powerup, Forward Battery. Normal talk and battery feed state. Pin PT is positive with respect to PR. On-hook transmission is enabled. High current limit is selected. 0 Disconnect. The tip and ring amplifiers are turned off, and the SLIC goes to a high-impedance state (>100 kΩ). Supervision outputs read on hook. Device will power up in this state. 1 Low-Power Scan. Except for off-hook detection, all circuits are shut down to conserve power. Pin PT is positive with respect to pin PR. On-hook transmission is disabled. Table 3. Supervision Coding NSTAT 0 = off-hook or ring trip. 1 = on-hook and no ring trip. 6 TSD 0 = Normal device operation. 1 = Device is in thermal shutdown. Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Absolute Maximum Ratings (at TA = 25 °C) Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter 5 V Power Supply Battery (talking) Supply Logic Input Voltage Analog Input Voltage Maximum Junction Temperature Storage Temperature Range Relative Humidity Range Ground Potential Difference (BGND to AGND) PT or PR Fault Voltage (dc) PT or PR Fault Voltage (10 x 1000 µs) Current into Ring Trip Inputs Symbol VCC VBAT — — TJ Tstg RH — PT V , VPR VPT, VPR RTSP I , IRTSN Min — — –0.5 –7.0 150 –40 5 — BAT V –5 VBAT – 15 — Typ — — — — — — — ±3 — — ±240 Max 7.0 –75 7.0 7.0 — 125 95 — 3 15 — Unit V V V V °C °C % V V V µA Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. Some of the known examples of conditions that cause such potentials during powerup are the following: 1. An inductor connected to tip and ring can force an overvoltage on VBAT through the protection devices if the VBAT connection chatters. 2. Inductance in the VBAT lead could resonate with the VBAT filter capacitor to cause a destructive overvoltage. Recommended Operating Conditions Parameter Ambient Temperature VCC Supply Voltage VBAT Supply Voltage Agere Systems Inc. Min –40 4.75 –24 Typ — 5.0 –48 Max 85 5.25 –70 Unit °C V V 7 Data Sheet November 2001 L9218A/G Low-Cost Line Interface Electrical Characteristics Minimum and maximum values are testing requirements in the temperature range of 25 °C to 85 °C and battery range of –24 V to –70 V. These minimum and maximum values are guaranteed to –40 °C based on component simulations and design verification of samples, but devices are not tested to –40 °C in production. The test circuit shown in Figure 4 is used, unless otherwise noted. Positive currents flow into the device. Typical values are characteristics of the device design at 25 °C based on engineering evaluations and are not part of the test requirements. Supply values used for typical characterization are VCC = 5.0 V, VBAT = –48 V, unless otherwise noted. Table 4. Power Supply Parameter Power Supply—Powerup, No Loop Current: ICC IBAT (VBAT = –48 V) Power Dissipation (VBAT = –48 V) Power Supply—Scan, No Loop Current: ICC IBAT (VBAT = –48 V) Power Dissipation (VBAT = –48 V) Power Supply—Disconnect, No Loop Current: ICC IBAT (VBAT = –48 V) Power Dissipation (VBAT = –48 V) Power Supply Rejection 500 Hz to 3 kHz (See Figure 5 and Figure 6)1: VCC VBAT Min Typ Max Unit — — — 4.6 –2.4 138 5.6 –2.7 158 mA mA mW — — — 2.8 –0.8 52 3.8 –1.0 67 mA mA mW — — — 1.6 –0.12 14 — — — mA mA mW 30 40 — — — — dB dB Thermal Protection Shutdown (Tjc)3 150 165 — °C — — — — 30 43 27 36 — — — — °C/W °C/W °C/W °C/W Thermal Resistance, Junction to Ambient (θJA)2, 3: Natural Convection 2S2P Board Natural Convection 2S0P Board Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board 1. This parameter is not tested in production. It is guaranteed by design and device characterization. 2. Careful thermal design as a function of maximum battery, loop length, maximum ambient temperature package thermal resistance, airflow, PCB board layers, and other related parameters must ensure that thermal shutdown temperature is not exceeded under normal use conditions. 3. Airflow, PCB board layers, and other factors can greatly affect this parameter. 8 Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Electrical Characteristics (continued) Table 5. 2-Wire Port Parameter Min Typ Max Unit Tip or Ring Drive Current = dc + Longitudinal + Signal Currents 80 — — mA Signal Current 15 — — mArms 8.5 15 — mArms 15 — — ±5 45 — mA % — |VBAT + 7.5| |VBAT + 8.0| VBAT/2 |VBAT + 6.5| |VBAT + 6.5| — |VBAT + 5.9| |VBAT + 5.9| V V V — 10 150 µA — 80 100 Ω 1800 — — Ω Longitudinal to Metallic Balance—IEEE Std. 455 (See Figure 7)5: 200 Hz to 3400 Hz 58 61 — dB Metallic to Longitudinal Balance (open loop): 200 Hz to 4 kHz 40 — — dB RFI Rejection (See Figure 8)3, 0.5 Vrms, 50 Ω Source, 30% AM Mod 1 kHz: 500 kHz to 100 MHz — — — –55 — –45 — dBV Longitudinal Current Capability per Wire 1 dc Loop Current Limit2: Allowed Range Including Tolerance3 Accuracy (RLOOP = 100 Ω, VBAT = –48 V) Powerup Open Loop Voltage Levels: Common-mode Voltage Differential Voltage VBAT = –48 V4 (Gain = 2) Differential Voltage VBAT = –48 V4 (Gain = 7.86) Disconnect State: Leakage dc Feed Resistance (for ILOOP below regulation level) (does not include protection resistor) Loop Resistance Range (–3.17 dBm overload into 900 Ω; not including protection): ILOOP = 20 mA at VBAT = –48 V ® 1. The longitudinal current is independent of dc loop current. 2. Current-limit ILIM is programmed by a resistor, RPROG , from pin IPROG to DCOUT. ILIM is specified at the loop resistance where current limiting begins (see Figure 13). 3. This parameter is not tested in production. It is guaranteed by design and device characterization. 4. Specification is reduced to |VBAT1 + 10.5 V| minimum when VBAT1 = –70 V at 85 °C. 5. Longitudinal balance of circuit card will depend on loop series protection resistor matching and magnitude. More information is available in the Applications section of this document. Agere Systems Inc. 9 Data Sheet November 2001 L9218A/G Low-Cost Line Interface Electrical Characteristics (continued) Table 6. Analog Pin Characteristics Parameter Differential PT/PR Current Sense (DCOUT): Gain (PT/PR to DCOUT) Offset Voltage at ILOOP = 0 Loop Closure Detector Threshold (RLCTH = 22.1 kΩ)1: On- to Off-hook Threshold (scan mode) Off- to On-hook Threshold (active mode) Ring Trip Comparator: Input Offset Voltage2 Internal Voltage Source Current at Input RTSP3 RCVN, RCVP: Input Bias Current Input Resistance Min Typ Max Unit 121 –100 125 — 129 100 V/A mV 8.8 6.0 — — 13.6 10.2 mA mA — –9.1 IN – 0.5 ±10 –8.6 IN — –8.1 IN + 0.6 mV V µA — — –0.2 1 –1 — µA MΩ 1. Loop closure threshold is programmed by resistor RLCTH from pin LCTH to pin DCOUT. The programming equation or relationship between off-hook threshold and resistor value is different for active mode versus scan mode (see Applications section for more details). 2. This parameter is not tested in production. It is guaranteed by design and device characterization. 3. IN is the sourcing current at RTSN. Guaranteed if IN is within 5 µA to 30 µA. 10 Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Electrical Characteristics (continued) Table 7. ac Feed Characteristics Parameter Min Typ Max Unit 150 — 1300 Ω Longitudinal Impedance at PT/PR2 — 0 — Ω Total Harmonic Distortion—200 Hz to 4 kHz2: Off-hook On-hook — — — — 0.3 1.0 % % –391 –403 –415 V/A 7.62 –7.62 7.86 –7.86 8.09 –8.09 — — 1.94 –1.94 2.00 –2.00 2.06 –2.06 — — Gain vs. Frequency (transmit and receive) (600 Ω termination; reference 1 kHz2): 200 Hz to 300 Hz 300 Hz to 3.4 kHz 3.4 kHz to 16 kHz 16 kHz to 266 kHz –1.00 –0.3 –3.0 — 0.0 0.0 –0.1 — 0.05 0.05 0.3 2.5 dB dB dB dB Gain vs. Level (transmit and receive)(reference 0 dBV2): –55 dB to +3 dB –0.05 0 0.05 dB 2-Wire Idle-channel Noise (600 Ω termination): Psophometric2 C-message 3 kHz Flat2 — — — –87 2 10 –77 12 20 dBmp dBrnC dBrn Transmit Idle-channel Noise: Psophometric2 C-message 3 kHz Flat2 — — — –82 7 15 –77 12 20 dBmp dBrnC dBrn ac Termination Impedance 1 Transmit Gain, f = 1 kHz (PT/PR to VITR) (current limit) L9218A, Open Loop: Receive + Gain, f = 1 kHz (RCVP to PT/PR)3 Receive – Gain, f = 1 kHz (RCVN to PT/PR)3 L9218G, Open Loop: Receive + Gain, f = 1 kHz (RCVP to PT/PR)4 Receive – Gain, f = 1 kHz (RCVN to PT/PR)4 1. With a first-generation codec, this parameter is set by external components. Any complex impedance R1 + R2 || C between 150 Ω and 1300 Ω can be synthesized. With a third-generation codec, this parameter is set by a codec or by a combination of a codec and an external network. 2. This parameter is not tested in production. It is guaranteed by design and device characterization. 3. Use this gain option with a first-generation or third-generation codec. 4. Use this gain option with an Agere third-generation codec. Agere Systems Inc. 11 Data Sheet November 2001 L9218A/G Low-Cost Line Interface Electrical Characteristics (continued) Table 8. Logic Inputs and Outputs All outputs are open collectors with internal, 30 kΩ pull-down resistor. Input pins have internal pull-down or some way to power up in disconnect state. Parameter Symbol Min Typ Max Unit Input Voltages: Low Level (permissible range) High Level (permissible range) VIL VIH –0.5 2.0 0.4 2.4 0.7 VCC V V Input Currents: Low Level (VCC = 5.25 V, VI = 0.4 V) High Level (VCC = 5.25 V, VI = 2.4 V) IIL IIH 0 +10 +4 +24 +10 +50 µA µA VOL VOH 0 2.4 0.2 — 0.4 VCC V V Output Voltages (open collector with internal pull-up resistor): Low Level (VCC = 4.75 V, IOL = 200 µA) High Level (VCC = 4.75 V, IOH = –20 µA) Ring Trip Requirements ■ ■ ■ Ringing signal: — Voltage, minimum 35 Vrms, maximum 100 Vrms. — Frequency, 17 Hz to 33 Hz. — Crest factor, 1.2 to 1.6. Ring trip: — ≤100 ms (typical). 8 µF TIP RING 10 kΩ 2 µF 100 Ω RING TIP Pretrip: — The circuits in Figure 3 will not cause ring trip. 12-2572 (F).f Figure 3. Ring Trip Circuits 12 Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Test Configurations VBAT VCC 0.1 µF VBAT 0.1 µF BGND VCC AGND 50 Ω TIP VITR PT XMT 75 kΩ RLOOP 100 Ω/600 Ω L9218 SLIC RCVN RCV 50 Ω RING 46 kΩ 19.4 kΩ RCVP PR DCOUT 8.06 kΩ TG 43.2 kΩ IPROG VTX 0.1 µF TXI 22.1 kΩ LCTH B0 B1 2 MΩ RTSP 402 Ω B2 NSTAT TSD 274 kΩ RTSN CF1 2 MΩ 0.47 µF CF2 VBAT 0.1 µF 2796 (F) Figure 4. L9218 Basic Test Circuit V BAT OR VCC 100 Ω V BAT OR VCC DISCONNECT BYPASS CAPACITOR 4.7 µF 100 Ω 4.7 µF VS VS VBAT OR VCC V BAT OR V CC 67.5 Ω TIP + 900 Ω VT/R – TIP 10 µF BASIC TEST CIRCUIT + VM – RING PSRR = 20 log DISCONNECT BYPASS CAPACITOR VS VT/R 67.5 Ω 56.3 Ω BASIC TEST CIRCUIT RING 10 µF PSRR = 20 log VS VM 12-2583 (F).b 12-2582 (F).b Figure 5. Metallic PSRR Agere Systems Inc. Figure 6. Longitudinal PSRR 13 Data Sheet November 2001 L9218A/G Low-Cost Line Interface Test Configurations (continued) ILONG 100 µF TIP + VPT – TIP VS 368 Ω + BASIC TEST CIRCUIT VM 368 Ω – ILONG RING 100 µF BASIC TEST CIRCUIT – VPR + RING LONGITUDINAL BALANCE = 20 log VS VM ZLONG = ∆ VPT ∆VPR OR ∆ ILONG ∆ ILONG 12-2584 (F).c 12-2585 (F).a Figure 7. Longitudinal Balance 0.01 µF Figure 9. Longitudinal Impedance 82.5 Ω TIP 600 Ω 50 Ω VS 1 6, 7 0.01 µF L7591 2.15 µF 4 2 + 600 Ω VT/R RING 82.5 Ω HP ® 4935A TIMS VS = 0.5 Vrms 30% AM 1 kHz modulation, f = 500 kHz—1 MHz device in powerup mode, 600 Ω termination. Figure 8. RFI Rejection XMT TIP BASIC TEST CIRCUIT V BAT – BASIC TEST CIRCUIT RCV RING VS GXMT = VXMT VT/R GRCV = VT/R VRCV 12-2587 (F).e Figure 10. ac Gains 14 Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Applications A basic loop start reference circuit, using bused ringing with the L9218 SLIC and the T7504 first-generation codec, is shown in Figure 11. This circuit is designed for a 200 Ω + 680 Ω || 0.1 µF complex termination impedance and transhybrid. Transmit gain is set at 0 dBm and receive gain is set at –7 dBm. VBAT CBAT 0.1 µF RPROG 1 35.7 kΩ RLCTH 7 9 VBAT IPROG VCC CCC 0.1 µF 4 VCC TG LCTH 22.1 kΩ VTX 8 VITR RPT 18 50 Ω L9218 SLIC RCVP RTS1 402 Ω CRTS1 0.015 µF RTSN 3.32 MΩ RCVN 20 TSD RTSP NSTAT 19 RTSN CF2 11 CF1 12 B2/NC B1 B0 AGND BGND 17 16 6 27 22 13 14 15 GSX CB1 0.47 µF RHB1 357 kΩ RRCV 137.0 kΩ + DX PCM HIGHWAY +2.4 V DR RGP 30.1 kΩ PR 50 Ω RTSP 2.94 MΩ RX 158.0 kΩ – 5 10 RPR RING 23 RT1 71.5 kΩ L7591 LCAS EMR CB 0.1 µF RT2 80.6 kΩ 24 PT CGS 6.8 nF RGP1 8.06 kΩ 25 DCOUT TXI TIP RGS 2.37 kΩ 26 CB2 RN1 143.0 kΩ 0.47 µF CGN 0.1 nF RN2 18.2 kΩ VFRO FSX FSR MCLK CONTROL AND CLOCK SUPERVISION OUTPUTS 1/4 T7504 CODEC CONTROL INPUTS CF1 0.47 µF VRING CF2 0.1 µF VBAT 2797 (F).a Figure 11. Basic Loop Start Application Circuit Using T7504-Type Codec Table 9 shows the design parameters of the application circuit shown in Figure 11. Components that are adjusted to program these values are also shown. Table 9. 200 Ω + 680 Ω || 0.1 µF First-Generation Codec Design Parameters Design Parameter Loop Closure Threshold dc Loop Current Limit 2-wire Signal Overload Level ac Termination Impedance Hybrid Balance Line Impedance Transmit Gain Receive Gain Agere Systems Inc. Parameter Value 10 mA 20 mA 3.14 dBm 200 Ω + 680 Ω || 0.1 µF 200 Ω + 680 Ω || 0.1 µF 0 dBm –7 dBm Components Adjusted RLCTH RPROG — RT1, RGP, RRCV, RGP1, RGS, CGS RHB1 RT2, RX, RN1, RN2, CN RRCV, RGP, RT1 15 Data Sheet November 2001 L9218A/G Low-Cost Line Interface Applications (continued) Table 10. Parts List for Loop Start Application Circuit Using T7504-Type Codec Name Integrated Circuits SLIC Protector Ringing Relay Codec Overvoltage Protection RPT RPR Power Supply CBAT1 CCC CF1 CF2 dc Profile RPROG ac Characteristics CB1 CB2 RT1 RRCV RGP Value Function L9218 Agere L7591 Agere L7581/2/3 or EMR T7504 Subscriber loop interface circuit (SLIC). Secondary protection. Switches ringing signals. First-generation codec. 50 Ω, Fusible 50 Ω, Fusible Protection resistor. Protection resistor. 0.1 µF, 20%, 100 V 0.1 µF, 20%, 10 V 0.47 µF, 20%, 100 V 0.1 µF, 20%, 100 V VBAT filter capacitor. VCC filter capacitor. With CF2, improves idle-channel noise. With CF1, improves idle-channel noise. 35.7 kΩ, 1%, 1/16 W Sets dc loop current limit. 0.47 µF, 20%, 10 V 0.47 µF, 20%, 10 V 71.5 kΩ, 1%, 1/16 W 137 kΩ, 1%, 1/16 W 30.1 kΩ, 1%, 1/16 W RT2 RX RHB1 CGS 80.6 kΩ, 1%, 1/16 W 158 kΩ, 1%, 1/16 W 357 kΩ, 1%, 1/16 W 6.8 nF, 10%, 10 V RGS 2.37 kΩ, 1%, 1/16 W RGP1 CN RN1 RN2 Supervision RLCTH RTS1 CRTS1 RTSN RTSP 8.06 kΩ, 1%, 1/16 W 0.1 nF, 20%, 10 V 143 kΩ, 1%, 1/16 W 18.2 kΩ, 1%, 1/16 W ac/dc separation capacitor. ac/dc separation capacitor. With RGP and RRCV, sets ac termination impedance. With RGP and RT1, sets receive gain. With RT1 and RRCV, sets ac termination impedance and receive gain. With RX, sets transmit gain in codec. With RT2, sets transmit gain in codec. Sets hybrid balance. With RGS, provides gain shaping for termination impedance matching. With CGS, provides gain shaping for termination impedance matching. Sets transmit gain of SLIC. With RN1 and RN2 high frequency compensation. With CN and RN2 high frequency compensation. With RN1 and CN high frequency compensation. 22.1 kΩ, 1%, 1/16 W 402 Ω, 5%, 2 W 0.015 µF, 20%, 10 V 3.32 MΩ, 1%, 1/16 W 2.94 MΩ, 1%, 1/16 W Sets loop closure (off-hook) threshold. Ringing source series resistor. With RTSN, RTSP, forms filter pole. With RTSP, sets threshold. With CRTS1, RTSN, sets threshold. 16 Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Applications (continued) A basic loop start reference circuit, using bused ringing with the L9218 SLIC and the T8536 third-generation codec, is shown in Figure 12. VBAT CBAT 0.1 µF VCC CCC 0.1 µF RPROG 1 35.7 kΩ RLCTH 7 22.1 kΩ 8 9 IPROG 4 VBAT VCC TG LCTH VTX DCOUT TXI RPT TIP 18 50 Ω L9218 SLIC 10 RPR 50 Ω RTSP 2.94 MΩ RTS1 510 Ω VITR L7591 LCAS EMR RING PT CRTS1 0.015 µF RTSN 3.4 MΩ RCVP RCVN NSTAT PR B0 20 B1 RTSP B2/NC 19 26 25 RGP1 8.06 kΩ 24 CB 0.1 µF 23 CB1 0.1 µF DX1 1/4 T8536 CODEC DX2 RCIN 20 MΩ 5 6 22 15 14 13 (OPTIONAL*) VFXI DR1 VFROP DR2 VFRON SLIC0a SLIC3a FS BCLK CONTROL AND CLOCK VDD CVDD 0.1 µF SLIC2a SLIC4a PCM HIGHWAY DGND RTSN CF2 11 CF1 12 AGND BGND 17 16 CF1 0.47 µF VRING CF2 0.1 µF VBAT 2798 (F).a * Optional nonfunctional connection for exact footprint match with L9219. Figure 12. Basic Loop Start Application Circuit Using T8536-Type Codec Agere Systems Inc. 17 Data Sheet November 2001 L9218A/G Low-Cost Line Interface Applications (continued) Table 11. Parts List for Loop Start Application Circuit Using T8536-Type Codec Name Integrated Circuits SLIC Protector Ringing Relay Codec Overvoltage Protection RPT RPR Power Supply CBAT1 CCC CF1 CF2 dc Profile RPROG ac Characteristics CB3 RGP1 RCIN Supervision RLCTH RTS1 CRTS1 RTSN RTSP 18 Value Function L9218 Agere L7591 Agere L7581/2/3 or EMR T8536 Subscriber loop interface circuit (SLIC). Secondary protection. Switches ringing signals. Third-generation codec. 50 Ω, Fusible 50 Ω, Fusible Protection resistor. Protection resistor. 0.1 µF, 20%, 100 V 0.1 µF, 20%, 10 V 0.47 µF, 20%, 100 V 0.1 µF, 20%, 100 V VBAT filter capacitor. VCC filter capacitor. With CF2, improves idle-channel noise. With CF1, improves idle-channel noise. 35.7 kΩ, 1%, 1/16 W Sets dc loop current limit. 0.1 µF, 20%, 10 V 8.06 kΩ, 1%, 1/16 W 20 MΩ, 5%, 1/16 W ac/dc separation capacitor. Sets transmit gain of SLIC. dc bias. 22.1 kΩ, 1%, 1/16 W 510 Ω, 5%, 2 W 0.015 µF, 20%, 10 V 3.4 MΩ, 1%, 1/16 W 2.94 MΩ, 1%, 1/16 W Sets loop closure (off-hook) threshold. Ringing source series resistor. With RTSN and RTSP, forms second 2 Hz filter pole. With RTSP, sets threshold. With RTSN, sets threshold. Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Applications (continued) Starting from the on-hook condition and going through to a short circuit, the curve passes through the following two regions: dc Applications Region 1: On-hook and low-loop currents. The slope corresponds to the dc resistance of the SLIC, Rdc1 (70 Ω typical). The open circuit voltage is the battery voltage minus the overhead voltage of the device, VOH (6.5 V typical). These values are suitable for most applications but can be adjusted if needed. Battery Feed The dc feed characteristic can be described by: V T/R = IL = ( VBAT – VOH) × RL --------------------------------------------R L + 2R P + R dc V B AT – V O H --------------------------------- R L + 2R P + R dc where: IL = dc loop current. VT/R = dc loop voltage. |VBAT| = battery voltage magnitude. VOH = overhead voltage. This is the difference between the battery voltage and the open loop tip/ring voltage. RL = loop resistance, not including protection resistors. RP = protection resistor value. Rdc = SLIC internal dc feed resistance. The design begins by drawing the desired dc template. An example is shown in Figure 13. LOOP CURRENT (mA) 50 Region 2: Current limit. The dc current is limited to a starting value determined by external resistor RPROG , an internal current source, and the gain from tip/ring to pin DCOUT. Current Limit With the B0/B1 logic inputs set to 11 (low current limit), current limit with a 100 Ω load is given by the following equation: 0.637 RPROG (kΩ) + 2 mA= ILIM x (mA) The relationship between low current limit (B0 = 1, B1 = 1) and high current limit (B0 = 1, B1 = 0) is I LIMIT ( Low ) ---------------------------------- = 0.7 I LIMIT ( High ) Overhead Voltage 40 ILIM TESTED 1 12.5 kΩ 30 ILIM ONSET In order to drive an on-hook ac signal, the SLIC must set up the tip and ring voltage to a value less than the battery voltage. The amount that the open loop voltage is decreased relative to the battery is referred to as the overhead voltage, expressed as the following equation: 20 –1 R dc1 10 VOH = |VBAT| – (VPT – VPR) 0 0 10 20 30 LOOP VOLTAGE (V) 40 50 12-3050 (F).i Notes: VBAT = –48 V. Without this buffer voltage, amplifier saturation will occur and the signal will be clipped. The L9218 is automatically set at the factory to allow undistorted on-hook transmission of a 3.14 dBm signal into a 900 Ω loop impedance. ILIM = 22 mA. Rdc1 = 115 Ω. Figure 13. Loop Current vs. Loop Voltage Agere Systems Inc. 19 Data Sheet November 2001 L9218A/G Low-Cost Line Interface Applications (continued) dc Applications (continued) Loop Range The equation below can be rearranged to provide the loop range for a required loop current: RL = VBAT – VOH --------------------------- – 2R P – R D C IL Off-Hook Detection The loop closure comparator has built-in longitudinal rejection, eliminating the need for an external 60 Hz filter. The loop closure detection threshold is set by resistor RLCTH. The supervision output bit NSTAT is high in an on-hook condition. The off-hook comparator goes low during an off-hook condition: ITR (mA) = 0.4167 RLCTH (kΩ) – 1.9 mA ACTIVE off-hook to on-hook ITR (mA) = 0.4167 RLCTH (kΩ) + 2.7 mA SCAN on-hook to off-hook RP TIP ITR + RL 0.125 V/mA DCOUT – RLCTH RING LCTH RP 0.05 mA + – NSTAT 12-2553 (F).f Figure 14. Off-Hook Detection Circuit 20 Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Applications (continued) dc Applications (continued) Ring Trip Detection The ring trip circuit is a comparator that has a special input section optimized for this application. The equivalent circuit is shown in Figure 15, along with its use in an application using unbalanced, battery-backed ringing. PHONE HOOK SWITCH RLOOP RTSP RC PHONE VBAT VRING RTSP + 2.94 MΩ RS 402 Ω/510 Ω CRTS1 0.015 µF RTSN 3.32 MΩ/3.40 MΩ NSTAT IP = IN IN + – 8.6 V – RTSN 15 kΩ 2799 (F) Figure 15. Ring Trip Equivalent Circuit and Equivalent Application Ring trip detection threshold is given by the following equation: [ RTSN ( MΩ ) + 0.015 – RTSP ( MΩ ) ] × [ V BAT – 8.6 ] × 1000 ITH (mA) = ------------------------------------------------------------------------------------------------------------------------------------------------------------------------[ RTSN ( MΩ ) + 0.015 ] × R S Longitudinal Balance The SLIC is graded to certain longitudinal balance specifications. The numbers are guaranteed by testing (Figure 5 and Figure 8). However, for specific applications, the longitudinal balance may also be determined by termination impedance, protection resistance, and especially by the mismatch between protection resistors at tip and ring. This can be illustrated by the following equation: ( 368 + RP ) × ( 368 + ZT – RP ) LB = 20 x log ------------------------------------------------------------------------------------------368 × ( 2 × [ ZT – 2 × RP ] × ∆ + ε ) where: LB: longitudinal balance. RP: protection resistor value in Ω. ZT: magnitude of the termination impedance in Ω. ε: protection resistor mismatch in Ω. ∆: SLIC internal tip/ring sensing mismatch. The ∆ can be calculated using the above equation with these exceptions: ε = 0, ZT = 600 Ω, RP = 100 Ω, and the longitudinal balance specification on a specific code. Now with ∆ available, the equation will predict the actual longitudinal balance for RP, ZT, and ε. Be aware that ZT may vary with frequency for complex impedance applications. Agere Systems Inc. 21 Data Sheet November 2001 L9218A/G Low-Cost Line Interface Applications (continued) ac Interface Network ac Design The ac interface network between the L9218 and the codec will vary depending on the codec selected. With a first-generation codec, the interface between the L9218 and codec actually sets the ac parameters. With a third-generation codec, all ac parameters are set digitally, internal to the codec; thus, the interface between the L9218 and this type of codec is designed to avoid overload at the codec input in the transmit direction, and to optimize signal-to-noise ratio (S/N) in the receive direction. Codec Types At this point in the design, the codec needs to be selected. The interface network between the SLIC and codec can then be designed. There are four key ac design parameters. Termination impedance is the impedance looking into the 2-wire port of the line card. It is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. Transmit gain is measured from the 2-wire port to the PCM highway, while receive gain is done from the PCM highway to the transmit port. Finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port. Below is a brief codec feature summary. First-Generation Codecs. These perform the basic filtering, A/D (transmit), D/A (receive), and µ-law/A-law companding. They all have an op amp in front of the A/D converter for transmit gain setting and hybrid balance (cancellation at the summing node). Depending on the type, some have differential analog input stages, differential analog output stages, 5 V only or ±5 V operation, and µ-law/A-law selectability. These are available in single and quad designs. This type of codec requires continuous time analog filtering via external resistor/capacitor networks to set the ac design parameters. An example of this type of codec is the Agere T7504 quad 5 V only codec. This type of codec tends to be the most economical in terms of piece part price, but tends to require more external components than a third-generation codec. Furthermore, ac parameters are fixed by the external R/C network, so software control of ac parameters is difficult. Third-Generation Codecs. This class of devices includes all ac parameters set digitally under microprocessor control. Depending on the device, it may or may not have data control latches. Additional functionality sometimes offered includes tone plant generation and reception, TTX generation, test algorithms, and echo cancellation. Again, this type of codec may be 5 V only or ±5 V operation, single quad or 16-channel, and µ-law/A-law or 16-bit linear coding selectable. Examples of this type of codec are the Agere T8535/6 (5 V only, quad, standard features), T8533/4 (5 V only, quad with echo-cancellation), and the T8531/36 (5 V only 16-channel with self-test). 22 Receive Interface Because the design requirements are very different with a first- or third-generation codec, the L9218 is offered with two different receive gains. Each receive gain was chosen to optimize, in terms of external components required, the ac interface between the L9218 and the codec. With a first-generation codec, the termination impedance is set by providing gain shaping through a feedback network from the SLIC VITR output to the SLIC RCVN/RCVP inputs. The L9218 provides a transconductance from T/R to VITR in the transmit direction and a single-ended to differential gain in the receive direction from either RCVN or RCVP to T/R. Assuming a short from VITR to RCVN or RCVP, the maximum impedance that is seen looking into the SLIC is the product of the SLIC transconductance times the SLIC receive gain, plus the protection resistors. The various specified termination impedance can range over the voice band as low as 300 Ω up to over 1000 Ω. Thus, if the SLIC gains are too low, it will be impossible to synthesize the higher termination impedances. Furthermore, the termination that is achieved will be far less than what is calculated by assuming a short for SLIC output to SLIC input. In the receive direction, in order to control echo, the gain is typically a loss, which requires a loss network at the SLIC RCVN/RCVP inputs, which will reduce the amount of gain that is available for termination impedance. For this reason, a high-gain SLIC is required with a first-generation codec. Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Applications (continued) better the S/N. The problem is, if the codec is feeding a high-gain SLIC, either an external resistor divider is needed to knock the gain down to meet the TLP requirements, or the codec is not operating near maximum signal levels, thus compromising the S/N. ac Design (continued) Receive Interface (continued) It appears the solution is to have a SLIC with a low gain, especially in the receive direction. This will allow the codec to operate near its maximum output signal (to optimize S/N), without an external resistor divider (to minimize cost). With a third-generation codec, the line card designer has different concerns. To design the ac interface, the designer must first decide upon all termination impedance, hybrid balances, and transmission-level points (TLP) requirements that the line card must meet. In the transmit direction, the only concern is that the SLIC does not provide a signal that is too hot and overloads the codec input. Thus, for the highest TLP that is being designed to, given the SLIC gain, the designer, as a function of voice band frequency, must ensure that the codec is not overloaded. With a given TLP and a given SLIC gain (if the signal will cause a codec overload), the designer must insert some sort of loss, typically a resistor divider, between the SLIC output and codec input. Note also that some third-generation codecs require the designer to provide an inherent resistive termination via external networks. The codec will then provide gain shaping, as a function of frequency to meet the return loss requirements. Further stability issues may add external components or excessive ground plane requirements to the design. To meet the unique requirements of both types of codecs, the L9218 offers two receive gain choices. These receive gains are mask-programmable at the factory and are offered as two different code variations. For interface with a first-generation codec, the L9218A is offered with a receive gain of 7.86. For interface with a third-generation codec, the L9218G is offered with a receive gain of 2. In either case, the transconductance in the transmit direction, or the transmit gain is 403 Ω. In the receive direction, the issue is to optimize S/N. Again, the designer must consider all the considered TLPs. The idea is, for all desired TLPs, to run the codec at or as close as possible to its maximum output signal, to optimize the S/N. Remember noise floor is constant, so the hotter the signal from the codec, the Example 1: Real Termination (First-Generation Codec) ac equivalent circuits for real termination using a T7504 codec is shown in Figure 15. RX VGSX –0.403 V/mA RT2 VFXIN VITR VFXIP ZT/R VS ZT – AV = 1 + RP TIP IT/R + VT/R – RP RING – AV = 3.93 + CURRENT SENSE RT1 RCVN RHB1 RRCV RCVP – + 2.4 V VFR RG + AV = –1 – L9218 SLIC 1/4 T7504 CODEC 12-3581 (F).d Figure 16. ac Equivalent Circuit Agere Systems Inc. 23 L9218A/G Low-Cost Line Interface Data Sheet November 2001 Applications (continued) ac Design (continued) Example 1: Real Termination (First-Generation Codec) (continued) The following design equations refer to the circuit in Figure 16. Use these to synthesize real termination impedance. Termination Impedance: VT ⁄ R ZT = -------------–I T ⁄ R 3168 Z T = 2R P + ----------------------------------RT3 RT3 1 + --------- + -----------RGP RRCV Receive Gain: VT ⁄ R grcv = -------------V fr 7.86 grcv = ------------------------------------------------------------------------------------RCV RCV R ZT 1 + --------------- + R --------------- 1 + ------------- R T3 R GP Z T/R Transmit Gain: V GSX gtx = --------------VT ⁄ R RX 403 gtx = ---------- x ----------ZT R T6 Hybrid Balance: V GSX hbal = 20log --------------VT ⁄ R To optimize the hybrid balance, the sum of the currents at the VFX input of the codec op amp should be set to 0. The following expressions assume the test network is the same as the termination impedance: RX RHB = ------------------------g tx × g rcv RX hbal = 20log ------------ – g tx × g rcv R HB 24 Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Applications (continued) ac Design (continued) Example 2: Complex Termination (First-Generation Codec) Below are design equations for complex termination (see Figure 17 and Figure 18). ZT = RT1 + RT2 || CT R T1 7.86 = 2R P + -----------201.2 1 1 • ----------------------------------- – ------------------ RTGP || RTGS R T3 RN1 RT3 1 + --------- + ------------ 1 + -------- RGP R T2 = RRCV RN2 7.86 R T G P ⁄ R TGS 1 RTGP || RTGS ----------- • ----------------------------------- + ----------------201.2 RN1 RT3 R T3 1 + --------- + ------------ 1 + -------- RGP RRCV RN2 2 7.86 1 R N2 1 R TGP 1 1 = ---------------- ----------- ------------------------------------2- R TGP || R TGS + ----------- • ------------------------------------- • ---------------------------------------------- – --------------------- C TG R TGP + R TGS CT T3 T3 201.2 C N1 ( R N1 + R N2 ) R R N1 R 1 + ----------- + --------------- 1 + ----------- R GP R RCV R N2 1 ------- RX 1 Z TG gtx = ---------- ---------------- ----------R T6 201.2 Z T 7.86 1 grcv = ------------------------------------------------ × -----------------------RCV R RCV R ZT 1 + --------------- + --------------- 1 + ------------R T3 R GP ZT ⁄ R RX hbal = 20log ------------ – g tx × g rcv R HB where: ZT/R = R1 + R2 || C ZTG = RTGP || (RTGS + CG) RTGP = 8.06 kΩ R1 RTGS = ------- RTGP R2 R 22 CG = ------------------------------------------ x C R TGP ( R 1 + R 2 ) and 2R P CNRN2 = ------------- CG RTGP 3168 ( 3168 ) R TGS RN1 = RN2 ------------------ -------------- – 1 2R P R TGP The equations above do not include the blocking capacitors. Agere Systems Inc. 25 Data Sheet November 2001 L9218A/G Low-Cost Line Interface Applications (continued) ac Design (continued) Example 2: Complex Termination (First-Generation Codec) (continued) RTGS CGS RX RTGP = 8.06 kΩ –IT/R 201.2 CB RT6 AX AAC – + CODEC OP AMP CN RT3 RN1 RCVN RCVN RCVP RCVP CODEC OUTPUT DRIVE AMP RRCV RGP RN2 5-6401 (F).j Figure 17. Interface Circuit Using First-Generation Codec (±5 V Battery) RTGS CG RX –IT/R 201.2 RTGP = 8.06 kΩ RT6 AX AAC CB CB1 CN RN1 CODEC OP AMP –2.4 V RT3 RCVN RRCV RCVP CB2 RGP RN2 – + CODEC OUTPUT DRIVE AMP 5-6400 (F).n Figure 18. Interface Circuit Using First-Generation Codec (5 V Only Codec) 26 Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Applications (continued) Loop power = (25 mA • 1.05)2 • (200 Ω + 100 Ω) Power Derating Loop power = 0.207 W Operating temperature range, maximum current limit, maximum battery voltage, minimum dc loop, and protection resistor values will influence the overall thermal performance. This section shows the relevant design equations and considerations in evaluating the SLIC thermal performance. SLIC power = 1.523 W – 0.207 W = 1.28 Consider the L9218 SLIC in a 28-pin PLCC package. The still-air thermal resistance on a 2-layer board is typically 43 °C/W. The SLIC will enter the thermal shutdown state at a minimum of 150 °C. The thermal shutdown design should ensure that the SLIC temperature does not reach 150 °C under normal operating conditions. Assume a maximum ambient operating temperature of 85 °C, a maximum current limit of 25 mA (including tolerance), and a maximum battery of –52 V. Furthermore, assume a (worst-case) minimum dc loop of 200 Ω, and that 50 Ω protection resistors are used at both tip and ring. 1. TTSD – TAMBIENT(max) = allowed thermal rise. 150 °C – 85 °C = 65 °C 2. Allowed thermal rise = package thermal impedance • SLIC power dissipation. 65 °C = 43 °C/W • SLIC power dissipation SLIC power dissipation (PDISS) = 1.51 W Thus, if the total power dissipated in the SLIC is less than 1.51 W, it will not enter the thermal shutdown state. Total SLIC power is calculated as: Total PDISS = maximum battery • maximum current limit (including effects of accuracy) + SLIC quiescent power For the L9218, SLIC quiescent power (P Q) is maximum at 0.158 W. Thus, Total PDISS = (–52 V • [25 mA • 1.05]) + 0.158 W Total PDISS = 1.365 W + 0.158 W Total PDISS = 1.523 W The power dissipated in the SLIC is the total power dissipation minus the power that is dissipated in the loop. SLIC power = 1.28 W < 1.51 W Thus, in this example, the thermal design ensures that the SLIC will not enter the thermal shutdown state. Pin-for-Pin Compatibility with L9217/L9219 The L9218 is an exact pin-for-pin replacement for the L9217/19. The one minor exception is L9217/19 has three logic control inputs: B0, B1, and B2. The L9218 has only two logic control inputs, B0 and B1. B2 in the L9217/19 is pin 13. Pin 13 in L9218 is NC, so a connection between the controller and pin 13 will not affect L9218 operation. This allows an exact footprint match with L9217/19. PCB Layout Information Make the leads to BGND and VBAT as wide as possible for thermal and electrical reasons. Also, maximize the amount of PCB copper in the area of (and specifically on) the leads connected to this device for the lowest operating temperature. When powering the device, make certain that no external potential creates a voltage on any pin of the device that exceeds the device ratings. In this application, some of the conditions that cause such potentials during powerup are the following: 1. An inductor connected to PT and PR (this can force an overvoltage on VBAT through the protection devices if the VBAT connection chatters). 2. Inductance in the VBAT lead (this could resonate with the VBAT filter capacitor to cause a destructive overvoltage). This device is normally used on a circuit card that is subjected to hot plug-in, meaning the card is plugged into a biased backplane connector. In order to prevent damage to the IC, all ground connections must be applied before, and removed after, all other connections. SLIC PDISS = total power – loop power Loop power = (ILIM)2 • (RdcLOOP min + 2RP) Agere Systems Inc. 27 Data Sheet November 2001 L9218A/G Low-Cost Line Interface Outline Diagram 28-Pin PLCC Dimensions are in millimeters. 12.446 ± 0.127 11.506 ± 0.076 PIN #1 IDENTIFIER ZONE 4 1 26 25 5 11.506 ± 0.076 12.446 ± 0.127 11 19 12 18 4.572 MAX SEATING PLANE 1.27 TYP 0.51 MIN TYP 0.10 0.330/0.533 5-2608(F) 28 Agere Systems Inc. Data Sheet November 2001 L9218A/G Low-Cost Line Interface Ordering Information Device Package Comcode LUCL9218AAR-D 28-Pin PLCC (Dry Bag) Gain of 12 108558271 LUCL9218AAR-DT 28-Pin PLCC (Tape and Reel, Dry Bag) Gain of 12 108558289 LUCL9218GAR-D 28-Pin PLCC (Dry Bag) Gain of 2 108558156 LUCL9218GAR-DT 28-Pin PLCC (Tape and Reel, Dry Bag) Gain of 2 108558164 Agere Systems Inc. 29 IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. HP is a registered trademark of Hewlett-Packard Company. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: [email protected] N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright © 2001 Agere Systems Inc. All Rights Reserved November 2001 DS02-039ALC (Replaces DS01-318ALC)