STMicroelectronics M24256-BR3BN6T 256/128 kbit serial ic bus eeprom with three chip enable line Datasheet

M24256-B
M24128-B
256/128 Kbit Serial I C Bus EEPROM
With Three Chip Enable Lines
PRELIMINARY DATA
■
Compatible with I2C Extended Addressing
■
Two Wire I2C Serial Interface
Supports 400 kHz Protocol
■
Single Supply Voltage:
– 4.5V to 5.5V for M24xxx-B
14
8
– 2.5V to 5.5V for M24xxx-BW
– 1.8V to 3.6V for M24xxx-BR
■
Hardware Write Control
■
BYTE and PAGE WRITE (up to 64 Bytes)
■
RANDOM and SEQUENTIAL READ Modes
■
Self-Timed Programming Cycle
■
Automatic Address Incrementing
■
Enhanced ESD/Latch-Up Behavior
■
100000 Erase/Write Cycles (minimum)
■
40 Year Data Retention (minimum)
DESCRIPTION
These I 2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 32Kx8 bits (M24256-B) and 16Kx8 bits
(M24128-B).
These memory devices are compatible with the
I2C extended memory standard. This is a two wire
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4bit unique Device Type Identifier code (1010) in
accordance with the I2C bus definition.
1
1
PSDIP8 (BN)
0.25 mm frame
TSSOP14 (DL)
169 mil width
8
8
1
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
Figure 1. Logic Diagram
VCC
3
Table 1. Signal Names
E0-E2
E0, E1, E2
Chip Enable Inputs
SCL
SDA
Serial Data/Address Input/
Output
WC
SCL
Serial Clock
WC
Write Control
VCC
Supply Voltage
VSS
Ground
SDA
M24256-B
M24128-B
VSS
AI02809
February 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/19
M24256-B, M24128-B
Figure 2C. TSSOP14 Connections
Figure 2A. PSDIP8 Connections
M24256-B
M24128-B
M24256-B
M24128-B
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
E0
E1
NC
NC
NC
E2
VSS
VCC
WC
SCL
SDA
AI02810
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
WC
NC
NC
NC
SCL
SDA
AI02812
Note: 1. NC = Not Connected
Figure 2B. SO8 and TSSOP8 Connections
M24256-B
M24128-B
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
AI02811
The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and after a NoAck for READ.
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
Table 2. Absolute Maximum Ratings 1
Symbol
Value
Unit
Ambient Operating Temperature
-40 to 125
°C
T STG
Storage Temperature
-65 to 150
°C
TLEAD
Lead Temperature during Soldering
260
215
215
215
°C
TA
Parameter
PSDIP8: 10 seconds
SO8: 40 seconds
TSSOP8: 40 seconds
TSSOP14: 40 seconds
VIO
Input or Output range
-0.6 to 6.5
V
VCC
Supply Voltage
-0.3 to 6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) 2
4000
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
2/19
M24256-B, M24128-B
set (POR) circuit is included. The internal reset is
held active until the V CC voltage has reached the
POR threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when VCC drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command. A stable and valid VCC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from
the SCL line to VCC. (Figure 3 indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to VCC. (Figure 3 indicates how the value of the
pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs must be tied directly to VCC or VSS to
establish the device select code. When unconnected, the E2, E1 and E0 inputs are internally
read as VIL (see Table 7 and Table 8)
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=VIL) or disable (WC=VIH)
write instructions to the entire memory area. When
unconnected, the WC input is internally read as
VIL, and write operations are allowed.
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowledged.
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the I2C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001. Any device that sends data on to the bus
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all communication.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device continuously monitors (except during a programming
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC
Maximum RP value (kΩ)
20
16
RL
12
RL
SDA
MASTER
8
fc = 100kHz
4
fc = 400kHz
CBUS
SCL
CBUS
0
10
100
1000
CBUS (pF)
AI01665
3/19
M24256-B, M24128-B
Figure 4. I2C Bus Protocol
SCL
SDA
START
CONDITION
SCL
1
SDA
MSB
SDA
INPUT
2
SDA
CHANGE
STOP
CONDITION
3
7
8
9
ACK
START
CONDITION
SCL
1
SDA
MSB
2
3
7
8
9
ACK
STOP
CONDITION
AI00792
cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communication between the memory device and the bus master. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9th clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
4/19
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transition, and the data must change only when the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is further subdivided into: a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (E2, E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
M24256-B, M24128-B
Table 3. Device Select Code 1
Device Type Identifier
Device Select Code
Chip Enable
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2
E1
E0
RW
Note: 1. The most significant bit, b7, is sent first.
Up to eight memory devices can be connected on
a single I2C bus. Each one is given a unique 3-bit
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the memory only responds if the Chip Select Code is the
same as the pattern applied to its Chip Enable
pins.
The 8th bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding memory gives an acknowledgment on the SDA bus during the 9th bit time. If the memory does not match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Table 4) is sent first, followed by the Least significant
Byte (Table 5). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as a Don’t
Care bit on the M24256-B memory. Bits b15 and
b14 are treated as Don’t Care bits on the M24128B memory.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory re-
Table 4. Most Significant Byte
b15
b14
b13
b12
b11
b10
b9
b8
Note: 1. b15 is treated as Don’t Care on the M24256-B series.
b15 and b14 are Don’t Care on the M24128-B series.
Table 5. Least Significant Byte
b7
b6
b5
b4
b3
b2
b1
b0
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the memory contents, and the accompanying data bytes will not be acknowledged,
as shown in Figure 5.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed location is write
protected by the WC pin, the memory replies with
a NoAck, and the location is not modified. If, instead, the WC pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.
Page Write
The Page Write mode allows up to 64 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
Table 6. Operating Modes
Mode
Current Address Read
RW bit
WC 1
Data Bytes
1
X
1
0
X
Random Address Read
Initial Sequence
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
1
1
X
reSTART, Device Select, RW = ‘1’
Sequential Read
1
X
≥1
Byte Write
0
VIL
1
START, Device Select, RW = ‘0’
Page Write
0
VIL
≤ 64
START, Device Select, RW = ‘0’
Similar to Current or Random Address Read
Note: 1. X = VIH or VIL.
5/19
M24256-B, M24128-B
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
BYTE ADDR
ACK
BYTE ADDR
NO ACK
DATA IN
STOP
DEV SEL
START
BYTE WRITE
ACK
R/W
WC
ACK
DEV SEL
START
PAGE WRITE
ACK
BYTE ADDR
ACK
BYTE ADDR
NO ACK
DATA IN 1
DATA IN 2
R/W
WC (cont’d)
NO ACK
DATA IN N
STOP
PAGE WRITE
(cont’d)
NO ACK
AI01120B
that is the most significant memory address bits
(b14-b6 for the M24256-B and b13-b6 for the
M24128-B) are the same. If more bytes are sent
than will fit up to the end of the row, a condition
known as ‘roll-over’ occurs. Data starts to become
overwritten (in a way not formally specified in this
data sheet).
The master sends from one up to 64 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the contents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 6 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition immediately after the Ack bit (in the “10th bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
6/19
A STOP condition at any other time does not trigger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not respond to any requests.
M24256-B, M24128-B
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
BYTE ADDR
ACK
BYTE ADDR
ACK
DATA IN
STOP
DEV SEL
START
BYTE WRITE
ACK
R/W
WC
ACK
DEV SEL
START
PAGE WRITE
ACK
BYTE ADDR
ACK
BYTE ADDR
ACK
DATA IN 1
DATA IN 2
R/W
WC (cont’d)
ACK
DATA IN N
STOP
PAGE WRITE
(cont’d)
ACK
AI01106B
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory disconnects itself from the bus, and copies the data from
its internal latches to the memory cells. The maximum write time (tw) is shown in Table 9, but the
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it responds with
an Ack, indicating that the memory is ready to
receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
Read Operations
Read operations are performed independently of
the state of the WC pin.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, the master sends another START condition, and repeats
the Device Select Code, with the RW bit set to ‘1’.
The memory acknowledges this, and outputs the
contents of the addressed byte. The master must
not acknowledge the byte output, and terminates
the transfer with a STOP condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to ‘1’. The memory acknowledges this, and outputs the byte addressed by the
7/19
M24256-B, M24128-B
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
NO
ACK
Returned
YES
First byte of instruction
with RW = 0 already
decoded by M24xxx
NO
Next
Operation is
Addressing the
Memory
YES
Send
Byte Address
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI01847
internal address counter. The counter is then incremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8, without acknowledging the byte output.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
The output data comes from consecutive addresses, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from
memory address 00h.
8/19
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9th
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
M24256-B, M24128-B
Figure 8. Read Mode Sequences
ACK
DATA OUT
STOP
START
DEV SEL
NO ACK
R/W
ACK
START
DEV SEL *
ACK
BYTE ADDR
ACK
DEV SEL *
ACK
NO ACK
DATA OUT N
R/W
ACK
ACK
BYTE ADDR
R/W
ACK
ACK
BYTE ADDR
ACK
DEV SEL *
START
START
DEV SEL *
DATA OUT
R/W
ACK
DATA OUT 1
NO ACK
STOP
START
DEV SEL
SEQUENTIAL
RANDOM
READ
BYTE ADDR
R/W
ACK
SEQUENTIAL
CURRENT
READ
ACK
START
RANDOM
ADDRESS
READ
STOP
CURRENT
ADDRESS
READ
ACK
DATA OUT 1
R/W
NO ACK
STOP
DATA OUT N
AI01105C
st
th
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical.
9/19
M24256-B, M24128-B
Table 7. DC Characteristics
(TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5 V)
(TA = –20 to 85 °C; VCC = 1.8 to 3.6 V)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
ILI
Input Leakage Current
(SCL, SDA)
0 V ≤ VIN ≤ VCC
±2
µA
ILO
Output Leakage Current
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
±2
µA
VCC=5V, fc=400kHz (rise/fall time < 30ns)
2
mA
-W series:
VCC =2.5V, f c=400kHz (rise/fall time < 30ns)
1
mA
-R series:
VCC =1.8V, f c=100kHz (rise/fall time < 30ns)
0.5 1
mA
VIN = VSS or V CC , VCC = 5 V
10
µA
-W series:
VIN = VSS or VCC , VCC = 2.5 V
2
µA
-R series:
VIN = VSS or VCC , VCC = 1.8 V
11
µA
ICC
ICC1
Supply Current
Supply Current
(Stand-by)
V IL
Input Low Voltage (SCL, SDA)
–0.3
0.3V CC
V
V IH
Input High Voltage (SCL, SDA)
0.7VCC
VCC+1
V
V IL
Input Low Voltage
(E0-E2, WC)
–0.3
0.5
V
V IH
Input High Voltage
(E0-E2, WC)
0.7VCC
VCC+1
V
IOL = 3 mA, VCC = 5 V
0.4
V
VOL
Output Low
Voltage
-W series:
IOL = 2.1 mA, V CC = 2.5 V
0.4
V
-R series:
IOL = 0.7 mA, V CC = 1.8 V
0.2 1
V
Note: 1. This is preliminary data.
Table 8. Input Parameters1 (TA = 25 °C, f = 400 kHz)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
C IN
Input Capacitance (SDA)
8
pF
C IN
Input Capacitance (other pins)
6
pF
ZL
Input Impedance (E0-E2, WC)
VIN ≤ 0.5 V
50
kΩ
ZH
Input Impedance (E0-E2, WC)
V IN ≥ 0.7VCC
500
kΩ
tNS
Pulse width ignored
(Input Filter on SCL and SDA)
Single glitch
Note: 1. Sampled only, not 100% tested.
10/19
100
ns
M24256-B, M24128-B
Table 9. AC Characteristics
M24256-B / M24128-B
Symbol
Alt.
VCC=4.5 to 5.5 V V CC=2.5 to 5.5 V V CC=1.8 to 3.6 V
Unit
TA=–40 to 85°C TA=–40 to 85°C TA=–20 to 85°C4
Parameter
Min
Max
Min
Max
Min
Max
tCH1CH2
tR
Clock Rise Time
300
300
300
ns
tCL1CL2
300
300
300
ns
tF
Clock Fall Time
2
tR
SDA Rise Time
20
300
20
300
20
300
ns
tDL1DL2 2
tF
SDA Fall Time
20
300
20
300
20
300
ns
tDH1DH2
tCHDX 1
600
600
600
ns
Clock Pulse Width High
600
600
600
ns
tDLCL
tHD:STA Input Low to Clock Low (START)
600
600
600
ns
tCLDX
tHD:DAT Clock Low to Input Transition
0
0
0
µs
tCHCL
tSU:STA Clock High to Input Transition
tHIGH
tCLCH
tLOW
Clock Pulse Width Low
1.3
1.3
1.3
µs
t DXCX
tSU:DAT
Input Transition to Clock
Transition
100
100
100
ns
tCHDH
tSU:STO Clock High to Input High (STOP)
600
600
600
ns
1.3
1.3
µs
tDHDL
tBUF
Input High to Input Low (Bus
Free)
1.3
tCLQV 3
tAA
Clock Low to Data Out Valid
200
tCLQX
tDH
Data Out Hold Time After Clock
Low
200
fC
fSCL
Clock Frequency
400
400
400
kHz
tW
tWR
Write Time
10
10
10
ms
Note: 1.
2.
3.
4.
900
200
900
200
200
900
200
ns
ns
For a reSTART condition, or following a write cycle.
Sampled only, not 100% tested.
To avoid spurious STAR T and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
This is preliminary data.
Table 10. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing
Reference Voltages
≤ 50 ns
Figure 9. AC Testing Input Output Waveforms
0.8VCC
0.2V CC to 0.8VCC
0.3V CC to 0.7VCC
0.2VCC
0.7VCC
0.3VCC
AI00825
11/19
M24256-B, M24128-B
Figure 10. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
tDXCX
tCHDH
SDA IN
tCHDX
START
CONDITION
tCLDX
tDHDL
SDA
INPUT
SDA
CHANGE
STOP &
BUS FREE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
SCL
tW
SDA IN
tCHDH
STOP
CONDITION
tCHDX
WRITE CYCLE
START
CONDITION
AI00795B
12/19
M24256-B, M24128-B
Table 11. Ordering Information Scheme
Example:
M24256
–B
W
MN
6
T
Memory Capacity
256
256 Kbit (32K x 8)
128
128 Kbit (16K x 8)
Option
T
Tape and Reel Packing
Temperature Range
6
–40 °C to 85 °C
5
–20 °C to 85 °C
Operating Voltage
Package
blank 1 4.5 V to 5.5 V
BN
PSDIP8 (0.25 mm frame)
W
2.5 V to 5.5 V
MN
SO8 (150 mil width)
R
1.8 V to 3.6 V
DW
TSSOP8 (169 mil width)
DL
TSSOP14 (169 mil width)
Note: 1. Available only on request.
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.
13/19
M24256-B, M24128-B
Table 12. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
inches
Symb.
Typ.
Min.
Max.
A
3.90
A1
Min.
Max.
5.90
0.154
0.232
0.49
–
0.019
–
A2
3.30
5.30
0.130
0.209
B
0.36
0.56
0.014
0.022
B1
1.15
1.65
0.045
0.065
C
0.20
0.36
0.008
0.014
D
9.20
9.90
0.362
0.390
–
–
–
–
6.00
6.70
0.236
0.264
–
–
–
–
7.80
–
0.307
–
E
7.62
E1
e1
2.54
eA
eB
Typ.
0.300
0.100
10.00
L
3.00
N
8
0.394
3.80
0.118
8
Figure 11. PSDIP8 (BN)
A2
A1
B
A
L
e1
eA
eB
B1
D
C
N
E1
E
1
PSDIP-a
Note: 1. Drawing is not to scale.
14/19
0.150
M24256-B, M24128-B
Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
inches
Symb.
Typ.
Min.
Max.
A
1.35
A1
Min.
Max.
1.75
0.053
0.069
0.10
0.25
0.004
0.010
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
–
–
–
–
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
0.90
0.016
0.035
α
0°
8°
0°
8°
N
8
e
1.27
Typ.
0.050
8
CP
0.10
0.004
Figure 12. SO8 narrow (MN)
h x 45°
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Note: 1. Drawing is not to scale.
15/19
M24256-B, M24128-B
Table 14. TSSOP8 - 8 lead Thin Shrink Small Outline
mm
inches
Symb.
Typ.
Min.
Max.
A
Typ.
Min.
1.10
0.043
A1
0.05
0.15
0.002
0.006
A2
0.85
0.95
0.033
0.037
B
0.19
0.30
0.007
0.012
C
0.09
0.20
0.004
0.008
D
2.90
3.10
0.114
0.122
E
6.25
6.50
0.246
0.256
E1
4.30
4.50
0.169
0.177
–
–
–
–
L
0.50
0.70
0.020
0.028
α
0°
8°
0°
8°
N
8
e
0.65
0.026
8
CP
0.08
0.003
Figure 13. TSSOP8 (DW)
D
DIE
N
C
E1 E
1
N/2
α
A1
A
CP
A2
B
L
e
TSSOP
Note: 1. Drawing is not to scale.
16/19
Max.
M24256-B, M24128-B
Table 15. TSSOP14 - 14 lead Thin Shrink Small Outline
mm
inches
Symb.
Typ.
Min.
Max.
A
Typ.
Min.
1.10
Max.
0.043
A1
0.05
0.15
0.002
0.006
A2
0.85
0.95
0.033
0.037
B
0.19
0.30
0.007
0.012
C
0.09
0.20
0.004
0.008
D
4.90
5.10
0.193
0.197
E
6.25
6.50
0.246
0.256
E1
4.30
4.50
0.169
0.177
–
–
–
–
L
0.50
0.70
0.020
0.028
α
0°
8°
0°
8°
N
14
e
0.65
0.026
14
CP
0.08
0.003
Figure 14. TSSOP14 (DL)
D
DIE
N
C
E1 E
1
N/2
α
A1
A
CP
A2
B
L
e
TSSOP
Note: 1. Drawing is not to scale.
17/19
M24256-B, M24128-B
Table 16. Revision History
Date
Description of Revision
28-Dec-1999
TSSOP8 package added (pp 1, 2, OrderingInfo, PackageMechData).
24-Feb-2000
E2, E1, E0 must be tied to Vcc or Vss, on page 3
Low Pass Filter Time Constant changed to Glitch Filter in Table 8
18/19
M24256-B, M24128-B
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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authorized for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics.
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19/19
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