STMicroelectronics M28256-20WNS6T 256 kbit 32kb x8 parallel eeprom with software data protection Datasheet

M28256
256 Kbit (32Kb x8) Parallel EEPROM
with Software Data Protection
PRELIMINARY DATA
FAST ACCESS TIME:
– 90ns at 5V
– 120ns at 3V
SINGLE SUPPLY VOLTAGE:
– 5V ± 10% for M28256
– 2.7V to 3.6V for M28256-xxW
LOW POWER CONSUMPTION
FAST WRITE CYCLE:
– 64 Bytes Page Write Operation
– Byte or Page Write Cycle
ENHANCED END of WRITE DETECTION:
– Data Polling
– Toggle Bit
STATUS REGISTER
HIGH RELIABILITY DOUBLE POLYSILICON,
CMOS TECHNOLOGY:
– Endurance >100,000 Erase/Write Cycles
– Data Retention >10 Years
JEDEC APPROVED BYTEWIDE PIN OUT
ADDRESS and DATA LATCHED ON-CHIP
SOFTWARE DATA PROTECTION
28
1
PDIP28 (BS)
PLCC32 (KA)
28
1
SO28 (MS)
300 mils
TSOP28 (NS)
8 x13.4mm
Figure 1. Logic Diagram
VCC
DESCRIPTION
The M28256 and M28256-Ware 32K x8 low power
Parallel EEPROM fabricatedwith STMicroelectronics proprietary double polysilicon CMOS technology.
Table 1. Signal Names
15
8
A0-A14
W
A0-A14
Address Input
E
DQ0-DQ7
Data Input / Output
G
W
Write Enable
E
Chip Enable
G
Output Enable
VCC
Supply Voltage
VSS
Ground
DQ0-DQ7
M28256
VSS
AI01885
January 1999
This is preliminary information on a new product now in developmentor undergoing evaluation . Detail s are subject to change without notice.
1/21
M28256
1
28
2
27
3
26
4
25
5
24
6
23
7
22
M28256
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A12
A14
DU
VCC
W
A13
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Figure 2B. LCC Pin Connections
1 32
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
9
M28256
25
A8
A9
A11
NC
G
A10
E
DQ7
DQ6
17
DQ1
DQ2
VSS
DU
DQ3
DQ4
DQ5
Figure 2A. DIP Pin Connections
AI01886
AI01887
Warning: NC = Not Connected, DU = Don’t Use.
Figure 2C. SO Pin Connections
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
M28256
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Figure 2D. TSOP Pin Connections
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
G
A11
A9
A8
A13
W
VCC
A14
A12
A7
A6
A5
A4
A3
22
28
1
7
21
M28256
15
14
8
AI01888
AI01889
2/21
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
M28256
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Ambient Operating Temperature
Value
(2)
Unit
– 40 to 85
°C
T STG
Storage Temperature Range
– 65 to 150
°C
VCC
Supply Voltage
– 0.3 to 6.5
V
V IO
Input/Output Voltage
– 0.3 to VCC +0.6
V
VI
Input Voltage
– 0.3 to 6.5
V
4000
V
VESD
Electrostatic Discharge Voltage (Human Body model)
(3)
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Depends on range.
3. 100pF through 1500Ω; MIL-STD-883C, 3015.7
Figure 3. Block Diagram
E
A6-A14
(Page Address)
A0-A5
RESET
ADDRESS
LATCH
X DECODE
VPP GEN
G
W
CONTROL LOGIC
256K ARRAY
ADDRESS
LATCH
Y DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
AI01697
3/21
M28256
Table 3. Operating Modes (1)
Mode
E
G
W
DQ0 - DQ7
Read
VIL
VIL
VIH
Data Out
Write
VIL
VIH
VIL
Data In
Standby / Write Inhibit
VIH
X
X
Hi-Z
Write Inhibit
X
X
VIH
Data Out or Hi-Z
Write Inhibit
X
VIL
X
Data Out or Hi-Z
Output Disable
X
VIH
X
Hi-Z
Notes: 1. X = VIH or VIL.
DESCRIPTION (Cont’d)
The devices offer fast access time with low power
dissipation and requires a 5V or 3V power supply.
The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
and software handshaking with Data Polling and
Toggle Bit and access to a status register. The
devices support a 64 byte page write operation. A
Software Data Protection (SDP) is also possible
using the standard JEDEC algorithm.
PIN DESCRIPTION
Addresses (A0-A14). The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E). The chip enable input must be
low to enable all read/write operations.When Chip
Enable is high, power consumption is reduced.
Output Enable (G). The Output Enable input controls the data output buffers and is used to initiate
read operations.
Data In/ Out (DQ0- DQ7). Data is written to or read
from the memory through the I/O pins.
Write Enable (W). The Write Enable input controls
the writing of data to the memory.
OPERATIONS
Write Protection
In order to prevent data corruption and inadvertent
write operations; an internal VCC comparatorinhibits Write operations if VCC is below VWI (see Table
7 andTable 9).Access to the memoryin write mode
is allowed after a power-up as specified in Table 7
and Table 9.
4/21
Read
The device is accessed like a static RAM. When E
and G are low with W high, the data addressed is
presented on the I/O pins. The I/O pins are high
impedance when either G or E is high.
Write
Write operations are initiated when both W and E
are low and G is high.The device supports both E
and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurs last and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion and
the status of the Data Polling and the Toggle Bit
functions on DQ7 and DQ6 is controlled accordingly.
Page Write
Page write allows up to 64 bytes within the same
page to be consecutively latched into the memory
prior to initiating a programming cycle. All bytes
must be located in a single page address, that is
A14-A6 must be the same for all bytes; if not, the
Page Write instruction is not executed. The page
write can be initiated by any byte write operation.
A page write is composed of successive Write
instructions which have to be sequenced with a
specific period of time between two consecutive
Write instructions, period of time which has to be
smaller than the tWHWH value (see Table 12 and
Table 13).
If this period of time exceeds the tWHWH value, the
internal programmingcycle will start. Once initiated
the write operation is internally timed until completion and the status of the Data Polling and the
Toggle Bit functions on DQ7 and DQ6 is controlled
accordingly.
M28256
Status Register
The devices provide several Write operation status
flags that can be used to minimize the application
write time. These signals are available on the I/O
port bits during programming cycle only.
Data Polling bit (DQ7). During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is finished the true logic value appears on DQ7 in the
read cycle.
Toggle bit (DQ6). The devices offer another way
for determining when the internal write cycle is
completed. During the internal Erase/Write cycle,
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
first read value is ”0”) on subsequent attempts to
read any byte of the memory. When the internal
cycle is completed the toggling will stop and the
data read on DQ7-DQ0 is the addressed memory
byte. The device is now accessible for a new Read
or Write operation.
Page Load TimerStatus bit(DQ5). Duringa Page
Write instruction, the devices expect to receive the
stream of data with a minimum period of time
between each data byte. This period of time
(tWHWH) is defined by the on-chip Page Load timer
which running/overflow status is available on DQ5.
DQ5 Low indicates that the timer is running, DQ5
High indicates the time-out after which the internal
write cycle will start.
Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP
TB
PLTS
X
X
DP
= Data Polling
TB
= Toggle Bit
PLTS = Page Load Timer Status
X
X
X
Software Data Protection
The devices offer a software controlled write protection facility that allows the user to inhibit all write
modes to the device. This can be useful in protecting the memory from inadvertent write cycles that
may occur due to uncontrolledbus conditions.
The devices are shipped as standardin the ”unprotected” state meaning that the memory contents
can be changed as required by the user. After the
Software Data Protection enable algorithm is issued, the device enters the ”Protect Mode” of
operation where no further write commands have
any effect on the memory contents.
The devices remain in this mode until a valid
Software Data Protection (SDP) disable sequence
is received whereby the device reverts to its ”unprotected” state. The Software Data Protection is
fully non-volatile and is not changed by power
on/off sequences. To enable the Software Data
Protection (SDP) the device requires the user to
write (with a Page Write addressing three specific
data bytes to three specific memorylocations,each
location in a different page) as per Figure 6. Similarly to disable the Software Data Protection the
user has to write specific data bytes into six different locations as per Figure 5 (with a Page Write
adressing different bytes in different pages).
This complexseries ensures that the userwill never
enable or disable the Software Data Protection
accidentally.
To write into the devices when SDP is set, the
sequence shown in Figure 6 must be used. This
sequence provides an unlock key to enable the
write action, and at the same time SDP continues
to be set.
An extension to this is where SDP is required to be
set, and data is to be written.
Using the same sequence as above, the data can
be written and SDP is set at the same time, giving
both these actions in the same Write cycle (tWC).
5/21
M28256
Figure 5. Software Data Protection Enable Algorithm and Memory Write
SDP
Set
Page
Write
Instruction
SDP
not Set
WRITE AAh in
Address 5555h
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
WRITE 55h in
Address 2AAAh
WRITE A0h in
Address 5555h
Page
Write
Instruction
WRITE A0h in
Address 5555h
WRITE
is enabled
SDP is set
WRITE Data to
be Written in
any Address
Write
in Memory
SDP ENABLE ALGORITHM
Write Data
+
SDP Set
after tWC
AI01698B
Figure 6. Software Data Protection Disable Algorithm
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
Page
Write
Instruction
WRITE 80h in
Address 5555h
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
WRITE 20h in
Address 5555h
Unprotected State
after
tWC (Write Cycle time)
AI01699B
6/21
M28256
Table 4. AC Measurement Conditions
≤ 20ns
Input Rise and Fall Times
Input Pulse Voltages (M28256)
0.4V to 2.4V
0V to V CC –0.3V
Input Pulse Voltages (M28256-W)
Input and Output Timing Ref. Voltages (M28256)
0.8V to 2.0V
Input and Output Timing Ref. Voltages (M28256-W)
0.5 VCC
Figure 7. AC Testing Input Output Waveforms
Figure 8. AC Testing Equivalent Load Circuit
4.5V to 5.5V Operating Voltage
2.4V
2.0V
0.8V
0.4V
IOL
DEVICE
UNDER
TEST
2.7V to 3.6V Operating Voltage
OUT
IOH
VCC – 0.3V
CL = 100pF
0.5 VCC
0V
AI02101B
CL includes JIG capacitance
AI02102B
Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
C OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 6. Read Mode DC Characteristics for M28256
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
10
µA
ILO
Output Leakage Current
0V ≤ VIN ≤ VCC
10
µA
Supply Current (TTL inputs)
E = VIL, G = VIL , f = 5 MHz
30
mA
ICC
(1)
Supply Current (CMOS inputs)
E = VIL, G = VIL , f = 5 MHz
25
mA
ICC1
(1)
Supply Current (Standby) TTL
E = VIH
1
mA
ICC2
(1)
Supply Current (Standby) CMOS
E > VCC –0.3V
100
µA
VIL
Input Low Voltage
– 0.3
0.8
V
VIH
Input High Voltage
2
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.4
V
VOH
Output High Voltage
IOH = –400 µA
2.4
Note: 1. All I/O’s open circuit.
7/21
M28256
Table 7. Power Up Timing for M28256 (1)
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol
Parameter
Min
Max
Unit
tPUR
Time Delay to Read Operation
1
µs
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
5
ms
VWI
Write Inhibit Threshold
4.2
V
3.0
Note: 1. Sampled only, not 100% tested.
Table 8. Read Mode DC Characteristics for M28256-W
(TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
10
µA
ILO
Output Leakage Current
0V ≤ VIN ≤ VCC
10
µA
E = VIL, G = VIL, f = 5 MHz, V CC = 3.3V
15
mA
E = VIL, G = VIL, f = 5 MHz, V CC = 3.6V
15
mA
E > VCC –0.3V
20
µA
ICC
(1)
ICC2
(1)
Supply Current (CMOS inputs)
Supply Current (Standby) CMOS
VIL
Input Low Voltage
– 0.3
0.6
V
VIH
Input High Voltage
2
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.2 VCC
V
VOH
Output High Voltage
IOH = –400 µA
0.8 VCC
V
Note: 1. All I/O’s open circuit.
Table 9. Power Up Timing for M28256-W (1)
(TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol
Parameter
Max
Unit
tPUR
Time Delay to Read Operation
1
µs
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
10
ms
VWI
Write Inhibit Threshold
2.5
V
Note: 1. Sampled only, not 100% tested.
8/21
Min
1.5
M28256
Table 10. Read Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
M28256
Symbol
Alt
Parameter
Test Condition
-90
-12
min max
tAVQV
tACC
Address Valid to
Output Valid
tELQV
tCE
tGLQV
-15
Unit
-20
min max min max
min max
E = VIL, G = VIL
90
120
150
200
ns
Chip Enable Low to
Output Valid
G = VIL
90
120
150
200
ns
tOE
Output Enable Low
to Output Valid
E = VIL
40
45
50
50
ns
tEHQZ (1)
tDF
Chip Enable High to
Output Hi-Z
G = VIL
0
40
0
45
0
50
0
50
ns
tGHQZ (1)
tDF
Output Enable High
to Output Hi-Z
E = VIL
0
40
0
45
0
50
0
50
ns
tAXQX
tOH
Address Transition
to Output Transition
E = VIL, G = VIL
0
0
0
0
ns
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Table 11. Read Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
M28256-W
Symbol
Alt
Parameter
Test Condition
-12
-15
min max
tAVQV
tACC
Address Valid to
Output Valid
tELQV
tCE
tGLQV
-20
Unit
-25
min max min max
min max
E = VIL, G = VIL
120
150
200
250
ns
Chip Enable Low to
Output Valid
G = VIL
120
150
200
250
ns
tOE
Output Enable Low
to Output Valid
E = VIL
45
70
80
100
ns
(1)
tDF
Chip Enable High to
Output Hi-Z
G = VIL
0
45
0
50
0
55
0
60
ns
tGHQZ (1)
tDF
Output Enable High
to Output Hi-Z
E = VIL
0
45
0
50
0
55
0
60
ns
tAXQX
tOH
Address Transition
to Output Transition
E = VIL, G = VIL
0
tEHQZ
0
0
0
ns
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
9/21
M28256
Table 12. Write Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol
Alt
Parameter
Test Condition
M28256
Min
Unit
Max
tAVWL
tAS
Address Valid to Write Enable Low
E = VIL, G = VIH
0
ns
tAVEL
tAS
Address Valid to Chip Enable Low
G = VIH, W = VIL
0
ns
tELWL
tCES
Chip Enable Low to Write Enable Low
G = VIH
0
ns
tGHWL
tOES
Output Enable High to Write Enable
Low
E = VIL
0
ns
tGHEL
tOES
Output Enable High to Chip Enable Low
W = VIL
0
ns
tWLEL
tWES
Write Enable Low to Chip Enable Low
G = VIH
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
50
ns
tELAX
tAH
Chip Enable Low to Address Transition
50
ns
tWLDV
tDV
Write Enable Low to Input Valid
E = VIL, G = VIH
1
µs
tELDV
tDV
Chip Enable Low to Input Valid
G = VIH, W = VIL
1
µs
tELEH
tWP
Chip Enable Low to Chip Enable High
50
ns
tWHEH
tCEH
Write Enable High to Chip Enable High
0
ns
tWHGL
tOEH
Write Enable High to Output Enable
Low
0
ns
tEHGL
tOEH
Chip Enable High to Output Enable Low
0
ns
tEHWH
tWEH
Chip Enable High to Write Enable High
0
ns
tWHDX
tDH
Write Enable High to Input Transition
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
100
ns
tWLWH
tWP
Write Enable Low to Write Enable High
50
ns
tWHWH
tBLC
Byte Load Repeat Cycle Time
tWHRH
tWC
Write Cycle Time
tEL, tWL
E or W Input Filter Pulse Width
0.15
Note 1
150
µs
5
ms
10
ns
tDVWH
tDS
Data Valid before Write Enable High
50
ns
tDVEH
tDS
Data Valid before Chip Enable High
50
ns
Note: 1. Characterized only but not tested in production.
10/21
M28256
Table 13. Write Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol
Alt
Parameter
Test Condition
M28256-W
Min
Unit
Max
tAVWL
tAS
Address Valid to Write Enable Low
E = VIL, G = VIH
0
ns
tAVEL
tAS
Address Valid to Chip Enable Low
G = VIH, W = VIL
0
ns
tELWL
tCES
Chip Enable Low to Write Enable Low
G = VIH
0
ns
tGHWL
tOES
Output Enable High to Write Enable
Low
E = VIL
0
ns
tGHEL
tOES
Output Enable High to Chip Enable Low
W = VIL
0
ns
tWLEL
tWES
Write Enable Low to Chip Enable Low
G = VIH
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
70
ns
tELAX
tAH
Chip Enable Low to Address Transition
70
ns
tWLDV
tDV
Write Enable Low to Input Valid
E = VIL, G = VIH
1
µs
tELDV
tDV
Chip Enable Low to Input Valid
G = VIH, W = VIL
1
µs
tELEH
tWP
Chip Enable Low to Chip Enable High
100
ns
tWHEH
tCEH
Write Enable High to Chip Enable High
0
ns
tWHGL
tOEH
Write Enable High to Output Enable
Low
0
ns
tEHGL
tOEH
Chip Enable High to Output Enable Low
0
ns
tEHWH
tWEH
Chip Enable High to Write Enable High
0
ns
tWHDX
tDH
Write Enable High to Input Transition
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
100
ns
tWLWH
tWP
Write Enable Low to Write Enable High
100
ns
tWHWH
tBLC
Byte Load Repeat Cycle Time
0.2
tWHRH
tWC
Write Cycle Time
tEL, tWL
E or W Input Filter Pulse Width
Note 1
150
µs
5
ms
10
ns
tDVWH
tDS
Data Valid before Write Enable High
50
ns
tDVEH
tDS
Data Valid before Chip Enable High
50
ns
Note: 1. Characterized only but not tested in production.
11/21
M28256
Figure 9. Read Mode AC Waveforms
A0-A14
VALID
tAVQV
tAXQX
E
tGLQV
tEHQZ
G
tELQV
tGHQZ
DQ0-DQ7
Hi-Z
DATA OUT
AI01700
Note: Write Enable (W) = High.
Figure 10. Write Mode AC Waveforms - Write Enable Controlled
A0-A14
VALID
tAVWL
tWLAX
E
tELWL
tWHEH
G
tWLWH
tGHWL
tWHGL
W
tWLDV
DQ0-DQ7
tWHWL
DATA IN
tDVWH
tWHDX
AI01701
12/21
M28256
Figure 11. Write Mode AC Waveforms - Chip Enable Controlled
A0-A14
VALID
tAVEL
tELAX
E
tGHEL
tELEH
G
tWLEL
tEHGL
W
tELDV
tEHWH
DATA IN
DQ0-DQ7
tDVEH
tEHDX
AI01702
Figure 12. Page Write Mode AC Waveforms - Write Enable Controlled
A0-A14
Addr 0
Addr 1
Addr 2
Addr n
E
G
tWHWL
tWHRH
W
tWLWH
DQ0-DQ7
DQ5
tWHWH
Byte 0
Byte 1
Byte 2
tWHWH
Byte n
Byte n
AI01703B
13/21
M28256
Figure 13. Software Protected Write Cycle Waveforms
G
E
tWLWH
tWHWL
tWHWH
W
tAVEL
tWLAX
A0-A5
Byte Address
tWHDX
A6-A14
5555h
2AAAh
5555h
Page Address
tDVWH
DQ0-DQ7
AAh
55h
A0h
Byte 0
Byte 62
Byte 63
AI01704
Note: A6 through A14 must specify the same page address during each high to low transition of W (or E) after the software code has been
entered. G must be high only when W and E are both low.
Figure 14. Data Polling Waveform Sequence
A0-A14
Address of the last byte of the Page Write instruction
E
G
W
DQ7
DQ7
LAST WRITE
DQ7
DQ7
DQ7
INTERNAL WRITE SEQUENCE
DQ7
READY
AI01705
14/21
M28256
Figure 15. Toggle Bit Waveform Sequence
A0-A14
E
G
W
DQ6
(1)
DQ6
LAST WRITE
TOGGLE
INTERNAL WRITE SEQUENCE
DQ6
READY
AI01706
Note: 1. First Toggle bit is forced to ’0’.
15/21
M28256
ORDERING INFORMATION SCHEME
Example:
Speed
(1)
M28256 – 15
Operating Voltage
W
KA 6
Package
BS PDIP28
90ns
blank
4.5V to 5.5V
12
120ns
W
2.7V to 3.6V
15
150ns
MS SO28 300 mils
20
200ns
25 (2)
250ns
NS TSOP28
8 x 13.4mm
90
KA PLCC32
T
Temperature Range
1
(3)
6
0 to 70 °C
–40 to 85 °C
Option
T
Tape & Reel
Packing
Notes: 1. Not available for ”W” operating voltage.
2. Available for ”W” operating voltage only.
3. Temperature Range on request only.
Devices are shipped from the factory with the memory content set at all ”1’s” (FFh).
For a list of available options (Speed, Package, etc...) or for further informationon any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
16/21
M28256
PDIP28 - 28 pin Plastic DIP, 600 mils width
mm
Symb
Typ
inches
Min
Max
Min
Max
A
–
5.08
–
0.200
A1
0.38
–
0.015
–
A2
3.56
4.06
0.140
0.160
B
0.38
0.51
0.015
0.020
–
–
–
–
C
0.20
0.30
0.008
0.012
D
36.83
37.34
1.450
1.470
B1
1.52
Typ
0.060
D2
33.02
–
–
1.300
–
–
E
15.24
–
–
0.600
–
–
13.59
13.84
0.535
0.545
E1
e1
2.54
–
–
0.100
–
–
eA
14.99
–
–
0.590
–
–
eB
15.24
17.78
0.600
0.700
L
3.18
3.43
0.125
0.135
S
1.78
2.08
0.070
0.082
α
0°
10°
0°
10°
N
28
28
A2
A1
B1
B
A
L
e1
α
eA
D2
C
eB
D
S
N
E1
E
1
PDIP
Drawing is not to scale.
17/21
M28256
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
Symb
Typ
inches
Min
Max
Min
Max
A
2.54
3.56
0.100
0.140
A1
1.52
2.41
0.060
0.095
A2
–
0.38
–
0.015
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
12.32
12.57
0.485
0.495
D1
11.35
11.56
0.447
0.455
D2
9.91
10.92
0.390
0.430
E
14.86
15.11
0.585
0.595
E1
13.89
14.10
0.547
0.555
E2
12.45
13.46
0.490
0.530
–
–
–
–
0.00
0.25
0.000
0.010
–
–
–
–
e
1.27
F
R
0.89
Typ
0.050
0.035
N
32
32
Nd
7
7
Ne
9
9
D
D1
A1
A2
1 N
B1
E1 E
Ne
e
D2/E2
F
B
0.51 (.020)
1.14 (.045)
A
Nd
R
PLCC
Drawing is not to scale.
18/21
CP
M28256
SO28 - 28 lead Plastic Small Outline, 300 mils body width
mm
Symb
Typ
inches
Min
Max
A
2.46
A1
Min
Max
2.64
0.097
0.104
0.13
0.29
0.005
0.011
B
0.35
0.48
0.014
0.019
C
0.23
0.32
0.009
0.013
D
17.81
18.06
0.701
0.711
E
7.42
7.59
0.292
0.299
–
–
–
–
H
10.16
10.41
0.400
0.410
L
0.61
1.02
0.024
0.040
α
0°
8°
0°
8°
N
28
e
1.27
CP
Typ
0.050
28
0.10
A2
0.004
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-b
Drawing is not to scale.
19/21
M28256
TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm
mm
Symb
Typ
inches
Min
Max
Typ
Min
A
1.25
0.049
A1
0.20
0.008
A2
0.95
1.15
0.037
0.045
B
0.17
0.27
0.007
0.011
C
0.10
0.21
0.004
0.008
D
13.20
13.60
0.520
0.535
D1
11.70
11.90
0.461
0.469
E
7.90
8.10
0.311
0.319
-
-
-
-
L
0.50
0.70
0.020
0.028
α
0°
5°
0°
5°
N
28
e
0.55
0.022
28
CP
0.10
0.004
A2
22
21
e
28
1
E
B
7
8
D1
A
CP
D
DIE
C
TSOP-c
Drawing is not to scale.
20/21
Max
A1
α
L
M28256
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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21/21
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